Data processing method and device

Abstract

The present application provides a data processing method and device, which can solve the problem of resource waste, thereby improving data processing efficiency, and can be applied to a data processing system. The method includes: determining I seed programs called by N parent programs, and obtaining the execution count L of the i-th seed program in the I seed programs. i . Where N>I, N, I are positive integers greater than 1. #imgabs0#L i is a positive integer. According to the execution times of various subroutines, determine J instruction cycles and K in the jth instruction cycle. j A set of thread groups. Among them, #imgabs1#J, K j is a positive integer. A thread group set includes one or more thread groups. The types of subroutines executed by all thread group sets in J instruction cycles are different. In each thread group set, the number of threads that have not executed subroutines is less than the number of threads in a thread group.

Description

Technical Field

[0001] The present application relates to the field of data processing, and in particular to a data processing method and device. Background Art

[0002] Program iterative call refers to the situation where one program calls another program during execution. For example, in ray tracing, there will be multiple shader programs that are iteratively called in a rendering pipeline.

[0003] Currently, in ray tracing, program iterative calling can be implemented based on two schemes: ray intersection test results and status. Specifically, in the scheme based on ray intersection test results, the subroutine that the parent program needs to call can be determined based on the intersection test results corresponding to the parent program, such as whether the ray intersects or does not intersect with the object. In the state-based scheme, the subroutine that the parent program needs to call can be determined based on the execution status of the parent program. In the above two program iterative calling schemes, the parent program and the subroutine that the parent program needs to call are executed by the same thread.

[0004] However, if different threads of the same thread group need to execute different subroutines, different subroutines need to be executed in multiple instruction cycles, which results in threads that do not execute subroutines in each instruction cycle of the same thread group, that is, threads that are in an idle state, resulting in resource waste and low data processing efficiency. In addition, in each instruction cycle, threads in the same thread group need to read instructions corresponding to the subroutines from the instruction buffer. Due to the limited size of the instruction buffer, only instructions corresponding to some subroutines can be stored. Therefore, when the subroutines to be executed change frequently, there may be no instructions corresponding to the subroutines in the instruction buffer, and the instructions of the subroutines need to be read from the main memory, such as the double datarate synchronous dynamic random access memory (DDR), that is, the instruction hit rate decreases at this time. In addition, since it takes a long time to read instructions from the main memory, the corresponding thread is still in an idle state during the reading of instructions from the main memory, which also leads to resource waste and low efficiency. Summary of the invention

[0005] The embodiments of the present application provide a data processing method and device, which can solve the problem of resource waste and thus improve data processing efficiency.

[0006] In order to achieve the above objectives, this application adopts the following technical solutions:

[0007] In a first aspect, a data processing method is provided. The data processing method comprises: determining I seed programs called by N parent programs, and obtaining the execution count L of the i-th seed program in the I seed programs. i. Wherein, N>I, N and I are positive integers greater than 1. L i is a positive integer. According to the execution times of various subroutines, determine J instruction cycles and K in the jth instruction cycle. j A collection of thread groups. Among them, J.K j is a positive integer. A thread group set includes one or more thread groups. The types of subroutines executed by all thread group sets in J instruction cycles are different. In each thread group set, the number of threads that have not executed subroutines is less than the number of threads in a thread group.

[0008] Based on the data processing method provided in the first aspect, the number of instruction cycles used to execute multiple sub-programs and the number of thread group sets in each instruction cycle can be determined according to the multiple sub-programs called by multiple parent programs and the number of execution times of each sub-program, so that the same sub-program can be executed in the same instruction cycle, so as to minimize the number of required instruction cycles and / or the number of required thread groups, which can improve resource utilization and thus improve data processing efficiency.

[0009] In addition, the same seed program is executed in the same instruction cycle, avoiding the situation where threads in different thread groups frequently switch the instructions read in the same instruction cycle and threads in the same thread group frequently switch the instructions read in different instruction cycles. This can improve the hit rate of instruction fetch operations, thereby improving resource utilization and data processing efficiency.

[0010] In one possible design, the number of J instruction cycles and the number of K in the jth instruction cycle are determined based on the number of executions of various subroutines. j The thread group set may include: determining the thread group set corresponding to the i-th subprogram and the instruction cycle corresponding to the thread group set corresponding to the i-th subprogram according to the number of executions. In this way, by determining the thread group set and the instruction cycle corresponding to each subprogram according to the number of executions of the subprogram, the number of thread groups executing the same subprogram can be reduced, and / or the number of instruction cycles required for all subprograms can be reduced, so as to further improve resource utilization and data processing efficiency.

[0011] Optionally, the number of thread groups in the thread group set corresponding to the i-th seed program, the number of threads in a thread group, and the number of execution times corresponding to the i-th seed program satisfy one or more of the following conditions: Or, (W i -1)*m≤L i ≤W i *m. Among them, W iis the number of thread groups in the thread group set corresponding to the i-th subprogram, and m is the number of threads in a thread group. In this way, the same subprogram uses as few thread groups as possible to execute, so as to further improve resource utilization and data processing efficiency.

[0012] Optionally, determining the thread group set corresponding to the i-th subprogram and the instruction cycle in which the thread group set corresponding to the i-th subprogram is located according to the number of executions may include: determining the first order of the i-th subprogram according to the number of executions. The first order is used to indicate the order in which the thread group set corresponding to each subprogram is obtained. According to the first order, the thread group set corresponding to the i-th subprogram and the instruction cycle corresponding to the thread group set corresponding to the i-th subprogram are determined. In this way, the thread group set corresponding to the subprogram with a higher order can be preferentially determined, thereby further improving resource utilization and data processing efficiency.

[0013] Furthermore, the first order indicates that the thread group set corresponding to the subprogram with a large number of execution times is obtained first. In this way, the thread group set corresponding to the subprogram with a large number of execution times is determined first, and the subprogram with a large number of threads can be executed in an earlier instruction cycle, thereby further improving resource utilization and data processing efficiency.

[0014] In a possible design, the number of thread groups in all thread group sets in the jth instruction cycle is greater than or equal to the number of thread groups in all thread group sets in the j+1th instruction cycle. In this way, the total number of threads used to execute subroutines in each instruction cycle remains unchanged or gradually decreases, which can avoid the situation where idle thread groups cannot be released, thereby further improving resource utilization and data processing efficiency.

[0015] In a possible design, the number of executions can be determined based on the number of parent programs that call the i-th subprogram. In this way, by determining the number of executions of the i-th subprogram based on the number of parent programs that call the i-th subprogram, the obtained number of executions can be made more accurate, and the thread group set of each subprogram can be accurately determined, thereby reducing the number of idle threads in each instruction cycle, and further improving resource utilization and data processing efficiency.

[0016] In a second aspect, a data processing device is provided. The data processing device includes: a determination module and an acquisition module. The determination module is used to determine I seed programs called by N parent programs. N>I, N, I are positive integers greater than 1. The acquisition module is used to obtain the execution count L of the i-th seed program in the I seed programs. i .in, L i is a positive integer. The determination module is also used to determine J instruction cycles and K in the jth instruction cycle according to the execution times of various subroutines. j A collection of thread groups. Among them, J.K j is a positive integer. A thread group set includes one or more thread groups. The types of subroutines executed by all thread group sets in J instruction cycles are different. In each thread group set, the number of threads that have not executed subroutines is less than the number of threads in a thread group.

[0017] In a possible design, the determination module is further used to determine the thread group set corresponding to the i-th seed program and the instruction cycle corresponding to the thread group set corresponding to the i-th seed program according to the number of executions.

[0018] Optionally, the number of thread groups in the thread group set corresponding to the i-th seed program, the number of threads in a thread group, and the number of execution times corresponding to the i-th seed program satisfy one or more of the following: Or, (W i -1)*m≤L i ≤W i *m. Among them, W i is the number of thread groups in the thread group set corresponding to the i-th seed program, and m is the number of threads in a thread group.

[0019] Optionally, the determination module is further used to determine the first order of the ith subprogram according to the number of executions, and to determine the thread group set corresponding to the ith subprogram and the instruction cycle corresponding to the thread group set corresponding to the ith subprogram according to the first order. The first order is used to indicate the order in which the thread group set corresponding to each subprogram is obtained.

[0020] Furthermore, the first order indicates that the thread group set corresponding to the subroutine with a large number of execution times is obtained first.

[0021] In a possible design, the number of thread groups in the set of all thread groups in the j-th instruction cycle is greater than or equal to the number of thread groups in the set of all thread groups in the j+1-th instruction cycle.

[0022] In a possible design, the number of executions may be determined according to the number of parent programs that call the i-th subprogram.

[0023] It should be noted that, optionally, the determination module and the acquisition module may also be integrated into one module, such as a processing module, wherein the processing module is used to implement the operations of the above-mentioned functional modules.

[0024] Optionally, the data processing method described in the second aspect may further include a storage module, such as an instruction cache, which stores a program or instruction. When the processing module executes the program or instruction, the data processing device can execute the data processing method described in the first aspect.

[0025] Optionally, the data processing device described in the second aspect may further include an input / output port, wherein the input / output port is used to implement the input and / or output function of instructions and / or data of the data processing device described in the second aspect.

[0026] Furthermore, the input and output ports may also be coupled to a transceiver. The transceiver is used for information exchange between the data processing device and other data processing devices, and the processor executes program instructions to execute the data processing method described in the first aspect. The data processing device described in the second aspect may be a computing device, such as a mobile phone, a tablet (PAD), a personal computer, a server, or a chip (system) or other components or components that can be set in a computing device, such as a processor, or a computing device cluster including a computing device, such as a server cluster, which is not limited in this application.

[0027] In addition, the technical effects of the data processing device described in the second aspect can refer to the technical effects of the data processing method described in the first aspect, and will not be repeated here.

[0028] In a third aspect, a data processing device is provided, which is used to execute the data processing method described in the implementation mode of the first aspect.

[0029] In the present application, the data processing device described in the third aspect may be the computing device described in the first aspect, or a chip (system) or other parts or components that may be arranged in the computing device, or a device including the computing device.

[0030] It should be understood that the data processing device described in the third aspect includes a module, unit, or means corresponding to the data processing method described in the first aspect, and the module, unit, or means can be implemented by hardware, software, or by hardware executing the corresponding software. The hardware or software includes one or more modules or units for performing the functions involved in the above-mentioned data processing method.

[0031] In addition, the technical effects of the data processing device described in the third aspect can refer to the technical effects of the data processing method described in the first aspect, and will not be repeated here.

[0032] In a fourth aspect, a data processing device is provided, which includes: a processor, which is used to execute the data processing method described in the possible implementation manner of the first aspect.

[0033] In a possible design solution, the data processing device described in the fourth aspect may further include a transceiver. The transceiver may be a transceiver circuit or an interface circuit. The transceiver may be used for the data processing device described in the fourth aspect to communicate with other data.

[0034] In a possible design scheme, the data processing device described in the fourth aspect may further include a memory. The memory may be integrated with the processor or may be separately provided. The memory may be used to store the computer program and / or data involved in the data processing method described in the first aspect.

[0035] In the present application, the data processing device described in the fourth aspect may be the computing device in the first aspect, or a chip (system) or other parts or components that may be arranged in the computing device, or a device including the computing device.

[0036] In addition, the technical effects of the data processing device described in the fourth aspect can refer to the technical effects of the data processing method described in the implementation method of the first aspect, and will not be repeated here.

[0037] In a fifth aspect, a data processing device is provided, comprising: a processor coupled to a memory, the processor being configured to execute a computer program stored in the memory, so that the data processing device executes the data processing method described in the implementation of the first aspect.

[0038] In a possible design solution, the data processing device described in the fifth aspect may further include a transceiver. The transceiver may be a transceiver circuit or an interface circuit. The transceiver may be used for the data processing device described in the fifth aspect to communicate with other data processing devices.

[0039] In the present application, the data processing device described in the fifth aspect may be the computing device of the first aspect, or a chip (system) or other parts or components that may be arranged in the computing device, or a device including the computing device.

[0040] In addition, the technical effects of the data processing device described in the fifth aspect can refer to the technical effects of the data processing method described in the implementation method of the first aspect, and will not be repeated here.

[0041] In a sixth aspect, a data processing device is provided, comprising: a processor and a memory; the memory is used to store a computer program, and when the processor executes the computer program, the data processing device executes the data processing method described in the implementation manner of the first aspect.

[0042] In a possible design solution, the data processing device described in the sixth aspect may further include a transceiver. The transceiver may be a transceiver circuit or an interface circuit. The transceiver may be used for the data processing device described in the sixth aspect to communicate with other data processing devices.

[0043] In the present application, the data processing device described in the sixth aspect may be the computing device of the first aspect, or a chip (system) or other parts or components that may be arranged in the computing device, or a device including the computing device.

[0044] In addition, the technical effects of the data processing device described in the sixth aspect can refer to the technical effects of the data processing method described in the implementation method of the first aspect, and will not be repeated here.

[0045] In a seventh aspect, a data processing device is provided, comprising: a processor; the processor is used to couple with a memory, and after reading a computer program in the memory, execute the data processing method as described in the implementation manner of the first aspect according to the computer program.

[0046] In a possible design solution, the data processing device described in the seventh aspect may further include a transceiver. The transceiver may be a transceiver circuit or an interface circuit. The transceiver may be used for the data processing device described in the seventh aspect to communicate with other data processing devices.

[0047] In the present application, the data processing device described in the seventh aspect may be the computing device of the first aspect, or a chip (system) or other parts or components that may be arranged in the computing device, or a device including the computing device.

[0048] In addition, the technical effects of the data processing device described in the seventh aspect can refer to the technical effects of the data processing method described in the implementation method of the first aspect, and will not be repeated here.

[0049] In addition, the technical effects of the data processing devices described in the fifth to seventh aspects above can refer to the technical effects of the data processing method described in the first aspect above, and will not be repeated here.

[0050] In an eighth aspect, a processor is provided, wherein the processor is used to execute the data processing method described in the implementation of the first aspect.

[0051] In a ninth aspect, a data processing system is provided, wherein the data processing system includes one or more computing devices.

[0052] In a tenth aspect, a computer-readable storage medium is provided, comprising: a computer program or instructions; when the computer program or instructions are run on a computer, the computer executes the data processing method described in the implementation manner of the first aspect.

[0053] In an eleventh aspect, a computer program product is provided, comprising a computer program or instructions, which, when executed on a computer, enables the computer to execute the data processing method described in the implementation manner of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 A schematic diagram of the structure of a terminal device provided in an embodiment of the present application;

[0055] Figure 2 A flowchart of a data processing method provided in an embodiment of the present application;

[0056] Figure 3 Schematic diagram of the relationship between the parent program and the child program provided in the embodiment of the present application Figure 1 ;

[0057] Figure 4 Schematic diagram of the relationship between the parent program and the child program provided in the embodiment of the present application Figure 2 ;

[0058] Figure 5 Schematic diagram of the relationship between the thread group set and the subroutine provided in the embodiment of the present application Figure 1 ;

[0059] Figure 6 Schematic diagram of the relationship between the thread group set and the thread group provided in the embodiment of the present application Figure 1 ;

[0060] Figure 7 Schematic diagram of the relationship between the thread group set and the subroutine provided in the embodiment of the present application Figure 2 ;

[0061] Figure 8 Schematic diagram of the relationship between the thread group set and the thread group provided in the embodiment of the present application Figure 2 ;

[0062] Fig. 9 Schematic diagram of the relationship between the parent program and the child program provided in the embodiment of the present application Figure 3 ;

[0063] Fig.10 Schematic diagram of the relationship between the thread group set and the subroutine provided in the embodiment of the present application Figure 3 ;

[0064] Fig.11 Schematic diagram of the relationship between the thread group set and the subroutine provided in the embodiment of the present application Figure 4 ;

[0065] Fig.12 A schematic diagram of the structure of the data processing device provided in the embodiment of the present application Figure 1 ;

[0066] Fig.13 A schematic diagram of the structure of the data processing device provided in the embodiment of the present application Figure 2 . DETAILED DESCRIPTION

[0067] The following is an introduction to the technical terms involved in the embodiments of the present application.

[0068] 1. Ray tracking: A method of displaying objects. This method tracks the light in the opposite direction of the light reaching the viewpoint, passes through each pixel on the screen, finds the surface point of the object that intersects the line of sight, and continues to track to find all light sources that affect the light intensity of the surface point of the object, thereby calculating the precise light intensity at the surface point of the object.

[0069] 2. Shader program: A shader program is an editable program used to implement image rendering.

[0070] 3. Subroutine: A subroutine, such as a shader program, is a code consisting of one or more blocks of statements. It is responsible for completing a specific task and has relative independence from other codes. Subroutines can be called by other programs.

[0071] 4. Parent program: A parent program is a set of codes that can implement certain functions. During execution, the parent program can call subprograms.

[0072] 5. Thread: The smallest unit on which a graphics processing unit (GPU) can perform computational scheduling, and can be used to execute programs, such as a parent program and subprograms called by the parent program.

[0073] The technical solution in this application will be described below in conjunction with the accompanying drawings.

[0074] The technical solution of the embodiment of the present application can be applied to a computing device. The computing device can be a terminal device, such as a client, a mobile phone, or a tablet computer, or a server, or a computing device cluster including a computing device, such as a server cluster, which is not limited in the present application.

[0075] The present application will present various aspects, embodiments or features around a system that may include multiple devices, components, modules, etc. It should be understood and appreciated that each system may include additional devices, components, modules, etc., and / or may not include all of the devices, components, modules, etc. discussed in conjunction with the figures. In addition, combinations of these schemes may also be used.

[0076] In addition, in the embodiments of the present application, words such as "exemplarily" and "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplary" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of the word "exemplary" is intended to present concepts in a concrete way.

[0077] In the embodiments of the present application, "information", "signal", "message", "channel" and "signaling" may be used interchangeably. It should be noted that when the distinction between them is not emphasized, the meanings they intend to express are consistent. "of", "corresponding, relevant" and "corresponding" may be used interchangeably. It should be noted that when the distinction between them is not emphasized, the meanings they intend to express are consistent.

[0078] The device structure described in the embodiments of the present application is intended to more clearly illustrate the technical solution of the embodiments of the present application, and does not constitute a limitation on the technical solution provided in the embodiments of the present application. Ordinary technicians in this field can know that with the evolution of equipment and the emergence of new business scenarios, the technical solution provided in the embodiments of the present application is also applicable to similar technical problems.

[0079] To facilitate understanding of the embodiments of the present application, first Figure 1 The terminal device shown in the figure is used as an example to describe in detail the device applicable to the embodiments of the present application.

[0080] For example, Figure 1 This is a schematic diagram of the structure of a terminal device 100 to which the data processing method provided in the embodiment of the present application is applicable. Figure 1 As shown, the terminal device 100 includes a processor 110, an internal memory 121, an external memory interface 122, an antenna A, a mobile communication module 131, an antenna B, a wireless communication module 132, an audio module 140, a speaker 140A, a receiver 140B, a microphone 140C, an earphone interface 140D, a display screen 151, a subscriber identification module (SIM) card interface 152, a camera 153, a button 154, a sensor module 160, a universal serial bus (USB) interface 170, a charging management module 180, a power management module 181 and a battery 182. In other embodiments, the terminal device 100 may also include a motor, an indicator, etc.

[0081] Among them, the processor 110 may include one or more processing units. For example, the processor 110 may include an application processor (application processor, AP), a modem, a graphics processor (graphics processing unit, GPU), an image signal processor (image signal processor, ISP), a controller, a video codec, a digital signal processor (digital signal processor, DSP), a baseband processor, and / or a neural-network processing unit (neural-network processing unit, NPU), etc. It should be noted that different processing units can be independent devices, or they can be integrated into one or more independent processors, and can be integrated with other modules in the terminal device in the same device. Taking the modem as an example, the modem can be a processing unit independent of the processor 110, or it can be integrated with other processing units (such as AP, ISP, GPU, etc.) in the same device, and some or all functions can be integrated with the mobile communication module 131 in the same device. Taking the controller as an example again, the controller can be a processing unit independent of the processor 110, or it can be integrated with other processing units (such as video codec, digital signal processor, etc.) in the same device, and some or all functions can be integrated with the mobile communication module 131 in the same device.

[0082] The internal memory 121 can be used to store data and / or at least one computer program, which includes instructions. Specifically, the internal memory 121 may include a program storage area and a data storage area. Among them, the program storage area can store at least one computer program. Computer programs may include applications (such as gallery, contacts, etc.), operating systems (such as Android operating system, or IOS operating system, etc.), or other programs, for example, computer programs may include programs for static detection. The data storage area can store at least one of the data created during the use of the terminal device, the data received from other devices (such as other terminal devices, network devices, servers, external memory, etc.), or the data pre-stored before leaving the factory. For example, the data stored in the internal memory 121 can be at least one of the information such as an application, the source code of the application, an image, a file, or an identification.

[0083] In some embodiments, the internal memory 121 may include a high-speed random access memory and / or a non-volatile memory. For example, the internal memory 121 includes one or more disk storage devices, flash memory devices (flash), or universal flash storage (UFS).

[0084] The processor 110 may enable the terminal device to implement one or more functions and meet the needs of the user by calling one or more computer programs and / or data stored in the internal memory 121. For example, the processor 110 may enable the terminal device to execute the dead loop detection method provided in the embodiment of the present application by calling the instructions and data stored in the internal memory 121.

[0085] The external memory interface 122 can be used to connect an external memory card (e.g., a Micro SD card) to expand the storage capacity of the terminal device. The external memory interface 122 can also be used to connect a hard disk, an optical disk, a USB flash drive, etc. The external memory card communicates with the processor 110 through the external memory interface 122 to implement a data storage function. For example, files such as images, music, videos, application installation packages, and application source codes are stored in an external memory card. In some embodiments, a cache area can also be set in the processor 110 to store instructions and / or data that the processor 110 needs to use cyclically. If the processor 110 needs to use the instruction or data again, it can be directly called from the cache area, thereby helping to avoid repeated accesses and reduce the waiting time of the processor 110, thereby helping to improve the efficiency of the system. For example, the cache area can be implemented by a cache memory.

[0086] Optionally, the processor 110 may obtain data to be processed or instructions to be executed from the internal memory 121 or from the external memory through the external memory interface 122. After the processor 110 obtains the data to be processed or the instructions to be executed, it may first store the data to be processed or the instructions to be executed in the cache area.

[0087] Antenna A and antenna B are used to transmit and receive electromagnetic wave signals. Each antenna in the terminal device can be used to cover a single or multiple communication frequency bands. Different antennas can also be reused to improve the utilization of the antennas. For example, antenna A can be reused as a diversity antenna for a wireless local area network. In some other embodiments, the antenna can be used in combination with a tuning switch.

[0088] The mobile communication module 131 can be used to realize the communication between the terminal device and the network device according to the mobile communication technology (such as 2G, 3G, 4G or 5G, etc.) supported by the terminal device. For example, the mobile communication technology supported by the terminal device may include at least one of the global system for mobile communication (GSM), general packet radio service (GPRS), code division multiple access (CDMA), wideband code division multiple access (WCDMA), time division-synchronous code division multiple access (TD-SCDMA), long term evolution (LTE), or new radio (NR). For example, the terminal device supports GSM, and when the terminal device accesses the network through the cell provided by the base transceiver station (BTS) in the GSM communication system, the network signal strength of the accessed cell is not less than the decision threshold, that is, when the terminal device is in the network station state, the mobile communication module 131 can be used to realize the communication between the terminal device and the BTS. For example, the mobile communication module 131 can amplify the signal modulated by the modem and send it to the network device via the antenna A; the mobile communication module 131 can also receive the signal sent by the network device through the antenna A, amplify it, and then send it to the modem, and the modem demodulates the received signal into a low-frequency baseband signal, and then performs other corresponding processing. In some embodiments, the mobile communication module 131 may include a filter, a switch, a power amplifier, a low noise amplifier (LNA), etc.

[0089] The wireless communication module 132 can provide wireless communication solutions including wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) network), bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), infrared (IR), etc., which are applied to the terminal device. The GNSS may include at least one of the global positioning system (GPS), global navigation satellite system (GLONASS), Beidou navigation satellite system (BDS), quasi-zenith satellite system (QZSS) and / or satellite-based augmentation systems (SBAS). For example, the wireless communication module 132 can be one or more devices integrating at least one communication processing module. Among them, the wireless communication module 132 can communicate with the corresponding device through the antenna B according to the wireless communication technology (such as Wi-Fi, Bluetooth, FM or NFC, etc.) supported by itself.

[0090] The terminal device can implement audio functions such as music playing and recording through the audio module 140, the speaker 140A, the receiver 140B, the microphone 140C, the earphone interface 140D and the AP.

[0091] The terminal device can realize the display function through the GPU, the display screen 151, and the AP. The display screen 151 can be used to display images, videos, etc. The display screen 151 may include a display panel. The display panel may be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light emitting diode or an active-matrix organic light emitting diode (AMOLED), a flexible light-emitting diode (FLED), Miniled, MicroLed, Micro-oLed, a quantum dot light emitting diode (QLED), etc. In some embodiments, the terminal device may include 1 or N display screens 151, where N is a positive integer greater than 1.

[0092] The key 154 may include a power key, a volume key, etc. The key 154 may be a mechanical key, or a virtual button or a virtual option, etc. The terminal device may receive key input and generate key signal input related to user settings and function control of the terminal device. For example, in response to selecting a virtual option for indicating consent to participate in the "User Experience Improvement Program", the terminal device may count or collect some information about the user's use of the terminal device to provide the user with more personalized services, thereby improving the user experience.

[0093] The sensor module 160 may include one or more sensors. For example, the sensor module 160 includes an acceleration sensor 160A, a touch sensor 160B, a fingerprint sensor 160C, etc. In some embodiments, the sensor module 160 may also include a pressure sensor, a gyroscope sensor, an environmental sensor, a distance sensor, a proximity light sensor, a bone conduction sensor, etc.

[0094] The acceleration sensor (ACC sensor) 160A can collect the magnitude of the acceleration of the terminal device in all directions (generally three axes). When the terminal device is stationary, the magnitude and direction of gravity can be detected. In addition, the acceleration sensor 160A can also be used to identify the posture of the terminal device, and is applied to applications such as horizontal and vertical screen switching and pedometers. In some embodiments, the acceleration sensor 160A can be connected to the processor 110 through a micro controller unit (MCU), thereby helping to save power consumption of the terminal device. For example, the acceleration sensor 160A can be connected to the AP and modem through the MCU. In some embodiments, the MCU can be a universal intelligent sensor hub (sensorhub).

[0095] The touch sensor 160B may also be referred to as a "touch panel". The touch sensor 160B may be disposed on the display screen 151, and the touch sensor 160B and the display screen 151 form a touch screen, also referred to as a "touch screen". The touch sensor 160B is used to detect touch operations acting on or near it. The touch sensor 160B may transmit the detected touch operation to the AP to determine the type of touch event. Then, the terminal device provides visual output related to the touch operation through the display screen 151 according to the determined type of touch event. In other embodiments, the touch sensor 160B may also be disposed on the surface of the terminal device, which is different from the position where the display screen 151 is located.

[0096] The fingerprint sensor 160C is used to collect fingerprints. The terminal device can use the collected fingerprint characteristics to achieve fingerprint unlocking, access application locks, fingerprint photography, fingerprint answering calls, etc.

[0097] In other embodiments, the processor 110 may further include one or more interfaces. For example, the interface may be a SIM card interface 152. For another example, the interface may also be a USB interface 170. For another example, the interface may also be an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, etc. It is understandable that the processor 110 of the embodiment of the present application can connect different modules of the terminal device through an interface, so that the terminal device can realize different functions. For example, searching the Internet, taking pictures, etc. It should be noted that the embodiment of the present application does not limit the connection method of the interface in the terminal device.

[0098] The SIM card interface 152 is used to connect a SIM card. The SIM card can be connected to and separated from the terminal device by inserting it into the SIM card interface 152 or pulling it out from the SIM card interface 152. The terminal device can support 1 or N SIM card interfaces, where N is a positive integer greater than 1. The SIM card interface 152 can support Nano SIM cards, Micro SIM cards, SIM cards, and the like. Multiple cards can be inserted into the same SIM card interface 152 at the same time. The types of the multiple cards can be the same or different. The SIM card interface 152 can also be compatible with different types of SIM cards. In some embodiments, the SIM card interface 152 can also be compatible with external memory cards. The terminal device uses a SIM card to implement functions such as calls and data communications. In some embodiments, the terminal device can also use an eSIM, i.e., an embedded SIM card. The eSIM card can be embedded in the terminal device and cannot be separated from the terminal device.

[0099] The USB interface 170 is an interface that complies with the USB standard specification, and specifically can be a Mini USB interface, a Micro USB interface, a USB Type C interface, etc. The USB interface 170 can be used to connect a charger to charge the terminal device, and can also be used to transfer data between the terminal device and peripheral devices. It can also be used to connect headphones to play audio through the headphones. The interface can also be used to connect other electronic devices, such as AR devices, etc.

[0100] It is understandable that the interface connection relationship between the modules illustrated in the embodiment of the present invention is only a schematic illustration and does not constitute a structural limitation on the terminal device. In other embodiments of the present application, the terminal device may also adopt different interface connection methods in the above embodiments, or a combination of multiple interface connection methods.

[0101] The charging management module 180 is used to receive charging input from a charger. The charger can be a wireless charger or a wired charger. The power management module 181 is used to connect the battery 182, the charging management module 180 and the processor 110. The power management module 181 receives input from the battery 182 and / or the charging management module 180 to power the processor 110 and other modules. In some embodiments, the power management module 181 can also be used to monitor parameters such as battery capacity, battery cycle number, battery health status (leakage, impedance), etc.

[0102] It should be understood that Figure 1 The structure of the terminal device shown is only an example. The computing device of the embodiment of the present application may have more or fewer components than those shown in the figure, may combine two or more components, or may have different component configurations. The various components shown in the figure may be implemented in hardware, software, or a combination of hardware and software including one or more signal processing and / or application specific integrated circuits.

[0103] It should be noted that the data processing method provided in the embodiment of the present application can be applied to Figure 1 The terminal devices shown, such as mobile phones, tablets, computers, etc., can be specifically implemented by referring to the following method embodiments, which will not be repeated here.

[0104] It should be noted that the solutions in the embodiments of the present application can also be applied to other computing devices, and the corresponding names can also be replaced by the names of corresponding functions in other computing devices. Figure 1 This is a simplified schematic diagram for ease of understanding only. The terminal device may also include other modules and / or other components. Figure 1 Not drawn in.

[0105] It is easy to understand that the solutions in the embodiments of the present application can be applied to computing devices, such as mobile phones, tablets (PADs), personal computers, and servers. They can also be chips (systems) or other parts or components that can be set in computing devices, such as processors. They can also be computing device clusters that include computing devices, such as server clusters. The present application does not limit this.

[0106] The following will be combined Figure 2-Figure 13 The data processing method provided in the embodiment of the present application is specifically described.

[0107] For example, Figure 2 Schematic diagram of the data processing method provided in the embodiment of the present application Figure 1 The data processing method can be applied to Figure 1 The terminal device shown.

[0108] like Figure 2 As shown, the data processing method includes the following steps:

[0109] S201, determining I seed programs called by N parent programs.

[0110] Wherein, N>I, N and I are positive integers greater than 1.

[0111] Exemplarily, a parent program is a code set that can implement a certain function. When the program is executed, it will call other programs. Each parent program is executed by a thread, and N parent programs are the same parent programs executed by N threads. Exemplarily, the same parent program can be a program corresponding to the same code set.

[0112] Exemplarily, a subprogram is a program called by a parent program. The code of the same subprogram is the same, but the subprograms in the same subprogram called by different parent programs process different data.

[0113] For example, in ray tracing, the type of the subprogram called by each parent program can be determined based on the intersection test result corresponding to the parent program. The type of the subprogram called by the parent program can also be determined based on other data corresponding to each parent program.

[0114] Figure 3 Schematic diagram of data flow between parent program and child program Figure 1 .like Figure 3 As shown, the same parent program may call different types of subprograms, and data can be transferred between the parent program and the subprogram called by the parent program through a data packet, that is, the parent program and the subprogram called by the parent program can read and write data in the same data packet. Exemplarily, the data packet may include data stored in a specific storage area.

[0115] Figure 4 Schematic diagram of data flow between parent program and child program Figure 2 .like Figure 4As shown, in ray tracing, the parent program can be a program for determining the light generated by a light source, such as a ray generation parent shader program. The subprograms that the parent program may call include sub-shading programs A and B, and the data packet corresponding to the ray generation parent shader program is a ray data packet. The ray generation parent shader program can determine which subprogram to be called based on the result of the intersection test between the corresponding ray and the object in the image area corresponding to the parent program. If the ray intersects with the object in the image area corresponding to the parent program, the sub-shading program A can be called, and if the ray does not intersect with the object in the image area corresponding to the parent program, the sub-shading program B can be called. Exemplarily, the result of the intersection test between the ray and the object can be obtained according to the intersection test result after executing the intersection test instruction (traceRay). Among them, the function of the intersection test can be implemented by the parent program, or by other programs other than the parent program.

[0116] It should be noted that the threads in the embodiments of the present application may be one-dimensional threads. For example, threads identified as 0, 1, 2, or 3. The threads in the embodiments may also be two-dimensional or multi-dimensional threads. For example, threads identified as arrays such as (0, 0), (1, 0), (0, 1), or (1, 1).

[0117] S202, obtaining the execution count L of the i-th seed program in the I seed programs i .

[0118] in, L i Is a positive integer.

[0119] Exemplarily, the number of executions is the number of times each subroutine will be executed.

[0120] For example, That is, the number of parent programs is equal to the sum of the execution times of all child programs.

[0121] Optionally, the number of executions may be determined according to the number of parent programs that call the i-th subprogram.

[0122] As shown in Table 1, the threads corresponding to thread group 0 are thread 0-thread 3, the threads corresponding to thread group 1 are thread 4-thread 7, and the threads corresponding to thread group 2 are thread 8-thread 11. The parent program of 8 threads, thread 0-thread 4, thread 6, thread 8, and thread 10, calls subprogram 0, and the number of executions of subprogram 0 is 8. The parent program of 4 threads, thread 5, thread 7, thread 9, and thread 11, calls subprogram 1, and the number of executions of subprogram 1 is 4.

[0123] Table 1

[0124]

[0125] In this way, by determining the execution times of the i-th subprogram according to the number of parent programs that call the i-th subprogram, the obtained execution times can be made more accurate, and then the thread group set of each subprogram can be accurately determined, reducing the number of idle threads in each instruction cycle, and further improving resource utilization and data processing efficiency.

[0126] S203, according to the execution times of various subroutines, determine J instruction cycles and K in the jth instruction cycle j A collection of thread groups.

[0127] in, J.K j is a positive integer. A thread group set includes one or more thread groups. The types of subroutines executed by all thread group sets in J instruction cycles are different. In each thread group set, the number of threads that have not executed subroutines is less than the number of threads in a thread group.

[0128] For example, an instruction cycle may be the length of time taken to execute a subroutine.

[0129] Exemplarily, the thread group set is the sum of all thread groups used to execute a subroutine in each instruction cycle.

[0130] It should be noted that a thread group set may include one thread group or multiple thread groups.

[0131] For example, It means that the total number of thread group sets in all instruction cycles is the same as the number of subroutine types.

[0132] Exemplarily, the types of subroutines executed by all thread group sets in J instruction cycles are different, that is, each thread group set in each cycle executes a subroutine. For example, there are three instruction cycles in the multiple instruction cycles: instruction cycle T1-instruction cycle T3. Instruction cycle T1 includes thread group set 0 and thread group set 1, instruction cycle T2 includes thread group set 2 and thread group set 3, and instruction cycle T3 includes thread group set 4. Thread group set 0, thread group set 1, thread group set 2, thread group set 3, and thread group set 4 each execute a different subroutine. Figure 5 The following is a schematic diagram of the corresponding relationship between thread group sets and subroutines. Figure 5 As shown, thread group set 0 executes subroutine 0, thread group set 1 executes subroutine 1, thread group set 2 executes subroutine 2, thread group set 3 executes subroutine 3, and thread group set 4 executes subroutine 4.

[0133] Exemplarily, in each thread group set, the number of threads that have not executed a subroutine is less than the number of threads in a thread group, that is, in each instruction cycle, each thread group has at least one thread for executing a subroutine.

[0134] In one possible design, the number of J instruction cycles and the number of K in the jth instruction cycle are determined based on the number of executions of various subroutines. j The thread group set may include: determining the thread group set corresponding to the i-th seed program and the instruction cycle corresponding to the thread group set corresponding to the i-th seed program according to the number of executions.

[0135] The determined instruction cycle may be multiple. Figure 5 Taking subprogram 0 to subprogram 4 as an example, the thread groups executing the parent program include thread group W0 to thread group W11. There are 2 thread groups in the thread group set corresponding to subprogram 0, 3 thread groups in the thread group set corresponding to subprogram 1, 2 thread groups in the thread group set corresponding to subprogram 2, 2 thread groups in the thread group set corresponding to subprogram 3, and 3 thread groups in the thread group set corresponding to subprogram 4. Figure 6 It is a diagram showing the relationship between thread group sets and thread groups. Figure 1 .like Figure 6 As shown, if five thread groups are used to execute threads in instruction cycle T1, thread group set 0 including thread groups W0 and W1 and thread group set 1 including thread groups W2-W4 may be determined in instruction cycle T1. Thread group set 2 including thread group W0 and thread group W1 and thread group set 3 including thread group W2 and thread group W3 may be determined in instruction cycle T2. Thread group set 4 including thread group W0-W2 may be determined in instruction cycle T3.

[0136] Figure 7 This is a diagram showing the relationship between thread group sets and subroutines. Figure 2 .like Figure 7 As shown, Figure 6 Thread group set 0 can execute subroutine 0, thread group set 1 can execute subroutine 1, thread group set 2 can execute subroutine 2, thread group set 3 can execute subroutine 3, and thread group set 4 can execute subroutine 4.

[0137] It can be understood that in this embodiment, the number of instruction cycles determined can be 1, in other words, all subroutines can be executed in the same instruction cycle. Figure 5 For example, subroutine 0 to subroutine 4 in the example, subroutine 0 to subroutine 4 can be executed in instruction cycle T1. Figure 8 illustrate.

[0138] Figure 8Schematic diagram of the relationship between thread group set and sub-thread group Figure 2 .like Figure 8 As shown, thread group set 0 corresponding to subprogram 0 may include thread group W0 and thread group W1; thread group set 1 corresponding to subprogram 1 may include thread group W2-thread group W4. Thread group set 2 corresponding to subprogram 2 may include thread group W5 and thread group W6; thread group set 3 corresponding to subprogram 3 may include thread group W7 and thread group W8; thread group set 4 corresponding to subprogram 4 may include thread group W9-thread group W11.

[0139] It should be noted that Figure 5-Figure 8 The example is only used to help understand this embodiment. The numbers of the thread groups corresponding to each subroutine may be discontinuous, and the thread groups included in the thread group set corresponding to each subroutine may also be other thread groups. For example, the thread group set corresponding to subroutine 1 may include thread group W9-thread group W11, or the thread group set corresponding to subroutine 1 may include thread group W0, thread group W3 and thread group W6, etc. The number of thread groups in the thread group set is not limited in this embodiment. When multiple instruction cycles are included, the thread group set corresponding to each subroutine can be in any cycle.

[0140] Optionally, determining the thread group set corresponding to the i-th seed program and the instruction cycle in which the thread group set corresponding to the i-th seed program is located according to the number of executions may include step 1 and step 2.

[0141] Step 1, determine the first order of I seed programs according to the number of executions.

[0142] The first order is used to indicate the order of obtaining the thread group sets corresponding to each subroutine.

[0143] In this embodiment, before the above step 1, the data processing method may further include: obtaining the second order of each subprogram. Specifically, the second order may be obtained according to the attribute information corresponding to the parent program that calls each subprogram. The attribute information may include a material identifier, and the material identifier may be an integer data.

[0144] Taking the subprograms in Table 2 as an example, for threads 0-thread 2, thread 4, thread 6-thread 8 and thread 10 that are called by the parent program for subprogram 0, the threads are sorted according to the attribute information of each thread, thereby obtaining the second order of subprogram 0 called by the parent program of threads 0-thread 2, thread 4, thread 6-thread 8 and thread 10. For threads 3, thread 5, thread 9 and thread 11 that are called by the parent program for subprogram 1, the threads are sorted according to the attribute information of each thread, thereby obtaining the second order of threads 3, thread 5, thread 9 and thread 11.

[0145] Table 2

[0146]

[0147] For example, the attribute information includes material 1, material 2, material 3, and material 4. The priorities of material 1, material 2, material 3, and material 4 are respectively: material 4, material 3, material 2, and material 1. The materials corresponding to thread 3, thread 5, thread 9, and thread 11 are material 1, material 2, material 3, and material 4, respectively. Then, the sorting results of the subroutines corresponding to thread 3, thread 5, thread 9, and thread 11 are: thread 11, thread 9, thread 5, and thread 3. The acquisition method of the second sequence of subroutine 0 is similar to that of subroutine 1, which will not be repeated here.

[0148] Step 2: Determine the thread group set corresponding to the i-th subprogram and the instruction cycle corresponding to the thread group set corresponding to the i-th subprogram according to the first order.

[0149] Still taking the threads and subroutines in Table 2 as an example, in thread group 0-thread group 2, the subroutines called by the parent programs of thread 0-thread 11 are: subroutines 0, subroutines 0, subroutines 0, subroutines 1, subroutines 0, subroutines 1, subroutines 0, subroutines 0, subroutines 1, subroutines 0, and subroutines 1. The number of executions of subroutines 0 is 8, and the number of executions of subroutines 1 is 4. Therefore, it can be determined that the first order is subroutines 0, subroutines 0, subroutines 0, subroutines 0, subroutines 0, subroutines 0, subroutines 1, subroutines 1, subroutines 1, and subroutines 1. The thread group set corresponding to subroutines 0 includes thread group 0 and thread group 1, and the thread group set corresponding to subroutines 0 includes thread group 2.

[0150] It should be noted that when each thread executes each subroutine, it can obtain the data for executing the subroutine, such as a data packet or a ray data packet in ray tracing, based on the thread where the parent program that calls the subroutine is located. The subroutine actually executed by each thread may be a subroutine called by the parent program in any thread in the thread group. For example, the subroutine executed by a thread may be a subroutine called by the parent program in the thread, or it may be a subroutine called by the parent program in other threads. In other words, when a thread executes a subroutine, it may execute the subroutine based on the data corresponding to the thread itself, or it may execute the subroutine based on the data corresponding to other threads. Specifically, data can be obtained based on the identifier of the thread where the parent program that calls the subroutine is located.

[0151] The following still combines Table 2 to illustrate how each thread obtains the data required for the thread to execute the subroutine. For example, in ray tracing, the thread group can obtain a light data packet according to the subroutine that the thread needs to execute. Thread 0 can obtain the light data packet corresponding to thread 0, thread 1 obtains the light data packet corresponding to thread 1, thread 2 obtains the light data packet corresponding to thread 2, thread 3 obtains the light data packet corresponding to thread 4, thread 4 obtains the light data packet of thread 6, thread 5 obtains the light data packet corresponding to thread 7, thread 6 obtains the light data packet corresponding to thread 8, thread 7 obtains the light data packet corresponding to thread 10, thread 8 obtains the light data packet corresponding to thread 3, thread 9 obtains the light data packet corresponding to thread 5, thread 10 obtains the light data packet corresponding to thread 9, and thread 11 obtains the light data packet corresponding to thread 11.

[0152] In the embodiment of the present application, obtaining data according to the identifier of the thread can avoid sorting operations on the data required for executing the subroutine, thereby improving efficiency.

[0153] In this way, the thread group set corresponding to the subroutine with a higher order can be determined preferentially, thereby further improving resource utilization.

[0154] It should be noted that the first order can be obtained by a sorting module, which can be a software function module, such as a shader program in ray tracing, or a hardware structure, or a module combining software and hardware. Still taking ray tracing as an example to illustrate the working process of the sorting module, Figure 4 As shown, when obtaining the first sequence, the sorting module obtains the subroutine identifier, or the subroutine identifier and attribute information from the data buffer, and obtains the first sequence. After obtaining the first sequence, the sorting module stores the first sequence in the data buffer.

[0155] It should be noted that the sorting module can obtain the subprogram identifier from the parent program, wherein the subprogram identifier is information identifying the type of the subprogram, and then obtain the first order according to the subprogram identifier. The sorting module can also be used to create a new task. Fig. 9 illustrate.

[0156] Fig. 9 This is a diagram showing the relationship between the parent program and the child program. Figure 3 .like Fig. 9 As shown, in ray tracing, after the ray generation shader program obtains the subroutine identifier, the subroutine identifier is transmitted to the sorting module. The sorting module counts the execution times of each subroutine and creates a new task according to the execution times of each subroutine.

[0157] Furthermore, the first order may indicate that the thread group set corresponding to the subroutine with a large number of execution times is obtained first.

[0158] Still taking the subroutines and threads in Table 2 as an example, as shown in Table 3, if in each instruction cycle, the number of thread groups used to execute the subroutines is at most 2, then the thread group set corresponding to subroutines 0 can be obtained as thread group 0 and thread group 1 in instruction cycle T1, and the thread set corresponding to subroutines 1 is thread group 1 in instruction cycle T2. It is easy to understand that in instruction cycle T1, the threads in thread group 2 did not execute the subroutines, so the resources occupied by the threads in thread group 2 can be released. In instruction cycle T2, the threads in thread group 1 did not execute the subroutines, so the resources occupied by the threads in thread group 1 can be released.

[0159] Table 3

[0160]

[0161]

[0162] In this way, the thread group set corresponding to the subroutine with a large number of execution times is preferentially determined, so that the subroutine with a large number of threads can be executed in an earlier instruction cycle, and the resources occupied by the idle thread group can be released, thereby further improving resource utilization.

[0163] Or, further, the first order may also indicate that the thread group set corresponding to the subroutine with a small number of execution times is obtained first.

[0164] The implementation of preferentially obtaining the thread group set corresponding to the subprogram with fewer execution times is similar to the implementation of preferentially obtaining the thread group set corresponding to the subprogram with more execution times, which will not be described in detail here.

[0165] In this way, by determining the thread group set and instruction cycle corresponding to the seed program based on the number of executions of each subroutine, the number of thread groups executing the same seed program can be reduced, and / or the number of instruction cycles required for all subroutines can be reduced, so as to further improve resource utilization and data processing efficiency.

[0166] Or, optionally, determining the thread group set corresponding to the i-th seed program and the instruction cycle in which the thread group set corresponding to the i-th seed program is located based on the number of executions may include: determining the thread group set corresponding to the i-th seed program and the instruction cycle in which the thread group set is located based on the number of executions of each of the I seed programs.

[0167] The following is an example to illustrate how to determine the thread group set corresponding to the i-th seed program and the instruction cycle in which the thread group set is located according to the execution times of each of the I seed programs.

[0168] For example, there are 4 threads in a thread group, and the parent program is executed by threads in 5 thread groups respectively, among which subprogram 0 is executed 7 times, subprogram 1 is executed 5 times, subprogram 2 is executed 3 times, subprogram 3 is executed 4 times, and subprogram 4 is executed 1 times. It can be obtained that the thread group set corresponding to subprogram 0 includes two thread groups, the thread group set corresponding to subprogram 1 includes two thread groups, the thread group set corresponding to subprogram 2 includes one thread group, the thread group set corresponding to subprogram 3 includes one thread group, and the thread group set corresponding to subprogram 4 includes one thread group. The following is combined with Fig.10 To illustrate how to determine Fig. 9 The instruction cycle of the thread group set corresponding to the neutron program.

[0169] Fig.10 Schematic diagram of the correspondence between subroutines and thread groups Figure 3 .like Fig.10 As shown, a total of three thread groups, thread group W0-thread group W3, are used to execute subroutines. In instruction cycle T1, the thread group set of subroutine 0 is obtained, including thread group W0 and thread group W1. At this time, in instruction cycle T1, thread group W2 is still left, so the remaining thread group W2 can be used as a subroutine with an execution time less than 4, such as the thread group set of subroutine 2. In instruction cycle T2, the thread group set corresponding to subroutine 1 can be obtained, including thread group W0 and thread group W1, and the remaining thread group W2 can be used as the thread group set corresponding to subroutine 3, such as thread group W0. In instruction cycle T3, the thread group set corresponding to subroutine 4 can be obtained as any one of thread groups W0-thread group W2. In this way, in instruction cycle T1 and instruction cycle T2, only three thread groups are needed, so the resources occupied by the remaining thread groups can be released. In instruction cycle T3, only one thread group is needed, so the resources occupied by the remaining thread groups can be released. In this way, the resources occupied by thread groups W0 to W3 can be released in the instruction cycle T1, thereby improving resource utilization.

[0170] like Fig.11 As shown, in each instruction cycle, there are 7 thread groups that can be used to execute subroutines, so the thread group sets corresponding to subroutines 0-4 can all be in instruction cycle T1. Specifically, the thread group set corresponding to subroutine 0 can include thread group W0 and thread group W1, the thread group set corresponding to subroutine 1 can include thread group W3 and thread group W4, the thread group set corresponding to subroutine 2 can include thread group W2, the thread group set corresponding to subroutine 3 can include thread group W5, and the thread group set corresponding to subroutine 4 can include thread group W6. In this way, after instruction cycle T1, all subroutines will be executed, so the resources occupied by all thread groups can be released.

[0171] It is understandable that, in this embodiment, the number of thread groups used to execute the subroutine in each instruction cycle may be the same or different.

[0172] It should be noted that, in the embodiment of the present application, each subroutine identifier, or a subroutine identifier and attribute information can be stored in a data buffer. Figure 4 As shown, in ray tracing, the ray generation shader program obtains a subroutine identifier, or a subroutine identifier and attribute information, and stores it in a data buffer. The first order is obtained according to the subroutine identifier, or the subroutine identifier and attribute information in the data buffer. The second order is obtained according to the attribute information.

[0173] Optionally, the number of thread groups in the thread group set corresponding to the i-th seed program, the number of threads in a thread group, and the number of execution times corresponding to the i-th seed program may satisfy one or more of the following conditions:

[0174] or,

[0175] (W i -1)*m≤L i ≤W i *m.

[0176] Among them, W i is the number of thread groups in the thread group set corresponding to the i-th seed program, W i is a positive integer. m is the number of threads in a thread group.

[0177] That is, the number of threads in the thread group set corresponding to each subroutine is the number of times the subroutine is executed divided by the number of threads in a thread group, rounded up. For example, if the number of threads in a thread group is 4 and the number of times the i-th subroutine is executed is 9, then the thread group set W corresponding to the subroutine is i for:

[0178]

[0179] (W i -1)*m≤L i ≤W i *m, that is, the number of threads contained in the thread group set corresponding to each subroutine is between the sum of the number of threads in n thread groups and the sum of the number of threads in n+1 thread groups. Assuming that the number of threads in a thread group is 4 and the number of executions of the i-th subroutine is 9, the calculation formula for the number of thread groups in the thread group set corresponding to the i-th subroutine is:

[0180] (W i -1)*4≤9,

[0181] 9≤W i *4,

[0182] Thus, the number of thread groups W in the thread group set corresponding to the i-th subroutine is obtained. i is 3.

[0183] In this way, the same subprogram is executed using as few thread groups as possible, thereby further improving resource utilization.

[0184] In a possible design, the number of thread groups in the set of all thread groups in the j-th instruction cycle is greater than or equal to the number of thread groups in the set of all thread groups in the j+1-th instruction cycle.

[0185] Still Figure 6 Taking the subroutine and thread group set as an example, in instruction cycle T1, the total number of thread groups in all thread group sets is 5; in instruction cycle T2, the total number of thread groups in all thread group sets is 4; in instruction cycle T3, the total number of thread groups in all thread group sets is 3.

[0186] In this way, the total number of thread groups used to execute subroutines in each instruction cycle remains unchanged or gradually decreases, thereby avoiding the situation where the entire thread group is idle, and further improving resource utilization.

[0187] The embodiments of the present application are further described below with reference to specific examples.

[0188] For example, the thread groups that execute a certain parallel computing task are thread group 0-thread group 2, the threads of thread group 0 include thread 0-thread 3, the threads of thread group 1 include thread 4-thread 7, and the threads of thread group 2 include thread 8-thread 11. Each thread executes a parent program, each parent program calls a subprogram, and the subprogram called by each parent program may be subprogram 0, subprogram 1 or subprogram 2. The parent programs corresponding to threads 0-thread 11 are parent program 0-parent program 11 respectively.

[0189] As shown in Table 4 below, thread 0, thread 2, thread 6 and thread 8 execute subroutine 0, thread 3, thread 5, thread 9 and thread 11 execute subroutine 1; thread 1, thread 4, thread 7 and thread 10 execute subroutine 2. Based on the ray intersection test results, each thread executes the subroutine called by its parent program, then thread 0, thread 2, thread 6 and thread 8 execute subroutine 0, thread 3, thread 5, thread 9 and thread 11 execute subroutine 1; thread 1, thread 4, thread 7 and thread 10 execute subroutine 2. The threads in thread group 0 need to execute subroutine 0-subroutine 2, the threads in thread group 1 need to execute subroutine 0-subroutine 2, and the threads in thread group 2 need to execute subroutine 0-subroutine 2. It can be understood that each thread group has threads executing subroutines in instruction cycle T1-instruction cycle T3, and each thread group has idle threads in instruction cycle T1-instruction cycle T3. All subroutines called by the parent program in thread group 1-thread group 2 are executed, which requires a total of 3 instruction cycles.

[0190] Table 4

[0191]

[0192] Still taking the thread groups and subroutines in Table 4 as an example, as shown in Table 5, after adopting the solution described in the embodiment of the present application, the threads of thread group 0 execute subroutine 0, the threads of thread group 1 execute subroutine 1, and the threads of thread group 2 execute subroutine 2. It is not difficult to see that all subroutines can be executed in just one instruction cycle. Compared with the solution in Table 4, each thread group can be released two instruction cycles in advance.

[0193] It is understandable that the subroutines described in Table 4 above can also be executed in two instruction cycles. As shown in Table 6, thread group 0 can execute subroutine 0 in instruction cycle T1, thread group 2 can execute subroutine 1 in instruction cycle T1, and thread group 0 can execute subroutine 4 in instruction cycle T2. In this way, the resources occupied by thread group 2 can be released in instruction cycle T1, and the resources occupied by thread group 1 can be further released in instruction cycle T2.

[0194] Table 5

[0195]

[0196] It is understandable that the subroutines in Table 4 can also be executed in three different instruction cycles. As shown in Table 7, the threads of thread group 0 execute subroutine 0 in instruction cycle T1; the threads of thread group 0 execute subroutine 1 in instruction cycle T2; and the threads of thread group 0 execute subroutine 2 in instruction cycle T3. In this way, the resources occupied by thread group 1 and thread group 2 can be released before the start of instruction cycle T1.

[0197] Table 6

[0198]

[0199] Table 7

[0200]

[0201] For another example, thread group 0 includes thread 0-thread 3, and thread group 1 includes thread 4-thread 7. The parent program of thread 0 calls subprogram 1, the parent program of thread 1 calls subprogram 0, the parent program of thread 2 calls subprogram 2, the parent program of thread 3 calls subprogram 2, the parent program of thread 4 calls subprogram 2, the parent program of thread 5 calls subprogram 1, the parent program of thread 6 calls subprogram 0, and the parent program of thread 7 calls subprogram 1. The following is explained in conjunction with Table 8. As shown in Table 8, the thread that executes the subprogram is determined according to the subprogram status. When the state of the parent program is 0, subprogram 0 is called, when the state of the parent program is 1, subprogram 1 is called, and when the state of the parent program is 2, subprogram 2 is called. Since the same thread group can only execute the same subprogram at the same time, it takes a total of three instruction cycles for the thread group in Table 8 to complete execution.

[0202] Table 8

[0203]

[0204] Still taking the threads and subroutines in Table 8 as an example, the execution times of subroutine 0 is 3, the execution times of subroutine 1 is 3, and the execution times of subroutine 2 is 3. If the same subroutine is assigned to the same thread group for execution, the execution status of each subroutine is shown in Table 9. Subroutine 0 is executed in instruction cycle T1, subroutine 1 is executed in instruction cycle T2, and subroutine 2 is executed in instruction cycle T3. It is not difficult to see that in Table 8, each thread group executes a subroutine in each instruction cycle, while in Table 9, only the threads of thread group 0 execute subroutines in instruction cycle T1-instruction cycle T3. In instruction cycle T1-instruction cycle T3, the resources occupied by thread group 1 are released, thereby improving resource utilization.

[0205] Table 9

[0206]

[0207] It should be noted that, in the embodiment of the present application, the thread that executes the subroutine may be a newly started thread. The newly started thread may be executed as follows: Fig. 9 Create a new task implementation in the sorting module.

[0208] For example, a newly created thread is a thread that only executes a subprogram but not a parent program. For example, if the threads that execute the parent program are threads 0' to 7', and the subprogram called by threads 0' to 3' is subprogram 0, and the subprogram called by threads 4' to 7' is subprogram 1, then threads 1, 2, 3, and 4 can be newly created to execute subprogram 0 and subprogram 1.

[0209] Specifically, the newly created thread can be determined according to the number of executions of each subroutine or the start-up time of the counter corresponding to each subroutine. For example, when the number of executions of a subroutine is greater than a number threshold, or when the start-up time of the counter corresponding to a subroutine exceeds a time threshold, a new task can be created according to the counting result of the counter corresponding to the subroutine to start a new thread. In this way, system deadlock can be prevented.

[0210] Specifically, a table including various subroutine identifiers can be stored in the memory of the graphics processor. Each subroutine corresponds to a counter. When the parent program outputs an identifier of a subroutine to be called, the counter corresponding to the subroutine is incremented by 1, so that the execution times of each subroutine can be obtained.

[0211] In this way, after the parent program is executed, the resources occupied by the thread where the parent program is located can be released, thereby improving resource utilization.

[0212] As shown in Table 10, thread group 0 includes threads 0 to 3, and thread group 1 includes threads 4 to 7.

[0213] Table 10

[0214]

[0215] The parent program of thread 0 calls subprogram 0, the parent program of thread 1 calls subprogram 1, the parent program of thread 2 calls subprogram 0, the parent program of thread 3 calls subprogram 1, the parent program of thread 4 calls subprogram 0, the parent program of thread 5 calls subprogram 1, the parent program of thread 6 calls subprogram 0, and the parent program of thread 7 calls subprogram 1. There are two types of subprograms that need to be executed, so two counters can be used to obtain the execution times of each subprogram.

[0216] As shown in Table 11, counter 0 can be used to obtain the execution times of subprogram 0, and counter 1 can be used to obtain the execution times of subprogram 1, and the execution times of subprogram 0 is 4, and the execution times of subprogram 1 is 4.

[0217] Table 11

[0218] Subroutines 0 1 counter 0 1 Execution times 4 4

[0219] based on Figure 2The data processing method shown in can determine the number of instruction cycles used to execute multiple sub-programs and the number of thread group sets in each instruction cycle based on the multiple sub-programs called by multiple parent programs and the number of execution times of each sub-program, so that the same sub-program can be executed in the same instruction cycle, so as to minimize the number of required instruction cycles and / or the number of required thread groups, which can improve resource utilization and thus improve data processing efficiency.

[0220] In addition, the same seed program is executed in the same instruction cycle, avoiding the situation where threads in different thread groups frequently switch the instructions read in the same instruction cycle and threads in the same thread group frequently switch the instructions read in different instruction cycles. This can improve the hit rate of instruction fetch operations, thereby improving resource utilization and data processing efficiency.

[0221] Combination of the above Figure 3-Figure 11 The data processing method provided by the embodiment of the present application is described in detail. Figure 12-13 A data processing device for executing the data processing method provided in an embodiment of the present application is described in detail.

[0222] For example, Fig.12 The structure of the data processing device provided in the embodiment of the present application is shown in FIG. Figure 1 .like Fig.12 As shown, the data processing device 1200 includes: a determination module 1201 and an acquisition module 1202 .

[0223] For ease of explanation, Fig.12 Only the essential components of the data processing arrangement are shown.

[0224] In some embodiments, the data processing device 1200 may be adapted to Figure 1 In the terminal device shown in FIG. , execute Figure 2 The data processing method shown in .

[0225] The determination module is used to determine I seed programs called by N parent programs. N>I, N and I are positive integers greater than 1.

[0226] The acquisition module is used to obtain the execution count L of the i-th seed program in the I seed programs. i .in, L i is a positive integer. The determination module is also used to determine J instruction cycles and K in the jth instruction cycle according to the execution times of various subroutines. j A collection of thread groups. Among them, J.K jis a positive integer. A thread group set includes one or more thread groups. The types of subroutines executed by all thread group sets in J instruction cycles are different. In each thread group set, the number of threads that have not executed subroutines is less than the number of threads in a thread group.

[0227] In a possible design, the determination module is further used to determine the thread group set corresponding to the i-th seed program and the instruction cycle corresponding to the thread group set corresponding to the i-th seed program according to the number of executions.

[0228] Optionally, the number of thread groups in the thread group set corresponding to the i-th seed program, the number of threads in a thread group, and the number of execution times corresponding to the i-th seed program satisfy one or more of the following conditions:

[0229] or,

[0230] (W i -1)*m≤L i ≤W i *m.

[0231] Among them, W i is the number of thread groups in the thread group set corresponding to the i-th seed program, m is the number of threads in a thread group, and n is 0 or a positive integer.

[0232] Optionally, the determination module is further used to determine the first order of the ith subprogram according to the number of executions, and determine the thread group set corresponding to the ith subprogram and the instruction cycle corresponding to the thread group set corresponding to the ith subprogram according to the first order. The first order is used to indicate the order in which the thread group set corresponding to each subprogram is obtained.

[0233] Furthermore, the first order indicates that the thread group set corresponding to the subroutine with a large number of execution times is obtained first.

[0234] In a possible design, the number of thread groups in the set of all thread groups in the j-th instruction cycle is greater than or equal to the number of thread groups in the set of all thread groups in the j+1-th instruction cycle.

[0235] In a possible design, the number of executions may be determined according to the number of parent programs that call the i-th subprogram.

[0236] The data processing device 1200 may be a computing device, or a chip (system) or other parts or components that can be set in a computing device, or a device that includes a computing device, which is not limited in this application.

[0237] In addition, the technical effects of the data processing device 1200 can be referred to Figure 2 The technical effects of the data processing method are not described in detail here.

[0238] Optionally, the determination module and the acquisition module may also be integrated into one module, such as a processing module, wherein the processing module is used to implement the operations of the above-mentioned functional modules.

[0239] Optionally, the data processing device 1200 may further include an input / output port, wherein the input / output port is used to implement the input and / or output function of instructions and / or data of the data processing device 1200 .

[0240] Furthermore, the input and output ports may also be coupled to a transceiver. The transceiver is used for information exchange between the data processing device and other data processing devices, and the processor executes program instructions to execute Figure 2 The data processing method shown.

[0241] Optionally, the data processing device 1200 may further include a storage module ( Fig.12 ), such as an instruction cache, the storage module stores a program or instruction, and when the processing module executes the program or instruction, the data processing device can execute Figure 2 The data processing method shown.

[0242] It should be noted that the data processing device 1200 can be a computing device, or a chip (system) or other parts or components that can be set in a computing device, or a device that includes a computing device, which is not limited in this application.

[0243] In addition, the technical effects of the data processing device 1200 can be referred to in Figure 2 The technical effects of the data processing method shown in will not be repeated here.

[0244] For example, Fig.13 A schematic diagram of the structure of the data processing device provided in the embodiment of the present application Figure 2 The data processing device may be a computing device, or a chip (system) or other component or assembly that can be arranged in a computing device. Fig.13 As shown, the data processing device 1300 may include a processor 1301 .

[0245] Optionally, the data processing device 1300 may further include a memory 1302 and / or a transceiver 1303. The processor 1301 is coupled to the memory 1302 and the transceiver 1303, for example, via a communication bus.

[0246] Combine the following Fig.13 The components of the data processing device 1300 are described in detail:

[0247] The processor 1301 is the control center of the data processing device 1300, and may be a processor or a general term for multiple processing elements. For example, the processor 1301 is one or more central processing units (CPUs), or may be an application specific integrated circuit (ASIC), or may be one or more integrated circuits configured to implement the embodiments of the present application, such as one or more microprocessors, or one or more field programmable gate arrays (FPGAs).

[0248] Optionally, the processor 1301 may execute various functions of the data processing device 1300 by running or executing a software program stored in the memory 1302 , and calling data stored in the memory 1302 .

[0249] In a specific implementation, as an embodiment, the processor 1301 may include one or more CPUs, such as Fig.13 CPU0 and CPU1 are shown in FIG.

[0250] The processor 1301 may also include one or more GPUs.

[0251] In a specific implementation, as an embodiment, the data processing device 1300 may also include multiple processors, such as Fig.13 1301 and 1304 are shown in FIG. Each of these processors may be a single-CPU or a multi-CPU. A processor herein may refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions).

[0252] The memory 1302 is used to store the software program for executing the solution of the present application, and the execution is controlled by the processor 1301. The specific implementation method can refer to the above method embodiment, which will not be repeated here.

[0253] Optionally, the memory 1302 may be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 1302 may be integrated with the processor 1301, or may exist independently and access the data through the interface circuit ( Fig.13 ) is coupled to the processor 1301, which is not specifically limited in the embodiment of the present application.

[0254] The transceiver 1303 is used for communication with other data processing devices. For example, the data processing device 1300 is a terminal device, and the transceiver 1303 can be used to communicate with a network device, or with another terminal device. For another example, the data processing device 1300 is a network device, and the transceiver 1303 can be used to communicate with a terminal device, or with another network device.

[0255] Optionally, the transceiver 1303 may include a receiver and a transmitter ( Fig.13 The receiver is used to implement a receiving function, and the transmitter is used to implement a sending function.

[0256] Optionally, the transceiver 1303 may be integrated with the processor 1301, or may exist independently and communicate with the processor 1301 through the interface circuit ( Fig.13 ) is coupled to the processor 1301, which is not specifically limited in the embodiment of the present application.

[0257] It should be noted that Fig.13 The structure of the data processing device 1300 shown in the figure does not constitute a limitation on the data processing device. The actual data processing device may include more or fewer components than those shown in the figure, or combine certain components, or arrange the components differently.

[0258] In addition, the technical effects of the data processing device 1300 can refer to the technical effects of the data processing method described in the above method embodiment, which will not be repeated here.

[0259] An embodiment of the present application also provides a chip system, including: a processor, the processor is coupled to a memory, the memory is used to store programs or instructions, when the program or instructions are executed by the processor, the chip system implements the method in any of the above method embodiments.

[0260] Optionally, the processor in the chip system may be one or more. The processor may be implemented by hardware or by software. When implemented by hardware, the processor may be a logic circuit, an integrated circuit, etc. When implemented by software, the processor may be a general-purpose processor implemented by reading software code stored in a memory.

[0261] Optionally, the memory in the chip system may be one or more. The memory may be integrated with the processor or may be separately provided with the processor, which is not limited in the present application. Exemplarily, the memory may be a non-transient processor, such as a read-only memory ROM, which may be integrated with the processor on the same chip or may be provided on different chips. The present application does not specifically limit the type of memory and the arrangement of the memory and the processor.

[0262] Exemplarily, the chip system can be a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on chip (SoC), a central processor unit (CPU), a network processor (NP), a digital signal processor (DSP), a microcontroller unit (MCU), a programmable logic device (PLD) or other integrated chips.

[0263] The embodiment of the present application provides a data processing system, which includes one or more computing devices mentioned above.

[0264] It should be understood that the processor in the embodiments of the present application may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0265] It should also be understood that the memory in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0266] The above embodiments can be implemented in whole or in part by software, hardware (such as circuits), firmware or any other combination. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that contains one or more available media sets. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a tape), an optical medium (for example, a DVD), or a semiconductor medium. The semiconductor medium can be a solid-state hard disk.

[0267] It should be understood that the term "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. A and B can be singular or plural. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship, but it may also indicate an "and / or" relationship. Please refer to the context for specific understanding.

[0268] In this application, "at least one" means one or more, and "more than one" means two or more. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can be represented by: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

[0269] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0270] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0271] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0272] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0273] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0274] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0275] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium, including several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks or optical disks.

[0276] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A data processing method, characterized in that: The method comprises: Determine I seed programs called by N parent programs; N>I, N and I are positive integers greater than 1; Get the execution count L of the i-th seed program in the I seed programs i ;in, L i is a positive integer; According to the execution times of various subroutines, determine J instruction cycles and K in the jth instruction cycle j A collection of thread groups; among them, J.K j is a positive integer, a thread group set includes one or more thread groups, and the types of subroutines executed by all thread group sets in the J instruction cycles are different; in each of the thread group sets, the number of threads that have not executed a subroutine is less than the number of threads in one thread group.

2. The data processing method according to claim 1, characterized in that: The J instruction cycles and the K in the jth instruction cycle are determined according to the execution times of various subroutines. j A collection of thread groups, including: According to the execution times, a thread group set corresponding to the i-th seed program and an instruction cycle corresponding to the thread group set corresponding to the i-th seed program are determined.

3. The data processing method according to claim 2, characterized in that: The number of thread groups in the thread group set corresponding to the i-th seed program, the number of threads in a thread group, and the number of execution times corresponding to the i-th seed program satisfy one or more of the following conditions: or, (W i -1)*m≤L i ≤W i *m; Among them, W i is the number of thread groups in the thread group set corresponding to the i-th seed program, and m is the number of threads in a thread group.

4. The data processing method according to claim 2 or 3, characterized in that: The determining, according to the number of executions, a thread group set corresponding to the i-th seed program and an instruction cycle in which the thread group set corresponding to the i-th seed program is located includes: Determining a first order of the I subprograms according to the number of executions, wherein the first order is used to indicate an acquisition order of thread group sets corresponding to each subprogram; According to the first sequence, a thread group set corresponding to the i-th seed program and an instruction cycle corresponding to the thread group set corresponding to the i-th seed program are determined.

5. The data processing method according to claim 4, characterized in that: The first order indicates that the thread group set corresponding to the subroutine with a large number of execution times is obtained first.

6. The data processing method according to any one of claims 1 to 5, characterized in that: The number of thread groups in all thread group sets in the j-th instruction cycle is greater than or equal to the number of thread groups in all thread group sets in the j+1-th instruction cycle.

7. The data processing method according to any one of claims 1 to 6, characterized in that: The execution times are determined according to the number of parent programs that call the i-th subprogram.

8. A data processing device, characterized in that: The device comprises: a determination module and an acquisition module; wherein, The determination module is used to determine I seed programs called by N parent programs; N>I, N and I are positive integers greater than 1; The acquisition module is used to acquire the execution count L of the i-th seed program in the I seed programs. i ;in, L i is a positive integer; The determination module is further used to determine J instruction cycles and K in the jth instruction cycle according to the execution times of various subroutines. j A collection of thread groups; among them, J.K j is a positive integer, a thread group set includes one or more thread groups, and the types of subroutines executed by all thread group sets in the J instruction cycles are different; in each of the thread group sets, the number of threads that have not executed a subroutine is less than the number of threads in one thread group.

9. The data processing device according to claim 8, characterized in that: The determination module is further configured to determine, according to the execution times, a thread group set corresponding to the i-th seed program and an instruction cycle corresponding to the thread group set corresponding to the i-th seed program.

10. The data processing device according to claim 9, characterized in that: The number of thread groups in the thread group set corresponding to the i-th seed program, the number of threads in a thread group, and the number of execution times corresponding to the i-th seed program satisfy one or more of the following: or, (W i -1)*m≤L i ≤W i *m; Among them, W i is the number of thread groups in the thread group set corresponding to the i-th seed program, and m is the number of threads in a thread group.

11. The data processing device according to claim 9 or 10, characterized in that: The determining module is further used to determine a first order of the I subprograms according to the number of executions, wherein the first order is used to indicate an acquisition order of the thread group sets corresponding to each subprogram; The determination module is further configured to determine, according to the first sequence, a thread group set corresponding to the i-th seed program and an instruction cycle corresponding to the thread group set corresponding to the i-th seed program.

12. The data processing device according to claim 11, characterized in that: The first order indicates that the thread group set corresponding to the subroutine with a large number of execution times is obtained first.

13. The data processing device according to any one of claims 8 to 12, characterized in that: The number of thread groups in all thread group sets in the j-th instruction cycle is greater than or equal to the number of thread groups in all thread group sets in the j+1-th instruction cycle.

14. The data processing device according to any one of claims 8 to 13, characterized in that: The execution times are determined according to the number of parent programs that call the i-th subprogram.

15. A data processing device, characterized in that: The data processing device is used to execute the data processing method according to any one of claims 1 to 7.

16. A data processing device, characterized in that: The data processing device comprises: a processor; wherein, The processor is used to execute the data processing method according to any one of claims 1 to 7.

17. A data processing device, characterized in that: include: a processor coupled to the memory; The processor is used to execute the computer program stored in the memory, so that the data processing device executes the data processing method according to any one of claims 1 to 7.

18. A data processing device, characterized in that: include: processor and interface circuit; wherein, The interface circuit is used to receive code instructions and transmit them to the processor; The processor is configured to run the code instructions to execute the data processing method according to any one of claims 1 to 7.

19. A data processing device, characterized in that: The data processing device includes a processor and a transceiver, the transceiver is used for information exchange between the data processing device and other data processing devices, and the processor executes program instructions to perform the data processing method according to any one of claims 1-7.

20. A processor, characterized in that: include: The processor is used to execute the data processing method according to any one of claims 1 to 7.

21. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a computer program or an instruction. When the computer program or the instruction is executed on a computer, the computer is caused to execute the data processing method according to any one of claims 1 to 7.

22. A computer program product, characterized in that The computer program product comprises: a computer program or instructions, and when the computer program or instructions are run on a computer, the computer is caused to execute the data processing method according to any one of claims 1 to 7.

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