Method, device, equipment and medium for detecting critical path in integrated circuit

Abstract

This application provides a method, apparatus, device, and medium for detecting critical paths in integrated circuits, relating to the field of chip technology. The method includes: acquiring a gate-level netlist of a target integrated circuit, and acquiring candidate critical paths in the target integrated circuit whose logic levels meet preset requirements based on the gate-level netlist. Each candidate critical path includes at least one target logic component. The method also includes: acquiring the target logic relationships of each target logic component in the candidate critical paths; and if the target logic relationships meet preset logic requirements, determining the candidate critical path to which the target logic component belongs as the target critical path. This method enables the determination of candidate critical paths based on the logic levels of each initial path in the target integrated circuit, and further filtering to obtain the target critical path based on the target logic relationships of each target logic component in the candidate critical paths. Compared to existing technologies, this eliminates the need for multiple iterations, effectively improving the efficiency of locating the target critical path in the target integrated circuit.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a method, apparatus, device and medium for detecting critical paths in integrated circuits. Background Technology

[0002] As chip integration becomes increasingly higher and process dimensions become smaller, the demand for higher frequencies also increases. Therefore, the ability to quickly locate the critical path in the design and provide timely feedback to front-end engineers for modification has become an essential part of improving frequency performance.

[0003] In existing technologies, when locating the critical path in an integrated circuit, it is often necessary to use static timing analysis tools to continuously analyze the integrated circuit's comprehensive netlist and determine it through continuous iterative design.

[0004] It can be seen that existing critical path detection methods are relatively cumbersome and have low detection efficiency. Summary of the Invention

[0005] The purpose of this application is to address the shortcomings of the prior art by providing a method, apparatus, device, and medium for detecting critical paths in integrated circuits, which can improve the positioning efficiency of target critical paths in target integrated circuits.

[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows:

[0007] In a first aspect, the present invention provides a method for detecting critical paths in integrated circuits, comprising:

[0008] Obtain the gate-level netlist of the target integrated circuit, and obtain candidate critical paths in the target integrated circuit whose logic levels meet preset requirements based on the gate-level netlist. The candidate critical paths include at least one target logic component.

[0009] Obtain the target logical relationships of each target logical component in the candidate critical path;

[0010] If the target logical relationship is determined to meet the preset logical requirements, then the candidate critical path to which the target logical component belongs is determined to be the target critical path.

[0011] In an optional implementation, the step of determining the candidate critical path to which the target logical component belongs as the target critical path if the target logical relationship is determined to meet preset logical requirements includes:

[0012] If the target logical relationship indicates that the candidate critical path to which the target logical component belongs includes at least two target logical components, and the output of the first target logical component is the input of the second target logical component, and the output of the second target logical component is the input of the first target logical component, then the candidate critical path to which the target logical component belongs is determined to be the target critical path; or, if the target logical relationship indicates that the output of any third target logical component is the input of the third target logical component, then the candidate critical path to which the target logical component belongs is determined to be the target critical path.

[0013] In an optional implementation, the method further includes:

[0014] Based on the target critical path, output the path information corresponding to the target critical path. The path information includes at least one of the following: the identifier of each target logic component in the target critical path, the target logic level corresponding to the target critical path, and the target logic relationship corresponding to the target critical path.

[0015] Based on the path information corresponding to the target critical path, the target critical path is adjusted so that the output frequency of the target critical path meets the preset frequency requirements.

[0016] In an optional implementation, obtaining candidate critical paths in the target integrated circuit whose logic levels meet preset requirements based on the gate-level netlist includes:

[0017] The path set of the target integrated circuit is obtained based on the gate-level netlist, and the path set includes at least one initial path;

[0018] Traverse each initial path in the path set and determine the logical level corresponding to each initial path;

[0019] Based on the logic level corresponding to each initial path, candidate critical paths in the target integrated circuit whose logic level meets the preset requirements are determined.

[0020] In an optional implementation, traversing each initial path in the path set and determining the logical level corresponding to each initial path includes:

[0021] Traverse each initial path in the path set and obtain the type of the logical component in each initial path;

[0022] Based on the type of logic component in each initial path, preset logic components in each initial path are removed to obtain each initial path after removal. The preset logic components include: inverters and buffer units.

[0023] Based on the initial paths after elimination, the logical level corresponding to each initial path is determined.

[0024] In an optional implementation, traversing each initial path in the path set and determining the logical level corresponding to each initial path includes:

[0025] Each initial path is passed as a variable to a preset script. The preset script then traverses each initial path in the path set to determine the logical level corresponding to each initial path.

[0026] In an optional implementation, the target logic component includes: registers and / or static random access memory.

[0027] In a second aspect, the present invention provides a detection device for critical paths in integrated circuits, comprising:

[0028] The first acquisition module is used to acquire the gate-level netlist of the target integrated circuit and acquire candidate critical paths in the target integrated circuit whose logic levels meet preset requirements based on the gate-level netlist. The candidate critical paths include at least one target logic component.

[0029] The second acquisition module is used to acquire the target logical relationships of each target logical component in the candidate critical path;

[0030] The determination module is used to determine the candidate critical path to which the target logical component belongs as the target critical path if the target logical relationship is determined to meet the preset logical requirements.

[0031] In an optional implementation, the determining module is specifically configured to determine the candidate critical path to which the target logic component belongs as the target critical path if the target logical relationship indicates that the candidate critical path to which the target logic component belongs includes at least two target logic components, and the output of the first target logic component is the input of the second target logic component, and the output of the second target logic component is the input of the first target logic component; or, if the target logical relationship indicates that the output of any third target logic component is the input of the third target logic component, then the candidate critical path to which the target logic component belongs is the target critical path.

[0032] In an optional embodiment, the detection device further includes: an adjustment module, configured to output path information corresponding to the target critical path based on the target critical path, wherein the path information includes at least one of the following: the identifier of each target logic component in the target critical path, the target logic level corresponding to the target critical path, and the target logic relationship corresponding to the target critical path;

[0033] Based on the path information corresponding to the target critical path, the target critical path is adjusted so that the output frequency of the target critical path meets the preset frequency requirements.

[0034] In an optional implementation, the first acquisition module is specifically used to acquire a path set of the target integrated circuit based on the gate-level netlist, the path set including at least one initial path;

[0035] Traverse each initial path in the path set and determine the logical level corresponding to each initial path;

[0036] Based on the logic level corresponding to each initial path, candidate critical paths in the target integrated circuit whose logic level meets the preset requirements are determined.

[0037] In an optional implementation, the first acquisition module is specifically used to traverse each initial path in the path set and acquire the type of logical component in each initial path;

[0038] Based on the type of logic component in each initial path, preset logic components in each initial path are removed to obtain each initial path after removal. The preset logic components include: inverters and buffer units.

[0039] Based on the initial paths after elimination, the logical level corresponding to each initial path is determined.

[0040] In an optional implementation, the first acquisition module is specifically used to pass each of the initial paths as variables into a preset script, and to traverse each initial path in the path set through the preset script to determine the logical level corresponding to each initial path.

[0041] In an optional implementation, the target logic component includes: registers and / or static random access memory.

[0042] Thirdly, the present invention provides an electronic device, comprising: a processor, a storage medium, and a bus, wherein the storage medium stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor communicates with the storage medium via the bus, and the processor executes the machine-readable instructions to perform the steps of the critical path detection method in an integrated circuit as described in any of the foregoing embodiments.

[0043] Fourthly, the present invention provides a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the steps of the critical path detection method in an integrated circuit as described in any of the foregoing embodiments.

[0044] The beneficial effects of this application are:

[0045] The method, apparatus, device, and medium for detecting critical paths in integrated circuits provided in this application include: acquiring a gate-level netlist of a target integrated circuit, and acquiring candidate critical paths in the target integrated circuit whose logic levels meet preset requirements based on the gate-level netlist, wherein each candidate critical path includes at least one target logic component; acquiring the target logic relationship of each target logic component in the candidate critical path; and determining the candidate critical path to which the target logic component belongs as the target critical path if the target logic relationship meets the preset logic requirements. By applying this application, it is possible to determine candidate critical paths based on the logic levels of each initial path in the target integrated circuit, and further filter them based on the target logic relationship of each target logic component in the candidate critical path to obtain the target critical path. Compared with the prior art, it does not require multiple iterations for determination, and has the characteristics of simple and fast location of target critical paths, which can effectively improve the location efficiency of target critical paths in target integrated circuits. Attached Figure Description

[0046] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 A flowchart illustrating a method for detecting critical paths in an integrated circuit, provided in an embodiment of this application;

[0048] Figure 2 A schematic diagram of an integrated circuit provided for an embodiment of this application;

[0049] Figure 3 A schematic diagram of another integrated circuit provided in an embodiment of this application;

[0050] Figure 4 A flowchart illustrating another method for detecting critical paths in an integrated circuit, provided as an embodiment of this application;

[0051] Figure 5 A flowchart illustrating another method for detecting critical paths in an integrated circuit, provided as an embodiment of this application;

[0052] Figure 6 A flowchart illustrating another method for detecting critical paths in an integrated circuit, provided as an embodiment of this application;

[0053] Figure 7 A flowchart illustrating another method for detecting critical paths in an integrated circuit, provided as an embodiment of this application;

[0054] Figure 8 A functional module diagram of a critical path detection device in an integrated circuit provided in an embodiment of this application;

[0055] Figure 9 This is a schematic diagram of an electronic device structure provided in an embodiment of this application. Detailed Implementation

[0056] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0057] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0058] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0059] In existing technologies, locating critical paths in integrated circuits often requires continuous analysis of the integrated circuit's comprehensive netlist using static timing analysis tools, involving iterative design processes to unravel the complexities and pinpoint the critical path. Therefore, existing critical path detection methods suffer from low detection efficiency.

[0060] In view of this, embodiments of this application provide a method for detecting critical paths in integrated circuits. By applying this detection method, the detection efficiency of critical paths in integrated circuits can be improved.

[0061] Figure 1 This is a flowchart illustrating a method for detecting critical paths in an integrated circuit, provided as an embodiment of this application. The execution subject of this method can be an electronic device with computing capabilities, such as a server, computer, or desktop computer. Figure 1 As shown, the method may include:

[0062] S101. Obtain the gate-level netlist of the target integrated circuit, and obtain the candidate critical path in the target integrated circuit whose logic level meets the preset requirements based on the gate-level netlist. The candidate critical path includes at least one target logic component.

[0063] The gate-level netlist of the target integrated circuit serves as a netlist file describing the connection relationships between logic gates and flip-flops in the target integrated circuit. It can be obtained using EDA tools based on the Register Transfer Level (RTL) code corresponding to the target integrated circuit. Optionally, the logic gates in the target integrated circuit may include AND gates, NOT gates, NAND gates, NOR gates, etc., and the flip-flops in the target integrated circuit may include D flip-flops, JK flip-flops, etc., without limitation.

[0064] Based on the obtained gate-level netlist of the target integrated circuit, the logic levels corresponding to each initial path in the target integrated circuit can be counted using the gate-level netlist. The initial paths whose logic levels meet the preset requirements can be determined as candidate critical paths, thereby realizing the initial statistics of the target critical paths in the target integrated circuit.

[0065] It should be noted that the determined candidate critical path may include at least one target logic component. Of course, this application does not limit the number of target logic components, and may include one or more depending on the actual application scenario.

[0066] S102. Obtain the target logic relationship of each target logic component in the candidate critical path.

[0067] Optionally, the candidate critical paths identified above may include one or more paths. For each candidate critical path, the target logic components in the candidate critical path can be analyzed to determine the target logic relationships of each target logic component.

[0068] The target logical relationship of each target logical component can indicate the logical complexity of the candidate critical path to which that target logical component belongs. Optionally, this logical complexity can be represented by the connection relationship corresponding to each target logical component. The more complex the connection relationship corresponding to the target logical component, the higher the logical complexity of the candidate critical path to which that target logical component belongs; the simpler the connection relationship, the lower the logical complexity of the candidate critical path to which that target logical component belongs.

[0069] S103. If the target logical relationship is determined to meet the preset logical requirements, then the candidate critical path to which the target logical component belongs is determined as the target critical path.

[0070] Since the candidate critical paths identified above are not necessarily the target critical paths, in other words, a candidate critical path may be a non-target critical path, after obtaining the target logic relationships of each target logic component in each candidate critical path, it is possible to further determine whether each candidate critical path is the target critical path based on this.

[0071] Specifically, the determination can be made by checking whether the target logic relationships of each target logic component in each candidate critical path meet the preset logic requirements. If they do, the candidate critical path is determined to be the target critical path; otherwise, it is determined not to be the target critical path. These target critical paths are timing paths that have a decisive impact on the design performance of the target integrated circuit. They cannot be optimized using back-end physical design methods, but can be optimized using front-end logic design methods to ensure that the output frequency of the target critical path meets the preset frequency requirements.

[0072] By applying the embodiments of this application, it is possible to determine candidate critical paths based on the logic levels of each initial path in the target integrated circuit, and further filter them based on the target logic relationships of each target logic component in the candidate critical paths to obtain the target critical path. This method has the characteristics of being simple and fast in locating the target critical path, and can effectively improve the locating efficiency of the target critical path in the target integrated circuit.

[0073] In summary, this application provides a method for detecting critical paths in an integrated circuit. The method includes: acquiring a gate-level netlist of a target integrated circuit, and acquiring candidate critical paths in the target integrated circuit whose logic levels meet preset requirements based on the gate-level netlist. Each candidate critical path includes at least one target logic component. The method also includes acquiring the target logic relationships of each target logic component in the candidate critical paths. If the target logic relationship meets the preset logic requirements, the candidate critical path to which the target logic component belongs is determined as the target critical path. By applying this application, candidate critical paths can be determined based on the logic levels of each initial path in the target integrated circuit, and further filtered based on the target logic relationships of each target logic component in the candidate critical paths to obtain the target critical path. Compared with the prior art, this method eliminates the need for multiple iterations and features simple and fast location of the target critical path, effectively improving the location efficiency of the target critical path in the target integrated circuit.

[0074] Figure 2 This is a schematic diagram of an integrated circuit provided in an embodiment of this application. Figure 3 This is a schematic diagram of another integrated circuit provided in an embodiment of this application. Optionally, if the target logic relationship is determined to meet preset logic requirements, then determining the candidate critical path to which the target logic component belongs as the target critical path includes:

[0075] If the target logic relation indicates that the candidate critical path to which the target logic component belongs includes at least two target logic components, and the output of the first target logic component is the input of the second target logic component, and the output of the second target logic component is the input of the first target logic component, then the candidate critical path to which the target logic component belongs is determined to be the target critical path. Alternatively, if the target logic relation indicates that the output of any third target logic component is the input of the third target logic component, then the candidate critical path to which the target logic component belongs is determined to be the target critical path.

[0076] As can be seen from the above description, it can be determined whether the candidate critical path to which the target logic component belongs is the target critical path by either of the two methods described above.

[0077] In Method 1, for a candidate critical path, the number of target logic components in the candidate critical path can be counted first. If the candidate critical path includes at least two target logic components (e.g., 2, 5, 6, etc.), and any two of these at least two target logic components are each other's start and end points, forming a checkerboard-like logical relationship, then the candidate critical path can be determined as the target critical path. The condition where any two of the at least two target logic components are each other's start and end points means that the at least two target logic components include a first target logic component and a second target logic component, and the output of the first target logic component is the input of the second target logic component, and vice versa.

[0078] For example, refer to Figure 2 As shown, if a candidate critical path includes: a first target logic component A, a second target logic component B, a D logic component, and an E logic component, wherein the output of the first target logic component A is the input of the second target logic component B, and the output B of the second target logic component is the input of the first target logic component A, then the candidate critical path can be considered as the target critical path.

[0079] In Method 2, for a candidate critical path, if the output of any third target logic component serves as its input, then the candidate critical path can be determined as the target critical path.

[0080] For example, refer to Figure 3 As shown, if a candidate critical path includes a third target logic component C, a D logic component, and an E logic component, and the output C of the third target logic component is used as the input of the third target logic component C, then the candidate critical path can be considered as the target critical path.

[0081] It should be noted that this application does not limit the order of execution of the two methods. Depending on the actual application scenario, method one can be used first. If method one determines that a candidate critical path is not the target critical path, then method two can be used for determination. Alternatively, method two can be used first. If method two determines that a candidate critical path is not the target critical path, then method two can be used for determination. The choice can be made flexibly according to the actual application scenario.

[0082] Figure 4 This is a flowchart illustrating another method for detecting critical paths in an integrated circuit, provided as an embodiment of this application. Optionally, as... Figure 4 As shown, the above method also includes:

[0083] S301. Based on the target critical path, output the path information corresponding to the target critical path.

[0084] The path information includes at least one of the following: the identifier of each target logic component in the target critical path, the target logic level corresponding to the target critical path, and the target logic relationship corresponding to the target critical path.

[0085] In some embodiments, the path information corresponding to the target critical path can be output in the form of tables, images, text, etc., and the specific output format is not limited here.

[0086] It is understandable that outputting the path information corresponding to the target critical path can quickly and easily locate the target critical path. In some embodiments, during specific location, the target critical path can be further located based on the candidate critical paths determined above, using the identifiers of each target logic component in the path information.

[0087] S302. Based on the path information corresponding to the target critical path, adjust the target critical path so that the output frequency of the target critical path meets the preset frequency requirements.

[0088] Based on the identified critical path, the path information corresponding to this critical path can be fed back to the front-end engineer, who can then adjust the critical path. Optionally, adjustments can be made by optimizing the target logic relationships between the target logic components within the critical path, or by optimizing the target logic levels corresponding to the critical path. For example, the target logic relationships between the target logic components can be simplified to achieve the adjustment purpose. Of course, it should be noted that the specific adjustment methods are not limited to these.

[0089] The adjustment process can be based on whether the output frequency of the target critical path meets the preset frequency requirements. If it does, the adjustment operation can be stopped; otherwise, the adjustment can continue until the output frequency of the target critical path meets the preset frequency requirements. By applying the embodiments of this application, the target critical path can be located and optimized at an early stage in the target integrated circuit.

[0090] Of course, it should be noted that this application does not limit the value of the output frequency of the target critical path, that is, it does not limit the applicable scenarios of the method of this application. Optionally, the output frequency of the target critical path can be 3GHz, 10GHz, etc.

[0091] Figure 5 This is a flowchart illustrating another method for detecting critical paths in an integrated circuit, provided as an embodiment of this application. Optionally, as... Figure 5 As shown, the above method for obtaining candidate critical paths in a target integrated circuit whose logic levels meet preset requirements based on a gate-level netlist includes:

[0092] S401. Obtain the path set of the target integrated circuit based on the gate-level netlist. The path set includes at least one initial path.

[0093] S402. Traverse each initial path in the path set and determine the logical level corresponding to each initial path.

[0094] In some embodiments, based on the acquired gate-level netlist, the initial paths in the target integrated circuit can be counted, and a traversal operation can be performed on each initial path to determine the number of logic levels corresponding to each initial path. Each initial path may include at least two logic components, and the number of logic levels corresponding to each initial path can be determined based on the number of logic levels between the logic components in each initial path.

[0095] S403. Based on the logic level corresponding to each initial path, determine the candidate critical path in the target integrated circuit whose logic level meets the preset requirements.

[0096] The preset requirement can be that the number of logic levels is greater than a preset logic level threshold. Optionally, the preset logic level threshold can be 22, but its value is not limited to this. For example, taking a 7nm process as an example, assuming that all reference paths in the reference integrated circuit are standard logic cells (Ultra Low Voltage Threshold, ULVT), then the average sum of the delay and line delay per logic cell level can be calculated to be 15ps. In addition, assuming that the clock skew is 0 and the clock uncertainty is 0, according to the setup time calculation formula, if the reference integrated circuit is to reach a frequency of 3GHz, the maximum number of logic levels is 22. The setup time refers to the time during which the data is stable before the rising edge of the clock signal of the flip-flop arrives. If the setup time is insufficient, the data will not be able to be triggered into the flip-flop at the rising edge of the clock.

[0097] Based on the above explanation, after determining the logical level corresponding to each initial path, it can be determined whether the logical level corresponding to each initial path meets the preset requirement. If it does not meet the requirement, the initial path can be filtered out. If it does meet the requirement, the initial path can be determined as a candidate critical path.

[0098] Figure 6 This is a flowchart illustrating another method for detecting critical paths in an integrated circuit, provided as an embodiment of this application. Optionally, as... Figure 6 As shown, for each initial path in the above traversal path set, the logical level corresponding to each initial path is determined, including:

[0099] S501. Traverse each initial path in the path set and obtain the type of the logical component in each initial path.

[0100] During the traversal of each initial path, the type of logic component in each initial path can be obtained. Optionally, each initial path may include at least one of the following types of logic components: inverter, buffer unit, register, static random access memory, AND gate, etc.

[0101] Of course, it should be noted that this application does not limit the number of types of logic components or the number of logic components of each type in each initial path. For example, an initial path may include 2 buffer units and 3 AND gates, but is not limited thereto.

[0102] S502. Based on the type of logic component in each initial path, remove the preset logic component in each initial path to obtain the initial paths after removal.

[0103] The preset logic components include: an inverter and a buffer unit.

[0104] S503. Based on the initial paths after elimination, determine the logical level corresponding to each initial path.

[0105] The logic level corresponding to each initial path can be the maximum logic level among the logic components in each initial path. The maximum logic level among the logic components is also the number of combinational logic components that exist in the largest number among the logic components. Combinational logic components can include AND gates, OR gates, NOT gates, etc., and are not limited here.

[0106] Optionally, when determining the number of logic levels corresponding to each initial path, it is considered that the initial path may include inverters and buffer units added during the physical design stage of the integrated circuit. The physical design is also called the back-end design, which corresponds to the logic design, also known as the front-end design. Since the inverters and buffer units added during the physical design stage need to be optimized through the back-end physical design method, they can be disregarded when determining the target critical path.

[0107] Based on the above explanation, the preset logic components in each initial path can be eliminated according to their types to obtain the eliminated initial paths. Then, when determining the logic level corresponding to each initial path based on the eliminated initial paths, the inverters and buffer units in each initial path can be ignored. That is, when calculating the logic level corresponding to each initial path, the inverters and buffer units in each initial path can be omitted. Therefore, when determining the target critical path based on this, the accuracy can be improved.

[0108] Figure 7 This is a flowchart illustrating another method for detecting critical paths in an integrated circuit, provided as an embodiment of this application. Optionally, as... Figure 7 As shown, for each initial path in the above traversal path set, the logical level corresponding to each initial path is determined, including:

[0109] S601. Pass each initial path as a variable into the preset script, and traverse each initial path in the path set through the preset script to determine the logical level corresponding to each initial path.

[0110] In some embodiments, the logical level corresponding to each initial path can be determined by a preset script. Specifically, the initial paths can be retrieved based on a gate-level netlist, and each initial path can be passed as a variable to the preset script. The preset script then processes each initial path to obtain the logical level corresponding to each initial path. Optionally, the preset script can be a shell script, a Python script, etc., and the type of the preset script is not limited here.

[0111] By applying the embodiments of this application, it is possible to quickly determine the logical level corresponding to each initial path through an embedded preset script, which has the characteristics of being simple and fast to implement.

[0112] Optionally, the target logic components mentioned above include: registers and / or static random access memory.

[0113] For each candidate critical path, depending on the actual application scenario, it may include registers, or it may include static random access memory, or it may include both registers and static random access memory; no limitation is made here.

[0114] Figure 8 This is a functional module diagram of a critical path detection device in an integrated circuit provided in this application embodiment. The basic principle and technical effects of this device are the same as those of the corresponding method embodiment described above. For the sake of brevity, parts not mentioned in this embodiment can be referred to the corresponding content in the method embodiment. Figure 8 As shown, the detection device 100 includes:

[0115] The first acquisition module 110 is used to acquire the gate-level netlist of the target integrated circuit and acquire candidate critical paths in the target integrated circuit whose logic levels meet preset requirements based on the gate-level netlist. The candidate critical paths include at least one target logic component.

[0116] The second acquisition module 120 is used to acquire the target logical relationship of each target logical component in the candidate critical path;

[0117] The determination module 130 is used to determine the candidate critical path to which the target logical component belongs as the target critical path if the target logical relationship is determined to meet the preset logical requirements.

[0118] In an optional implementation, the determining module 130 is specifically configured to determine the candidate critical path to which the target logic component belongs as a target critical path if the target logical relationship indicates that the candidate critical path to which the target logic component belongs includes at least two target logic components, and the output of the first target logic component is the input of the second target logic component, and the output of the second target logic component is the input of the first target logic component; or, if the target logical relationship indicates that the output of any third target logic component is the input of the third target logic component, then the candidate critical path to which the target logic component belongs is determined as a target critical path.

[0119] In an optional embodiment, the detection device further includes: an adjustment module, configured to output path information corresponding to the target critical path based on the target critical path, wherein the path information includes at least one of the following: the identifier of each target logic component in the target critical path, the target logic level corresponding to the target critical path, and the target logic relationship corresponding to the target critical path;

[0120] Based on the path information corresponding to the target critical path, the target critical path is adjusted so that the output frequency of the target critical path meets the preset frequency requirements.

[0121] In an optional implementation, the first acquisition module 110 is specifically used to acquire the path set of the target integrated circuit based on the gate-level netlist, the path set including at least one initial path;

[0122] Traverse each initial path in the path set and determine the logical level corresponding to each initial path;

[0123] Based on the logic level corresponding to each initial path, candidate critical paths in the target integrated circuit whose logic level meets the preset requirements are determined.

[0124] In an optional implementation, the first acquisition module 110 is specifically used to traverse each initial path in the path set and acquire the type of logical component in each initial path;

[0125] Based on the type of logic component in each initial path, preset logic components in each initial path are removed to obtain each initial path after removal. The preset logic components include: inverters and buffer units.

[0126] Based on the initial paths after elimination, the logical level corresponding to each initial path is determined.

[0127] In an optional implementation, the first acquisition module 110 is specifically used to pass each of the initial paths as variables into a preset script, and to traverse each initial path in the path set through the preset script to determine the logical level corresponding to each initial path.

[0128] In an optional implementation, the target logic component includes: registers and / or static random access memory.

[0129] The above-described device is used to execute the method provided in the foregoing embodiments, and its implementation principle and technical effect are similar, so they will not be described again here.

[0130] These modules can be one or more integrated circuits configured to implement the above methods, such as one or more Application Specific Integrated Circuits (ASICs), one or more microprocessors, or one or more Field Programmable Gate Arrays (FPGAs). Alternatively, when a module is implemented using processing element scheduler code, the processing element can be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor capable of calling program code. Furthermore, these modules can be integrated together as a system-on-a-chip (SOC).

[0131] Figure 9 This is a schematic diagram of an electronic device provided in an embodiment of this application. This electronic device can be integrated into the aforementioned detection device. Figure 9 As shown, the electronic device may include a processor 210, a storage medium 220, and a bus 230. The storage medium 220 stores machine-readable instructions executable by the processor 210. When the electronic device is running, the processor 210 communicates with the storage medium 220 via the bus 230, and the processor 210 executes the machine-readable instructions to perform the steps of the above method embodiment. The specific implementation and technical effects are similar and will not be described in detail here.

[0132] Optionally, this application also provides a storage medium storing a computer program, which, when run by a processor, executes the steps of the above-described method embodiments. The specific implementation and technical effects are similar and will not be repeated here.

[0133] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0134] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0135] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in a combination of hardware and software functional units.

[0136] The integrated units implemented as software functional units described above can be stored in a computer-readable storage medium. These software functional units, stored in a storage medium, include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute some steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0137] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0138] The above are merely preferred embodiments of this application and are not intended to limit this application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application. It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need further definition and explanation in subsequent figures. The above are merely preferred embodiments of this application and are not intended to limit this application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for detecting critical paths in integrated circuits, characterized in that, include: Obtain the gate-level netlist of the target integrated circuit, and obtain candidate critical paths in the target integrated circuit whose logic levels meet preset requirements based on the gate-level netlist. The candidate critical paths include at least one target logic component. Obtain the target logical relationships of each target logical component in the candidate critical path; If the target logical relationship is determined to meet the preset logical requirements, then the candidate critical path to which the target logical component belongs is determined to be the target critical path; The step of obtaining candidate critical paths in the target integrated circuit whose logic levels meet preset requirements based on the gate-level netlist includes: The path set of the target integrated circuit is obtained based on the gate-level netlist, and the path set includes at least one initial path; each initial path in the path set is traversed to determine the logic level corresponding to each initial path; and candidate key paths in the target integrated circuit whose logic levels meet preset requirements are determined according to the logic level corresponding to each initial path. The step of traversing each initial path in the path set and determining the logical level corresponding to each initial path includes: Traverse each initial path in the path set to obtain the type of logic component in each initial path; based on the type of logic component in each initial path, remove preset logic components from each initial path to obtain each initial path after removal, wherein the preset logic components include: inverters and buffer units; based on each initial path after removal, determine the logic level corresponding to each initial path. or, Each initial path is passed as a variable to a preset script. The preset script then traverses each initial path in the path set to determine the logical level corresponding to each initial path.

2. The method according to claim 1, characterized in that, If the target logical relationship is determined to meet the preset logical requirements, then the candidate critical path to which the target logical component belongs is determined as the target critical path, including: If the target logical relationship indicates that the candidate critical path to which the target logical component belongs includes at least two target logical components, and the output of the first target logical component is the input of the second target logical component, and the output of the second target logical component is the input of the first target logical component, then the candidate critical path to which the target logical component belongs is determined to be the target critical path. or, If the target logic relation indicates that the output of any third target logic component is used as the input of the third target logic component, then the candidate critical path to which the target logic component belongs is determined as the target critical path.

3. The method according to claim 1, characterized in that, The method further includes: Based on the target critical path, output the path information corresponding to the target critical path. The path information includes at least one of the following: the identifier of each target logic component in the target critical path, the target logic level corresponding to the target critical path, and the target logic relationship corresponding to the target critical path. Based on the path information corresponding to the target critical path, the target critical path is adjusted so that the output frequency of the target critical path meets the preset frequency requirements.

4. The method according to any one of claims 1-3, characterized in that, The target logic component includes: registers and / or static random access memory.

5. A detection device for critical paths in integrated circuits, characterized in that, include: The first acquisition module is used to acquire the gate-level netlist of the target integrated circuit and acquire candidate critical paths in the target integrated circuit whose logic levels meet preset requirements based on the gate-level netlist. The candidate critical paths include at least one target logic component. The second acquisition module is used to acquire the target logical relationships of each target logical component in the candidate critical path; The determination module is used to determine the candidate critical path to which the target logical component belongs as the target critical path if the target logical relationship is determined to meet the preset logical requirements. The first acquisition module is specifically used to acquire the path set of the target integrated circuit based on the gate-level netlist, the path set including at least one initial path; traverse each initial path in the path set to determine the logic level corresponding to each initial path; and determine the candidate key path in the target integrated circuit whose logic level meets the preset requirements based on the logic level corresponding to each initial path. The step of traversing each initial path in the path set and determining the logical level corresponding to each initial path includes: Traverse each initial path in the path set to obtain the type of logic component in each initial path; based on the type of logic component in each initial path, remove preset logic components from each initial path to obtain each initial path after removal, wherein the preset logic components include: inverters and buffer units; based on each initial path after removal, determine the logic level corresponding to each initial path. or, Each initial path is passed as a variable to a preset script. The preset script then traverses each initial path in the path set to determine the logical level corresponding to each initial path.

6. An electronic device, characterized in that, include: The device includes a processor, a storage medium, and a bus, wherein the storage medium stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor communicates with the storage medium via the bus, and the processor executes the machine-readable instructions to perform the steps of the detection method for a critical path in an integrated circuit as described in any one of claims 1-4.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, performs the steps of the critical path detection method in any one of claims 1-4 of the integrated circuit.

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