Multi-board distributed clock synchronization method, device, test system and storage medium

Abstract

A multi-board distributed clock synchronization method is applied to a test system, comprising: a plurality of test boards equipped with a main control unit and a timer, the main control unit having a first and a second port; a system bus connected to a plurality of first and second ports respectively through a plurality of clock signal branches arranged in parallel; the method comprises setting a synchronization time period; setting a clock variable according to the set synchronization time period; generating a first timer interrupt request and outputting a second valid level signal through the first port under the condition that a set time length is satisfied; determining whether the second port receives a second timer interrupt request forwarded through the system bus through the clock signal branch; when the second port receives the second timer interrupt request, the main control unit is configured to output a first valid level signal through the first port, and simultaneously update the clock variable in the main control unit. A device, a test system and a storage medium are also provided. The present invention can maintain a stable balance of long-term clock accuracy.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a multi-board distributed clock synchronization method, a synchronization device, a test system and a storage medium. Background Art

[0002] There are multiple components in the test system, including multiple test boards with different functions. The test board is equipped with a single-chip microcomputer to control the test work, and finally report all test results to the host computer using the communication bus. In the test results, the test data of each board has its own test time, that is, the time coordinate of the data. Since each board has its own hardware clock source (crystal oscillator), it is inevitable that there will be certain errors. After a certain period of time, the time coordinates of the test data of each board will be out of sync, and the order of appearance will be different from the actual situation. It cannot objectively reflect the actual test and cannot provide an objective basis for subsequent analysis.

[0003] The existing technology can solve this problem through a master-slave architecture, but if the mainboard card fails, the system loses its time synchronization mechanism and the robustness of the system is reduced. Summary of the invention

[0004] In view of the problem that in a master-slave structure clock synchronization method, the system will lose the time synchronization mechanism when a main board card fails, the first aspect of the present application designs and provides a multi-board distributed clock synchronization method.

[0005] In order to achieve the above invention / design purpose, the present invention adopts the following technical solutions:

[0006] A multi-board distributed clock synchronization method is applied to a test system, the test system comprising:

[0007] A plurality of test boards, each of which is equipped with a main control unit and a timer, and any of the main control units has a first port and a second port that are independently configured;

[0008] A system bus, wherein the system bus is connected to the plurality of first ports and the second port respectively through a plurality of clock signal branches arranged in parallel;

[0009] The synchronization method comprises the following steps:

[0010] Set the synchronization period in the test system;

[0011] Setting and storing clock variables in the main control unit according to the set synchronization time period;

[0012] The main control unit is configured to generate a first timer interrupt request at the same time scale corresponding to the set synchronization period according to its own clock variable and output a first valid level signal to the system bus through the first port, and output a second valid level signal through the first port after the first timer interrupt request is generated and under the condition of meeting a set time length; wherein the set time length is less than a set synchronization period;

[0013] determining whether the second port receives a second timer interrupt request forwarded through the system bus through the clock signal branch;

[0014] When the second port receives the second timer interrupt request, the main control unit is configured to output a first valid level signal through the first port and simultaneously update the clock variable in the main control unit, and the updated clock variable in the main control unit is X n = int(X n-1 ÷T+0.5)×T, where X n-1 is the current value of the clock variable, X n is the updated clock variable, T is the set synchronization period, and int is the rounding.

[0015] In some optional embodiments of the present application, the set duration is half of the set synchronization period; the synchronization method also includes the following steps: configuring the main control unit to generate a first timer interrupt request at the starting time scale corresponding to the set synchronization period according to its own clock variable and output a first valid level signal of a low level to the system bus through the first port, and output a second valid level signal of a high level through the first port after generating the first timer interrupt request and satisfying the set duration.

[0016] In some optional embodiments of the present application, the set duration is half of the set synchronization period; the synchronization method also includes the following steps: configuring the main control unit to generate a first timer interrupt request at the end time scale corresponding to the set synchronization period according to its own clock variable and output a first valid level signal of high level to the system bus through the first port, and output a second valid level signal of low level through the first port after generating the first timer interrupt request and satisfying the set duration condition.

[0017] In some optional embodiments of the present application, the initial value X0 of the clock variable is accumulated and stored by a timer in the main control unit in units not greater than half of the set synchronization timing period; the main control unit corresponding to the first first valid level signal received by the system bus is set as the synchronization reference; after this round of synchronization is completed, the main control unit set as the synchronization reference for this round exits the next round of synchronization control.

[0018] A second aspect of the present application provides a multi-board distributed clock synchronization device, which is applied to a test system, and the test system includes:

[0019] A plurality of test boards, each of which is equipped with a main control unit and a timer, and any of the main control units has a first port and a second port that are independently configured;

[0020] A system bus, wherein the system bus is connected to the plurality of first ports and the second port respectively through a plurality of clock signal branches arranged in parallel;

[0021] Characterized in that the synchronization device comprises:

[0022] A setting module, the setting module is configured to set a synchronization time period in the test system;

[0023] A variable configuration module, wherein the variable configuration module is configured to set and store clock variables in the main control unit according to a set synchronization period;

[0024] An interrupt generation module, the interrupt generation module is used to configure the main control unit to generate a first timer interrupt request at a time scale corresponding to the set synchronization period according to its own clock variable and output a first valid level signal to the system bus through the first port, and after generating the first timer interrupt request and satisfying a set time length, output a second valid level signal through the first port; wherein the set time length is less than a set synchronization period;

[0025] a determination module, the determination module being configured to determine whether the second port receives a second timer interrupt request forwarded via the system bus through the clock signal branch;

[0026] An update module, wherein the update module is configured to, when the second port receives a second timer interrupt request, configure the main control unit to output a first valid level signal through the first port, and update a clock variable in the main control unit, wherein the updated clock variable in the main control unit is:

[0027] X n = int(X n-1 ÷T+0.5)×T, where X n-1is the current value of the clock variable, X n is the updated clock variable, T is the set synchronization period, and int is the rounding.

[0028] In some optional implementations of the present application, the set duration is half of the set synchronization period;

[0029] The interrupt generation module is also used to configure the main control unit to generate a first timer interrupt request at the starting time corresponding to the set synchronization period according to its own clock variable and output a first valid level signal of a low level to the system bus through the first port, and output a second valid level signal of a high level through the first port after generating the first timer interrupt request and satisfying the set time condition.

[0030] In some optional implementations of the present application, the set duration is half of the set synchronization period;

[0031] The interrupt generation module is also used to configure the main control unit to generate a first timer interrupt request at the end time scale corresponding to the set synchronization period according to its own clock variable and output a first valid level signal of high level to the system bus through the first port, and output a second valid level signal of low level through the first port after generating the first timer interrupt request and satisfying the set time condition.

[0032] In some optional embodiments of the present application, the initial value X0 of the clock variable is accumulated and stored by a timer in the main control unit with an accuracy not greater than half of the set synchronization timing period; the main control unit corresponding to the first first valid level signal received by the system bus is set as the synchronization reference; after this round of synchronization is completed, the main control unit set as the synchronization reference for this round exits the next round of synchronization control.

[0033] A third aspect of the present application provides a test system, which applies a multi-board distributed clock synchronization method; the test system comprises:

[0034] A plurality of test boards, each of which is equipped with a main control unit and a timer, and any of the main control units has a first port and a second port that are independently configured;

[0035] A system bus, wherein the system bus is connected to the plurality of first ports and the second port respectively through a plurality of clock signal branches arranged in parallel;

[0036] The synchronization method comprises the following steps:

[0037] Set the synchronization period in the test system;

[0038] Setting and storing clock variables in the main control unit according to the set synchronization time period;

[0039] The main control unit is configured to generate a first timer interrupt request at the same time scale corresponding to the set synchronization period according to its own clock variable and output a first valid level signal to the system bus through the first port, and output a second valid level signal through the first port after the first timer interrupt request is generated and under the condition of meeting a set time length; wherein the set time length is less than a set synchronization period;

[0040] determining whether the second port receives a second timer interrupt request forwarded through the system bus through the clock signal branch;

[0041] When the second port receives the second timer interrupt request, the main control unit is configured to output a first valid level signal through the first port and simultaneously update the clock variable in the main control unit, and the updated clock variable in the main control unit is X n = int(X n-1 ÷T+0.5)×T, where X n-1 is the current value of the clock variable, X n is the updated clock variable, T is the set synchronization period, and int is the rounding.

[0042] The fourth aspect of the present application provides a non-transitory computer-readable storage medium on which a computer program is stored. The computer program is executed to implement the above-mentioned multi-board distributed clock synchronization method.

[0043] Compared with the prior art, the advantages and positive effects of the present invention are:

[0044] In the test system of the present invention, a system bus is arranged, and the clock waveforms and logical relationships output by each main control unit are adopted to form a common contribution mechanism and an equal distribution model of a unified synchronous operation model. Clock synchronization can be realized efficiently and simply, and a random exit synchronization contribution mechanism is constructed to better balance the clock accuracy. The entire system is simple and efficient, has good consistency, and has a stable and balanced long-term clock accuracy.

[0045] After reading the specific embodiments of the present invention in conjunction with the accompanying drawings, other features and advantages of the present invention will become more clear. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0047] Figure 1 is a flow chart of a first embodiment of a multi-board distributed clock synchronization method provided by the first aspect of the present invention;

[0048] Figure 2 is a flow chart of a second embodiment of the multi-board distributed clock synchronization method provided by the first aspect of the present invention;

[0049] Figure 3 is a flow chart of a third embodiment of the multi-board distributed clock synchronization method provided by the first aspect of the present invention;

[0050] Figure 4 It is the principle architecture diagram of the test system;

[0051] Figure 5 is a timing diagram when the multi-board distributed clock synchronization method provided by the first aspect of the present invention is adopted;

[0052] Figure 6 is another timing diagram when the multi-board distributed clock synchronization method provided by the second aspect of the present invention is adopted;

[0053] Figure 7 It is a schematic block diagram of the structure of a first embodiment of a multi-board distributed clock synchronization device provided according to the second aspect of the present invention. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0055] The terms "first", "second", "third", etc. in the specification, claims and drawings of the present invention are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof represent non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0056] In the present invention, "embodiment" means that a specific feature, structure or characteristic described in conjunction with the embodiment can be included in at least one embodiment of the present application. In the specification, the phrase does not necessarily refer to the same embodiment at various locations, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It will be understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0057] In view of the problem that the system loses the clock synchronization mechanism when the main board fails in the master-slave structure clock synchronization method, the first aspect of the present application designs and provides a multi-board distributed clock synchronization method. Figure 1 , Figure 4 , Figure 5 and Figure 6 As shown in the introduction. Figure 1 The multi-board distributed clock synchronization method shown is applied to a test system, and the test system can be an automated test system, a compatibility test system, a security test system, and the like. Taking an automated test system as an example, the automated test system is used to test whether each component is operating normally, and the test is completed by running and using it. As the system functions gradually become more complex, the test system includes multiple test boards to realize different functions, and each test board is equipped with an independent main control unit. Multiple test boards are connected to the host computer of the test system in communication. The main control unit includes a control operation unit such as a central processing unit, a microprocessing unit, a digital signal processor, or a special purpose integrated circuit. The main control unit on the test board is also provided with a timer, which is a built-in clock generation circuit or an independent external crystal oscillator, which can generate a clock and can communicate with the main control unit. The test board is also provided with a main memory and an auxiliary memory, and the main memory can be a recording medium such as a dynamic random access memory and a static memory. The auxiliary memory can be a non-volatile memory such as a read-only memory and a flash memory to store control programs such as firmware and various data. Any of the main control units has an independently configured first port and a second port to realize the multi-board distributed clock synchronization method provided by the present invention.

[0058] Specifically, if Figure 4 As shown, the test system further includes a system bus L, which includes computer hardware that connects or otherwise provides a communication channel. The system bus L is respectively connected to a plurality of first ports and a plurality of second ports through a plurality of clock signal branches arranged in parallel.

[0059] In order to achieve the purpose of multi-board distributed clock synchronization in a non-master-slave architecture, such as Figure 1 The synchronization method shown comprises a number of steps.

[0060] Step S101: Set the synchronization time period in the test system. The synchronization time period can be represented by T. In some optional embodiments of the present application, the synchronization time period T can be set to T=1000ms. The synchronization time period T is pre-stored in the test system. For example, it can be pre-stored in the host computer of the test system and can be sent to each main control unit. The test system can start the synchronization as needed after running for a period of time, or perform distributed synchronization at a set frequency.

[0061] Step S102: Set the clock variable in each main control unit according to the set synchronization period T. In some optional embodiments of the present application, the initial value of the clock variable can be represented by X0. The initial value X0 of the clock variable is accumulated by the timer (clock generating circuit or external crystal oscillator) in the main control unit in a time unit not greater than half of the set synchronization period T, that is, the time unit of the clock variable X0 is less than or equal to T / 2. In some optional embodiments of the present application, the time unit of the initial value X0 of the clock variable may be T / 2, that is, the initial value X0 of the clock variable is N accumulated T / 2 durations, N is greater than or equal to 1, and N is a positive integer. Independent clock variables are pre-stored in each main control unit. In some optional embodiments of the present application, the initial value X0 of the clock variable may be T.

[0062] Step S103: configure each main control unit to generate a first timer interrupt request at a set time scale corresponding to the set synchronization period T, and output a first valid level signal to the system bus L through the first port when generating the first timer interrupt request. That is, the first valid level signal is transmitted to the system bus L through the corresponding clock signal branch, and can be further forwarded by the system bus L.

[0063] Step S104: configuring each main control unit to output a second valid level signal through the first port after generating the first timer interrupt request and satisfying a set time condition, wherein the set time condition is less than a set synchronization period T.

[0064] Step S105: Determine whether the second port receives the second timer termination request forwarded through the system bus L through the clock signal branch.

[0065] Step S106: When the second timer interrupt request is received at the second port, the main control unit is configured to output a first valid level signal through the first port and update the clock variable in the main control unit. The updated clock variable in the main control unit is X n = int(X n-1 ÷T+0.5)×T, where X n-1 is the current value of the clock variable, X n is the updated clock variable, T is the set synchronization period T, and int is the integer.

[0066] See also Figures 4 to 6As shown, take three main control parts as an example: the main control part M1 has a first port P11 and a second port P12, the main control part M2 has a first port P21 and a second port P22, and the main control part M3 has a first port P31 and a second port P32. The first ports P11, P21 and P31 are respectively connected to a clock signal branch L1, L2 and L3, and are connected to the system bus L through the clock signal branches L1, L2 and L3, and the second ports P12, P22 and P32 are also connected to the system bus L through the clock signal branches L1, L2 and L3. The first ports P11, P21 and P31 are configured to transmit the signals of the main control parts M1, M2 and M3 to the system bus L through the clock signal branches L1, L2 and L3, and the second ports P12, P22 and P32 are configured to transmit the signals on the system bus L to the main control parts M1, M2 and M3 locally through the clock signal branches L1, L2 and L3.

[0067] The main control units M1, M2 and M3 are configured to generate a first timer interrupt request at a time scale corresponding to the set synchronization period T based on the locally corresponding clock variables, that is, the main control unit M1 spontaneously generates a first timer interrupt request Q1 at a time scale corresponding to the set synchronization period T according to its own clock variables and outputs a first valid level signal S1 through the first port P11, and the first valid level signal S1 is output to the system bus L via the clock signal branch L1; similarly, the main control unit M2 also spontaneously generates a first timer interrupt request Q2 at the same time scale corresponding to the set synchronization period T according to its own clock variables and outputs a first valid level signal S2 through the first port P12, and the first valid level signal S2 is output to the system bus L via the clock signal branch L2; the main control unit M3 also spontaneously generates a first timer interrupt request Q3 at the same time scale corresponding to the set synchronization period T according to its own clock variables and outputs a first valid level signal S3 through the first port P13, and the first valid level signal S3 is output to the system bus L via the clock signal branch L3. Due to the hardware difference of the local timer, under the accumulation effect, the first effective level signals S1, S2 and S3 received by the system bus L exist in a time sequence (such as Figure 5 shown).

[0068] like Figure 6As shown, since the clock signal branches L1, L2 and L3 are all connected to the system bus L, when the earliest first port (for example, P13) outputs the first valid level signal in the timing, the level signal change (taking the falling edge as an example) will be detected at the three second ports, that is, the main controllers M1, M2 and M3 determine that the second timer interrupt request forwarded through the system bus L is received, and the three main control parts M1, M2 and M3 perform synchronous operation to update the clock variables in themselves. The updated clock variable in the main control part is X n = int(X n-1 ÷T+0.5)×T, where X n-1 is the current value of the clock variable, X n is the updated clock variable, T is the set synchronization period T, and int is the integer.

[0069] Since the first valid level signal outputted by the earliest first port is used as the second timer interrupt request detection, for the other two main control units, the clock variable accumulated value at this time has not reached T, that is, the clock variable accumulated value X at this time n-1 It can be slightly less than T, that is, the clock variable corresponding to the main control unit is divided by the set synchronization period T, rounded off and taken as the updated clock variable. The main control unit is configured to output a first valid level signal through the first port, accumulate the time after alignment, and output a second valid level signal through the first port under the condition that the set time length is met, that is, it can be seen that the waveforms on the time axis have been aligned.

[0070] In the above process, the test system uses the clock variable in the fastest main control unit as the alignment basis for synchronization, which can meet the reliable synchronization of clock circuits with a difference of 50%. Although the test system uses the fastest clock as the synchronization basis, it is possible to continuously speed up the clock. However, since the three second ports detect the second timer interrupt request at the same time, the fastest clock also performs synchronization operations for itself. Since the main control units in the test system are equal, there is a lag time difference from issuing the first timer interrupt request to completing the synchronization. This can smooth the system acceleration effect. It has been determined that the synchronized clock has not been accelerated, and the synchronization effect is ideal.

[0071] In some optional implementations of the present application, the set duration is set to half of the synchronization period T. The first port adopts an open-drain output, that is, a resistor R1 is set at the first port P11 to connect to the power supply Vcc, a resistor R2 is set at the first port P12 to connect to the power supply Vcc, and a resistor R3 is set at the first port P13 to connect to the power supply Vcc to provide a controllable effective level signal.

[0072] Step S21: configuring the main control unit to generate a first timer interrupt request at a start time scale corresponding to a set synchronization period according to its own clock variable and output a first valid level signal of a low level to the system bus through a first port.

[0073] Step S22: after the first timer interrupt request is generated and the set duration condition is met, a high-level second valid level signal is output through the first port.

[0074] Alternatively, in some other optional implementations of the present application, the set duration is half of the set synchronization period;

[0075] The synchronization method further comprises the following steps:

[0076] Step S31: configuring the main control unit to generate a first timer interrupt request at the end time scale corresponding to the set synchronization period according to its own clock variable and output a first valid level signal of high level to the system bus through the first port.

[0077] Step S32: after the first timer interrupt request is generated and the set duration condition is met, a second valid level signal of low level is output through the first port.

[0078] In order to improve the accuracy, the main control unit corresponding to the first valid level signal received by the system bus is set as the synchronization reference; after the current round of synchronization is completed, the main control unit that serves as the synchronization reference of this round is set to exit the next round of synchronization control. In this way, different main control units in the test system have the opportunity to serve as the synchronization basis, which can further balance the accuracy of the system clock.

[0079] In the test system, this solution arranges the synchronous clock line and adopts the clock waveform and logical relationship output by each main control unit to form a common contribution mechanism and an equal distribution model of the unified synchronous operation model. It can realize clock synchronization efficiently and simply, and the constructed random exit synchronization contribution mechanism can better balance the clock accuracy. The whole system is simple and efficient, with good consistency and stable and balanced long-term clock accuracy.

[0080] A second aspect of the present invention provides a multi-board distributed clock synchronization device, which is applied to a test system. The test system includes:

[0081] A plurality of test boards, each of which is equipped with a main control unit and a timer, and any main control unit has an independently configured first port and a second port;

[0082] A system bus, the system bus being connected to the plurality of first ports and the second port respectively through a plurality of clock signal branches arranged in parallel;

[0083] The synchronization device 1 comprises:

[0084] A setting module 11, the setting module 11 is configured to set a synchronization time period in the test system;

[0085] A variable configuration module 12, the variable configuration module 12 is configured to set and store clock variables in the main control unit according to a set synchronization period;

[0086] The interrupt generation module 13 is used to configure the main control unit to generate a first timer interrupt request at a time scale corresponding to a set synchronization period according to its own clock variable and output a first valid level signal to the system bus through the first port, and output a second valid level signal through the first port after the first timer interrupt request is generated and under the condition of meeting a set time length; wherein the set time length is less than a set synchronization period;

[0087] A determination module 14, the determination module 14 is configured to determine whether the second port receives a second timer interrupt request forwarded via the system bus through the clock signal branch;

[0088] The updating module 15 is configured to, when the second port receives the second timer interrupt request, the main control unit is configured to output the first valid level signal through the first port, and update the clock variable in the main control unit, and the updated clock variable in the main control unit is X n = int(X n-1 ÷T+0.5)×T, where X n-1 is the current value of the clock variable, X n is the updated clock variable, T is the set synchronization period, and int is the rounding.

[0089] In some optional embodiments of the present application, the set duration is half of the set synchronization period; the interrupt generation module 13 is also used to configure the main control unit to generate a first timer interrupt request at the starting time corresponding to the set synchronization period according to its own clock variable and output a first valid level signal of a low level to the system bus through the first port, and output a second valid level signal of a high level through the first port after the first timer interrupt request is generated and the set duration is met.

[0090] In some optional embodiments of the present application, the set duration is half of the set synchronization period; the interrupt generation module 13 is also used to configure the main control unit to generate a first timer interrupt request at the end time scale corresponding to the set synchronization period according to its own clock variable and output a first valid level signal of high level to the system bus through the first port, and output a second valid level signal of low level through the first port after generating the first timer interrupt request and satisfying the set duration condition.

[0091] In some optional embodiments of the present application, the initial value X0 of the clock variable is accumulated and stored by a timer in the main control unit with an accuracy not greater than half of the set synchronization timing period; the main control unit corresponding to the first first valid level signal received by the system bus is set as the synchronization reference; after this round of synchronization is completed, the main control unit set as the synchronization reference for this round exits the next round of synchronization control.

[0092] The embodiment of the present application also provides a test system, which applies the above-mentioned multi-board distributed clock synchronization method. For the specific steps of the control method of the multi-board distributed clock synchronization method, please refer to the detailed description of the above-mentioned embodiment and the detailed description of the drawings in the specification. No further description is given here, and the test system using the above-mentioned multi-board distributed clock synchronization method can achieve the same technical effect.

[0093] An embodiment of the present application also provides a non-transitory computer-readable storage medium, wherein the computer storage medium stores a computer program for electronic data exchange, and the computer program is executed to implement part or all of the steps of any method recorded in the above method embodiments.

[0094] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0095] In the several embodiments provided in the present application, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are only schematic, such as the division of the above-mentioned units or modules, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical or other forms.

[0096] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one physical space, or may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0097] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0098] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, it is still possible for a person skilled in the art to modify the technical solutions described in the aforementioned embodiments, or to replace some of the technical features therein by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions claimed to be protected by the present invention.

Claims

1. A multi-board distributed clock synchronization method, applied to a test system, the test system comprising: A plurality of test boards, each of which is equipped with a main control unit and a timer, and any of the main control units has a first port and a second port that are independently configured; A system bus, wherein the system bus is connected to the plurality of first ports and the second port respectively through a plurality of clock signal branches arranged in parallel; It is characterized in that the synchronization method comprises the following steps: Set the synchronization period in the test system; Setting and storing clock variables in each of the main control units according to the set synchronization time period; Each of the main control units is configured to generate a first timer interrupt request at the same time scale corresponding to the set synchronization period according to its own clock variable, and when generating the first timer interrupt request, output a first valid level signal to the system bus through its own first port; Each of the main control units is configured to output a second valid level signal through its first port after generating a first timer interrupt request and satisfying a set time period; wherein the set time period is less than a set synchronization period; and to determine whether its second port receives the second timer interrupt request forwarded through the system bus through its own clock signal branch; When the second port of the main control unit receives the second timer interrupt request, the corresponding main control unit is configured to output the first valid level signal through the first port of the main control unit, and simultaneously update the clock variable in the main control unit, and the updated clock variable in the main control unit is ,in is the current value of the clock variable, is the updated clock variable, is the set synchronization period, To round up; The first valid level signal outputted by the earliest first port is used as the second timer interrupt request.

2. The multi-board distributed clock synchronization method according to claim 1, characterized in that: The set duration is half of the set synchronization period; The synchronization method further comprises the following steps: The main control unit is configured to generate a first timer interrupt request at a starting time scale corresponding to the set synchronization period according to its own clock variable and output a first valid level signal of a low level to the system bus through the first port, and after generating the first timer interrupt request and satisfying the set time condition, output a second valid level signal of a high level through the first port.

3. The multi-board distributed clock synchronization method according to claim 1, characterized in that: The set duration is half of the set synchronization period; The synchronization method further comprises the following steps: The main control unit is configured to generate a first timer interrupt request at the end time scale corresponding to the set synchronization period according to its own clock variable and output a first valid level signal of high level to the system bus through the first port, and after generating the first timer interrupt request and satisfying the set time condition, output a second valid level signal of low level through the first port.

4. The multi-board distributed clock synchronization method according to claim 2 or 3, characterized in that: The initial value of the clock variable The timer in the main control unit accumulates and stores the time in units not greater than half of the set synchronization period; The main control unit corresponding to the first effective level signal received by the system bus is set as the synchronization reference; after the current round of synchronization is completed, the main control unit serving as the current round of synchronization reference is set to exit the next round of synchronization control.

5. A multi-board distributed clock synchronization device, applied to a test system, the test system comprising: A plurality of test boards, each of which is equipped with a main control unit and a timer, and any of the main control units has a first port and a second port that are independently configured; A system bus, wherein the system bus is connected to the plurality of first ports and the second port respectively through a plurality of clock signal branches arranged in parallel; Characterized in that the synchronization device comprises: A setting module, the setting module is configured to set a synchronization time period in the test system; A variable configuration module, wherein the variable configuration module is configured to set and store clock variables in each of the main control units according to the set synchronization period; An interrupt generation module, the interrupt generation module is used to configure each of the main control parts to generate a first timer interrupt request on the time scale corresponding to the set synchronization period according to its own clock variable, and output a first valid level signal to the system bus through its own first port when generating the first timer interrupt request, and configure each of the main control parts to output a second valid level signal through its own first port after generating the first timer interrupt request and satisfying a set time length; wherein the set time length is less than a set synchronization period; a determination module, the determination module being configured to determine whether the second port thereof receives a second timer interrupt request forwarded via the system bus via the clock signal branch thereof; An update module, wherein the update module is configured to, when the second port of the update module receives a second timer interrupt request, configure the corresponding main control unit to output a first valid level signal through the first port of the update module, and update a clock variable in the main control unit, wherein the updated clock variable in the main control unit is: ,in is the current value of the clock variable, is the updated clock variable, is the set synchronization period, To round up; The first valid level signal outputted by the earliest first port is used as the second timer interrupt request.

6. The multi-board distributed clock synchronization device according to claim 5, characterized in that: The set duration is half of the set synchronization period; The interrupt generation module is also used to configure the main control unit to generate a first timer interrupt request at the starting time scale corresponding to the set synchronization period according to its own clock variable and output a low-level first valid level signal to the system bus through the first port, and output a high-level second valid level signal through the first port after generating the first timer interrupt request and satisfying the set time condition.

7. The multi-board distributed clock synchronization device according to claim 5, characterized in that: The set duration is half of the set synchronization period; The interrupt generation module is also used to configure the main control unit to generate a first timer interrupt request at the end time scale corresponding to the set synchronization period according to its own clock variable and output a first valid level signal of high level to the system bus through the first port, and output a second valid level signal of low level through the first port after generating the first timer interrupt request and satisfying the set time condition.

8. The multi-board distributed clock synchronization device according to claim 6 or 7, characterized in that: The initial value of the clock variable The timer in the main control unit accumulates and stores the time with an accuracy not greater than half of the set synchronization period; The main control unit corresponding to the first effective level signal received by the system bus is set as the synchronization reference; after the current round of synchronization is completed, the main control unit serving as the current round of synchronization reference is set to exit the next round of synchronization control.

9. A testing system, characterized in that: Apply the multi-board distributed clock synchronization method as described in any one of claims 1 to 4.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: The computer program is executed to implement the multi-board distributed clock synchronization method as described in any one of claims 1 to 4.

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