A verification method, system, device and storage medium of a to-be-verified design apparatus

Abstract

This application discloses a verification method, system, device, and storage medium for a device under test (DUT), applied in the field of testing technology. The method includes: configuring N verification tasks for N operating modes of the DUT, with each verification task configured with a random delay; placing the N verification tasks into a first queue; selecting one verification task from the first queue; determining the cumulative number i of times the currently selected verification task has been selected from the first queue, and sending its i-th step to the DUT; after the DUT completes the execution of this step, after the random delay of the verification task, returning the verification task to the first queue, and repeating the operation of selecting one verification task from the first queue until all steps of each verification task have been executed by the DUT; and determining the verification result of the DUT. Applying the scheme of this application can effectively realize the verification of the DUT, improve the verification efficiency, and avoid errors.

Description

Technical Field

[0001] This invention relates to the field of testing technology, and in particular to a verification method, system, device, and storage medium for a design device to be verified. Background Technology

[0002] When a DUT (Design Under Test) supports multiple operating modes, the processing and response of the DUT to each operating mode are independent of each other, and it only operates in one mode at a time. That is, the operation steps of different modes are required to not interfere with each other.

[0003] Therefore, for functional verification of the DUT, external stimuli are required to randomly input the steps of each mode into the DUT. Currently, in actual DUT functional verification, staff write the steps for each mode and then randomly shuffle them. Because staff need to randomly shuffle the steps for each mode, the coding process is prone to errors and is time-consuming. Taking two modes as an example, when testing mode A of the DUT, the code sent to the DUT includes steps 1, 2, and 3, while when testing mode B, the code sent to the DUT includes steps 4, 5, and 6. For example, in one scenario, after manually writing the code and randomly shuffling the steps, the code might be: Step 1 - Step 4 - Step 2 - Step 6 - Step 5. Here, two coding errors occur: firstly, step 3 of mode A is omitted, and secondly, step 6 of mode B is preceded by step 5. Furthermore, in practical applications, the time-consuming process of manually writing code is not conducive to multi-round functional verification of the DUT, resulting in insufficient independent working tests of the DUT in multiple modes, low coverage of manually randomly shuffling operation steps, and difficulty in discovering hidden problems in the DUT.

[0004] In summary, how to effectively verify the DUT, improve verification efficiency, and avoid errors is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a verification method, system, device, and storage medium for a device under test (DUT) to effectively verify the DUT, improve verification efficiency, and avoid errors.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0007] A verification method for a device design to be verified includes:

[0008] For each of the N operating modes of the device to be verified, N corresponding verification tasks are configured, and each verification task is configured with a random delay; N is a positive integer and N≥2;

[0009] Place the N verification tasks into a preset first-in-first-out queue;

[0010] When at least one verification task exists in the first queue, one verification task is selected from the first queue;

[0011] For the currently selected verification task, determine the cumulative number of times i that the verification task was selected from the first queue during this verification process, and send the i-th step of the verification task to the design device to be verified so that the design device to be verified can execute it.

[0012] After the design to be verified completes the received steps, after a random delay of the currently selected verification task, the verification task is put back into the first queue. After the design to be verified completes the received steps, the operation of selecting one verification task from the first queue is returned to be executed until each step of each verification task is completed by the design to be verified.

[0013] The verification results of the design device to be verified are determined.

[0014] In one implementation, placing the N verification tasks into a preset first-in-first-out queue includes:

[0015] Place the N verification tasks into a preset first-in-first-out queue;

[0016] Among them, the N verification tasks simultaneously start their own random delay timers, and for any one of the N verification tasks, after the random delay configured for the verification task, the verification task is placed into a preset first-in-first-out first queue.

[0017] In one implementation, placing the N verification tasks into a preset first-in-first-out queue includes:

[0018] According to the task number in ascending or descending order, the N verification tasks are sequentially placed into a preset first-in-first-out queue.

[0019] In one implementation, determining the verification result of the design device to be verified includes:

[0020] When the verification results of all N operating modes of the design device to be verified are passed, the verification result of the design device to be verified is determined to be passed;

[0021] When the verification result of at least one of the N operating modes of the design device to be verified fails, the verification result of the design device to be verified is determined to be failed.

[0022] In one implementation, N verification tasks are configured for each of the N operating modes of the device to be verified, and a random delay is configured for each verification task, including:

[0023] Using the first language, N corresponding verification tasks are configured for the N working modes of the device to be verified, and a random delay is configured for each verification task.

[0024] The N verification tasks are placed into a preset first-in-first-out queue, including:

[0025] N threads are initiated using the first language to schedule N verification tasks respectively, and the N verification tasks are placed into a preset first-in-first-out queue.

[0026] In one implementation, selecting one verification task from the first queue includes:

[0027] Communication between the N threads is established using the first language, and a first key is set.

[0028] One verification task is selected from the head of the first queue, and the thread corresponding to the verification task obtains the first key to allow the thread to send the i-th step of the verification task to the design device to be verified.

[0029] In one implementation, it further includes:

[0030] When two or more verification tasks are detected to need to be placed in the first queue at the same time, the set conflict resolution mechanism is triggered so that each of the conflicting verification tasks is placed into the first queue in sequence.

[0031] In one implementation, when two or more verification tasks are detected to need to be placed in the first queue simultaneously, a pre-defined conflict resolution mechanism is triggered so that the conflicting verification tasks are placed into the first queue sequentially, including:

[0032] When two or more of the verification tasks are detected to need to be placed in the first queue at the same time, the set conflict resolution mechanism is triggered so that each of the conflicting verification tasks restarts its own random delay timer and is placed in the first queue after its own random delay.

[0033] In one implementation, it further includes:

[0034] Each time the verification result of the design device to be verified is determined to be passed, the design device to be verified is re-verified until the number of verification rounds of the design device to be verified reaches the set round threshold.

[0035] In particular, whenever the design device to be verified is re-verified, the random delay of each verification task is randomly updated.

[0036] A verification system for a design device to be verified includes:

[0037] The verification task random delay allocation module is used to configure N corresponding verification tasks for N working modes of the design device to be verified, and to configure 1 random delay for each verification task; N is a positive integer and N≥2;

[0038] The initial queue placement module is used to place the N verification tasks into a preset first-in-first-out first queue;

[0039] The verification task selection module is used to select one verification task from the first queue when there is at least one verification task in the first queue;

[0040] The sending module is used to determine, for the currently selected verification task, the cumulative number of times the verification task has been selected from the first queue during the current verification process, i, and send the i-th step of the verification task to the design device to be verified so that the design device to be verified can execute it;

[0041] The verification task return module is used to return the verification task to the first queue after the design device to be verified has completed the execution of the received steps, after a random delay of the currently selected verification task, and to return to trigger the verification task selection module after the design device to be verified has completed the execution of the received steps, until each step of each verification task has been completed by the design device to be verified.

[0042] The verification result determination module is used to determine the verification result of the design device to be verified.

[0043] A verification device for a design apparatus to be verified, comprising:

[0044] Memory, used to store computer programs;

[0045] A processor for executing the computer program to implement the steps of the verification method for the design device to be verified as described above.

[0046] A computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the verification method for a design device to be verified as described above.

[0047] The technical solution provided by the embodiments of this invention can automatically verify the design device under test, with high execution efficiency and low error rate. In this application's solution, firstly, N verification tasks are configured for each of the N operating modes of the design device under test. It can be seen that at this point, the random crossover of steps under different verification tasks has not yet occurred; that is, the configured N verification tasks are independent and complete, thus reducing the likelihood of errors. To achieve random crossover of steps under different verification tasks, this application's solution does not involve manual shuffling as in traditional solutions, but instead configures a random delay for each verification task. After configuring a random delay for each verification task, the N verification tasks can be placed into a first queue, which is a preset first-in-first-out queue. Since only one verification task is selected from the first queue each time, it ensures that the design device under test will only operate in one operating mode at any given time. Each time a verification task is selected from the first queue, the cumulative number of times (i) that the task has been selected from the first queue during this verification process is determined. The i-th step of this verification task is then sent to the device under test for execution. It can be seen that i gradually increases from 1, meaning that for any given working mode, the steps of the verification task corresponding to that mode are sent to the device under test sequentially, starting from step 1, without error. After the device under test completes the execution of the received steps, a random delay is applied to the currently selected verification task before it is returned to the first queue. Each verification task is configured with one random delay. Therefore, through this random delay mechanism, the steps of N verification tasks are randomly and alternately sent to the device under test. Since manual shuffling is not required, errors are less likely, and efficiency is high.

[0048] In summary, the solution proposed in this application can effectively verify the design device to be verified, improve the verification efficiency, and avoid errors. Attached Figure Description

[0049] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0050] Figure 1 This is a flowchart illustrating the implementation of a verification method for a design device to be verified according to the present invention.

[0051] Figure 2 This is a schematic diagram illustrating the random intersection of steps for implementing different verification tasks in one specific embodiment of the present invention;

[0052] Figure 3 This is a schematic diagram of the structure of a verification system for a design device to be verified in this invention;

[0053] Figure 4 This is a schematic diagram of the structure of a verification device for a design to be verified in this invention;

[0054] Figure 5 This is a schematic diagram of the structure of a computer-readable storage medium according to the present invention. Detailed Implementation

[0055] The core of this invention is to provide a verification method for a design device to be verified, which can effectively realize the verification of the design device, improve the verification efficiency, and avoid errors.

[0056] To enable those skilled in the art to better understand the present invention, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0057] Please refer to Figure 1 , Figure 1 This is a flowchart illustrating an implementation method for verifying a design device to be verified according to the present invention. The verification method for the design device to be verified may include the following steps:

[0058] Step S101: Configure N corresponding verification tasks for the N operating modes of the device to be verified, and configure one random delay for each verification task. N is a positive integer and N≥2.

[0059] The device to be verified (DUT) can also be called a DUT or a test design module. When performing simulation verification of the DUT, a functional excitation signal needs to be generated externally and input into the DUT. Then, the output signal at the DUT's output terminal is observed to determine whether it is correct, i.e., whether the output signal meets expectations, thereby judging whether the DUT's function meets the design requirements.

[0060] The design device to be verified may include N operating modes, where N is a positive integer not less than 2. For each operating mode of the design device to be verified, a corresponding verification task can be configured to implement the test of that operating mode, and the configured verification task may include one or more steps.

[0061] Furthermore, it is understandable that the specific content of the configured verification task can differ for different working modes, and the number of steps included in the configured verification task can also differ for different working modes. For example, in one scenario, for working mode A, the configured verification task corresponding to working mode A is called verification task A. Verification task A may include three steps executed sequentially, referred to as steps A1, A2, and A3. For working mode B, the configured verification task corresponding to working mode B is called verification task B. Verification task B may include five steps executed sequentially, referred to as steps B1, B2, B3, B4, and B5.

[0062] After configuring N corresponding verification tasks for the N operating modes of the device to be verified, in order to achieve random overlap of steps in different verification tasks, the scheme of this application requires configuring one random delay for each verification task. That is, for each verification task, one delay needs to be configured, and the delay of each verification task is randomly configured. Of course, in practical applications, a delay range is usually set so that the configured random delay needs to be within this range to avoid the situation where the execution time of the scheme of this application is too long due to the value of the random delay being too large.

[0063] Step S102: Place N verification tasks into the preset first queue of first in and first out.

[0064] In this application's solution, a first queue needs to be pre-defined. The first queue is a first-in-first-out queue, meaning that for different verification tasks in the first queue, the verification task that was placed into the first queue first will be retrieved first.

[0065] To verify N working modes, all N verification tasks need to be placed in the first queue. The specific placement method can be set and adjusted according to actual needs, as long as all N verification tasks are placed in the first queue.

[0066] For example, in one specific embodiment of the present invention, step S102 may include: placing N verification tasks into a preset first-in-first-out queue; wherein, the N verification tasks simultaneously start their own random delay timing, and for any one of the N verification tasks, after the random delay configured for the verification task has elapsed, the verification task is placed into the preset first-in-first-out queue.

[0067] This implementation takes into account that since each verification task is configured with a random delay, when placing N verification tasks into the first queue, the placement can also be achieved based on these N random delays. That is, the N verification tasks start their own random delay timing at the same time. For any one of the N verification tasks, after the random delay configured for that verification task has elapsed, the verification task can be placed into the preset first queue.

[0068] For example, in one scenario, N corresponding verification tasks are configured for N operating modes of the device to be verified. The random delay configured for verification task A is 2 seconds, and the random delay configured for verification task B is 5 seconds. Then, 2 seconds after triggering step S102, verification task A is placed into the first queue, and 3 seconds later, verification task B is placed into the first queue.

[0069] As can be seen, in this implementation method, placing N verification tasks into the first queue based on N random delays helps to ensure the randomness of the overlapping steps in implementing different verification tasks in the future.

[0070] For example, in one specific embodiment of the present invention, step S102 may include:

[0071] N verification tasks are placed into a pre-defined first-in-first-out queue in ascending or descending order of their task numbers.

[0072] In this implementation, N verification tasks can be sequentially placed into a pre-defined first-in-first-out queue according to their task numbers, either in ascending or descending order. For example, in one scenario, verification task A, verification task B, verification task C, and verification task D are sequentially placed into the first queue.

[0073] As can be seen, if this implementation method is adopted, when selecting verification tasks from the first queue, the selected verification tasks will conform to the order of task numbers from smallest to largest or from largest to smallest for a period of time at the beginning. For example, in the case described above, after verification tasks A, B, C, and D are placed into the first queue in sequence, steps A1 of task A, B1 of task B, C1 of task C, and D1 of task D will be sent to the device to be verified for execution in sequence. Of course, after this, due to the existence of random delay, the steps sent to the device to be verified for execution are random, that is, the random crossover of steps of different verification tasks is realized.

[0074] As described above, this implementation method is less effective than the previous method in terms of the randomness of the steps involved in implementing different verification tasks. However, when step S102 is triggered, this method can directly place all N verification tasks into the first queue without waiting, which helps reduce the execution time of the scheme. Although some sacrifice is made in the randomness of the steps involved in implementing different verification tasks, the impact is minor. In practical applications, either this implementation method or the previous method can be selected as needed.

[0075] Step S103: When there is at least one verification task in the first queue, select one verification task from the first queue.

[0076] To ensure that the device under test operates in only one mode at any given time, only one verification task will be selected from the first queue at a time. It can be understood that for a verification task to be selected from the first queue, there must be at least one verification task in the first queue.

[0077] After step S102 is triggered, step S103 can be executed for the first time as long as there is at least one verification task in the first queue. That is, after step S102 is triggered, it is not necessary to wait for all N verification tasks to be placed in the preset first-in-first-out first queue; rather, step S103 can be triggered for the first time as long as there is at least one verification task in the first queue, i.e., one verification task is selected from the first queue for the first time. In subsequent implementation, step S103 will be triggered again whenever a step of a verification task is completed by the device to be verified.

[0078] Since the first queue is a first-in-first-out queue, the verification tasks placed in the first queue will be taken out first. Therefore, when selecting a verification task from the first queue, the selection is made from the head of the first queue. However, if a verification task needs to be placed into the first queue, it is placed into the tail of the first queue.

[0079] Step S104: For the currently selected verification task, determine the cumulative number of times i of the verification task was selected from the first queue during this verification process, and send the i-th step of the verification task to the design device to be verified so that the design device to be verified can execute it.

[0080] A verification task may include one or more steps. For example, verification task A includes three steps, referred to as steps A1, A2, and A3. While steps from different verification tasks can overlap during the verification of the device to be verified, the order of steps within the same verification task cannot be reversed. That is, in this example, steps A2 and A3 cannot be sent to the device to be verified before step A1, and step A3 cannot be sent to the device to be verified before step A2; they should be executed in the order of step A1-step A2-step A3.

[0081] Therefore, in this embodiment, for the currently selected verification task, the cumulative number of times i of the verification task was selected from the first queue during this verification process will be determined, and then the i-th step of the verification task will be sent to the design device to be verified so that the design device to be verified can execute it.

[0082] Understandably, for any given verification task, when it is first selected from the first queue, the cumulative count i = 1, and the first step of the verification task is sent to the design device to be verified for execution. When the verification task is selected from the first queue a second time, the cumulative count i = 2, and the second step of the verification task is sent to the design device to be verified for execution. When the verification task is selected from the first queue a third time, the cumulative count i = 3, and the third step of the verification task is sent to the design device to be verified for execution. This process continues until all steps of the verification task have been sent to the design device to be verified for execution. At this point, the verification task will not be returned to the first queue.

[0083] For any given verification task, the cumulative number of times i selected from the first queue for that verification task starts from 1 and increments. Therefore, each step of the verification task is sent to the design device to be verified in the order of the steps, and there will be no situation where the steps are reversed or omitted due to manual coding, which ensures the accuracy of the solution.

[0084] Step S105: After the device to be verified has completed the execution of the received steps, after a random delay of the currently selected verification task, the verification task is put back into the first queue. After the device to be verified has completed the execution of the received steps, the operation of step S103 is returned to be executed until all steps of each verification task have been completed by the device to be verified.

[0085] After a step of a verification task is sent to the device to be verified, the device can execute the received step. Once the device has completed executing the received step, it can immediately return to step S103 to select a new verification task from the first queue. When all steps of each verification task have been executed by the device to be verified, there is no need to return to step S103; instead, step S106 is triggered.

[0086] To achieve random crossover of steps in different verification tasks, the solution in this application sends a step of a verification task to the device under test. The device then executes the received step. However, upon completion of the received step, the verification task is not immediately returned to the first queue; instead, it waits for a period of time, which is the random delay configured for that verification task. Only after this random delay has elapsed is the verification task returned to the first queue. It should be noted that for any given verification task, if all steps of that task have been sent to the device under test for execution, it is not necessary to return the task to the first queue. That is, if the cumulative number of times the verification task has been selected from the first queue reaches the total number of steps for that verification task, it is not necessary to return the task to the first queue.

[0087] See also Figure 2 This is a schematic diagram illustrating the random crossover of steps in different verification tasks in one specific implementation. It can be seen that at the same simulation moment, only one step of a verification task will be sent to the device to be verified for execution, and random crossover between the steps of different verification tasks is achieved. Figure 2 The shaded area indicates that a certain step of a verification task is sent to the device to be verified for execution.

[0088] Step S106: Determine the verification results of the design device to be verified.

[0089] Once each step of each verification task has been completed by the design device to be verified, the verification result of the design device to be verified can be determined based on the output data of the design device to be verified during this verification process.

[0090] For example, in one specific embodiment of the present invention, step S106 may include:

[0091] When the verification results of all N operating modes of the device to be verified are passed, the verification result of the device to be verified is determined to be passed.

[0092] The verification result of the design device is determined to be unsuccessful if the verification result of at least one of the N operating modes of the device to be verified fails.

[0093] This implementation takes into account that if the verification results of all N operating modes of the device under test pass, that is, the verification results of the device under test meet expectations for each operating mode, then the verification result of the device under test can be determined to be pass. Conversely, if the verification result of at least one operating mode fails, then the verification result of the device under test can be determined to be fail. This implementation method is also a commonly used implementation method in practical applications.

[0094] In one specific embodiment of the present invention, step S101 may include:

[0095] Using the first language, configure N corresponding verification tasks for the N working modes of the device to be verified, and configure 1 random delay for each verification task;

[0096] Step S102 may include:

[0097] N threads are initiated using the first language to schedule N verification tasks, and the N verification tasks are placed into a pre-defined first-in-first-out queue.

[0098] In this application's solution, N verification tasks need to be configured for each of the N operating modes of the device to be verified. However, a random delay is not configured for each verification task. In practical applications, this can be achieved using a first-language programming language. Furthermore, the first-language programming language supports multiple threads, each executing independently without interference. This allows the N verification tasks of this application to be scheduled separately based on the N threads initiated by the first-language programming language.

[0099] The specific type of the first language can be set and adjusted as needed, as long as the solution of this application can be achieved through the first language.

[0100] For example, in a specific scenario, the primary language is SystemVerilog, which makes it relatively easy to construct randomized test stimuli and initiate and execute multiple threads, each executing independently without affecting the others. SystemVerilog has specific communication methods between threads, such as events, which can ensure the sequential execution of threads; semaphores, which can handle conflicts in resource sharing between threads; and mailboxes, which can achieve synchronized data transmission between threads.

[0101] In one specific embodiment of the present invention, step S103 may include:

[0102] Establish communication between N threads using the first language and set the first key;

[0103] One verification task is selected from the head of the first queue, and the thread corresponding to the verification task obtains the first key to allow the thread to send the i-th step of the verification task to the design device to be verified.

[0104] As described above, in the solution of this application, it is necessary to ensure that the device to be verified only operates in a certain mode at any given time. Therefore, only one verification task will be selected from the first queue at any given time. In this implementation, this is achieved based on a first key, ensuring that only one verification task is selected from the first queue at any given time.

[0105] Taking SystemVerilog as the primary language again, a semaphore can be created at the task initiation level using SystemVerilog, and a key can be assigned to this semaphore—the first key in this implementation. When selecting a verification task from the first queue, only the thread corresponding to the verification task at the head of the queue can obtain the first key. The thread that obtains the first key can then send the i-th step of the verification task to the device to be verified. After the device to be verified completes this step, it needs to return the first key so that other threads can obtain it.

[0106] In one specific embodiment of the present invention, it may further include:

[0107] Each time the verification result of the device to be verified is determined to be passed, the device to be verified is re-verified until the number of verification rounds of the device to be verified reaches the set round threshold.

[0108] In particular, whenever the device to be verified is re-verified, the random delay of each verification task is randomly updated.

[0109] This implementation takes into account that in order to improve the coverage of the verification, that is, to improve the sufficiency of the verification, the design device to be verified needs to be verified in multiple rounds. Therefore, in this implementation, whenever the verification result of the design device to be verified is determined to be passed, the design device to be verified will be verified again until the number of rounds of verification of the design device to be verified reaches the set round threshold.

[0110] Furthermore, in this embodiment, whenever the device to be verified is re-verified, the random delay of each verification task is randomly updated, so that the steps of each verification task are randomly interleaved in different rounds of verification for the device to be verified, thereby improving the sufficiency of verification.

[0111] In one specific embodiment of the present invention, it may further include:

[0112] When two or more verification tasks are detected that need to be placed in the first queue at the same time, the set conflict resolution mechanism is triggered so that the verification tasks that are in conflict are placed in the first queue in sequence.

[0113] During the implementation of the scheme, there may be situations where two or more verification tasks need to be returned to the first queue at the same time. For example, in one scenario, when executing step S102, the aforementioned scheme of simultaneously activating the random delay of each of the N verification tasks is adopted. If two or more verification tasks have the same random delay, their random delays will end at the same time, which means that these verification tasks need to be placed into the first queue simultaneously. In this case, a conflict occurs between these verification tasks.

[0114] For example, when executing step S105, after the device to be verified has completed the steps of a certain verification task, and after the random delay of the verification task, the verification task needs to be put back into the first queue. At this time, there may also be other verification tasks that have just finished their random delays and need to be put into the first queue, which may cause a conflict.

[0115] To address this, this implementation method includes a conflict resolution mechanism. This mechanism ensures that conflicting verification tasks are placed in the first queue sequentially. Of course, the specific method of conflict resolution can be set and selected according to actual needs, as long as it can resolve the conflict.

[0116] For example, in one specific embodiment of the present invention, when two or more verification tasks are detected to need to be placed in the first queue simultaneously, a pre-defined conflict resolution mechanism is triggered so that the conflicting verification tasks are placed in the first queue sequentially. This may specifically include:

[0117] When two or more verification tasks are detected to need to be added to the first queue simultaneously, the pre-defined conflict resolution mechanism is triggered. This causes each conflicting verification task to restart its own random delay timer and be added to the first queue after its own random delay.

[0118] In this implementation, if two or more verification tasks need to be placed in the first queue simultaneously, the conflict resolution mechanism involves restarting the random delay timer for each of these verification tasks. Only after their respective random delays have elapsed will they be placed in the first queue. It is understandable that if conflicts may still occur after restarting their random delay timers, the conflict resolution mechanism will be triggered again.

[0119] For example, in one specific implementation, when two or more verification tasks are detected that need to be placed in the first queue at the same time, the conflict resolution mechanism is to randomly set the order of these verification tasks and place them in the first queue.

[0120] The technical solution provided by the embodiments of this invention can automatically verify the design device under test, with high execution efficiency and low error rate. In this application's solution, firstly, N verification tasks are configured for each of the N operating modes of the design device under test. It can be seen that at this point, the random crossover of steps under different verification tasks has not yet occurred; that is, the configured N verification tasks are independent and complete, thus reducing the likelihood of errors. To achieve random crossover of steps under different verification tasks, this application's solution does not involve manual shuffling as in traditional solutions, but instead configures a random delay for each verification task. After configuring a random delay for each verification task, the N verification tasks can be placed into a first queue, which is a preset first-in-first-out queue. Since only one verification task is selected from the first queue each time, it ensures that the design device under test will only operate in one operating mode at any given time. Each time a verification task is selected from the first queue, the cumulative number of times (i) that the task has been selected from the first queue during this verification process is determined. The i-th step of this verification task is then sent to the device under test for execution. It can be seen that i gradually increases from 1, meaning that for any given working mode, the steps of the verification task corresponding to that mode are sent to the device under test sequentially, starting from step 1, without error. After the device under test completes the execution of the received steps, a random delay is applied to the currently selected verification task before it is returned to the first queue. Each verification task is configured with one random delay. Therefore, through this random delay mechanism, the steps of N verification tasks are randomly and alternately sent to the device under test. Since manual shuffling is not required, errors are less likely, and efficiency is high.

[0121] In summary, the solution proposed in this application can effectively verify the design device to be verified, improve the verification efficiency, and avoid errors.

[0122] Corresponding to the above method embodiments, this invention also provides a verification system for a design device to be verified, which can be referred to in conjunction with the above.

[0123] See Figure 3 The diagram shown is a structural schematic of a verification system for a design device to be verified according to the present invention, comprising:

[0124] The verification task random delay allocation module 301 is used to configure N corresponding verification tasks for the N working modes of the design device to be verified, and to configure 1 random delay for each verification task; N is a positive integer and N≥2;

[0125] The initial queue placement module 302 is used to place N verification tasks into a preset first-in-first-out first queue;

[0126] The verification task selection module 303 is used to select one verification task from the first queue when there is at least one verification task in the first queue.

[0127] The sending module 304 is used to determine, for the currently selected verification task, the cumulative number of times i was selected from the first queue during the current verification process, and send the i-th step of the verification task to the design device to be verified so that the design device to be verified can execute it.

[0128] The verification task return module 305 is used to return the verification task to the first queue after the design device to be verified has completed the execution of the received steps, after a random delay of the currently selected verification task, and return to the trigger verification task selection module 303 after the design device to be verified has completed the execution of the received steps, until all steps of each verification task have been executed by the design device to be verified.

[0129] The verification result determination module 306 is used to determine the verification result of the design device to be verified.

[0130] In one specific embodiment of the present invention, the initial queue placement module 302 is used for:

[0131] Place N verification tasks into a pre-defined first-in-first-out queue;

[0132] Among them, the N verification tasks simultaneously start their own random delay timers, and for any one of the N verification tasks, after the random delay configured for the verification task, the verification task is placed into a preset first-in-first-out first queue.

[0133] In one specific embodiment of the present invention, the initial queue placement module 302 is used for:

[0134] N verification tasks are placed into a pre-defined first-in-first-out queue in ascending or descending order of their task numbers.

[0135] In one specific embodiment of the present invention, the verification result determination module 306 is used for:

[0136] When the verification results of all N operating modes of the device to be verified are passed, the verification result of the device to be verified is determined to be passed.

[0137] The verification result of the design device is determined to be unsuccessful if the verification result of at least one of the N operating modes of the device to be verified fails.

[0138] In one specific embodiment of the present invention, the verification task random delay allocation module 301 is used for:

[0139] Using the first language, configure N corresponding verification tasks for the N working modes of the device to be verified, and configure 1 random delay for each verification task;

[0140] Initial queue insertion module 302 is used for:

[0141] N threads are initiated using the first language to schedule N verification tasks, and the N verification tasks are placed into a pre-defined first-in-first-out queue.

[0142] In one specific embodiment of the present invention, the verification task selection module 303 is used for:

[0143] Establish communication between N threads using the first language and set the first key;

[0144] One verification task is selected from the head of the first queue, and the thread corresponding to the verification task obtains the first key to allow the thread to send the i-th step of the verification task to the design device to be verified.

[0145] In one specific embodiment of the present invention, a repeat execution module is further included, for:

[0146] Each time the verification result of the device to be verified is determined to be passed, the device to be verified is re-verified until the number of verification rounds of the device to be verified reaches the set round threshold.

[0147] In particular, whenever the device to be verified is re-verified, the random delay of each verification task is randomly updated.

[0148] In one specific embodiment of the present invention, a conflict resolution module is further included, for:

[0149] When two or more verification tasks are detected that need to be placed in the first queue at the same time, the set conflict resolution mechanism is triggered so that the verification tasks that are in conflict are placed in the first queue in sequence.

[0150] In one specific embodiment of the present invention, the conflict resolution module is specifically used for:

[0151] When two or more verification tasks are detected to need to be placed in the first queue at the same time, the set conflict resolution mechanism is triggered so that each verification task that is in conflict restarts its own random delay timer and is placed in the first queue after its own random delay.

[0152] Corresponding to the above methods and system embodiments, this invention also provides a verification device for a design device to be verified and a computer-readable storage medium, which can be referred to in conjunction with the above.

[0153] See also Figure 4 The verification equipment for the design device to be verified may include:

[0154] Memory 401 is used to store computer programs;

[0155] Processor 402 is used to execute a computer program to implement the steps of the verification method for the design device to be verified as described above.

[0156] See also Figure 5 The computer-readable storage medium 50 stores a computer program 51, which, when executed by a processor, implements the steps of the verification method for the device to be verified as described above. The computer-readable storage medium 50 referred to herein includes random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0157] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0158] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0159] This article uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the protection scope of the present invention.

Claims

1. A verification method of a design device to be verified, characterized by, include: For each of the N operating modes of the device to be verified, N corresponding verification tasks are configured, and each verification task is configured with a random delay. N is a positive integer and N≥2; Place the N verification tasks into a preset first-in-first-out queue; When at least one verification task exists in the first queue, one verification task is selected from the first queue; For the currently selected verification task, determine the cumulative number of times i that the verification task was selected from the first queue during this verification process, and send the i-th step of the verification task to the design device to be verified so that the design device to be verified can execute it. After the design to be verified completes the received steps, after a random delay of the currently selected verification task, the verification task is put back into the first queue. After the design to be verified completes the received steps, the operation of selecting one verification task from the first queue is returned until each step of each verification task is completed by the design to be verified. The verification results of the design device to be verified are determined; It also includes: whenever the verification result of the design device to be verified is determined to be passed, the design device to be verified is re-verified until the number of rounds of verification of the design device to be verified reaches a set round threshold. In particular, whenever the design device to be verified is re-verified, the random delay of each verification task is randomly updated.

2. The verification method of a design under verification device according to claim 1, wherein, The step of placing the N verification tasks into a preset first-in-first-out queue includes: Place the N verification tasks into a preset first-in-first-out queue; Among them, the N verification tasks simultaneously start their own random delay timers, and for any one of the N verification tasks, after the random delay configured for the verification task, the verification task is placed into a preset first-in-first-out first queue.

3. The verification method of a design under verification device according to claim 1, wherein, The step of placing the N verification tasks into a preset first-in-first-out queue includes: According to the task number in ascending or descending order, the N verification tasks are sequentially placed into a preset first-in-first-out queue.

4. The verification method of a design under verification device according to claim 1, wherein, Determining the verification result of the design device to be verified includes: When the verification results of all N operating modes of the design device to be verified are passed, the verification result of the design device to be verified is determined to be passed; When the verification result of at least one of the N operating modes of the design device to be verified fails, the verification result of the design device to be verified is determined to be failed.

5. The verification method of a design under verification device according to claim 1, wherein, For each of the N operating modes of the device to be verified, N corresponding verification tasks are configured, and each verification task is configured with a random delay, including: Using the first language, N corresponding verification tasks are configured for the N working modes of the device to be verified, and a random delay is configured for each verification task. The N verification tasks are placed into a preset first-in-first-out queue, including: N threads are initiated using the first language to schedule N verification tasks respectively, and the N verification tasks are placed into a preset first-in-first-out queue.

6. The verification method of a design under verification device according to claim 5, wherein, Select one verification task from the first queue, including: Communication between the N threads is established using the first language, and a first key is set. One verification task is selected from the head of the first queue, and the thread corresponding to the verification task obtains the first key to allow the thread to send the i-th step of the verification task to the design device to be verified.

7. The verification method of a design under verification device according to claim 1, wherein, Also includes: When two or more verification tasks are detected to need to be placed in the first queue at the same time, the set conflict resolution mechanism is triggered so that each of the conflicting verification tasks is placed into the first queue in sequence.

8. The verification method of a design under verification device according to claim 7, wherein, When two or more verification tasks are detected to need to be placed in the first queue simultaneously, a pre-defined conflict resolution mechanism is triggered so that the conflicting verification tasks are placed into the first queue sequentially, including: When two or more of the verification tasks are detected to need to be placed in the first queue at the same time, the set conflict resolution mechanism is triggered so that each of the conflicting verification tasks restarts its own random delay timer and is placed in the first queue after its own random delay.

9. A verification system for a design device to be verified, characterized in that, include: The verification task random delay allocation module is used to configure N corresponding verification tasks for N working modes of the design device to be verified, and to configure 1 random delay for each verification task; N is a positive integer and N≥2; The initial queue placement module is used to place the N verification tasks into a preset first-in-first-out first queue; The verification task selection module is used to select one verification task from the first queue when there is at least one verification task in the first queue; The sending module is used to determine, for the currently selected verification task, the cumulative number of times the verification task has been selected from the first queue during the current verification process, i, and send the i-th step of the verification task to the design device to be verified so that the design device to be verified can execute it; The verification task return module is used to return the verification task to the first queue after the design device to be verified has completed the execution of the received steps, after a random delay of the currently selected verification task, and to return to trigger the verification task selection module after the design device to be verified has completed the execution of the received steps, until each step of each verification task has been completed by the design device to be verified. The verification result determination module is used to determine the verification result of the design device to be verified; It also includes a repetitive execution module for: Each time the verification result of the device to be verified is determined to be passed, the device to be verified is re-verified until the number of verification rounds of the device to be verified reaches the set round threshold. In particular, whenever the device to be verified is re-verified, the random delay of each verification task is randomly updated.

10. A verification apparatus of a design apparatus to be verified, characterized by comprising: include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the verification method for the design device to be verified as claimed in any one of claims 1 to 8.

11. A computer readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the verification method for the design device to be verified as described in any one of claims 1 to 8.

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