A PWM dimming circuit, a control chip and an LED driving power supply

Abstract

The application discloses a PWM dimming circuit, a control chip and an LED driving power supply, and relates to the technical field of PWM dimming, wherein the PWM conversion circuit in the dimming circuit is used for converting an input PWM dimming signal into a duty cycle current signal; the output current sampling circuit is connected with the PWM conversion circuit and is used for converting the duty cycle current signal into an output current sampling signal; the error amplifier circuit is connected with the output current sampling circuit and is used for outputting an error amplification current signal and an error amplification voltage signal according to the output current sampling signal and a reference voltage; the voltage-controlled oscillator circuit is connected with the error amplifier circuit and is used for outputting a frequency control signal according to the error amplification current signal; and the second comparator is used for outputting a peak current control signal according to the error amplification voltage signal. The application realizes the PWM non-frequency flash dimming function and eliminates the ripple caused by the PWM signal on the output current.

Description

Technical Field

[0001] The present invention relates to the technical field of PWM dimming, and in particular to a PWM dimming circuit, a control chip and an LED driving power supply. Background Art

[0002] LED lighting has seen significant development due to its advantages, including high brightness, high efficiency, and long lifespan. Smart LED lighting applications are expanding, and PWM dimming technology has become the primary control method for these devices. This technology uses a PWM signal to directly chop the output current of the driver. When the PWM signal is high, the driver outputs current; when the PWM signal is low, the output current is cut off. This allows the on- and off-durations of the driver output current to be adjusted based on the PWM duty cycle, thereby adjusting the average current in the LED load and, consequently, the brightness of the LED load. This PWM dimming method is relatively simple and easy to implement, but it does have a drawback: the LED load output current exhibits ripple at the same frequency as the PWM signal. Due to the low frequency of the PWM signal, this can cause a noticeable flicker in the human eye, which can cause eye fatigue, damage visual health, and negatively impact the user experience. Summary of the Invention

[0003] The purpose of the present invention is to provide a PWM dimming circuit, a control chip and an LED driving power supply, which can realize the PWM flicker-free dimming function and eliminate the ripple caused by the PWM signal in the output current.

[0004] To achieve the above object, the present invention provides the following solutions:

[0005] The present invention provides a PWM dimming circuit, comprising: a PWM conversion circuit, an output current sampling circuit, an error amplifier circuit, a voltage-controlled oscillator circuit and a second comparator, wherein:

[0006] The PWM conversion circuit is used to input a PWM dimming signal and convert the PWM dimming signal into a duty cycle current signal;

[0007] The output current sampling circuit is connected to the PWM conversion circuit and is used to convert the duty cycle current signal into an output current sampling signal;

[0008] The error amplifier circuit is connected to the output current sampling circuit and is used to output an error amplified current signal and an error amplified voltage signal according to the output current sampling signal and the reference voltage;

[0009] The voltage-controlled oscillator circuit is connected to the error amplifier circuit and is used to output a frequency control signal according to the error amplified current signal;

[0010] The second comparator is connected to the error amplifier circuit and is configured to output a peak current control signal according to the error amplified voltage signal.

[0011] Optionally, the PWM conversion circuit specifically includes: a first resistor, a second resistor, a first operational amplifier, a second operational amplifier, a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first current source, and a second current source, wherein:

[0012] One end of the first resistor is connected to the PWM port, and the other end of the first resistor is respectively connected to the negative phase input terminal of the first operational amplifier, the source of the first NMOS transistor and the gate of the second PMOS transistor; the positive phase input terminal of the first operational amplifier is used to input a first reference voltage signal, and the output terminal of the first operational amplifier is connected to the gate of the first NMOS transistor; the drain of the first NMOS transistor is used to input an internal power supply signal; the gate of the first PMOS transistor is used to input a second reference voltage signal, the drain of the first PMOS transistor is grounded, and the source of the first PMOS transistor is respectively connected to the output terminal of the first current source and the positive phase input terminal of the second operational amplifier; the input terminal of the first current source is used to input an internal power supply signal; the second PMOS transistor The drain of the S transistor is grounded, the source of the second PMOS transistor is respectively connected to the output end of the second current source and one end of the second resistor; the input end of the second current source is used to input an internal power supply signal; the other end of the second resistor is respectively connected to the negative input end of the second operational amplifier and the source of the second NMOS transistor; the output end of the second operational amplifier is connected to the gate of the second NMOS transistor; the drain of the second NMOS transistor is respectively connected to the gate of the third PMOS transistor, the drain of the third PMOS transistor and the gate of the fourth PMOS transistor; the source of the third PMOS transistor is used to input an internal power supply signal; the source of the fourth PMOS transistor is used to input an internal power supply signal, and the drain of the fourth PMOS transistor is used to output the duty cycle current signal.

[0013] Optionally, the output current sampling circuit specifically includes: a third resistor, a fourth resistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first NOR gate, a first AND gate, a second AND gate, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, and an eighth inverter, wherein:

[0014] The first circuit group is as follows: one end of the third resistor is connected to the drain of the fourth PMOS transistor and the drain of the third NMOS transistor respectively, and the other end of the third resistor is connected to one end of the fourth resistor, the drain of the seventh NMOS transistor and the drain of the eighth NMOS transistor respectively; the gate of the third NMOS transistor is used to input the first switch control signal, and the source of the third NMOS transistor is connected to the upper plate of the first capacitor and the drain of the fourth NMOS transistor respectively; the lower plate of the first capacitor is grounded; the gate of the fourth NMOS transistor is used to input the second switch control signal, and the source of the fourth NMOS transistor is connected to the upper plate of the second capacitor respectively. , the drain of the fifth NMOS tube and the drain of the sixth NMOS tube; the lower plate of the second capacitor is grounded; the gate of the fifth NMOS tube is used to input the first switch control signal, and the source of the fifth NMOS tube is grounded; the gate of the sixth NMOS tube is used to input the second switch control signal, the source of the sixth NMOS tube is respectively connected to the source of the seventh NMOS tube and the source of the eighth NMOS tube, and the source of the sixth NMOS tube is used to output the output current sampling signal; the gate of the seventh NMOS tube is used to input the first switch control signal; the gate of the eighth NMOS tube is connected to the output end of the first NOR gate;

[0015] The second circuit group comprises: the output end of the first inverter is respectively connected to the input end of the second inverter and the second input end of the second AND gate; the output end of the second inverter is respectively connected to the first input end of the first AND gate; the output end of the first AND gate is connected to the input end of the third inverter, and the output end of the first AND gate is used to output a first switch control signal; the output end of the third inverter is respectively connected to the upper plate of the third capacitor and the input end of the fourth inverter; the lower plate of the third capacitor is grounded; the output end of the fourth inverter is connected to the input end of the fifth inverter; the output end of the fifth inverter is connected to the first input end of the second AND gate; the output end of the second AND gate is connected to the input end of the sixth inverter, and the output end of the second AND gate is used to output a second switch control signal; the output end of the sixth inverter is respectively connected to the upper plate of the fourth capacitor and the input end of the seventh inverter; the lower plate of the fourth capacitor is grounded; the output end of the seventh inverter is connected to the input end of the eighth inverter; and the output end of the eighth inverter is connected to the second input end of the first AND gate.

[0016] Optionally, the error amplification circuit specifically includes: a third current source, a fifth resistor, a sixth resistor, a seventh resistor, a fifth capacitor, a sixth capacitor, a third operational amplifier, a fourth operational amplifier, a ninth NMOS transistor, and a tenth NMOS transistor, wherein:

[0017] One end of the fifth resistor is connected to the source of the sixth NMOS transistor, and the other end of the fifth resistor is respectively connected to the upper plate of the fifth capacitor and the negative input terminal of the third operational amplifier; the positive input terminal of the third operational amplifier is used to input a third reference voltage signal, and the output terminal of the third operational amplifier is connected to the gate of the ninth NMOS transistor; the drain of the ninth NMOS transistor is used to input an internal power supply signal; the source of the ninth NMOS transistor is respectively connected to the lower plate of the fifth capacitor, the input terminal of the third current source, the upper plate of the sixth capacitor, and the positive input terminal of the fourth operational amplifier; the output terminal of the third current source is grounded; the lower plate of the sixth capacitor is grounded; the negative input terminal of the fourth operational amplifier is respectively connected to the source of the tenth NMOS transistor and one end of the sixth resistor; the other end of the sixth resistor is connected to one end of the seventh resistor, and the other end of the sixth resistor is used to output the error amplified voltage signal; the other end of the seventh resistor is grounded; the gate of the tenth NMOS transistor is connected to the output terminal of the fourth operational amplifier, and the drain of the tenth NMOS transistor is used to output the error amplified current signal.

[0018] Optionally, the voltage-controlled oscillator circuit specifically includes: a discharge control module, a fifth PMOS transistor, a sixth PMOS transistor, an eleventh NMOS transistor, a seventh capacitor, a first comparator, a third AND gate and a ninth inverter, wherein:

[0019] The drain of the fifth PMOS tube is respectively connected to the drain of the tenth NMOS tube, the gate of the fifth PMOS tube and the gate of the sixth PMOS tube, and the source of the fifth PMOS tube is used to input an internal power supply signal; the source of the sixth PMOS tube is used to input an internal power supply signal, and the drain of the sixth PMOS tube is respectively connected to the drain of the eleventh NMOS tube, the upper plate of the seventh capacitor and the positive input terminal of the first comparator; the gate of the eleventh NMOS tube is connected to the output terminal of the discharge control module; the source of the eleventh NMOS tube is grounded; the lower plate of the seventh capacitor is grounded; the negative input terminal of the first comparator is used to input a fourth reference voltage signal, and the output terminal of the first comparator is connected to the first input terminal of the third AND gate; the second input terminal of the third AND gate is connected to the output terminal of the ninth inverter; and the output terminal of the third AND gate is used to output the frequency control signal.

[0020] Optionally, the negative phase input terminal of the second comparator is used to input the error amplified voltage signal generated by the error amplifier circuit.

[0021] The present invention also provides a control chip, including: a driving circuit, a demagnetization detection circuit, a control logic module and a PWM dimming circuit, wherein:

[0022] The output end of the driving circuit is connected to the input end of the demagnetization detection circuit; the output end of the demagnetization detection circuit is connected to the seventh input end of the PWM dimming circuit; the first input end of the PWM dimming circuit is used to input the PWM dimming signal, the third input end of the PWM dimming circuit is used to input the third reference voltage signal, the fourth input end of the PWM dimming circuit is used to input the second reference voltage signal, the fifth input end of the PWM dimming circuit is used to input the first reference voltage signal, the sixth input end of the PWM dimming circuit is connected to the output end of the control logic module, the first output end of the PWM dimming circuit is connected to the first input end of the control logic module, and the second output end of the PWM dimming circuit is connected to the second input end of the control logic module; the output end of the control logic module is also connected to the input end of the driving circuit.

[0023] The present invention also provides an LED driving power supply, comprising: a rectifier bridge, an input capacitor, a rectifier diode, an inductor, an output capacitor, a dummy load, an output LED load, a power tube, a current sampling resistor and a control chip, wherein

[0024] The positive output end of the rectifier bridge is respectively connected to the positive electrode of the input capacitor, the start end of the control chip, the negative electrode of the rectifier diode, the positive electrode of the output capacitor, one end of the dummy load and the positive electrode of the output LED load; the negative electrode of the input capacitor is connected to the negative output of the rectifier bridge and grounded; the positive electrode of the rectifier diode is respectively connected to the drain of the power tube and one end of the inductor; the other end of the inductor is respectively connected to the negative electrode of the output capacitor, the other end of the dummy load and the negative electrode of the output LED load; the gate of the power tube is connected to the output end of the control chip; the source of the power tube is respectively connected to one end of the current sampling resistor and the current sampling end of the control chip; the other end of the current sampling resistor is grounded.

[0025] According to the specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0026] The present invention provides a PWM dimming circuit, a control chip, and an LED driver power supply, wherein a PWM conversion circuit converts a PWM dimming signal into a duty cycle current signal, and then, through an output current sampling circuit, adds the duty cycle current signal to the output current to obtain an output current sampling signal. An error amplifier circuit makes the output current sampling signal equal to a reference voltage, so that the output current can vary linearly with the duty cycle of the PWM dimming signal. The frequency control signal output by the voltage-controlled oscillator circuit is used to modulate the operating frequency of the driver power supply, thereby realizing the PWM flicker-free dimming function and eliminating the ripple caused by the PWM signal in the output current. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0028] Figure 1 This is a PWM dimming circuit diagram of a PWM dimming circuit, a control chip, and a LED driver power supply of the present invention;

[0029] Figure 2 This is a PWM conversion circuit diagram of a PWM dimming circuit, a control chip, and an LED driver power supply of the present invention;

[0030] Figure 3 This is a working principle diagram of a PWM dimming circuit, a control chip, and a PWM conversion circuit of an LED driver power supply of the present invention;

[0031] Figure 4 This is a PWM dimming circuit, control chip and output current sampling circuit diagram of LED driver power supply of the present invention;

[0032] Figure 5 This is a first working principle diagram of a PWM dimming circuit, a control chip, and an output current sampling circuit of an LED driver power supply of the present invention;

[0033] Figure 6 This is a second working principle diagram of a PWM dimming circuit, a control chip, and an output current sampling circuit of an LED driver power supply of the present invention;

[0034] Figure 7 This is a PWM dimming circuit, a control chip, and an error amplification circuit diagram of an LED driver power supply of the present invention;

[0035] Figure 8 This is a circuit diagram of a PWM dimming circuit, a control chip, and a voltage-controlled oscillator of an LED driver power supply of the present invention;

[0036] Figure 9 This is a working principle diagram of a PWM dimming circuit, a control chip, and a voltage-controlled oscillator circuit of an LED driver power supply of the present invention;

[0037] Figure 10 This is a diagram of a PWM dimming circuit, a control chip, and a control chip of an LED driver power supply of the present invention;

[0038] Figure 11 This is a diagram of an LED driving power supply of a PWM dimming circuit, a control chip and an LED driving power supply of the present invention.

[0039] Explanation of symbols:

[0040] PWM dimming circuit-1, first input terminal-11 of PWM dimming circuit, second input terminal-12 of PWM dimming circuit, third input terminal-13 of PWM dimming circuit, fourth input terminal-14 of PWM dimming circuit, fifth input terminal-15 of PWM dimming circuit, sixth input terminal-16 of PWM dimming circuit, seventh input terminal-17 of PWM dimming circuit, first output terminal-18 of PWM dimming circuit, second output terminal-19 of PWM dimming circuit, control chip-2, drive circuit-21, demagnetization detection circuit-22, control logic module-23, LED driver power supply-3, rectifier bridge-31, input capacitor-32, rectifier Current diode 33, inductor 34, output capacitor 35, dummy load 36, output LED load 37, power transistor 38, current sampling resistor 39, PWM conversion circuit 100, first resistor 101, second resistor 102, first operational amplifier 103, second operational amplifier 104, first NMOS transistor 105, second NMOS transistor 106, first PMOS transistor 107, second PMOS transistor 108, third PMOS transistor 109, fourth PMOS transistor 110, first current source 111, second current source 112, output current sampling circuit 200, third resistor 201 , fourth resistor 202, third NMOS transistor 203, fourth NMOS transistor 204, fifth NMOS transistor 205, sixth NMOS transistor 206, seventh NMOS transistor 207, eighth NMOS transistor 208, first capacitor 209, second capacitor 210, third capacitor 211, fourth capacitor 212, first NOR gate 213, first AND gate 214, second AND gate 215, first inverter 216, second inverter 217, third inverter 218, fourth inverter 219, fifth inverter 220, sixth inverter 221, seventh inverter 222, eighth inverter 223 3. Error amplifier circuit 300, third current source 301, fifth resistor 302, sixth resistor 303, seventh resistor 304, fifth capacitor 305, sixth capacitor 306, third operational amplifier 307, fourth operational amplifier 308, ninth NMOS transistor 309, tenth NMOS transistor 310, voltage-controlled oscillator circuit 400, discharge control module 401, fifth PMOS transistor 402, sixth PMOS transistor 403, eleventh NMOS transistor 404, seventh capacitor 405, first comparator 406, third AND gate 407, ninth inverter 408, second comparator 500. DETAILED DESCRIPTION

[0041] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0042] The purpose of the present invention is to provide a PWM dimming circuit, a control chip and an LED driver power supply, which realize the PWM flicker-free dimming function through the PWM dimming circuit and eliminate the ripple caused by the PWM signal on the output current.

[0043] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0044] Example 1

[0045] like Figure 1 As shown, a PWM dimming circuit provided by an embodiment of the present invention includes: a PWM conversion circuit 100 , an output current sampling circuit 200 , an error amplifier circuit 300 , a voltage-controlled oscillator circuit 400 and a second comparator 500 .

[0046] The PWM conversion circuit 100 is configured to input a PWM dimming signal and convert the PWM dimming signal into a duty cycle current signal Idim. The output current sampling circuit 200 is connected to the PWM conversion circuit 100 and is configured to convert the duty cycle current signal Idim into an output current sampling signal Ioutsp. The error amplifier circuit 300 is connected to the output current sampling circuit 200 and is configured to output an error amplified current signal Ivco and an error amplified voltage signal Vcs_th based on the output current sampling signal Ioutsp and a third reference voltage Vref. The voltage-controlled oscillator circuit 400 is connected to the error amplifier circuit 300 and is configured to output a frequency control signal pfm based on the error amplified current signal Ivco. The second comparator 500 is connected to the error amplifier circuit 300 and is configured to output a peak current control signal ocp based on the error amplified voltage signal Vcs_th.

[0047] like Figure 2 As shown, the PWM conversion circuit 100 specifically includes: a first resistor 101, a second resistor 102, a first operational amplifier 103, a second operational amplifier 104, a first NMOS transistor 105, a second NMOS transistor 106, a first PMOS transistor 107, a second PMOS transistor 108, a third PMOS transistor 109, a fourth PMOS transistor 110, a first current source 111 and a second current source 112.

[0048] One end of the first resistor 101 is used to input the PWM signal, and the other end of the first resistor 101 is respectively connected to the negative phase input terminal of the first operational amplifier 103, the source of the first NMOS transistor 105 and the gate of the second PMOS transistor 108; the positive phase input terminal of the first operational amplifier 103 is used to input the first reference voltage signal VL, and the output terminal of the first operational amplifier 103 is connected to the gate of the first NMOS transistor 105; the drain of the first NMOS transistor 105 is used to input the internal power supply signal Vdd; the gate of the first PMOS transistor 107 is used to input the second reference voltage signal VH, the drain of the first PMOS transistor 107 is grounded, and the source of the first PMOS transistor 107 is respectively connected to the output terminal of the first current source 111 and the positive phase input terminal of the second operational amplifier 104; the input terminal of the first current source 111 is used to input the internal power supply signal Vdd; The drain of the second PMOS transistor 108 is grounded, the source of the second PMOS transistor 108 is connected to the output terminal of the second current source 112 and one end of the second resistor 102 respectively; the input terminal of the second current source 112 is used to input the internal power supply signal Vdd; the other end of the second resistor 102 is connected to the negative phase input terminal of the second operational amplifier 104 and the source of the second NMOS transistor 106 respectively; the output terminal of the second operational amplifier 104 is connected to the gate of the second NMOS transistor 106; the drain of the second NMOS transistor 106 is connected to the gate of the third PMOS transistor 109, the drain of the third PMOS transistor 109 and the gate of the fourth PMOS transistor 110 respectively; the source of the third PMOS transistor 109 is used to input the internal power supply signal Vdd; the source of the fourth PMOS transistor 110 is used to input the internal power supply signal Vdd, and the drain of the fourth PMOS transistor 110 is used to output the duty cycle current signal Idim, as shown in FIG. Figure 3 As shown in the figure, according to the circuit structure, the relationship between Idim and the duty cycle Duty of the PWM signal can be obtained as follows:

[0049]

[0050] Wherein, Idim is the duty cycle current signal, VH is the second reference voltage signal, VL is the first reference voltage signal, Duty is the duty cycle, K is the ratio of the current flowing through the fourth PMOS transistor 110 to the current flowing through the third PMOS transistor 109 , and R1 is the resistance of the second resistor 102 .

[0051] like Figure 4As shown, the output current sampling circuit 200 includes: a third resistor 201, a fourth resistor 202, a third NMOS transistor 203, a fourth NMOS transistor 204, a fifth NMOS transistor 205, a sixth NMOS transistor 206, a seventh NMOS transistor 207, an eighth NMOS transistor 208, a first capacitor 209, a second capacitor 210, a third capacitor 211, a fourth capacitor 212, a first NOR gate 213, a first AND gate 214, a second AND gate 215, a first inverter 216, a second inverter 217, a third inverter 218, a fourth inverter 219, a fifth inverter 220, a sixth inverter 221, a seventh inverter 222, and an eighth inverter 223.

[0052] The first circuit group is as follows: one end of the third resistor 201 is connected to the drain of the fourth PMOS transistor 110 and the drain of the third NMOS transistor 203 respectively, and the other end of the third resistor 201 is connected to one end of the fourth resistor 202, the drain of the seventh NMOS transistor 207 and the drain of the eighth NMOS transistor 208 respectively; the other end of the fourth resistor 202 is used to input the inductor current sampling signal CS; the gate of the third NMOS transistor 203 is used to input the first switch control signal KP, the source of the third NMOS transistor 203 is connected to the upper plate of the first capacitor 209 and the drain of the fourth NMOS transistor 204 respectively; the lower plate of the first capacitor 209 is grounded; the gate of the fourth NMOS transistor 204 is used to input the second switch control signal KN, the source of the fourth NMOS transistor 204 is connected to the upper plate of the second capacitor 210, the drain of the fifth NMOS transistor 205 and the drain of the sixth NMOS transistor The drain of the S transistor 206 is connected; the lower plate of the second capacitor 210 is grounded; the gate of the fifth NMOS transistor 205 is used to input the first switch control signal KP, and the source of the fifth NMOS transistor 205 is grounded; the gate of the sixth NMOS transistor 206 is used to input the second switch control signal KN, and the source of the sixth NMOS transistor 206 is connected to the source of the seventh NMOS transistor 207 and the source of the eighth NMOS transistor 208, respectively. The source of the sixth NMOS transistor 206 is also used to generate the output current sampling signal Ioutsp; the gate of the seventh NMOS transistor 207 is used to input the first switch control signal KP; the gate of the eighth NMOS transistor 208 is connected to the output end of the first NOR gate 213; one input end of the first NOR gate 213 is used to input the control chip conduction signal TON, and the other input end of the first NMOS gate 213 is used to input the inductor demagnetization time signal Tdem.

[0053] The second circuit group is as follows: the input end of the first inverter 216 is used to input the control chip conduction signal TON, the output end of the first inverter 216 is respectively connected to the input end of the second inverter 217 and the second input end of the second AND gate 215; the output end of the second inverter 217 is respectively connected to the first input end of the first AND gate 214; the output end of the first AND gate 214 is connected to the input end of the third inverter 218, and the output end of the first AND gate 214 is used to output the first switch control signal KP; the output end of the third inverter 218 is respectively connected to the upper plate of the third capacitor 211 and the input end of the fourth inverter 219; the lower plate of the third capacitor 211 is grounded; The output of the fourth inverter 219 is connected to the input of the fifth inverter 220; the output of the fifth inverter 220 is connected to the first input of the second AND gate 215; the output of the second AND gate 215 is connected to the input of the sixth inverter 221, and the output of the second AND gate 215 is used to output the second switch control signal KN; the output of the sixth inverter 221 is respectively connected to the upper plate of the fourth capacitor 212 and the input of the seventh inverter 222; the lower plate of the fourth capacitor 212 is grounded; the output of the seventh inverter 222 is connected to the input of the eighth inverter 223; the output of the eighth inverter 223 is connected to the second input of the first AND gate 214. Figure 5 As shown, according to the presented working waveform, KP and KN are two non-overlapping clocks.

[0054] The working principle of the output current sampling circuit 200 is as follows: Idim flows through the third resistor 201 and the fourth resistor 202 and then enters the inductor current sampling signal port CS. The resistance values ​​of the third resistor 201 and the fourth resistor 202 are both set to R2. When TON is logic high, KP is logic high, KN is logic low, the seventh NMOS transistor 207 is turned on, and Ioutsp is equal to the product of the CS ramp voltage plus Idim multiplied by R2. If the system operates in the inductor current critical conduction mode (BCM), then when TON is logic low, the seventh NMOS transistor 207 is turned off, and the third NMOS transistor 203, the fourth NMOS transistor 204, the fifth NMOS transistor 205, and the sixth NMOS transistor 206 sample the peak voltage at the port of the third resistor 201. The first capacitor 209 and the second capacitor 210 are equal in size. It can be obtained that Ioutsp in this stage is equal to half the CS peak voltage plus the product of Idim multiplied by R2. If the system operates in the inductor current discontinuous conduction mode (DCM), then after demagnetization is completed, CS=0, and Ioutsp is equal to the product of Idim multiplied by R2. Its operating waveform is as follows: Figure 6 shown.

[0055] like Figure 7As shown, the error amplifier circuit 300 specifically includes: a third current source 301, a fifth resistor 302, a sixth resistor 303, a seventh resistor 304, a fifth capacitor 305, a sixth capacitor 306, a third operational amplifier 307, a fourth operational amplifier 308, a ninth NMOS transistor 309 and a tenth NMOS transistor 310.

[0056] One end of the fifth resistor 302 is connected to the source of the sixth NMOS transistor 206 for inputting the Ioutsp signal. The other end of the fifth resistor 302 is respectively connected to the upper plate of the fifth capacitor 305 and the negative input terminal of the third operational amplifier 307; the positive input terminal of the third operational amplifier 307 is used to input the third reference voltage signal Vref, and the output terminal of the third operational amplifier 307 is connected to the gate of the ninth NMOS transistor 309; the drain of the ninth NMOS transistor 309 is used to input the internal power supply signal Vdd; the source of the ninth NMOS transistor 309 is respectively connected to the lower plate of the fifth capacitor 305, the input terminal of the third current source 301, and the sixth capacitor 306. and the positive input terminal of the fourth operational amplifier 308; the output terminal of the third current source 301 is grounded; the lower plate of the sixth capacitor 306 is grounded; the negative input terminal of the fourth operational amplifier 308 is respectively connected to the source of the tenth NMOS transistor 310 and one end of the sixth resistor 303; the other end of the sixth resistor 303 is connected to one end of the seventh resistor 304, and the other end of the sixth resistor 303 is used to output the error amplified voltage signal Vcs_th; the other end of the seventh resistor 304 is grounded; the gate of the tenth NMOS transistor 310 is connected to the output terminal of the fourth operational amplifier 308, and the drain of the tenth NMOS transistor 310 is used to output the error amplified current signal Ivco.

[0057] The working principle of the error amplifier circuit is as follows: if the bandwidth of the product of the fifth resistor 302 and the fifth capacitor 305 is set to be less than 100 Hz, the output signal of the third operational amplifier 307 can change very slowly and does not change with the PWM modulation signal, thereby filtering out the PWM signal ripple. In steady state, the following is obtained:

[0058] Ioutsp=Vref (2);

[0059] It can be seen from the output current sampling circuit 200 that:

[0060] Ioutsp=Iout×Rcs+Idim×R2 (3);

[0061] Substituting into formula (1), we can get:

[0062]

[0063] By setting appropriate VH, VL, K and the ratio of R2 to R1, when the following formula is satisfied:

[0064]

[0065] The PWM dimming function can be realized. According to (4), the output current Iout is linearly related to Duty.

[0066] When PWM reaches 100%, Duty = 1, so:

[0067] Vref=Iout×Rcs (6);

[0068] Formula (6) is the maximum output current formula of the driving power supply when dimming is not in progress.

[0069] Wherein, Ioutsp is the output current sampling signal, Vref is the third reference voltage signal, Iout is the output current, Rcs is the resistance of the current sampling resistor, R2 is the resistance of the third resistor 201 or the fourth resistor 202, Idim is the duty cycle current signal, VH is the second reference voltage signal, VL is the first reference voltage signal, Duty is the duty cycle, and K is the ratio of the current flowing through the fourth PMOS transistor 110 to the current flowing through the third PMOS transistor 109.

[0070] like Figure 8 As shown, the voltage-controlled oscillator circuit 400 specifically includes: a discharge control module 401 , a fifth PMOS transistor 402 , a sixth PMOS transistor 403 , an eleventh NMOS transistor 404 , a seventh capacitor 405 , a first comparator 406 , a third AND gate 407 and a ninth inverter 408 .

[0071] The drain of the fifth PMOS transistor 402 is connected to the drain of the tenth NMOS transistor 310, the gate of the fifth PMOS transistor 402, and the gate of the sixth PMOS transistor 403 respectively. The drain of the fifth PMOS transistor 402 is used to input the error amplification current signal Ivco, and the source of the fifth PMOS transistor 402 is used to input the internal power supply signal Vdd; the source of the sixth PMOS transistor 403 is used to input the internal power supply signal Vdd, and the drain of the sixth PMOS transistor 403 is connected to the drain of the eleventh NMOS transistor 404, the upper plate of the seventh capacitor 405, and the non-inverting input terminal of the first comparator 406 respectively; the gate of the eleventh NMOS transistor 404 is connected to the gate of the sixth PMOS transistor 403. The output end of the discharge control module 401 is connected, and the input end of the discharge control module 401 is used to input the control chip conduction signal TON; the source of the eleventh NMOS tube 404 is grounded; the lower plate of the seventh capacitor 405 is grounded; the negative input end of the first comparator 406 is used to input the fourth reference voltage signal Vth, and the output end of the first comparator 406 is connected to the first input end of the third AND gate 407; the second input end of the third AND gate 407 is connected to the output end of the ninth inverter 408; the output end of the third AND gate 407 is used to output the frequency control signal pfm; the input end of the ninth inverter 408 is used to input the inductor demagnetization time signal Tdem.

[0072] like Figure 1 As shown, the positive input terminal of the second comparator 500 is used to input the inductor current sampling signal CS, the negative input terminal of the second comparator 500 is used to input the error amplified voltage signal Vcs_th, and the output terminal of the second comparator 500 is used to output the peak current control signal ocp.

[0073] like Figure 9 As described above, during dimming, Vcs_th modulates the CS threshold voltage, i.e., the peak value of the inductor current, and the PFM modulates the operating frequency. When the PFM period is less than TON + Tdem, the driver operates in the critical conduction mode (BCM). When the PFM period is greater than TON + Tdem, the driver operates in the discontinuous conduction mode (DCM). When the system operates in DCM, the duty cycle (Toff) minus TON and Tdem increases as the duty cycle of the PWM signal decreases. Vsw is the voltage at the junction of inductor 34 and the drain of power transistor 38. The control chip can detect the current operating mode based on the Vsw voltage waveform.

[0074] Example 2

[0075] like Figure 10 As shown, a control chip includes: a driving circuit 21, a demagnetization detection circuit 22, a control logic module 23 and a PWM dimming circuit 1.

[0076] The output end of the driving circuit 21 is connected to the input end of the demagnetization detection circuit 22; the output end of the demagnetization detection circuit 22 is connected to the seventh input end 17 of the PWM dimming circuit; the first input end 11 of the PWM dimming circuit is used to input the PWM dimming signal, the third input end 13 of the PWM dimming circuit is used to input the third reference voltage signal Vref, the fourth input end 14 of the PWM dimming circuit is used to input the second reference voltage signal VH, the fifth input end 15 of the PWM dimming circuit is used to input the first reference voltage signal VL, the sixth input end 16 of the PWM dimming circuit is connected to the output end Q of the control logic module, the first output end 18 of the PWM dimming circuit is connected to the first input end R of the control logic module, and the second output end 19 of the PWM dimming circuit is connected to the second input end S of the control logic module; the output end Q of the control logic module 23 is also connected to the input end of the driving circuit 21.

[0077] Example 3

[0078] like Figure 11 As shown, an LED driving power supply includes: a rectifier bridge 31, an input capacitor 32, a rectifier diode 33, an inductor 34, an output capacitor 35, a dummy load 36, an output LED load 37, a power tube 38, a current sampling resistor 39 and a control chip 2.

[0079] The positive output end of the rectifier bridge 31 is respectively connected to the positive electrode of the input capacitor 32, the negative electrode of the rectifier diode 33, the positive electrode of the output capacitor 35, one end of the dummy load 36 and the positive electrode of the output LED load 37; the negative electrode of the input capacitor 32 is connected to the negative output of the rectifier bridge 31 and grounded; the positive electrode of the rectifier diode 33 is respectively connected to the drain of the power tube 38 and one end of the inductor 34; the other end of the inductor 34 is respectively connected to the negative electrode of the output capacitor 35, the other end of the dummy load 36 and the negative electrode of the output LED load 37; the gate of the power tube 38 is connected to the output end of the control chip 2; the source of the power tube 38 is respectively connected to one end of the current sampling resistor 39 and the current sampling end of the control chip 2; the other end of the current sampling resistor 39 is grounded.

[0080] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0081] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The above examples are only intended to help understand the method and core concept of the present invention. At the same time, those skilled in the art will find that the specific implementation methods and application scopes may vary based on the concept of the present invention. In summary, the contents of this specification should not be construed as limiting the present invention.

Claims

1. A PWM dimming circuit, characterized in that: include: PWM conversion circuit, output current sampling circuit, error amplifier circuit, voltage controlled oscillator circuit and second comparator, wherein, The PWM conversion circuit is used to input a PWM dimming signal and convert the PWM dimming signal into a duty cycle current signal; The output current sampling circuit is connected to the PWM conversion circuit and is used to generate an output current sampling signal according to the duty cycle current signal and the input inductor current sampling signal; The error amplifier circuit is connected to the output current sampling circuit and is used to output an error amplified current signal and an error amplified voltage signal according to the output current sampling signal and the reference voltage; the error amplifier circuit makes the output current sampling signal equal to the reference voltage, so that the output current can change linearly with the duty cycle of the PWM dimming signal; The voltage-controlled oscillator circuit is connected to the error amplifier circuit and is used to output a frequency control signal based on the error amplified current signal; the voltage-controlled oscillator circuit uses the frequency control signal to modulate the operating frequency of the driving power supply to achieve a PWM flicker-free dimming function and eliminate ripple caused by the PWM signal in the output current; The second comparator is connected to the error amplifier circuit and is configured to output a peak current control signal according to the error amplified voltage signal.

2. A PWM dimming circuit according to claim 1, characterized in that: The PWM conversion circuit specifically includes: a first resistor, a second resistor, a first operational amplifier, a second operational amplifier, a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first current source and a second current source, wherein: One end of the first resistor is connected to the PWM port, and the other end of the first resistor is respectively connected to the negative phase input terminal of the first operational amplifier, the source of the first NMOS transistor and the gate of the second PMOS transistor; the positive phase input terminal of the first operational amplifier is used to input a first reference voltage signal, and the output terminal of the first operational amplifier is connected to the gate of the first NMOS transistor; the drain of the first NMOS transistor is used to input an internal power supply signal; the gate of the first PMOS transistor is used to input a second reference voltage signal, the drain of the first PMOS transistor is grounded, and the source of the first PMOS transistor is respectively connected to the output terminal of the first current source and the positive phase input terminal of the second operational amplifier; the input terminal of the first current source is used to input an internal power supply signal; the second PMOS transistor The drain of the S transistor is grounded, the source of the second PMOS transistor is respectively connected to the output end of the second current source and one end of the second resistor; the input end of the second current source is used to input an internal power supply signal; the other end of the second resistor is respectively connected to the negative input end of the second operational amplifier and the source of the second NMOS transistor; the output end of the second operational amplifier is connected to the gate of the second NMOS transistor; the drain of the second NMOS transistor is respectively connected to the gate of the third PMOS transistor, the drain of the third PMOS transistor and the gate of the fourth PMOS transistor; the source of the third PMOS transistor is used to input an internal power supply signal; the source of the fourth PMOS transistor is used to input an internal power supply signal, and the drain of the fourth PMOS transistor is used to output the duty cycle current signal.

3. The PWM dimming circuit according to claim 2, characterized in that: The output current sampling circuit specifically includes: a third resistor, a fourth resistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first NOR gate, a first AND gate, a second AND gate, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter and an eighth inverter, wherein, The first circuit group is as follows: one end of the third resistor is connected to the drain of the fourth PMOS transistor and the drain of the third NMOS transistor respectively, and the other end of the third resistor is connected to one end of the fourth resistor, the drain of the seventh NMOS transistor and the drain of the eighth NMOS transistor respectively; the gate of the third NMOS transistor is used to input the first switch control signal, and the source of the third NMOS transistor is connected to the upper plate of the first capacitor and the drain of the fourth NMOS transistor respectively; the lower plate of the first capacitor is grounded; the gate of the fourth NMOS transistor is used to input the second switch control signal, and the source of the fourth NMOS transistor is connected to the upper plate of the second capacitor respectively. , the drain of the fifth NMOS tube and the drain of the sixth NMOS tube; the lower plate of the second capacitor is grounded; the gate of the fifth NMOS tube is used to input the first switch control signal, and the source of the fifth NMOS tube is grounded; the gate of the sixth NMOS tube is used to input the second switch control signal, the source of the sixth NMOS tube is respectively connected to the source of the seventh NMOS tube and the source of the eighth NMOS tube, and the source of the sixth NMOS tube is used to output the output current sampling signal; the gate of the seventh NMOS tube is used to input the first switch control signal; the gate of the eighth NMOS tube is connected to the output end of the first NOR gate; The second circuit group comprises: the output end of the first inverter is respectively connected to the input end of the second inverter and the second input end of the second AND gate; the output end of the second inverter is respectively connected to the first input end of the first AND gate; the output end of the first AND gate is connected to the input end of the third inverter, and the output end of the first AND gate is used to output a first switch control signal; the output end of the third inverter is respectively connected to the upper plate of the third capacitor and the input end of the fourth inverter; the lower plate of the third capacitor is grounded; the output end of the fourth inverter is connected to the input end of the fifth inverter; the output end of the fifth inverter is connected to the first input end of the second AND gate; the output end of the second AND gate is connected to the input end of the sixth inverter, and the output end of the second AND gate is used to output a second switch control signal; the output end of the sixth inverter is respectively connected to the upper plate of the fourth capacitor and the input end of the seventh inverter; the lower plate of the fourth capacitor is grounded; the output end of the seventh inverter is connected to the input end of the eighth inverter; and the output end of the eighth inverter is connected to the second input end of the first AND gate.

4. The PWM dimming circuit according to claim 3, characterized in that: The error amplifier circuit specifically includes: a third current source, a fifth resistor, a sixth resistor, a seventh resistor, a fifth capacitor, a sixth capacitor, a third operational amplifier, a fourth operational amplifier, a ninth NMOS transistor, and a tenth NMOS transistor, wherein: One end of the fifth resistor is connected to the source of the sixth NMOS transistor, and the other end of the fifth resistor is respectively connected to the upper plate of the fifth capacitor and the negative input terminal of the third operational amplifier; the positive input terminal of the third operational amplifier is used to input a third reference voltage signal, and the output terminal of the third operational amplifier is connected to the gate of the ninth NMOS transistor; the drain of the ninth NMOS transistor is used to input an internal power supply signal; the source of the ninth NMOS transistor is respectively connected to the lower plate of the fifth capacitor, the input terminal of the third current source, the upper plate of the sixth capacitor, and the positive input terminal of the fourth operational amplifier; the output terminal of the third current source is grounded; the lower plate of the sixth capacitor is grounded; the negative input terminal of the fourth operational amplifier is respectively connected to the source of the tenth NMOS transistor and one end of the sixth resistor; the other end of the sixth resistor is connected to one end of the seventh resistor, and the other end of the sixth resistor is used to output the error amplified voltage signal; the other end of the seventh resistor is grounded; the gate of the tenth NMOS transistor is connected to the output terminal of the fourth operational amplifier, and the drain of the tenth NMOS transistor is used to output the error amplified current signal.

5. The PWM dimming circuit according to claim 4, characterized in that: The voltage-controlled oscillator circuit specifically includes: a discharge control module, a fifth PMOS transistor, a sixth PMOS transistor, an eleventh NMOS transistor, a seventh capacitor, a first comparator, a third AND gate and a ninth inverter, wherein: The drain of the fifth PMOS tube is respectively connected to the drain of the tenth NMOS tube, the gate of the fifth PMOS tube and the gate of the sixth PMOS tube, and the source of the fifth PMOS tube is used to input an internal power supply signal; the source of the sixth PMOS tube is used to input an internal power supply signal, and the drain of the sixth PMOS tube is respectively connected to the drain of the eleventh NMOS tube, the upper plate of the seventh capacitor and the positive input terminal of the first comparator; the gate of the eleventh NMOS tube is connected to the output terminal of the discharge control module; the source of the eleventh NMOS tube is grounded; the lower plate of the seventh capacitor is grounded; the negative input terminal of the first comparator is used to input a fourth reference voltage signal, and the output terminal of the first comparator is connected to the first input terminal of the third AND gate; the second input terminal of the third AND gate is connected to the output terminal of the ninth inverter; and the output terminal of the third AND gate is used to output the frequency control signal.

6. The PWM dimming circuit according to claim 4, characterized in that: The negative phase input terminal of the second comparator is used to input the error amplified voltage signal generated by the error amplifier circuit.

7. A control chip, characterized in that: include: A driving circuit, a demagnetization detection circuit, a control logic module, and a PWM dimming circuit according to any one of claims 1 to 6, wherein: The output end of the driving circuit is connected to the input end of the demagnetization detection circuit; the output end of the demagnetization detection circuit is connected to the seventh input end of the PWM dimming circuit; the first input end of the PWM dimming circuit is used to input the PWM dimming signal, the third input end of the PWM dimming circuit is used to input the third reference voltage signal, the fourth input end of the PWM dimming circuit is used to input the second reference voltage signal, the fifth input end of the PWM dimming circuit is used to input the first reference voltage signal, the sixth input end of the PWM dimming circuit is connected to the output end of the control logic module, the first output end of the PWM dimming circuit is connected to the first input end of the control logic module, and the second output end of the PWM dimming circuit is connected to the second input end of the control logic module; the output end of the control logic module is also connected to the input end of the driving circuit.

8. An LED driving power supply, characterized in that: include: A rectifier bridge, an input capacitor, a rectifier diode, an inductor, an output capacitor, a dummy load, an output LED load, a power tube, a current sampling resistor, and a control chip according to claim 7, wherein The positive output end of the rectifier bridge is respectively connected to the positive electrode of the input capacitor, the start end of the control chip, the negative electrode of the rectifier diode, the positive electrode of the output capacitor, one end of the dummy load and the positive electrode of the output LED load; the negative electrode of the input capacitor is connected to the negative output of the rectifier bridge and grounded; the positive electrode of the rectifier diode is respectively connected to the drain of the power tube and one end of the inductor; the other end of the inductor is respectively connected to the negative electrode of the output capacitor, the other end of the dummy load and the negative electrode of the output LED load; the gate of the power tube is connected to the output end of the control chip; the source of the power tube is respectively connected to one end of the current sampling resistor and the current sampling end of the control chip; the other end of the current sampling resistor is grounded.

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