A semiconductor device with a thyristor suppression layer

Abstract

This invention provides a semiconductor device with a thyristor suppression layer, relating to the field of semiconductor optoelectronic device technology. It includes, from bottom to top, a substrate, a first n-type semiconductor layer, a second n-type semiconductor layer, a thyristor suppression layer, a quantum well layer, and a p-type semiconductor layer. The thyristor suppression layer is composed of a first thyristor suppression layer, a second thyristor suppression layer, and a third thyristor suppression layer from bottom to top. By inserting the thyristor suppression layer, and designing three semiconductor structures with different C content concentrations (with a double-step decreasing trend in C content) and Si, H, and O doping concentrations within the thyristor suppression layer, deep-level defect centers are suppressed, and inter-junction capacitance generated by the interleaving of PN junctions is suppressed. This reduces the probability of thyristor generation from 1-5% to 0, solving the problem of inconsistent lighting during the use of semiconductor light-emitting elements.

Description

Technical Field

[0001] This invention relates to the field of semiconductor optoelectronic device technology, and more specifically, to a semiconductor element having a thyristor suppression layer. Background Technology

[0002] Semiconductor components, especially semiconductor light-emitting components, have a wide range of adjustable wavelengths, high luminous efficiency, energy saving and environmental protection, a long lifespan of over 100,000 hours, small size, multiple application scenarios, and strong design flexibility. As a result, they have gradually replaced incandescent and fluorescent lamps, becoming the light source for ordinary household lighting and are widely used in new scenarios, such as indoor high-resolution displays, outdoor displays, Mini-LED, Micro-LED, mobile phone and TV backlights, backlighting, streetlights, car headlights, daytime running lights, car interior ambient lighting, flashlights, and other application areas.

[0003] Traditional nitride semiconductors are grown on sapphire substrates, resulting in large lattice and thermal mismatches, leading to high defect density and polarization effects. This generates non-radiative recombination centers, reducing the luminous efficiency of semiconductor light-emitting elements. Simultaneously, the hole ionization efficiency of traditional nitride semiconductors is far lower than that of electron ionization, resulting in a hole concentration more than two orders of magnitude lower than the electron concentration. Excess electrons overflow from the multiple quantum wells to the second conductivity type semiconductor, causing non-radiative recombination. The low hole ionization efficiency makes it difficult for holes from the second conductivity type semiconductor to be effectively injected into the multiple quantum wells, resulting in low hole injection efficiency and consequently low luminous efficiency of the multiple quantum wells. Furthermore, the non-centrosymmetric structure of nitride semiconductors generates strong spontaneous polarization along the c-axis, which, combined with the piezoelectric polarization effect of lattice mismatch, forms an intrinsic polarization field. This intrinsic polarization field, along the (001) direction, causes a strong quantum confinement Stark effect in the multiple quantum well layer, leading to band tilt and spatial separation of the electron-hole wavefunction, reducing the radiative recombination efficiency of electrons and holes, and thus affecting the luminous efficiency of the semiconductor light-emitting element. Defects in traditional nitride semiconductor light-emitting elements extend into the quantum well, creating deep-level defect centers. This results in inter-junction capacitance, forming thyristors, which causes the forward voltage of the light-emitting diode to rise during use and then drop after the diode lights up. This leads to inconsistencies in the forward voltage between normal and abnormal chips, resulting in inconsistent lighting during use. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device with a thyristor suppression layer, which solves the problems existing in the prior art.

[0005] A semiconductor device having a thyristor suppression layer includes, from bottom to top, a substrate, a first n-type semiconductor layer, a second n-type semiconductor layer, a thyristor suppression layer, a quantum well layer, and a p-type semiconductor layer.

[0006] As a preferred embodiment of the present invention, the thyristor suppression layer is composed of a first thyristor suppression layer, a second thyristor suppression layer and a third thyristor suppression layer from bottom to top.

[0007] As a preferred technical solution of the present invention, the C content of the second thyristor suppression layer to the first thyristor suppression layer exhibits a double-step decreasing trend, including a first C content decreasing step and a second C content decreasing step; the angle of the first C content decreasing step is α: 60°≥α≥15°, and the angle of the second C content decreasing step is β: 90°≥β≥30°.

[0008] As a preferred technical solution of the present invention, the C content from the second thyristor suppression layer to the third thyristor suppression layer exhibits a double-step decreasing trend, including a third C content decreasing step and a fourth C content decreasing step; the angle of the third C content decreasing step is γ: 80°≥γ≥20°, and the angle of the fourth C content decreasing step is θ: 90°≥θ≥30°.

[0009] As a preferred embodiment of the present invention, the angle β of the second C content decrease step ≥ the angle θ of the fourth C content decrease step ≥ the angle γ of the third C content decrease step ≥ the angle α of the first C content decrease step.

[0010] As a preferred embodiment of the present invention, the C content concentration of the second thyristor suppression layer remains constant, and the C content concentration is 1E17~5E18cm⁻¹. -3 The Si doping concentration of the second thyristor suppression layer remains constant at 5E17–5E18 cm⁻¹. -3 The Si doping concentration of the first thyristor suppression layer exhibits a peak-like distribution, with the peak Si doping concentration ranging from 1E18 to 2E19 cm⁻¹. -3 The Si doping concentration of the third thyristor suppression layer exhibits a peak-like distribution, with the peak Si doping concentration ranging from 8E17 to 5E18 cm⁻¹. -3 The Si doping concentration of the first thyristor suppression layer, the second thyristor suppression layer, and the third thyristor suppression layer is greater than the C content concentration.

[0011] Furthermore, the C content in the second thyristor suppression layer decreases in a double-step manner towards the first thyristor suppression layer, including a first C content decrease step and a second C content decrease step. The C content concentration in the first C content decrease step ranges from 5E17 to 5E18 cm⁻¹. -3 Decrease of 1E17~5E17cm -3 The C content concentration in the second decreasing step ranges from 1E17 to 5E17 cm⁻¹. -3 Decreased to 1E16~1E17cm -3The C content from the second thyristor suppression layer to the third thyristor suppression layer exhibits a double-step decreasing trend, including a third C content decreasing step and a fourth C content decreasing step. The C content concentration of the third C content decreasing step ranges from 5E17 to 5E18 cm⁻¹. -3 Decrease of 1E17~5E17cm -3 The C content concentration in the fourth C content decreasing step ranges from 1E17 to 5E17 cm⁻¹. -3 Decreased to 1E16~1E17cm -3 .

[0012] As a preferred embodiment of the present invention, the H content of the first thyristor suppression layer, the second thyristor suppression layer, and the third thyristor suppression layer remains constant, and the H content concentration is 1E17~1E18 cm⁻¹. -3 The O content of the first thyristor suppression layer 103a, the second thyristor suppression layer, and the third thyristor suppression layer 103c remains constant, with an O content concentration of 1E16~17E17 cm⁻¹. -3 .

[0013] As a preferred embodiment of the present invention, the first n-type semiconductor layer, the second n-type semiconductor layer, the thyristor suppression layer, the quantum well layer, and the p-type semiconductor layer are any one or any combination of GaN, AlGaN, InGaN, AlInGaN, AlN, InN, and AlInN.

[0014] As a preferred technical solution of the present invention, the quantum well layer is a periodic structure composed of a well layer and a barrier layer. The number of periods of the quantum well layer is x: 5≤x≤20, the thickness of the quantum well layer is a: 20 angstroms≤a≤60 angstroms, and the thickness of the barrier layer of the quantum well layer 104 is b: 20 angstroms≤b≤150 angstroms.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0016] In the solution of this invention:

[0017] Compared to existing technologies, this invention designs a thyristor suppression layer, which combines three semiconductor structures with different C content concentrations, a double-step decreasing C content, and Si, H, and O doping concentrations. This suppresses deep-level defect centers and inhibits the interjunction capacitance generated by the interleaving of PN junctions, reducing the probability of thyristor generation from 1-5% to 0, thus solving the problem of inconsistent lighting during the use of semiconductor light-emitting elements. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of a semiconductor device with a thyristor suppression layer in this invention;

[0019] Figure 2 This is a SIMS secondary ion mass spectrum of a semiconductor device with a thyristor suppression layer in this invention;

[0020] Figure 3 for Figure 2 A magnified view of a portion of the image.

[0021] Figure label:

[0022] 100. Substrate; 101. First n-type semiconductor layer; 102. Second n-type semiconductor layer; 103. Thyristor suppression layer; 103a: First thyristor suppression layer; 103b: Second thyristor suppression layer; 103c: Third thyristor suppression layer; 104. Quantum well layer; 105. P-type semiconductor layer. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0024] Therefore, the following detailed description of embodiments of the present invention is not intended to limit the scope of the claimed invention, but merely illustrates some embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0025] It should be noted that, unless otherwise specified, the embodiments and features and technical solutions in the present invention can be combined with each other.

[0026] Please see Figure 1 This embodiment provides a technical solution: a semiconductor device with a thyristor suppression layer, comprising a substrate 100, a first n-type semiconductor layer 101, a second n-type semiconductor layer 102, a thyristor suppression layer 103, a quantum well layer 104 and a p-type semiconductor layer 105 arranged sequentially from bottom to top.

[0027] Furthermore, the thyristor suppression layer 103 is composed of a first thyristor suppression layer 103a, a second thyristor suppression layer 103b, and a third thyristor suppression layer 103c from bottom to top.

[0028] Furthermore, the C content of the second thyristor suppression layer 103b to the first thyristor suppression layer 103a exhibits a double-step decreasing trend, including a first C content decreasing step and a second C content decreasing step; the angle of the first C content decreasing step is α: 60°≥α≥15°, and the angle of the second C content decreasing step is β: 90°≥β≥30°.

[0029] Furthermore, the C content from the second thyristor suppression layer 103b to the third thyristor suppression layer 103c exhibits a double-step decreasing trend, including a third C content decreasing step and a fourth C content decreasing step; the angle of the third C content decreasing step is γ: 80°≥γ≥20°, and the angle of the fourth C content decreasing step is θ: 90°≥θ≥30°.

[0030] Furthermore, the angle β of the second C content decrease step ≥ the angle θ of the fourth C content decrease step ≥ the angle γ of the third C content decrease step ≥ the angle α of the first C content decrease step.

[0031] Furthermore, such as Figures 2-3 As shown, the C content concentration of the second thyristor suppression layer 103b remains constant, ranging from 1E17 to 5E18 cm⁻¹. -3 The Si doping concentration of the second thyristor suppression layer 103b remains constant at 5E17–5E18 cm⁻¹. -3 The Si doping concentration of the first thyristor suppression layer 103a exhibits a peak-like distribution, with the peak Si doping concentration ranging from 1E18 to 2E19 cm⁻¹. -3 The Si doping concentration of the third thyristor suppression layer 103c exhibits a peak-like distribution, with the peak Si doping concentration ranging from 8E17 to 5E18 cm⁻¹. -3 The Si doping concentration of the first thyristor suppression layer 103a, the second thyristor suppression layer 103b, and the third thyristor suppression layer 103c is greater than the C content concentration.

[0032] Furthermore, the C content in the second thyristor suppression layer 103b decreases in a double-step manner towards the first thyristor suppression layer 103a, including a first C content decrease step and a second C content decrease step. The C content concentration in the first C content decrease step ranges from 5E17 to 5E18 cm⁻¹. -3 Decrease of 1E17~5E17cm -3 The C content concentration in the second decreasing step ranges from 1E17 to 5E17 cm⁻¹. -3 Decreased to 1E16~1E17cm -3 The C content in the second thyristor suppression layer 103b to the third thyristor suppression layer 103c exhibits a double-step decreasing trend, including a third C content decreasing step and a fourth C content decreasing step. The C content concentration in the third C content decreasing step ranges from 5E17 to 5E18 cm⁻¹. -3 Decrease of 1E17~5E17cm -3 The C content concentration in the fourth C content decreasing step ranges from 1E17 to 5E17 cm⁻¹. -3 Decreased to 1E16~1E17cm -3 .

[0033] Furthermore, the H content of the first thyristor suppression layer 103a, the second thyristor suppression layer 103b, and the third thyristor suppression layer 103c remains constant, with an H content concentration of 1E17 to 1E18 cm⁻¹. -3 The O content of the first thyristor suppression layer 103a, the second thyristor suppression layer 103b, and the third thyristor suppression layer 103c remains constant, with an O content concentration of 1E16~17E17 cm⁻¹. -3 .

[0034] In the thyristor suppression layer, three semiconductor structures with different C content concentrations, a double-step decreasing trend of C content, and Si doping, H content concentration, and O content concentration are designed together to suppress deep level defect centers and suppress the interjunction capacitance generated by the interleaving of PN junctions. This reduces the probability of thyristor generation from 1-5% to 0, solving the problem of inconsistent lighting during the use of semiconductor light-emitting elements.

[0035] Furthermore, the first n-type semiconductor layer 101, the second n-type semiconductor layer 102, the thyristor suppression layer 103, the quantum well layer 104, and the p-type semiconductor layer 105 are any one or any combination of GaN, AlGaN, InGaN, AlInGaN, AlN, InN, and AlInN.

[0036] Furthermore, the quantum well layer 104 is a periodic structure composed of a well layer and a barrier layer. The number of periods of the quantum well layer 104 is x: 5≤x≤20, the thickness of the quantum well layer 104 is a: 20 angstroms≤a≤60 angstroms, and the thickness of the barrier layer 104 is b: 20 angstroms≤b≤150 angstroms.

[0037] An experiment was conducted using the technical solution described in the embodiments to test a green laser. The experimental results are as follows. relatively The data comparison with traditional semiconductor devices is as follows: ： ;

[0038] semiconductor components Traditional semiconductor components Semiconductor element of the present invention range of change Bruxelle generation rate 4.8 0％ -100％ White light photoelectric conversion efficiency (lm / W) 180 260 44％

[0039] Compared to existing technologies, this invention designs a thyristor suppression layer, which combines three semiconductor structures with different C content concentrations, a double-step decreasing C content, and Si, H, and O doping concentrations. This suppresses deep-level defect centers and inhibits the interjunction capacitance generated by the interleaving of PN junctions, reducing the probability of thyristor generation from 1-5% to 0, thus solving the problem of inconsistent lighting during the use of semiconductor light-emitting elements.

[0040] The above embodiments are only used to illustrate the present invention and are not intended to limit the technical solutions described herein. Although the present invention has been described in detail with reference to the above embodiments, the present invention is not limited to the specific embodiments described above. Therefore, any modifications or equivalent substitutions to the present invention, as well as all technical solutions and improvements that do not depart from the spirit and scope of the invention, are covered within the scope of the claims of the present invention.

Claims

1. A semiconductor element having a gate current suppressing layer, characterized by, The semiconductor structure comprises, from bottom to top, a substrate (100), a first n-type semiconductor layer (101), a second n-type semiconductor layer (102), a gate runner suppression layer (103), a quantum well layer (104), and a p-type semiconductor layer (105). The gate runner suppression layer (103) is designed to have three layers of different C content concentrations, including a semiconductor structure of Si doping concentration, H content concentration, and O content concentration, wherein the C content has a double-step downward trend. The gate runner suppression layer (103) is composed of a first gate runner suppression layer (103a), a second gate runner suppression layer (103b), and a third gate runner suppression layer (103c) from bottom to top; the second gate runner suppression layer (103b) has a double-step downward trend of C content to the first gate runner suppression layer (103a), including a first C content downward step and a second C content downward step; the first C content downward step has an angle α: 60°≥α≥15°, and the second C content downward step has an angle β: 90°≥β≥30°; the second gate runner suppression layer (103b) has a double-step downward trend of C content to the third gate runner suppression layer (103c), including a third C content downward step and a fourth C content downward step; the third C content downward step has an angle γ: 80°≥γ≥20°, and the fourth C content downward step has an angle θ: 90°≥θ≥30°.

2. The semiconductor element having a gate current suppressing layer according to claim 1, wherein The second C content downward step angle β≥the fourth C content downward step angle θ≥the third C content downward step angle γ≥the first C content downward step angle α.

3. The semiconductor device having a gate current suppressing layer according to claim 2, wherein The C content concentration of the second gate current suppression layer (103b) is kept constant, and the C content concentration is 1E17-5E18 cm -3 ; the Si doping concentration of the second gate current suppression layer (103b) is kept constant, and the Si doping concentration is 5E17-5E18 cm -3 ; the Si doping concentration of the first gate current suppression layer (103a) is in a mountain shape, and the peak Si doping concentration is 1E18-2E19 cm -3 ; the Si doping concentration of the third gate current suppression layer (103c) is in a mountain shape, and the peak Si doping concentration is 8E17-5E18 cm -3 ; and the Si doping concentration of the first gate current suppression layer (103a), the second gate current suppression layer (103b), and the third gate current suppression layer (103c) is greater than the C content concentration.

4. The semiconductor device having a gate current suppressing layer according to claim 3, wherein The C content in the second thyristor suppression layer (103b) decreases in a double-step manner towards the first thyristor suppression layer (103a), including a first C content decrease step and a second C content decrease step. The C content concentration in the first C content decrease step ranges from 5E17 to 5E18 cm⁻¹. -3 Decrease of 1E17~5E17cm -3 The C content concentration in the second decreasing step ranges from 1E17 to 5E17 cm⁻¹. -3 Decreased to 1E16~1E17cm -3 The C content in the second thyristor suppression layer (103b) decreases in a double-step manner towards the third thyristor suppression layer (103c), including a third C content decrease step and a fourth C content decrease step. The C content concentration in the third C content decrease step ranges from 5E17 to 5E18 cm⁻¹. -3 Decrease of 1E17~5E17cm -3 The C content concentration in the fourth C content decreasing step ranges from 1E17 to 5E17 cm⁻¹. -3 Decreased to 1E16~1E17cm -3 .

5. The semiconductor device having a gate current suppressing layer according to claim 1, wherein The H content of the first gate fluid suppression layer (103a), the second gate fluid suppression layer (103b), and the third gate fluid suppression layer (103c) is kept constant, with an H content concentration of 1E17 to 1E18 cm -3 The O content of the first gate fluid suppression layer (103a), the second gate fluid suppression layer (103b), and the third gate fluid suppression layer (103c) is kept constant, with an O content concentration of 1E16 to 17E17 cm -3 .

6. The semiconductor device having a gate current suppressing layer according to claim 1, wherein The first n-type semiconductor layer (101), the second n-type semiconductor layer (102), the gate runner suppression layer (103), the quantum well layer (104), and the p-type semiconductor layer (105) are any one or any combination of GaN, AlGaN, InGaN, AlInGaN, AlN, InN, and AlInN.

7. The semiconductor device having a gate current suppressing layer according to claim 1, wherein The quantum well layer (104) is a periodic structure composed of a well layer and a barrier layer, the quantum well layer (104) has a period number x: 5≤x≤20, the well layer of the quantum well layer (104) has a thickness a: 20 angstrom meters≤a≤60 angstrom meters, and the barrier layer of the quantum well layer (104) has a thickness b: 20 angstrom meters≤b≤150 angstrom meters.

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