Voltage reduction converter and control method

Abstract

An apparatus is disclosed that includes a PWM ramp generator coupled between a switch node of a power converter and a first input of a comparator. The PWM ramp generator includes a first resistor and a first capacitor connected in series between the switch node and the first input of the comparator, and a second resistor and a second capacitor connected in parallel between the first input of the comparator and a feedback node. A PFM control circuit includes an error amplifier and a current zero-crossing detection comparator, where the error amplifier is coupled between a second input of the comparator and a reference node. The PFM control circuit is configured to generate a gate drive signal for the power converter when the power converter is configured to operate in a PFM mode.

Description

[0001] Priority claims and cross-references

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 268,112, filed February 16, 2022, entitled “Buck Converter and Control Method”, and U.S. Application No. 18 / 056,758, filed November 18, 2022, entitled “Buck Converter and Control Method”, which are hereby incorporated herein by reference. Technical Field

[0003] This application relates to the field of DC-DC power conversion systems, and more specifically, to a buck DC / DC converter that provides the fastest output load transient response and enables users to set the desired output voltage using an output feedback resistor divider. This buck DC / DC converter allows users to design power supplies for different applications using a single integrated circuit (IC) device. Background Technology

[0004] The modern evolution of mobile devices (such as smartphones), tablets, laptops, and data centers demands DC / DC converters with the fastest input transient response and load transient response. On the other hand, there is a desire for each DC / DC converter to be designed for many different system applications to simplify materials.

[0005] Various control schemes have been applied to buck converters. Among all the control schemes applied to buck converters, hysteresis control has been widely adopted because it has the fastest output transient response under transient events of input or output load. However, to achieve the fastest output transient response, the output voltage must be directly fed back to the hysteresis comparator, which limits the range of output voltages that a hysteresis-controlled buck converter can operate on. This is because, in many cases, the output ripple voltage is used as the ramp voltage required by the hysteresis comparator.

[0006] In some hysteresis control schemes, the ramp voltage can be generated by a dedicated circuit. Therefore, the ramp voltage can be independent of the output ripple voltage. However, to achieve excellent output transient response, the output voltage still needs to be connected to the input of the hysteresis comparator via an output feedback divider. The output feedback divider is designed so that the output voltage can be adjusted to different values. One disadvantage of using such an output feedback divider is that the attenuation introduced by the output feedback divider reduces the output voltage deviation signal fed back to the input during output transient events. The reduced voltage deviation therefore results in a slower input and load transient response. Due to the slower input and load transient response, more capacitors are needed to keep the output transient response within specification limits. This results in a solution that requires a more expensive and larger printed circuit board (PCB) area. One known hysteresis control method is... Figure 1 As shown, this problem can be solved.

[0007] Figure 1 A schematic diagram of a power converter is shown. Power converter 100 is a buck converter, including an input filter capacitor 101, a high-side switch 102, a low-side switch 103, an output inductor 104, and an output filter capacitor 105. The hysteresis controller of power converter 100 includes a resistor 111, a capacitor 108, a hysteresis comparator 112, and a drive circuit 113. The hysteresis controller of power converter 100 also includes an output feedback voltage divider, which includes resistors 106, 107, 109, and a capacitor 110. Figure 1 The REF voltage shown is a constant reference voltage. The output voltage (VOUT) of the power converter 100 can be expressed by the following formula:

[0008] = (1 + R106 / R107) * REF(1)

[0009] In equation (1), R106 is the resistance value of resistor 106, and R107 is the resistance value of resistor 107.

[0010] The slow output transient response problem can be addressed by adding capacitor 110. In operation, capacitor 110 acts as a feedforward capacitor to directly transmit the output voltage deviation to the inverting input of the hysteresis comparator 112 without any attenuation. Furthermore, capacitor 110 also absorbs the DC voltage difference between the output VOUT and the feedback node FB. Resistor 109 provides a DC path for the leakage current flowing out of the inverting input of comparator 112. Additionally, resistor 109, capacitor 108, and capacitor 110 form a high-pass filter. This high-pass filter is designed so that most of the output voltage deviation during output transient events is directly fed to the inverting input of the hysteresis comparator 112.

[0011] Figure 1 The hysteresis control method shown has three drawbacks. First, the capacitance of capacitor 110 must be larger than that of capacitor 108 to avoid capacitive voltage division when the output voltage deviation is fed to comparator 112 during output load transient events. A larger capacitor means a larger silicon area, additional power consumption, and complexity. Second, Figure 1The hysteresis control method shown requires two inputs, VOUT and FB. This control system configuration is incompatible with the most popular control schemes (e.g., voltage-mode control, current-mode control, and constant on-time control) because FB is the only input required in these schemes. Third, the voltage drop across the DC resistance (DCR) of the output inductor will appear across capacitor 108 due to the output load current. This means that the average voltage across capacitor 108 during the output load transient response depends on the different output load currents. The voltage change across capacitor 108 affects the voltage at the inverting input of hysteresis comparator 112. This voltage change at the inverting input of hysteresis comparator 112 can affect the output transient response of power converter 100.

[0012] Therefore, there is a need in the art for a control device with only FB input to set the output voltage to different values ​​for different applications, such as pulse width modulation (PWM) applications and pulse frequency modulation (PFM) applications. At the same time, the control device should be able to achieve the same functionality as described above. Figure 1 The output transient response of the circuits discussed is the same or similar. Summary of the Invention

[0013] The embodiments of this application aim to provide a hysteresis control device and method for a buck converter, which generally solves or avoids the above-mentioned problems and can achieve technical advantages.

[0014] To achieve the above objectives, in a first aspect, this application provides an apparatus including a PWM ramp generator coupled between a switching node of a power converter and a first input terminal of a comparator. The PWM ramp generator includes a first resistor and a first capacitor connected in series between the switching node and the first input terminal of the comparator, and a second resistor and a second capacitor connected in parallel between the first input terminal of the comparator and a feedback node. The apparatus also includes an error amplifier and a PFM control circuit for a current zero-crossing detection comparator. The error amplifier is coupled between a second input terminal of the comparator and a reference node, and the PFM control circuit is configured to generate a signal for driving the gate of the power converter when the power converter is configured to operate in PFM mode.

[0015] Secondly, this application provides a method comprising configuring multiple control switches in the PWM mode of a power converter to generate a gate drive signal for the power converter based on a comparison between the output of a PWM ramp generator and a preset reference voltage. Furthermore, in the PFM mode of the power converter, multiple control switches are configured to generate a gate drive signal for the power converter based on a signal generated by an error amplifier and a current zero-crossing detection comparator.

[0016] Thirdly, this application provides a system including a high-side switch and a low-side switch connected in series between an input voltage bus and ground, wherein the common node of the high-side switch and the low-side switch is a switching node. The system also includes an inductor connected between the common node of the high-side switch and the low-side switch and the system output, and a PWM ramp generator coupled between the switching node and a first input terminal of a comparator. The PWM ramp generator includes a first resistor and a first capacitor connected in series between the switching node and the first input terminal of the comparator, and a second resistor and a second capacitor connected in parallel between the first input terminal of the comparator and a feedback node. The system also includes a PFM control circuit, which includes an error amplifier and a current zero-crossing detection comparator circuit, wherein the error amplifier is coupled between a second input terminal of the comparator and a reference node. When the system operates in PFM mode, the PFM control circuit is configured to generate a gate drive signal for the system.

[0017] The features and technical advantages of this application have been outlined quite extensively above to facilitate a better understanding of the detailed description thereof below. Additional features and advantages of this application will be described below, forming the subject matter of the claims. Those skilled in the art will understand that the disclosed concepts and specific embodiments can be readily used as the basis for modifying or designing other structures or processes to achieve the same purpose as this application. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this application as set forth in the appended claims. Attached Figure Description

[0018] To gain a more comprehensive understanding of this application and its advantages, the following description is now taken in conjunction with the accompanying drawings, in which:

[0019] Figure 1 This is a schematic diagram of a power converter;

[0020] Figure 2 This application provides a power converter and associated PWM and PFM control circuits in its embodiments.

[0021] Figure 3 This application provides an embodiment of a power converter configured to operate in PWM mode. Figure 2 A schematic diagram of the power converter shown;

[0022] Figure 4 The embodiments provided in this application are related to Figure 3 A schematic diagram of the various signals associated with the power converter shown;

[0023] Figure 5 This is a schematic diagram of the frequency response curve of the feedback voltage divider network gain provided in the embodiments of this application;

[0024] Figure 6 This is a schematic diagram of the frequency response curve of the gain of an error amplifier with a dominant pole provided in an embodiment of this application;

[0025] Figure 7 The embodiments provided in this application are related to Figure 6 A schematic diagram of the various signals associated with the error amplifier shown;

[0026] Figure 8 This is a schematic diagram of a first embodiment of the PFM control circuit provided in this application.

[0027] Figure 9 The embodiments provided in this application are related to Figure 8 A schematic diagram of the various voltage and current signals associated with the PFM control circuit shown;

[0028] Figure 10 This is a schematic diagram of a second embodiment of the PFM control circuit provided in this application.

[0029] Figure 11 The embodiments provided in this application are related to Figure 10 The diagram shows the various voltage and current signals associated with the PFM control circuit.

[0030] Figure 12 This is a schematic diagram of a third embodiment of the PFM control circuit provided in this application.

[0031] Figure 13 The embodiments provided in this application are related to Figure 12 A schematic diagram of the various voltage and current signals associated with the PFM control circuit shown;

[0032] Figure 14 This application provides embodiments for operation. Figure 2 The flowchart shows the control method of the power converter.

[0033] Unless otherwise stated, corresponding numbers and symbols in different figures generally refer to corresponding parts. The accompanying drawings are provided to clearly illustrate relevant aspects of various embodiments and are not necessarily drawn to scale. Detailed Implementation

[0034] The construction and use of the present preferred embodiments are discussed in detail below. However, it should be understood that this application provides many applicable inventive concepts that can be embodied in a wide variety of specific environments. The specific embodiments discussed are merely illustrative of specific ways of making and using this application and do not limit the scope of this application.

[0035] This application will be described in conjunction with preferred embodiments in a specific context, namely, a hysteresis control device and method for a buck converter. However, this application can also be applied to various power conversion systems. Various embodiments will be explained in detail below with reference to the accompanying drawings.

[0036] Figure 2 The illustration shows a power converter and associated PWM and PFM control circuitry according to various embodiments of this application. The power converter is a buck converter, including an input filter capacitor 201, a high-side switch 202, a low-side switch 203, an output inductor 204, and an output filter capacitor 205. Figure 2 As shown, high-side switch 202 and low-side switch 203 are connected in series between the input voltage bus and ground. The common node of high-side switch 202 and low-side switch 203 is the switching node of the power converter. Figure 2 (SW in the diagram). Output inductor 204 is connected between the common node of high-side switch 202 and low-side switch 203 and the output of the power converter.

[0037] The control circuit of the power converter includes a PWM ramp generator 210, a PFM control circuit 250, a comparator 215, a feedback voltage divider, and control logic and gate drive circuit 216.

[0038] In some embodiments, comparator 215 is implemented as a hysteresis comparator. Comparator 215 is configured to generate control signals fed into the control logic and gate drive circuitry 216.

[0039] like Figure 2 As shown, the feedback voltage divider consists of resistors 206 and 207. The common node of resistors 206 and 207 is the feedback node of the power converter. To obtain a better transient response, capacitor 208 is connected in parallel with resistor 206. Capacitor 208 serves as a feedforward capacitor.

[0040] like Figure 2 As shown, the PWM ramp generator 210 is coupled between the switching node SW of the power converter and the first input of the comparator 215. More specifically, the PWM ramp generator 210 is connected to the switching node SW via a third control switch S3.

[0041] The PWM ramp generator 210 includes a first resistor 211 and a first capacitor 212 connected in series between the third control switch S3 and the first input terminal of the comparator 215. The first input terminal is the inverting input terminal of the comparator 215. The PWM ramp generator 210 also includes a second resistor 214 and a second capacitor 213 connected in parallel between the first input terminal of the comparator 215 and the feedback node FB.

[0042] like Figure 2As shown, the PFM control circuit 250 includes an error amplifier 230 and a current zero-crossing detection comparator 220. The error amplifier 230 is coupled between the second input of the comparator 215 and the reference node REF. The second input is the non-inverting input of the comparator 215. When the power converter operates in PFM mode, the PFM control circuit 250 is configured to generate the gate drive signal required by the power converter.

[0043] It should be noted that, Figure 2 The block diagram of the PFM control circuit 250 shown only includes the basic functional units of the PFM control circuit 250. The structure of the PFM control circuit 250 can vary depending on the different PFM control schemes. In some embodiments, the threshold voltage generator can be coupled between the non-inverting input of the comparator 215 and the error amplifier 230. A detailed implementation of this PFM control scheme will be referenced below. Figure 8-9 The following description is provided. In an alternative embodiment, a peak current detection comparator can be used to determine the on-time of the high-side switch 202. The following will refer to... Figures 10-11 This describes the detailed implementation of the PFM control scheme. In an alternative embodiment, a constant on-time generator can be used to determine the on-time of the high-side switch. The following will refer to... Figure 12-13 Describe the detailed implementation of this PFM control scheme.

[0044] Three control switches are used to change the control circuit configuration according to different operating modes. For example... Figure 2 As shown, the first control switch S1 is connected between the first input terminal of comparator 215 and the feedback node FB. The second control switch S2 is connected between the second input terminal of comparator 215 and the reference node REF. The third control switch S3 is connected between the switching node SW and the first resistor 211. In operation, when the power converter is configured to operate in PWM mode, the second switch S2 and the third switch S3 are configured to be on, and the first switch S1 is configured to be off. On the other hand, when the power converter is configured to operate in PFM mode, the second switch S2 and the third switch S3 are configured to be off, and the first switch S1 is configured to be on. It is worth mentioning that, depending on the design requirements, the third switch S3 can be placed at any position between the switching node SW and the first input terminal of comparator 215. In other words, the third switch S3 is coupled between the switching node SW and the first input terminal of comparator 215. It should also be noted that, depending on the design requirements, the positions of the first resistor 211 and the first capacitor 212 can be interchanged.

[0045] In some embodiments, a resistor-capacitor filter (not shown) may be connected to the switching node SW. In operation, the resistor-capacitor filter is configured such that its output voltage is used to determine the output voltage Vo of the power converter when the power converter is configured to operate in PWM mode during the initial power-on cycle. Vo, along with the input voltage, may be used to determine the output value of the constant on-time generator used in constant on-time PFM control.

[0046] In some embodiments, the PWM ramp generator 210, three control switches S1-S3, comparator 215, PFM control circuitry 250, and control logic and gate drive circuitry 216 can be integrated into a single IC device or on a printed circuit board. In an alternative embodiment, switches 202 and 203 can also be integrated into the single IC device.

[0047] In PWM mode operation, the PWM ramp generator 210 generates a sawtooth ramp voltage based on the voltage at the FB node. The sum of the sawtooth ramp voltage and the voltage at the FB node is compared with the REF voltage to control the on and off time intervals of power switches 202 and 203, thereby regulating the output voltage of the power converter within specification limits.

[0048] In PWM mode operation, only the ramp voltage across capacitor 213 is used to determine the on and off time intervals of power switches 202 and 203. Capacitor 208 is introduced to pass the deviation of the output voltage from VOUT to the feedback node FB, which is then input to the inverting input of the hysteresis comparator 215. This attenuation is minimal, resulting in good output transient response and good DC regulation. The capacitance value of capacitor 208 is chosen such that the impedance formed by resistor 206 and capacitor 208 is much smaller at the switching frequency of interest than the impedance formed by capacitor 213 and resistor 214. In some embodiments, the impedance formed by resistor 214 and capacitor 213 is at least five times larger than the impedance formed by resistor 206 and capacitor 208.

[0049] like Figure 2As shown, the DC voltage difference between VOUT and the feedback node FB decreases across resistors 211 and 214 and capacitors 212 and 213. Since capacitor 213 and resistor 214 are connected in parallel, their DC impedance depends on resistor 214. Resistor 211 and capacitor 212 are connected in series. Their DC impedance is determined by capacitor 212. Furthermore, if resistors 211 and 214 are designed such that the value of resistor 211 is much larger than the value of resistor 214 (e.g., resistor 211 is 10 times larger than resistor 214), most of the DC voltage difference between the VOUT node and the feedback node FB decreases across capacitor 212. This relationship is independent of the capacitance value of capacitor 212. For example, the capacitance value of capacitor 212 can even be smaller than the capacitance value of capacitor 213.

[0050] Figure 2 One advantage of the power converter shown is that all control components can be integrated into a single IC device. Furthermore, due to the output current, most of the voltage across the output inductor DCR is applied to capacitor 212 in the steady state. During transient events in the output load, when the output current changes, the voltage across the output inductor DCR also changes. The voltage across capacitor 212 cannot change instantaneously. Therefore, the changing voltage is primarily reflected across resistors 211 and 214. Since the resistance of resistor 214 is much smaller than that of resistor 211, most of the changing voltage is applied across resistor 211. Therefore, the inverting input of the hysteresis comparator 215 remains relatively constant. Figure 1 Compared to the control circuit shown, those skilled in the art will understand that during output load transient events, capacitor 212 is not in the path between the output node VOUT and the inverting input of the hysteresis comparator 215. Therefore, capacitor 212 will not cause a capacitive voltage divider effect.

[0051] Figure 3 The illustrations depict various embodiments of the present application when the power converter is configured to operate in PWM mode. Figure 2 A schematic diagram of the power converter shown. Once Figure 2 The power converter shown is configured to operate in PWM mode. Figure 2 The control switches S2 and S3 shown are on, and the control switch S1 is off. Figure 2 The circuit shown can be simplified to Figure 3 The circuit shown.

[0052] like Figure 3As shown, the PWM ramp generator 210 includes a first resistor 211 and a first capacitor 212 connected in series between the switching node SW and the inverting input of the comparator 215. The PWM ramp generator 210 also includes a second resistor 214 and a second capacitor 213 connected in parallel between the inverting input of the comparator 215 and the feedback node FB. Resistor 214 provides a DC path for the leakage current flowing out of the inverting input of the comparator 215. Furthermore, resistor 214 can eliminate the effect of the capacitive voltage divider formed by capacitors 212 and 213. Therefore, regardless of the capacitance value of capacitor 212, most of the voltage difference between VOUT and the feedback node FB is applied across capacitor 212.

[0053] In operation, resistors 211 and 214, along with capacitors 212 and 213, are used to generate a sawtooth ramp voltage V applied to the inverting input of comparator 215. RAMP Specifically, after the high-side switch 202 is turned on, the voltage across the switching node SW is pulled up to the input voltage VIN. After the high-side switch 202 is turned off and the low-side switch 203 is turned on, the voltage across the switching node SW is pulled down to ground. When the voltage across the switching node SW is pulled up to VIN, capacitor 213 is charged by the voltage across the switching node SW through resistor 211 and capacitor 212. When the voltage across the switching node SW is pulled down to ground, capacitor 213 discharges through resistor 211 and capacitor 212. As a result, a ramp voltage V is generated across capacitor 213. RAMP .

[0054] Furthermore, one end of capacitor 213 is connected to the feedback node FB. When the feedback voltage at the feedback node FB shifts up and down, the voltage at the inverting input of comparator 215 shifts up and down accordingly. In some embodiments, the capacitance of capacitor 208 is much larger than that of capacitor 213. Because the capacitance of capacitor 208 is much larger than that of capacitor 213, any voltage deviation at VOUT is almost attenuated through capacitor 208. This feature helps the power converter 200 achieve a fast transient response during output transient events.

[0055] ramp voltage V RAMP The magnitude can be adjusted by adjusting the time constant. The time constant τ is given by the following equation:

[0056] τ=((R211×R214) / (R211+R214))×C213(2)

[0057] In equation (2), R211 is the resistance of resistor 211. R214 is the resistance of resistor 214. C213 is the capacitance of capacitor 213. In some embodiments, the time constant τ should be much larger than the switching cycle in PWM mode. For example, the time constant τ is at least five times the switching cycle in PWM mode.

[0058] The time constant determined by equation (2) determines the gain of the hysteresis comparator. The gain affects the stability of the closed-loop performance of the power converter 200. Once the values ​​of resistors 211 and 214 and capacitors 212 and 213 are determined, the amplitude of the ramp voltage across capacitor 213 is a function of the input and output voltages. The amplitude variations of different input and output voltages are independent of the output load current.

[0059] In some embodiments, the voltage REF at the non-inverting input of comparator 215 includes a square wave signal (not shown, but...). Figure 4 (As shown in the diagram). The peak and valley values ​​of the square wave signal represent the trigger thresholds for the high-side switch 202 of comparator 215 to turn on and off, respectively. The difference between the peak and valley values ​​of the square wave represents the hysteresis of comparator 215. This difference determines the switching frequency of power converter 200. The threshold (i.e., the difference between the peak and valley values) can be adjusted to obtain a constant switching frequency over a wide range of input and / or output voltages.

[0060] It should be noted that, under hysteresis control, the power converter 200 needs to operate at a constant switching frequency. A phase-locked loop (PLL) circuit can be used to adjust the difference between the peak and valley values ​​of the REF voltage to maintain a constant switching frequency over a wide range of input and / or output voltages.

[0061] Figure 4 The illustrations depict various embodiments of the present application. Figure 3 The diagram shows the various signals associated with the power converter. The horizontal axis represents time intervals, and there are six rows in total. The first row represents... Figure 3 The output voltage of the power converter is shown in the second row. The second row represents the ramp voltage V. RAMP And the reference voltage REF. The solid line in the second row represents the ramp voltage V. RAMP The dashed line represents the square wave portion of the reference voltage REF. The third line represents the current IL flowing through the output inductor of the power converter. The fourth line represents the output voltage Vc of comparator 215. The fifth line represents the gate drive signal V of the high-side switch of the power converter. GS1 The sixth line represents the gate drive signal V of the low-side switch of the power converter. GS2 .

[0062] At time t1, high-side switch 202 is turned on. The reference voltage REF jumps from its valley value to its peak value. From t1 to t2, high-side switch 202 remains on. Once high-side switch 202 is on, the input voltage VIN is applied to the switching node SW, and capacitor 213 is charged by the input voltage VIN. At time t2, comparator 215 is triggered because the voltage at the inverting input of comparator 215 reaches the peak value of the reference voltage REF. The output of comparator 215 generates a signal through control logic and gate drive circuit 216 to turn off high-side switch 202 and turn on low-side switch 203. At time t2, the reference voltage REF switches back to its valley value to maintain the output state of comparator 215.

[0063] During the time interval (t2-t3) when low-side switch 203 is on, switch node SW is pulled low to ground by low-side switch 203, capacitor 213 discharges, and the voltage at the inverting input of comparator 215 decreases. At time t3, the voltage at the inverting input reaches the valley of the reference voltage REF. In response, comparator 215 is triggered. The output of comparator 215 generates a signal to turn off low-side switch 203 and turns on high-side switch 202 through control logic and gate drive circuit 216. Starting from time t3, the switching cycle is as follows: Figure 4 The result is repeated.

[0064] During operation, various voltage deviations may occur at the output of the power converter 200. These voltage deviations are caused by input transients or output load transients. Depending on the operating conditions, the voltage deviation may be overshoot or undershoot. Furthermore, voltage deviations may occur at... Figure 4 During any of the indicated durations (e.g., from t1 to t2 or from t2 to t3). Figure 3 The control circuit shown provides a fast transient response to keep the output voltage within specification limits. The following discussion explains... Figure 3 The control circuit shown is able to provide a fast transient response under different voltage deviations.

[0065] During operation, if the voltage deviation is in an undershoot state and the high-side switch 202 is in the on state (from t1 to t2), the voltage deviation causes the voltage at the inverting input of comparator 215 to decrease. For example... Figure 4 As shown, a voltage drop at the inverting input of comparator 215 increases the on-time of high-side switch 202. This increased on-time of high-side switch 202 helps to increase the output voltage, thereby reducing voltage deviation. On the other hand, if the voltage deviation is in an undershoot state and low-side switch 203 is on (from t2 to t3), the voltage deviation will cause a voltage drop at the inverting input of comparator 215. Figure 4As shown in the diagram, the voltage drop at the inverting input of comparator 215 shortens the on-time of the low-side switch 203. This reduction in the on-time of the low-side switch 203 helps increase the output voltage, thereby reducing voltage deviation.

[0066] During operation, if the voltage deviation is in an overshoot state and the high-side switch 202 is in the on state (from t1 to t2), the voltage deviation causes the voltage at the inverting input of comparator 215 to increase. According to... Figure 4 As shown in the diagram, the increase in voltage at the inverting input of comparator 215 reduces the on-time of high-side switch 202. This reduction in the on-time of high-side switch 202 helps lower the output voltage, thereby reducing voltage deviation. On the other hand, if the voltage deviation is in an overshoot state and low-side switch 203 is on (from t2 to t3), the voltage deviation causes voltage overshoot at the inverting input of comparator 215. Based on the operating principle as follows... Figure 4 As shown, the voltage overshoot at the inverting input of comparator 215 increases the on-time of low-side switch 203. Increasing the on-time of low-side switch 203 helps to reduce the output voltage, thereby reducing voltage deviation.

[0067] From the above description, those skilled in the art can conclude that regardless of whether switch 202 or switch 203 is turned on when a deviation occurs, the power converter 200 with hysteresis control can respond instantly to the output voltage deviation. Figure 1 Compared to the power converter shown, Figure 3 The power converter 200 shown can provide the fastest output transient response, and the control circuit of the power converter 200 can be integrated into a single IC.

[0068] In some applications, power converters can be configured to operate under very light load conditions. Under light load conditions, the power converter is configured to operate in PFM mode to reduce power loss. In PFM mode, an error amplifier is required to improve the performance of the control circuitry. The following... Figures 5-6 This explains why a dominant pole error amplifier is used in PFM mode.

[0069] Figure 5 The illustration shows the frequency response curves of the feedback voltage divider network gain according to various embodiments of this application. The output feedback voltage divider network 300 is shown in the dashed rectangle 550. Resistors 301 and 302 determine the output voltage. The output voltage VOUT of the power converter can be expressed by the following formula:

[0070] VOUT=(1+R301 / R302)×REF(3)

[0071] In equation (3), R301 is the resistance of resistor 301. R302 is the resistance of resistor 302. The feedback node FB is connected to the first input terminal of the error amplifier. REF is connected to the second input terminal of the error amplifier. REF is the preset reference voltage.

[0072] Capacitor 303 helps the control circuit improve the output transient response. The gain of the FB node voltage relative to the output voltage VOUT is expressed by the following formula:

[0073] Gain = V_FB(S) / VOUT(S) (4)

[0074] The gain of equation (4) is plotted in the dashed rectangle 560. For example... Figure 5 As shown, the attenuation provided by resistors 301 and 302 decreases as the frequency increases. Once the frequency reaches levels above 100kHz, the attenuation becomes very small. In PFM mode operation, the switching frequency is a function of the output load current. The switching frequency varies widely across different load currents, ranging from a few hertz to several megahertz.

[0075] In traditional hysteresis controller PFM mode operation, the output ripple voltage is directly fed into the inverting input of the comparator. This implementation is simple and effective. However, this implementation cannot work in conjunction with the output of a feedback voltage divider network. For example... Figure 5 As shown, the gain of the feedback voltage divider network is approximately 0.17 at frequencies below 10kHz, while it shows almost no attenuation at high frequencies (>1MHz). This means that when the PFM switching frequency is 1MHz, the 20mV ripple voltage at the output VOUT can generate a voltage deviation of approximately 20mV at the feedback node FB without any attenuation. In contrast, when the PFM switching frequency is 10kHz, the 20mV ripple voltage at the output VOUT, after attenuation by the feedback voltage divider network, will generate a voltage deviation of approximately 3.4mV at the feedback node FB. The output ripple voltage at the feedback node FB feeds a very small signal to the inverting input of the comparator, which is likely to cause false triggering, resulting in frequency jitter and irregular output ripple voltage. To address the false triggering problem, this application introduces a voltage error amplifier with a dominant pole to improve the performance of the power converter in PFM mode.

[0076] Figure 6The diagram illustrates the gain versus frequency response curves of an error amplifier with a dominant pole according to various embodiments of this application. The error amplifier with a dominant pole is shown in the dashed rectangle 650. In some embodiments, the error amplifier is implemented as a transconductance operational amplifier 403. A resistor 402 and a capacitor 401 are connected in parallel between the output of the error amplifier 403 and ground. The frequency of the dominant pole is determined by the product of the capacitance of capacitor 401 and the resistance of resistor 402. The DC gain is determined by Gm (the gain of the transconductance operational amplifier) ​​and resistor 402. The voltage V at the output of the error amplifier is... ER Relative to the voltage V at the feedback node FB FB The gain is expressed by the following formula:

[0077] Gain = V_ER(S) / V_FB(S) (5)

[0078] The gain is plotted within the dashed rectangle 660. (Example) Figure 6 As shown, the gain is very high (about 70dB) when the frequency is less than 10Hz, while the gain is less than 0dB when the frequency is greater than 100kHz. Figure 6 The gain shown indicates that if the switching frequency is less than 100kHz, the voltage at the feedback node FB will be amplified. If the frequency is greater than 100kHz, the voltage at the feedback node FB will be attenuated. Figure 6 The error amplifier 403 shown will be used for PFM operation, which will be referred to below. Figures 8-13 Let's have a discussion.

[0079] It should be noted that the dominant pole of the error amplifier 403 should be designed at a 0dB frequency, and higher than the pole frequency formed by the feedback voltage divider network (e.g., as shown in the image). Figure 8 The pole shown is formed by resistors 506 and 507 and feedforward capacitor 508.

[0080] Figure 7 Description of various embodiments according to this application Figure 6 The diagram shows the various signals associated with the error amplifier. The horizontal axis represents the time interval. There are three rows in total. The first row represents the output voltage of the power converter. The second row represents the voltage V at the feedback node FB. FB The third line represents the voltage V at the output of the error amplifier. ER .

[0081] like Figure 7 As shown, if the ripple voltage on the feedback node FB is compared with the output voltage of the voltage error amplifier at a low PFM operating frequency, the error amplifier can improve the noise immunity of the FPM hysteresis comparator. Figure 7As shown, from t1 to t2, the output voltage of the voltage error amplifier may drop below a preset clamping point. To improve the output transient response during PFM mode operation, an active clamp (not shown) can be used to prevent the output of the error amplifier from becoming too low at very low frequencies. For example, from t1 to t2, the output of the error amplifier is clamped to keep the output of the error amplifier at a preset clamping point (…). Figure 7 (Clamping voltage shown).

[0082] Figure 8 The illustration shows a first embodiment of a PFM control circuit according to various embodiments of this application. Reference is also made to... Figure 2 When the power converter is configured to operate in PFM mode, Figure 2 As shown, S2 and S3 are turned off, while S1 is turned on. Figure 2 The circuit shown can be simplified to Figure 8 The circuit shown. In the first implementation of the PFM control circuit, a threshold voltage generator 515 is added to the PFM control circuit. (See diagram below.) Figure 8 As shown, the threshold voltage generator 515 is coupled between the second input terminal of the comparator 513 and the output terminal of the error amplifier 514. Figure 8 As shown, the functional unit in the dashed box 510 is the PFM control circuit of the power converter 500.

[0083] like Figure 8 As shown, the power converter 500 includes a buck power stage, an output feedback divider, and a PFM control circuit. The buck power stage includes an input filter capacitor 501, a power switch 502, a power switch 503, an output inductor 504, and an output filter capacitor 505. The output feedback divider includes resistors 506 and 507, and a feedforward capacitor 508. The PFM control circuit includes control logic and a gate drive circuit 511, a current zero-crossing detection comparator 512, a comparator 513, a threshold voltage generator 515, and an error amplifier 514.

[0084] In some embodiments, the error amplifier 514 is a transconductance operational amplifier with a dominant pole, for example... Figure 6 The error amplifier shown. Return to reference. Figure 6 Capacitor 401 and resistor 402 are connected in parallel between the output of the error amplifier and ground. Capacitor 401 and resistor 402 form the dominant pole.

[0085] In some embodiments, the non-inverting input of the error amplifier 514 is connected to a preset reference voltage REF. For example... Figure 6 As shown, the inverting input of the error amplifier 514 is connected to the feedback node FB.

[0086] During operation, the voltage V at the feedback nodeFB With the output voltage V of the error amplifier 514 ER and the threshold voltage V from the threshold voltage generator 515 TH The comparison of the sums is used to determine the on-time of the high-side switch 502 of the power converter 500. The voltage V at the feedback node... FB With the output voltage V of the error amplifier 514 ER The comparison is used to determine the turn-on time of the high-side switch 502. The current zero-crossing detection comparator 512 is configured to determine the turn-on time of the low-side switch 503 of the power converter 500 once the current flowing through the low-side switch 503 of the power converter 500 reaches zero.

[0087] Figure 9 Various embodiments of this application are illustrated with Figure 8 The first embodiment of the PFM control circuit shown in the diagram is associated with various voltage and current signals, arranged in ten rows, where the horizontal axis represents time intervals. The first row represents... Figure 8 The output voltage of the power converter is shown in the first row. The second row represents the current I_Q1 flowing through the high-side switch of the power converter. The third row represents the current I_Q2 flowing through the low-side switch of the power converter. The fourth row represents the current IL flowing through the inductor of the power converter. The fifth row represents... Figure 8 The signal V1 is shown. The sixth row represents... Figure 8 The signal V2 is shown. The seventh row represents... Figure 8 The signal shown is V3. The eighth row represents the output voltage V of the error amplifier. ER and the voltage V at the feedback node FB The solid line represents the V. ER The dashed line is a V. FB The ninth line represents the gate drive signal V of the high-side switch of the power converter. GS1 The tenth line represents the gate drive signal V of the low-side switch of the power converter. GS2 .

[0088] During operation, during the time interval (t1 to t2) when the high-side switch 502 is on, the inductor current IL increases from zero, and the output ripple voltage increases accordingly. In response to the increased output ripple voltage, the voltage at the feedback node FB also increases. Since the voltage at the feedback node FB is fed into the inverting input of the error amplifier (e.g., ...), ... Figure 6 (As shown), therefore the output voltage VER of the voltage error amplifier decreases. Once the voltage at the feedback node FB increases to a certain value, at which point the voltage at the inverting input of comparator 513 exceeds the threshold voltage V. TH and the output voltage V of the voltage error amplifier ERThe sum of these values ​​triggers comparator 513 (from logic high to logic low). In response to this logic state change, logic signal V1 flips from logic high to logic low at time t2. Logic signal V3 flips from logic low to logic high at time t2.

[0089] like Figure 9 As shown, in response to changes in logic signals V1 and V3, the control logic and gate drive circuit 511 turns off the high-side switch 502 and turns on the low-side switch 503 at time t2. Once the low-side switch 503 is turned on, the current zero-crossing detection comparator 512 is enabled to monitor the current (I_Q503) flowing through the low-side switch 503. At time t2, logic signal V2 changes from a logic low state to a logic high state. Figure 8 As shown, once the current flowing through the low-side switch 503 reaches zero (IZC_REF), the logic signal V2 changes from a logic high state to a logic low state at time t3. Figure 9 As shown, this change in the logic state of logic signal V2 causes the control logic and gate drive circuit 511 to turn off the low-side switch 503 at time t3, while keeping the high-side switch 502 off.

[0090] At time t3, the threshold voltage V from the threshold voltage generator 515 is removed. TH In other words, the output of the voltage error amplifier is directly connected to comparator 513. During the time interval t3 to t4, both switches 502 and 503 are open. The output voltage of the power converter gradually decreases as the output load current is maintained by discharging the output capacitor 505.

[0091] At time t4, the voltage (V) at the inverting input of comparator 513 is... FB This reaches the output voltage of the voltage error amplifier. For example... Figure 9 As shown, control logic signal V3 toggles from a logic high state to a logic low state. Control logic signal V1 toggles from a logic low state to a logic high state. These two logic state changes cause the control logic and gate drive circuit 511 to turn on the high-side switch 502 and keep the low-side switch 503 off. At time t4, the hysteresis threshold V from threshold voltage generator 515... TH This voltage is added to the output voltage of the error amplifier 514. The output voltage of the power converter 500 begins to increase. Once the output voltage of the power converter increases to a certain value, making the voltage at the inverting input of comparator 513 equal to the voltage at the non-inverting input, comparator 513 is triggered again, and as... Figure 9 The loop repeats as shown.

[0092] It should be noted that the threshold voltage V can be adjusted. THThis controls the energy transferred to the output during each PFM switching cycle. The energy transferred to the output during a PFM cycle also determines the peak value of the output ripple voltage during PFM mode operation.

[0093] During operation, when a voltage deviation occurs at the output of the power converter, the voltage at the FB node changes accordingly. In some embodiments, the output voltage deviation is in an undershoot state, and the output voltage deviation occurs during the time interval between when both switches 502 and 503 are open (e.g., from t3 to t4), causing a voltage undershoot at the feedback node FB. The voltage undershoot at the feedback node FB pulls the voltage at the inverting input of comparator 513 down to exceed the voltage at the non-inverting input of comparator 513. Figure 9 As shown in the diagram, comparator 513 triggers high-side switch 502 to transfer energy from input to output to maintain the output voltage in a regulated state.

[0094] In other embodiments, the output voltage deviation is in an undershoot state, and the output voltage deviation occurs during the time interval during which the high-side switch 502 is turned on (e.g., from t1 to t2). The voltage at the inverting input of comparator 513 drops sharply to increase the time it takes for it to rise to the voltage at the non-inverting input of comparator 513. Therefore, the high-side switch 502 remains on for a longer period to transfer more power from the input to the output to maintain a stable output voltage.

[0095] In some embodiments, the output voltage deviation is in an overshoot state, and the output voltage deviation occurs during the time interval (e.g., from t3 to t4) when both switches 502 and 503 are off. The output voltage overshoot causes an increase in the voltage at the inverting input of comparator 513. This increase in the voltage at the inverting input of comparator 513 causes a trigger delay. Therefore, both switches 502 and 503 remain off for a longer period to reduce the energy delivered to the output within one PFM switching cycle, thereby maintaining the output voltage in a regulated state.

[0096] In other embodiments, the output voltage deviation is in an overshoot state, and the output voltage deviation occurs during the time interval of the high-side switch 502 being turned on (e.g., from t1 to t2). The overshoot causes an increase in the voltage at the inverting input of comparator 513. The increase in the voltage at the inverting input of comparator 513 causes comparator 513 to trigger prematurely. Premature triggering turns off the high-side switch 502 to reduce the energy transferred to the output during one PFM switching cycle, thereby maintaining the output voltage in a regulated state.

[0097] It should be noted that the above transient response may cause frequency variations in the PFM mode.

[0098] From the above description, those skilled in the art will recognize that the voltage threshold VTH Determine the energy delivered to the power converter output within one PFM switching cycle. Voltage threshold V TH It also determines the peak output ripple voltage during PFM operation. Threshold voltage V TH The output ripple voltage can be adjusted according to the input and output voltages to maintain a relatively constant output ripple voltage in PFM mode.

[0099] Figure 10 A second embodiment of the PFM control circuit according to various embodiments of this application is illustrated. Reference is also made to... Figure 2 When the power converter is configured to operate in PFM mode, Figure 2 As shown, S2 and S3 are turned off, while S1 is turned on. Figure 2 The circuit shown can be simplified to Figure 10 The circuit shown. In the second implementation of the PFM control circuit, a peak current detection comparator 615 is added to the PFM control circuit. (See diagram below.) Figure 10 As shown, the peak current detection comparator 615 is configured to receive the current (I_Q602) flowing through the high-side switch 602 and a preset peak current reference IPK_RE. Figure 10 As shown, the functional unit in the dashed box 610 is the PFM control circuit of the power converter 600.

[0100] like Figure 10 As shown, the power converter 600 includes a buck power stage, an output feedback divider, and a PFM control circuit. The buck power stage includes an input filter capacitor 601, a power switch 602, a power switch 603, an output inductor 604, and an output filter capacitor 605. The output feedback divider includes resistors 606 and 607, and a feedforward capacitor 608. The PFM control circuit includes a control logic gate driver circuit 611, a current zero-crossing detection comparator 612, a comparator 613, a peak current detection comparator 615, and an error amplifier 614.

[0101] In some embodiments, the error amplifier 614 is a transconductance operational amplifier with a dominant pole, for example... Figure 6 The error amplifier shown is also referenced. Figure 6 Capacitor 401 and resistor 402 are connected in parallel between the output of the error amplifier and ground. Capacitor 401 and resistor 402 form the dominant pole.

[0102] In operation, the comparison between the current (I_Q602) of the high-side switch 602 and the peak current reference IPK_REF at the peak current detection comparator 615 is used to determine the on-time of the high-side switch 602. The comparison between the voltage at the feedback node FB of the converter 600 and the output voltage of the error amplifier is used to determine the on-time of the high-side switch 602 of the power converter 600. The current zero-crossing detection comparator 612 is used to determine the on-time of the low-side switch 603 of the power converter 600 when the current flowing through it reaches zero.

[0103] Figure 11 The illustrations depict various embodiments of the present application. Figure 10 The second embodiment of the PFM control circuit shown in the diagram is associated with various voltage and current signals, arranged in ten rows, where the horizontal axis represents time intervals. The first row represents... Figure 10 The output voltage of the power converter is shown in the first row. The second row represents the current I_Q1 flowing through the high-side switch of the power converter. The third row represents the current I_Q2 flowing through the low-side switch of the power converter. The fourth row represents the current IL flowing through the output inductor of the power converter. The fifth row represents... Figure 10 The signal V1 is shown. The sixth row represents... Figure 10 The signal V2 is shown. The seventh row represents... Figure 10 The signal shown is V3. The eighth row represents the output voltage V of the error amplifier. ER and the voltage V at the feedback node FB The solid line represents the V. ER The dashed line is a V. FB The ninth line represents the gate drive signal V of the high-side switch of the power converter. GS1 The tenth line represents the gate drive signal V of the low-side switch of the power converter. GS2 .

[0104] During operation, during the time interval (t1-t2) when the high-side switch 602 is on, the inductor current IL rises from zero, and the output ripple voltage increases. In response to the increased output ripple voltage, the voltage at the feedback node FB also increases. Since the voltage at the feedback node FB is fed to the inverting input of the error amplifier (e.g., ...), ... Figure 6 As shown), the output voltage of the voltage error amplifier decreases. Once the current on the output inductor reaches the preset threshold IPK_REF, the peak current detection comparator 615 triggers at time t2 and generates a short low-level pulse at the control logic signal V1 (from logic high to logic low at time t2). Figure 11 As shown, in response to this short low-level pulse, the control logic and gate drive circuit 611 turn off the high-side switch 602 and turn on the low-side switch 603 at time t2.

[0105] Once the low-side switch 603 is turned on, the zero-crossing current detection comparator 612 is activated to monitor the current flowing through the low-side switch 603 (I_Q603). Simultaneously, at time t2, the logic signal V2 changes from a logic low to a logic high state. Once the current flowing through the low-side switch 603 reaches zero (e.g., at time t3), the logic signal V2 changes from a logic high state to a logic low state. Figure 11 As shown, this logic state change of V2 causes the control logic and gate drive circuit 611 to turn off the low-side switch 603 at time t3, while keeping the high-side switch 602 off.

[0106] During the time interval t3 to t4, both switches 602 and 603 are open. As the output load current is maintained by discharging the output capacitor 605, the output voltage of the power converter gradually decreases.

[0107] At time t4, the voltage (V) at the inverting input of comparator 613 is... FB The voltage reaches the output voltage of the voltage error amplifier. Comparator 613 is triggered accordingly. Comparator 613 generates a short low-level pulse at control logic signal V3. Figure 11 As shown, control logic signal V3 flips from a logic high state to a logic low state at time t4. This logic state change of V3 causes the control logic and gate drive circuit 611 to turn on the high-side switch 602 and keep the low-side switch 603 off. Then, the inductor current increases from zero. Once the inductor current reaches the preset threshold IPK_REF, the peak current detection comparator 615 is triggered and generates a short pulse on control logic signal V1, causing the control logic and gate drive circuit 611 to turn off power switch 602 and turn on power switch 603. Control logic signal V2 resets from a logic low state to a logic high state and enables the zero-crossing current detection comparator 612. Figure 11 As shown, the PFM mode switching cycle repeats repeatedly.

[0108] It should be noted that the peak value of the energy delivered to the output and the peak value of the output ripple can be controlled by controlling the peak inductor current.

[0109] The transient response of power converter 600 is very similar to that of power converter 500, so it will not be described in detail here.

[0110] Figure 12 A third embodiment of the PFM control circuit according to various embodiments of this application is illustrated. Reference is also made to this application. Figure 2 When the power converter is configured to operate in PFM mode, Figure 2 As shown, S2 and S3 are turned off, while S1 is turned on. Figure 2 The circuit shown can be simplified to Figure 12The circuit shown. In the third implementation of the PFM control circuit, a constant on-time generator 715 is added to the PFM control circuit. (See diagram below.) Figure 12 As shown, the constant on-time generator 715 is configured to receive the input voltage VIN and the detected output voltage VOUT_S. Figure 12 As shown, the functional unit in the dashed box 710 is the PFM control circuit of the power converter 700.

[0111] In some embodiments, a resistor-capacitor low-pass filter is required to obtain the detected output voltage VOUT_S from the SW node because the PFM control circuitry has no access to the actual output voltage. Once the output feedback divider is determined and the reference voltage REF of the voltage error amplifier is known, the output voltage is determined. Therefore, output voltage sensing can be performed each time during soft-start to detect the output voltage via the SW switching node. It is not necessary to continue sensing the output voltage during operation.

[0112] like Figure 12 As shown, the power converter 700 includes a buck power stage, an output feedback divider, and a PFM control circuit. The buck power stage includes an input filter capacitor 701, a power switch 702, a power switch 703, an output inductor 704, and an output filter capacitor 705. The output feedback divider includes resistors 706 and 707, and a feedforward capacitor 708. The PFM control circuit includes control logic and a gate drive circuit 711, a current zero-crossing detection comparator 712, a comparator 713, a constant on-time generator 715, and an error amplifier 714.

[0113] In some embodiments, the error amplifier 714 is a transconductance operational amplifier with a dominant pole, for example... Figure 6 The error amplifier shown. (Continue to refer to...) Figure 6 Capacitor 401 and resistor 402 are connected in parallel between the output of the error amplifier and ground. Capacitor 401 and resistor 402 form the dominant pole.

[0114] In operation, the output of the constant on-time generator 715 is used to determine the on-time of the high-side switch 702 of the power converter 700. A comparison of the voltage at the feedback node with the output voltage of the error amplifier is used to determine the on-time of the high-side switch 702 of the power converter 700. The current zero-crossing detection comparator 712 is configured to determine the on-time of the low-side switch 703 of the power converter 700 when the current flowing through the low-side switch of the power converter reaches zero.

[0115] Figure 13 The illustrations depict various embodiments of the present application. Figure 12The third implementation of the PFM control circuit shown in the diagram is associated with various voltage and current signals, arranged in ten rows, where the horizontal axis represents time intervals. The first row represents... Figure 12 The output voltage of the power converter is shown in the first row. The second row represents the current I_Q1 flowing through the high-side switch of the power converter. The third row represents the current I_Q2 flowing through the low-side switch of the power converter. The fourth row represents the current IL flowing through the inductor in the power converter. The fifth row represents... Figure 12 The signal V1 is shown. The sixth row represents... Figure 12 The signal V2 is shown. The seventh row represents... Figure 12 The signal shown is V3. The eighth row represents the output voltage V of the error amplifier. ER and the voltage V at the feedback node FB The solid line represents the V. ER The dashed line is a V. FB The ninth line represents the gate drive signal V of the high-side switch of the power converter. GS1 The tenth line represents the gate drive signal V of the low-side switch of the power converter. GS2 .

[0116] During operation, during the time interval (t1 to t2) when the high-side switch 702 is on, the inductor current IL increases from zero, and the output ripple voltage increases accordingly. In response to the increased output ripple voltage, the voltage at the feedback node FB also increases. Since the voltage at the feedback node FB is fed to the inverting input of the error amplifier (e.g., ...), ... Figure 6 As shown), the output voltage of the voltage error amplifier decreases. Once the constant on-time interval expires, the constant on-time generator 715 pulls the control logic signal V1 low (from logic high to logic low at time t2). Figure 13 As shown, in response to this short low-level pulse, the control logic and gate drive circuit 711 turn off the high-side switch 702 and turn on the low-side switch 703 at time t2.

[0117] Once the low-side switch 703 is turned on, the zero-crossing current detection comparator 712 is activated to monitor the current flowing through the low-side switch 703 (I_Q703). At time t2, the logic signal V2 changes from a logic low level to a logic high level. Once the current flowing through the low-side switch 703 reaches zero (e.g., at time t3), the logic signal V2 changes from a logic high state to a logic low state. Figure 13 As shown, this change in the logic state of logic signal V2 causes the control logic and gate drive circuit 711 to turn off the low-side switch 703 at time t3, while keeping the high-side switch 702 off.

[0118] During the time interval t3 to t4, both switches 702 and 703 are open. Since the output load current is maintained by discharging the output capacitor 705, the output voltage of the power converter decreases.

[0119] At time t4, the voltage (V) at the inverting input of comparator 713 is... FB The voltage reaches the output voltage of the voltage error amplifier. Comparator 713 is triggered accordingly. Comparator 713 generates a short low-level pulse at control logic signal V3. The short low-level pulse at control logic signal V3 enables constant on-time generator 715. Control logic signal V1 changes from low to high. The change in logic state of logic signal V1 causes control logic and gate drive circuit 711 to turn on high-side switch 702 and keep low-side switch 703 off. Inductor current increases again from zero. Once the constant on-time expires, control logic signal V1 is pulled low, causing control logic and gate drive circuit 711 to turn off high-side switch 702 and turn on low-side switch 703. Control logic signal V2 changes from logic reset low to logic high, and current zero-crossing detection comparator 712 is enabled. Figure 13 As shown, the PFM pattern repeats periodically in this manner.

[0120] It should be noted that the energy delivered to the output and the peak value of the output ripple can be controlled by adjusting the constant conduction time interval.

[0121] The transient response of power converter 700 is very similar to that of power converter 500, so it will not be described in detail here.

[0122] Figure 14 The illustrations depict various embodiments of the present application for operation. Figure 2 The flowchart shows the control method of the power converter. Figure 14 The flowchart shown is merely an example and should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, additions, removals, substitutions, rearrangements, and repetitions may be made. Figure 14 The steps shown are as follows.

[0123] In step 1402, in the PWM mode of the power converter, multiple control switches are configured to generate the gate drive signal of the power converter based on a comparison between the output of the PWM ramp generator and a preset reference.

[0124] In step 1404, in the PFM mode of the power converter, multiple control switches are configured to generate the gate drive signal of the power converter based on the signal generated by the error amplifier and the current zero-crossing detection comparator.

[0125] In some embodiments, the high-side switch and the low-side switch are connected in series between the input voltage bus and ground, wherein the common node of the high-side switch and the low-side switch is the switching node of the power converter.

[0126] In some embodiments, an inductor is connected between the common node of the high-side and low-side switches and the output of the power converter.

[0127] In some embodiments, a PWM ramp generator is coupled between the switching node of the power converter and the first input terminal of the comparator. The PWM ramp generator includes a first resistor and a first capacitor connected in series between the switching node and the first input terminal of the comparator, and a second resistor and a second capacitor connected in parallel between the first input terminal of the comparator and the feedback node.

[0128] In some embodiments, the comparator has an output coupled to control logic and gate drive circuitry.

[0129] In some embodiments, the error amplifier is coupled between the second input of the comparator and the reference node.

[0130] In some embodiments, the current zero-crossing detection comparator is coupled to the control logic and the gate drive circuitry.

[0131] In some embodiments, a first control switch of the plurality of control switches is connected between a first input terminal of the comparator and a feedback node. A second control switch of the plurality of control switches is connected between a second input terminal of the comparator and a reference node. A third control switch of the plurality of control switches is coupled between a switching node and a first input terminal of the comparator.

[0132] The method also includes setting the second and third switches to be on and the first switch to be off in the PWM operating mode of the power converter.

[0133] The method also includes setting the second and third switches to off and the first switch to on in the PFM operating mode of the power converter.

[0134] The method further includes, in the PFM operating mode of the power converter, comparing the voltage at the feedback node with the sum of the output voltage of the error amplifier and the threshold voltage from the threshold generator to determine the on-time of the high-side switch of the power converter; comparing the voltage at the feedback node with the output voltage of the error amplifier to determine the on-time of the high-side switch of the power converter; and determining the time when the current flowing through the low-side switch of the power converter reaches zero by using a current zero-crossing detection comparator to determine the on-time of the low-side switch of the power converter.

[0135] The method further includes, in the PFM operating mode of the power converter, comparing the current flowing through the high-side switch of the power converter with a preset peak current reference value to determine the on-time of the high-side switch of the power converter; comparing the voltage at the feedback node with the output voltage of the error amplifier to determine the on-time of the high-side switch of the power converter; and determining the time when the current flowing through the low-side switch of the power converter reaches zero by using a current zero-crossing detection comparator to determine the on-time of the low-side switch of the power converter.

[0136] The method further includes determining the on-time of the high-side switch of the power converter based on the output of a constant on-time generator in the PFM operating mode of the power converter; comparing the voltage at the feedback node with the output voltage of the error amplifier to determine the on-time of the high-side switch of the power converter; and determining the time when the current flowing through the low-side switch of the power converter reaches zero by using a current zero-crossing detection comparator, thereby determining the on-time of the low-side switch of the power converter.

[0137] Although embodiments of the present application and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations may be made herein without departing from the spirit and scope of the present application as defined by the appended claims.

[0138] Furthermore, the scope of this application is not intended to be limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. As will be readily understood by those skilled in the art from the disclosure of this application, processes, machines, manufactures, compositions of matter, means, methods, or steps, whether currently existing or to be developed thereafter, perform substantially the same function or achieve substantially the same results as the corresponding embodiments described herein, which can be used according to this application. Therefore, the appended claims are intended to include such processes, machines, manufactures, compositions of matter, apparatus, methods, or steps within their scope.

Claims

1. A control device for a buck converter, characterized in that, include: A PWM ramp generator is coupled between a switching node of a power converter and a first input terminal of a comparator. The PWM ramp generator includes a first resistor and a first capacitor connected in series between the switching node and the first input terminal of the comparator, and a second resistor and a second capacitor connected in parallel between the first input terminal of the comparator and a feedback node. The PFM control circuit includes an error amplifier and a current zero-crossing detection comparator, wherein the error amplifier is coupled between a second input terminal of the comparator and a reference node, and the PFM control circuit is configured to generate a gate drive signal for the power converter when the power converter is configured to operate in PFM mode. A first control switch is connected between the first input terminal of the comparator and the feedback node; A second control switch is connected between the second input terminal of the comparator and the reference node; A third control switch is coupled between a switch node and a first input terminal of the comparator; When the power converter is configured to operate in PWM mode, the second control switch and the third control switch are configured to be turned on, and the first control switch is configured to be turned off. When the power converter is configured to operate in PFM mode, the second control switch and the third control switch are configured to be off, and the first control switch is configured to be on.

2. The apparatus according to claim 1, characterized in that, The power converter includes: A high-side switch and a low-side switch are connected in series between the input voltage bus and ground, wherein the common node of the high-side switch and the low-side switch is the switching node of the power converter; An inductor is connected between the common node of the high-side switch and the low-side switch and the output of the power converter.

3. The apparatus according to claim 1, characterized in that, Also includes: A voltage divider, comprising a third resistor and a fourth resistor connected in series between the output terminal of the power converter and ground, wherein the common node of the third resistor and the fourth resistor is the feedback node; The third capacitor is connected in parallel with the third resistor.

4. The apparatus according to claim 1, characterized in that, Also includes: A threshold voltage generator is coupled between the second input terminal of the comparator and the output terminal of the error amplifier, wherein the error amplifier is a transconductance operational amplifier; A fourth capacitor and a fifth resistor are connected in parallel between the output of the error amplifier and ground, and the fourth capacitor and the fifth resistor form a pole of the error amplifier; The non-inverting input of the error amplifier is connected to a preset reference voltage, and the inverting input of the error amplifier is connected to the feedback node. The comparison between the voltage at the feedback node and the sum of the output voltage of the error amplifier and the threshold voltage from the threshold voltage generator is used to determine the turn-on time of the high-side switch of the power converter. The comparison between the voltage at the feedback node and the output voltage of the error amplifier is used to determine the on-time of the high-side switch of the power converter. The current zero-crossing detection comparator is configured to determine the on-time of the low-side switch of the power converter based on the moment when the current flowing through the low-side switch of the power converter reaches zero.

5. The apparatus according to claim 1, characterized in that, Also includes: A peak current detection comparator, wherein the error amplifier is a transconductance operational amplifier; A fourth capacitor and a fifth resistor are connected in parallel between the output terminal of the error amplifier and ground, and the fourth capacitor and the fifth resistor constitute one pole of the error amplifier; The non-inverting input of the error amplifier is connected to a preset reference voltage, and the inverting input of the error amplifier is connected to the feedback node. The comparison between the current flowing through the high-side switch of the power converter and the preset reference peak current is used to determine the on-time of the high-side switch of the power converter. The comparison between the voltage at the feedback node and the output voltage of the error amplifier is used to determine the turn-on time of the high-side switch of the power converter. The current zero-crossing detection comparator is configured to determine the on-time of the low-side switch of the power converter based on the moment when the current flowing through the low-side switch of the power converter reaches zero.

6. The apparatus according to claim 1, characterized in that, Also includes: A constant on-time generator, wherein the error amplifier is a transconductance operational amplifier; A fourth capacitor and a fifth resistor are connected in parallel between the output terminal of the error amplifier and ground, and the fourth capacitor and the fifth resistor constitute a pole of the error amplifier; The non-inverting input of the error amplifier is connected to a preset reference voltage, and the inverting input of the error amplifier is connected to the feedback node. The output of the constant on-time generator is used to determine the on-time of the high-side switch of the power converter. The comparison between the voltage at the feedback node and the output voltage of the error amplifier is used to determine the turn-on time of the high-side switch of the power converter; The current zero-crossing detection comparator is configured to determine the on-time of the low-side switch of the power converter based on the moment when the current flowing through the low-side switch of the power converter reaches zero.

7. The apparatus according to claim 6, characterized in that, It also includes a resistor-capacitor filter connected between the switch node and ground; The resistor-capacitor filter is configured such that its output voltage is equal to the output voltage of the power converter. When the power converter is configured to operate in constant on-time PFM mode, the output voltage of the resistor-capacitor filter is used to determine the output pulse width of the constant on-time generator.

8. The apparatus according to claim 1, characterized in that, The comparator is a hysteresis comparator; The first input terminal of the comparator is the inverting input terminal, and the second input terminal of the comparator is the non-inverting input terminal.

9. The apparatus according to claim 1, characterized in that, The resistance of the first resistor is more than ten times the resistance of the second resistor; The second resistor is configured to provide a DC current path to the first input of the comparator; The first capacitor is configured such that most of the DC voltage difference between the output of the power converter and the feedback node is applied across the first capacitor.

10. A control method for a buck converter, characterized in that, include: In the PWM mode of the power converter, multiple control switches are configured to generate a gate drive signal for the power converter based on a comparison between the output of the PWM ramp generator and a preset reference voltage. The PWM ramp generator is coupled between the switching node of the power converter and the first input terminal of the comparator. The PWM ramp generator includes a first resistor and a first capacitor connected in series between the switching node and the first input terminal of the comparator, and a second resistor and a second capacitor connected in parallel between the first input terminal of the comparator and the feedback node. In the PFM mode of the power converter, multiple control switches are configured to generate the gate drive signal of the power converter based on the signal generated by the error amplifier and the current zero-crossing detection comparator; wherein the error amplifier is coupled between the second input terminal of the comparator and the reference node, and the multiple control switches include a first control switch, a second control switch and a third control switch; The first control switch is connected between the first input terminal of the comparator and the feedback node; The second control switch is connected between the second input terminal of the comparator and the reference node; The third control switch is coupled between the switching node and the first input terminal of the comparator; When the power converter is configured to operate in PWM mode, the second control switch and the third control switch are configured to be turned on, and the first control switch is configured to be turned off. When the power converter is configured to operate in PFM mode, the second control switch and the third control switch are configured to be off, and the first control switch is configured to be on.

11. The method according to claim 10, characterized in that, The high-side switch and the low-side switch are connected in series between the input voltage bus and ground, wherein the common node of the high-side switch and the low-side switch is the switching node of the power converter; An inductor is connected between the common node of the high-side switch and the low-side switch and the output of the power converter; The comparator has an output coupled to the control logic and the gate drive circuitry; The current zero-crossing detection comparator is coupled to the control logic and the gate drive circuit.

12. The method according to claim 11, characterized in that, Also includes: In the PFM operating mode of the power converter, The voltage at the feedback node is compared with the sum of the output voltage of the error amplifier and the threshold voltage from the threshold generator to determine the turn-on time of the high-side switch of the power converter; The voltage at the feedback node is compared with the output voltage of the error amplifier to determine the on-time of the high-side switch of the power converter; The current zero-crossing detection comparator detects the moment when the current flowing through the low-side switch of the power converter reaches zero, thereby determining the on-time of the low-side switch of the power converter.

13. The method according to claim 11, characterized in that, Also includes: In the PFM operating mode of the power converter, The current flowing through the high-side switch of the power converter is compared with a preset reference peak current to determine the on-time of the high-side switch of the power converter. The voltage at the feedback node is compared with the output voltage of the error amplifier to determine the turn-on time of the high-side switch of the power converter; The current zero-crossing detection comparator detects the moment when the current flowing through the low-side switch of the power converter reaches zero, thereby determining the on-time of the low-side switch of the power converter.

14. The method according to claim 11, characterized in that, Also includes: In the PFM operating mode of the power converter, The on-time of the high-side switch of the power converter is determined based on the output of the constant on-time generator; The voltage at the feedback node is compared with the output voltage of the error amplifier to determine the turn-on time of the high-side switch of the power converter; The current zero-crossing detection comparator detects the moment when the current flowing through the low-side switch of the power converter reaches zero, thereby determining the on-time of the low-side switch of the power converter.

15. A control system for a buck converter, characterized in that, include: A high-side switch and a low-side switch are connected in series between the input voltage bus and ground, wherein the common node of the high-side switch and the low-side switch is a switch node; An inductor connected between the common node of the high-side switch and the low-side switch and the output of the system; A PWM ramp generator is coupled between the switching node and the first input terminal of the comparator. The PWM ramp generator includes a first resistor and a first capacitor connected in series between the switching node and the first input terminal of the comparator, and a second resistor and a second capacitor connected in parallel between the first input terminal of the comparator and the feedback node. The PFM control circuit includes an error amplifier and a current zero-crossing detection comparator, wherein the error amplifier is coupled between a second input of the comparator and a reference node, and the PFM control circuit is configured to generate a gate drive signal for the system when the system is configured to operate in PFM mode. A first control switch is connected between the first input terminal of the comparator and the feedback node; A second control switch is connected between the second input terminal of the comparator and the reference node; A third control switch is coupled between the switch node and the first input terminal of the comparator; When the system is configured to operate in PWM mode, the second control switch and the third control switch are configured to be turned on, and the first control switch is configured to be turned off. When the system is configured to operate in PFM mode, the second control switch and the third control switch are configured to be off, and the first control switch is configured to be on.

16. The system according to claim 15, characterized in that, Also includes: A voltage divider, comprising a third resistor and a fourth resistor connected in series between the output terminal of the system and ground, wherein the common node of the third resistor and the fourth resistor is the feedback node; A third capacitor, wherein the third capacitor is connected in parallel with the third resistor; A resistor-capacitor filter, connected between the switching node and ground, is used to determine the output pulse width of the constant on-time generator when the power converter is configured to operate in constant on-time PFM mode.

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