Input processing method and circuit of an image data interface
By judging and processing the pre-full and pre-empty signals and data validity at the input and output terminals of the asynchronous FIFO, the problem of data loss or redundancy in asynchronous FIFO processing is solved, and data integrity and image stability are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ZHUHAI HI-CHIP SEMICON LTD
- Filing Date
- 2023-03-20
- Publication Date
- 2026-07-03
AI Technical Summary
In existing technologies, asynchronous FIFOs are prone to data loss or redundant data when processing image data from different clocks, resulting in image instability and making it difficult for the receiver to process the data.
By checking the validity of the pre-full signal and input data at the input of the asynchronous FIFO, the writing of invalid data is paused; at the output, the validity of the pre-empty signal and output data is checked, and invalid data is copied to ensure data integrity.
This ensures data integrity in asynchronous FIFO processing, reduces the processing difficulty for the receiver, and guarantees image stability.
Smart Images
Figure CN116614651B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of image processing technology, and more specifically to an input processing method and circuit for an image data interface. Background Technology
[0002] Currently, typical uncompressed video interfaces use an interface similar to that provided by CEA-861. This interface is used to transmit uncompressed video images, transmitting the frame blanking area (vblank), the line blanking area (hblank), and the active image, which includes frame synchronization (vsync), line synchronization (hsync), data enable signal (DE), pixel clock (pix_clk), and uncompressed video data. The timing relationship of the frame synchronization / line synchronization / data enable signals is as follows: Figure 1 As shown, in Figure 1 In this context, DE must remain continuous within the valid region without any breaks.
[0003] The pixel clock is a clock frequency that is a multiple of the pixel rate. Most commonly, it's the same as the pixel rate, but it can also be two or more times the pixel rate, and in some cases, half the pixel rate. A common example of a pixel clock frequency is in high-definition 1920x1080p@60. In this case, the pixel clock is typically 148.5MHz, the same as the pixel transmission rate.
[0004] Uncompressed video data transmission images are transmitted line by line from top to bottom, and each line is transmitted pixel by pixel from left to right. (In some cases, it is not exactly absolute line by line and pixel by pixel, but this is the basic order).
[0005] like Figure 2 As shown, Figure 2 On the left is the RGB image data input from a third party. After passing through the input processing circuit, the data, maintaining its previous timing, is sent to the HDMI TX controller. After processing via the HDMI protocol, it is sent to the HDMI TX PHY, and finally received by the TV. Throughout this process, the data is not placed into the DRAM buffer.
[0006] The HDMI TX Ctrl controller's clock is provided by the HDMI TX PHY. Because of the high precision requirements, the clock sent from the RGB source cannot be used; instead, it is provided by the HDMI TX PHY's PLL. This results in the two clock frequencies not being perfectly proportional. Therefore, an asynchronous FIFO must be used for processing. However, if a traditional asynchronous FIFO is used, it will cause some pixels to be missing from the image, which will appear as an unstable image on a television.
[0007] Additionally, when receiving such an uncompressed video interface, different clock conversion is required (while still using this uncompressed interface method) – for example, relative to the pixel clock of the input interface, the output interface data needs to be processed using a clock with a corresponding multiple (such as twice the pixel clock). However, since it is impossible to use the input pixel clock to generate those clocks, another clock generator is needed to generate an output clock and the corresponding clock used for subsequent processing (such as twice the pixel clock). Here, the output clock and input clock frequencies are basically the same – but there will definitely be some slight difference between the input and output clock frequencies, such as a difference of 1 / 1000 (this difference comes from the two clocks coming from clock generators from different sources).
[0008] Because the input and output have different clocks, an asynchronous FIFO is usually used to handle this, such as... Figure 3 and Figure 6 As shown. Figure 3 In this context, Push_tx is a write data request sent by external control logic. If the FIFO is full (i.e., full is true) at this time, data cannot be written until it is not full. A NAND gate is used, with the input signal being the inverted logic of the full signal and Push_tx, and the output signal being the write signal to the FIFO, Push_en. The basic logic is that Push_en is true only when Push_tx is true and full is false. Pop_tx is a read data request sent by external control logic, and its logic is similar to Push_tx, but empty replaces full as the signal to suppress reads.
[0009] However, doing so may lead to two situations:
[0010] 1. Ensure that the input and output data are completely identical to prevent data loss. Input data (push_data) consists of vsync / hsync / DE / data. When the asynchronous FIFO is not full (full is false), data is written to the asynchronous FIFO; when the asynchronous FIFO is not empty (empty is false), data is read from it. Push_en is true when writing data, and pop_en is true when reading data. Since the input and output clock frequencies are not exactly the same, there will always be times when the FIFO is full (full is true) or empty (empty is false). If the FIFO is full, it will be impossible to write input interface data, which is unacceptable to the receiving end because, as mentioned earlier, the interface transmits data every clock cycle, and this transmission cannot be paused. If writing fails, the input data will be lost, which does not meet the previous expectations. If the FIFO is empty, pop_en will be intermittent, and the output DE may also be intermittent, which does not meet the requirements of this interface. Therefore, this asynchronous FIFO logic does not meet the requirements.
[0011] 2. Ensure that input and output are never interrupted, i.e., `push_en` and `pop_en` are always true. However, this still allows for empty or full states. If the FIFO is full, it won't input `push_data` at that moment (because there's no space to load new data), resulting in a missing data entry when reading from the output. If the FIFO is empty, it won't output `pop_data` at that moment (because there's no data left), leading to discontinuous output. Alternatively, when empty, the output could continue with the previous data to prevent discontinuity, but this would result in an extra data entry at the output. Therefore, this approach may lead to lost or extra data at the output. Specifically, in graphics, this could mean that every few lines, one line might have one more or one less point relative to other lines. This could cause instability on the screen. For example... Figure 4 and Figure 5 As shown, where, Figure 4 This is a common occurrence in asynchronous FIFOs when they are full, and the final image will exhibit certain characteristics. Figure 5 This refers to the final image display when an asynchronous FIFO frequently becomes empty.
[0012] Therefore, in order to prevent the above situation from occurring and to ensure that the number of pixels received by each line by the receiver is the same, thereby reducing the difficulty of data processing by the receiver, is a technical problem that urgently needs to be solved. Summary of the Invention
[0013] In order to overcome the shortcomings of the prior art, the present invention aims to provide an input processing method and circuit for an image data interface. The method and circuit are used to solve problems such as incomplete effective image data after asynchronous FIFO processing and the difficulty of data processing by the receiver.
[0014] To solve the above problems, the technical solution adopted by the present invention is as follows:
[0015] An input processing method for an image data interface, applied to an input processing circuit of an image data interface, the method comprising:
[0016] The memory size of the asynchronous FIFO and the threshold conditions for the occurrence of the pre-full and pre-empty signals of the asynchronous FIFO are determined. The asynchronous FIFO is used to transfer image data signals with different input and output clocks.
[0017] At the input of the asynchronous FIFO, it is determined whether the pre-full signal is true;
[0018] If the judgment result is yes, then continue to judge whether the currently input data is valid image data;
[0019] If so, continue writing data to the asynchronous FIFO; otherwise, pause writing data to the asynchronous FIFO once.
[0020] If the pre-full signal is determined to be false, then real-time data is written to the asynchronous FIFO;
[0021] At the output of the asynchronous FIFO, determine whether the pre-empt signal is true;
[0022] If the judgment result is yes, then continue to judge whether the output of the last clock cycle before the pre-empt signal is valid image data;
[0023] If the data is valid, output the real-time data; if the data is not valid, copy the data from the last clock cycle before the pre-empt signal appears and output it.
[0024] If the judgment result indicates that the pre-emptive signal is false, then a real-time signal is output.
[0025] The threshold conditions for determining the flag signals of the asynchronous FIFO include: Let the horizontal pixel count of the image be M, and the clock error range be -N to N, where N is a percentage. Then, the threshold for determining the pre-full and pre-empty signals of the asynchronous FIFO is K: K = M * N * 2. When there are K empty positions remaining in the asynchronous FIFO, it enters the pre-full state; when there are K data positions remaining in the asynchronous FIFO, it enters the pre-empty state. For example, assuming the horizontal pixel count M of the image is 4096, and the clock error range N is ±0.5%, then the threshold K is M * N * 2 = 41. The multiplication by 2 is because N has a minimum of -0.5% and a maximum of 0.5%, and the difference between the two is N * 2.
[0026] The inventive concept of the above technical solution is as follows: When entering the almost_full state, the asynchronous FIFO still has K empty positions to fill pixel values. When the asynchronous FIFO is just entering the valid line of the image, it needs to continuously input M pixels before reaching the blank area. Since the input clock of the asynchronous FIFO is N values faster than the output clock, when M pixels are continuously input, the output is approximately L pixels, where M>L. Because the asynchronous FIFO has K empty positions, overflow will not occur. After a line of continuous pixel input is completed and it enters the blank area, the asynchronous FIFO will continuously ignore the input data after confirming that it has entered the blank area. At this time, the input data is blank data until it exits the pre-full state.
[0027] In some implementations, the valid image data is represented by a DE signal, which is a valid data strobe signal, and the video data signal corresponding to the period when the DE signal is true is the valid image data signal.
[0028] A corresponding image data interface input processing circuit, used to implement image protocol input processing at a different clock, includes: an asynchronous FIFO circuit and a protocol control logic circuit that interacts with the asynchronous FIFO circuit.
[0029] In some implementations, the protocol control logic circuit is used to: determine whether to continue writing data to the asynchronous FIFO and perform the write operation based on the pre-full signal and whether the currently input data is valid data; and determine whether to output real-time data or output copied invalid data based on the pre-empty signal and whether the data in the last clock cycle before the pre-empty signal is valid data and perform the output operation.
[0030] One implementation method is as follows:
[0031] The protocol control logic circuit includes a pre-full control unit, a pre-empty control unit, and an output control unit;
[0032] The pre-full control unit includes a first logic inverting circuit, a first NAND gate, and a first AND gate. The pre-full signal of the asynchronous FIFO is connected to one input of the first NAND gate. The DE signal input to the asynchronous FIFO is connected to the other input of the first NAND gate after passing through the first logic inverting circuit. The output of the first NAND gate is connected to one input of the first AND gate. The write data request sent by the external control logic is connected to the other input of the first AND gate. The output of the first AND gate is connected to the input of the asynchronous FIFO.
[0033] The pre-empt control unit includes a second logic inverting circuit, a second NAND gate, and a second AND gate. The pre-empt signal of the asynchronous FIFO is connected to one input of the second NAND gate. The DE signal at the output of the asynchronous FIFO is connected to the other input of the second NAND gate after passing through the second logic inverting circuit. The output of the second NAND gate is connected to one input of the second AND gate. The read data request sent by the external control logic is connected to the other input of the second AND gate. The output of the second AND gate is connected to the read enable terminal of the asynchronous FIFO.
[0034] The output control unit includes a register and a selector. The input terminal of the register is connected to the read data, the output terminal of the register is connected to one input terminal of the selector, the other input terminal of the selector is connected to the read data, and the output terminal of the selector outputs data.
[0035] When it is determined that invalid data output in the last clock cycle before the occurrence of almost_empty needs to be output, the register will not store new data; at other times, the output data of the FIFO needs to be stored.
[0036] Compared with the prior art, the present invention has the following advantages:
[0037] This invention adds a protocol control logic circuit to the current asynchronous FIFO design to implement image protocol input processing at different clocks. By discarding some invalid data at the input end and copying some invalid data at the output end, it can ensure that the valid image data in the data format processed by the asynchronous FIFO is complete enough, thereby reducing the difficulty of data processing for the receiver.
[0038] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. Attached Figure Description
[0039] Figure 1 This is a timing diagram of the frame synchronization / line synchronization / data valid signals in the existing technology.
[0040] Figure 2 This is a schematic diagram of an input processing circuit based on existing technology.
[0041] Figure 3 This is a schematic diagram of the application principle of an asynchronous FIFO in existing technology.
[0042] Figure 4 This is a diagram illustrating the frequent occurrence of a full asynchronous FIFO in existing technologies.
[0043] Figure 5 This is a diagram illustrating the frequent occurrence of empty states in asynchronous FIFOs in existing technologies.
[0044] Figure 6 This is a schematic diagram of an input processing method for an image data interface in the prior art.
[0045] Figure 7 and Figure 8 The flowcharts are respectively the input end and the output end of an embodiment of an image data interface input processing method provided by the present invention.
[0046] Figure 9 This is a schematic diagram of an image protocol input processing circuit for implementing different clock edges, provided by the present invention.
[0047] Figure 10 yes Figure 9 The diagram shows the structural block diagram of the image protocol input processing circuit.
[0048] Figure 11This is a schematic diagram of the signal presentation principle of an embodiment of the input processing circuit for an image data interface provided by the present invention.
[0049] Figure 12 Is with Figure 11 The corresponding logic circuit schematic.
[0050] Figure 13 Is with Figure 12 The corresponding specific circuit schematic. Detailed Implementation
[0051] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.
[0052] See Figure 7 and Figure 8 This embodiment provides an input processing method for an image data interface, applied to an input processing circuit of an image data interface. The method includes the following:
[0053] Based on the image protocol specifications and clock error range, determine the memory size of the asynchronous FIFO, as well as the threshold conditions for the almost_full and almost_empty signals of the asynchronous FIFO.
[0054] Input: Input a write signal to the asynchronous FIFO. When almost_full is 1, determine whether to continue writing data to the asynchronous FIFO based on the input DE signal. If the DE signal indicates that valid image data is currently being transmitted, continue writing data to the asynchronous FIFO. If the DE signal indicates that valid image data is no longer being transmitted, pause writing data to the asynchronous FIFO once until almost_full is 0.
[0055] Output: The output signal is generated by the asynchronous FIFO. When almost_empty is 1, the nature of the output signal is determined by the DE signal at the output end. If the DE signal indicates that the last clock cycle before the almost_empty signal is valid image data, then the output continues. If the DE signal indicates that the last clock cycle before the almost_empty signal is invalid image data, then the invalid data is copied and output until almost_empty is 0.
[0056] The threshold conditions for determining the flag signals of the asynchronous FIFO mentioned above include, assuming the horizontal pixel count of the image is M and the clock error range is N, the threshold for determining the almost_full and almost_empty signals of the asynchronous FIFO is K. When there are K empty positions remaining in the asynchronous FIFO, it enters the almost_full state; when there are K data positions remaining in the asynchronous FIFO, it enters the almost_empty state. For example, assuming the horizontal pixel count M of the image is 4096 and the clock error range N is ±0.5%, then the threshold K is M*N*2=41. The multiplication by 2 is because N has a minimum of -0.5% and a maximum of 0.5%, and the difference between the two is N*2.
[0057] Correspondingly, the input and output scenarios are as follows: If the input clock of the asynchronous FIFO is N times faster than the output clock, the asynchronous FIFO will prioritize entering the almost_full state. When entering the almost_full state, the asynchronous FIFO has K spare positions to fill with pixel values. When the asynchronous FIFO is just entering a valid line of the image, it needs to continuously input M pixels before reaching the blank area. Because the input clock of the asynchronous FIFO is N times faster than the output clock, when M pixels are continuously input, the output is approximately L pixels (M>L). Since the asynchronous FIFO has K spare positions, overflow will not occur. When a line of pixels has been continuously input and enters the blank area, the asynchronous FIFO, after confirming entry into the blank area, will continuously ignore the input data; at this time, the input data is blank data, until it exits the almost_full state.
[0058] Through the image data interface input processing method described above, at the input end of the asynchronous FIFO, some invalid data is discarded in the blanking region, slightly reducing the length of the blanking region. At the output end, some invalid data is copied in the blanking region, slightly increasing the length of the blanking region. Generally speaking, although the input and output clocks of the asynchronous FIFO differ, the frequency difference is usually not significant. The blanking region will only decrease or increase in length slightly, without affecting the frame synchronization and line synchronization seen by the receiver, thus having no impact on the receiver.
[0059] In practical applications, this embodiment provides an input processing method for an image data interface, specifically including:
[0060] The size of the asynchronous FIFO and the threshold conditions for the almost_full and almost_empty signals of the asynchronous FIFO are determined based on protocol specifications and clock error range limitations, such as the maximum supported image resolution and the clock error range allowed by the interface protocol. These conditions can be flexibly configured.
[0061] This invention adds protocol control logic to the current asynchronous FIFO design. When there is a slight difference between the input and output clocks, the asynchronous FIFO will inevitably become empty or full, leading to data loss or duplication. This embodiment uses protocol control logic to prevent data loss or duplication within the effective image range. In other words, this invention can control when these situations occur, moving them to less important frame and line blanking regions (for the receiver, the blanking region only needs to see the frame and line synchronization signals).
[0062] Since mature asynchronous FIFO designs can generally output two signals, almost_full and almost_empty, they indicate that the asynchronous FIFO is about to be full or empty. Usually, if the remaining data in the asynchronous FIFO is more than a certain threshold, it means that it is about to be full, and if it is less than a certain threshold, it means that it is about to be empty.
[0063] like Figure 7 and 8 As shown, this embodiment combines the protocol control logic circuit with the asynchronous FIFO: when almost_full is 1, it simultaneously checks the input DE signal. If the DE signal indicates that valid image data is currently being transmitted, no further processing is performed. This continues until the DE signal indicates that valid image data transmission is no longer underway (i.e., the blanking region has been entered), at which point writing data to the asynchronous FIFO is paused once. Then, it checks if almost_full is still equal to 1. If it is still equal to 1, and the region is still in the blanking region, writing data to the asynchronous FIFO is paused once more, until almost_full equals 0. In other words, this processing method discards a portion of invalid data in the blanking region.
[0064] The processing method is similar when almost_empty is 1 to that when almost_full is 1, the difference is that when almost_empty is 1, the DE signal at the output is checked. If it indicates that the current area is a blanking region, the previously output data can be copied once, until almost_empty equals 0. In other words, through this processing method, some invalid data is copied in the blanking region.
[0065] If the uncompressed image interface used for transmission is not CEA-861, but another method, such as BT656, as long as it can also generate DE signals based on the data, the method provided in this embodiment can also be used by adding corresponding DE generation logic.
[0066] Specifically, the almost_full and almost_empty threshold condition configurations for asynchronous FIFO include:
[0067] For example, assuming the horizontal pixel count of the image is 2000 (M=2000) and the clock error range is ±5 / 1000 (N=±5 / 1000), then the threshold condition K is 2000*5 / 1000=10. This means that when the asynchronous FIFO has 10 pixels of empty space remaining, it enters the almost_full state; when it has 10 pixels of data remaining, it enters the almost_empty state. If the asynchronous FIFO's input clock is 5 / 1000 seconds faster than its output clock, it will more easily enter the almost_full state. When entering the almost_full state, the asynchronous FIFO still has 10 empty spaces available to fill with pixel values. In the worst case, the asynchronous FIFO is just entering the valid image line, meaning it will continuously input 2000 pixels before reaching the blank area. Because the input clock is 5 / 1000 faster than the output clock, when 2000 pixels are continuously input, only about 1990 pixels are output. However, because there are 10 spare positions in the asynchronous FIFO beforehand, there will be no overflow.
[0068] Then, after a line of consecutive pixels has been input, the system enters the blank region. Once the asynchronous FIFO confirms entry into the blank region, it continuously ignores the input data, which is then blank data and mostly consists of fixed values, until it exits the almost_full state. If the asynchronous FIFO's input clock is 5 / 1000 slower than its output clock, the asynchronous FIFO is more likely to enter the almost_empty state, and the processing method is the opposite of almost_full. This will not be elaborated further here.
[0069] The following is an example of an input processing circuit for an image data interface:
[0070] like Figure 9 and Figure 10 As shown, this invention aims to provide an input processing circuit for an image data interface with different clock edges. This circuit includes an asynchronous FIFO circuit and a protocol control logic circuit. In this embodiment, the protocol control logic circuit is used to determine the threshold condition of the asynchronous FIFO's flag signal, and, in conjunction with almost_full and almost_empty, as well as the DE signals at the input and output terminals, to determine whether to continue writing data to the asynchronous FIFO, and what kind of data the asynchronous FIFO should output. This achieves the goal of ensuring the integrity of valid image data by discarding or copying partially invalid data.
[0071] In this embodiment, the pre-full signal is indicated as true by whether the almost_full signal is high (1). If almost_full is low, the pre-full signal is false. Similarly, if the almost_empty signal is high (1), the pre-empty signal is true; conversely, if almost_empty is low (0), the pre-empty signal is false. In practical applications, other settings can be used, such as using a high level to represent false and a low level to represent true, or other methods, as long as the signal's true or false status can be accurately represented.
[0072] like Figure 11-13 As shown, this embodiment provides the logical association method and specific connection method of the asynchronous FIFO circuit and the protocol control logic circuit.
[0073] Considering that mature asynchronous FIFO designs generally output two signals, almost_full and almost_empty, indicating that the FIFO is about to fill or empty, typically, more than a certain threshold of remaining data indicates it's about to fill, and less than a certain threshold indicates it's about to empty. Therefore, incorporating the almost_full and almost_empty states into... Figure 3 In the conventional image protocol input processing circuit shown, a formation is formed Figure 11 The logic is shown.
[0074] Further, see Figure 12 As shown, it is Figure 11 The specific implementation of the logic is as follows: At the input of the asynchronous FIFO, when almost_full is 1, the DE signal is checked simultaneously. If the DE signal indicates that valid image data is being transmitted, transmission continues until the DE signal indicates that valid image data is no longer being transmitted. At this point, the writing of data to the asynchronous FIFO is paused once, and then almost_full is checked again. If it is still equal to 1, and if the area is still in the blanking zone, the writing of data to the asynchronous FIFO is paused once more until almost_full equals 0. When almost_full equals 0, real-time data can be input normally. Through this processing method, some invalid data is discarded in the blanking zone. At the output of the asynchronous FIFO, when almost_empty is 1, the DE signal at the output is checked. If the DE signal indicates that the area is currently in the blanking zone, the invalid data output in the last clock cycle before almost_empty is reached can be copied once, until almost_empty equals 0. Through this processing method, some invalid data is copied in the blanking zone.
[0075] Specifically, in combination Figure 12 and 13The protocol control logic circuit includes a pre-full control unit, a pre-empty control unit, and an output control unit. The pre-full control unit includes a first logic inverting circuit 1, a first NAND gate 2, and a first AND gate 3. The almost_full signal of the asynchronous FIFO is connected to one input of the first NAND gate 2. The input DE signal is connected to the other input of the first NAND gate 2 after passing through the first logic inverting circuit 1. The output of the first NAND gate 2 is connected to one input of the first AND gate 3. The write data request Push_tx sent from the external control logic is connected to the other input of the first AND gate 3. The output of the first AND gate 3 is connected to the input of the asynchronous FIFO. The preemption control unit includes a second logic inverting circuit 6, a second NAND gate 5, and a second AND gate 4. The almost_empty signal of the asynchronous FIFO is connected to one input of the second NAND gate 5. The DE signal of the asynchronous FIFO output is connected to the other input of the second NAND gate 5 after passing through the second logic inverting circuit 6. The output of the second NAND gate 5 is connected to one input of the second AND gate 4. The read data request Pop_tx from the external control logic is connected to the other input of the second AND gate 4. The output of the second AND gate 4 is connected to the output of the asynchronous FIFO. The output control unit includes a register and a selector 7. The input of the register is connected to pop_data, the output of the register is connected to one input of the selector 7, the other input of the selector 7 is connected to pop_data, and the output of the selector 7 outputs data. When it is determined that invalid data output in the last clock cycle before the almost_empty event needs to be output, the register will not store new data; otherwise, the FIFO output data needs to be stored.
[0076] The operating logic of the pre-full control unit is as follows: At the input of the asynchronous FIFO, when almost_full is 1, if the DE signal is true (high level), it indicates that valid image data is currently being transmitted. After logical inversion, it becomes low level, so the output of the first NAND gate 2 is high level. At the same time, the write data request Push_tx sent by the external control logic is true (high level), so the output of the first AND gate 3 is high level, meaning that real-time data transmission continues. When almost_full is 1, if the DE signal is false (low level), it indicates that valid image data is not currently being transmitted. After logical inversion, it becomes high level, the output of the first NAND gate 2 is low level, and at the same time, the write data request Push_tx sent by the external control logic is true (high level), so the output of the first AND gate 3 is low level, meaning that writing data to the asynchronous FIFO is paused once. In this way, some invalid data is discarded in the blanking area.
[0077] The operating logic of the pre-empty control unit is as follows: At the output of the asynchronous FIFO, when almost_empty is 1, if the DE signal is true (high level), it indicates that the currently outputting image data is valid. After logical inversion, it is low level, so the output of the second NAND gate 5 is high level. At the same time, the read data request Pop_tx sent by the external control logic is true (high level), so the output of the second AND gate 4 is high level, that is, it continues to output real-time data; when almost_empty is 1, if the DE signal is low level, it indicates that almost_empty output... The last clock cycle before this point did not transmit valid image data; that is, the transmitted data was in the blanking region. After the logic is inverted, it becomes high, so the output of the second NAND gate 5 is low. At the same time, the write data request Push_tx sent by the external control logic is true, that is, high. When this is the case, the output of the second AND gate 4 is low, meaning that real-time data is no longer output. Instead, the invalid data transmitted in the last clock cycle before almost_empty occurs is copied once and then output, until almost_empty equals 0. Through this processing method, a portion of invalid data is copied in the blanking region.
[0078] The above embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of protection of the present invention. Any non-substantial changes and substitutions made by those skilled in the art based on the present invention shall fall within the scope of protection claimed by the present invention.
Claims
1. An input processing method for an image data interface, characterized in that, An input processing circuit applied to an image data interface, the method comprising: The memory size of the asynchronous FIFO and the threshold conditions for the occurrence of the pre-full and pre-empty signals of the asynchronous FIFO are determined. The asynchronous FIFO is used to transfer image data signals with different input and output clocks. At the input of the asynchronous FIFO, it is determined whether the pre-full signal is true; If the judgment result is yes, then continue to judge whether the currently input data is valid image data; If so, continue writing data to the asynchronous FIFO; otherwise, pause writing data to the asynchronous FIFO once. If the pre-full signal is determined to be false, then real-time data is written to the asynchronous FIFO; At the output of the asynchronous FIFO, determine whether the pre-empt signal is true; If the judgment result is yes, then continue to judge whether the output of the last clock cycle before the pre-empt signal is valid image data; If the data is valid, output the real-time data; if the data is not valid, copy the data from the last clock cycle before the pre-empt signal appears and output it. If the judgment result indicates that the pre-emptive signal is false, then output a real-time signal; The threshold conditions for determining the flag signal of the asynchronous FIFO include: assuming the horizontal pixel count of the image is M, the clock error range is -N to N, and N is a percentage, then the threshold for determining the pre-full signal and pre-empty signal of the asynchronous FIFO is K: K = M * N * 2. When there are K empty positions remaining in the asynchronous FIFO, it enters the pre-full state; when there are K data remaining in the asynchronous FIFO, it enters the pre-empty state.
2. The method according to claim 1, characterized in that, The valid image data is represented by the DE signal, which is a valid data strobe signal. The video data signal corresponding to the period when the DE signal is true is the valid image data signal.
3. An input processing circuit for implementing the input processing method of the image data interface according to claim 1, characterized in that, The input processing circuit is used to implement image protocol input processing at different clocks, and includes: an asynchronous FIFO circuit and a protocol control logic circuit that interacts with the asynchronous FIFO circuit; The protocol control logic circuit is used to: determine whether to continue writing data to the asynchronous FIFO and execute the write operation based on the pre-full signal and whether the currently input data is valid; and determine whether to output real-time data or output copied invalid data based on the pre-empty signal and whether the data in the last clock cycle before the pre-empty signal is valid.
4. The circuit according to claim 3, characterized in that: The protocol control logic circuit includes a pre-full control unit, a pre-empty control unit, and an output control unit; The pre-full control unit includes a first logic inverting circuit, a first NAND gate, and a first AND gate. The pre-full signal of the asynchronous FIFO is connected to one input of the first NAND gate. The DE signal input to the asynchronous FIFO is connected to the other input of the first NAND gate after passing through the first logic inverting circuit. The output of the first NAND gate is connected to one input of the first AND gate. The write data request sent by the external control logic is connected to the other input of the first AND gate. The output of the first AND gate is connected to the input of the asynchronous FIFO. The pre-empty control unit includes a second logic inverting circuit, a second NAND gate, and a second AND gate. The pre-empty signal of the asynchronous FIFO is connected to one input of the second NAND gate. The DE signal at the output of the asynchronous FIFO is connected to the other input of the second NAND gate after passing through the second logic inverting circuit. The output of the second NAND gate is connected to one input of the second AND gate. The read data request sent by the external control logic is connected to the other input of the second AND gate. The output of the second AND gate is connected to the read enable terminal of the asynchronous FIFO. The output control unit includes a register and a selector. The input terminal of the register is connected to the read data, the output terminal of the register is connected to one input terminal of the selector, the other input terminal of the selector is connected to the read data, and the output terminal of the selector outputs data. The DE signal is a valid data strobe signal, and the video data signal corresponding to the period when the DE signal is true is a valid image data signal.
5. The circuit according to claim 4, characterized in that: When the determination result is that invalid data needs to be copied, the register does not store the invalid data; at other times, the output data of the asynchronous FIFO needs to be stored.