Pixel circuits, display panels and display devices

Abstract

This application provides a pixel circuit, a display panel, and a display device. At least one transistor in the pixel circuit is a first dual-gate transistor. The first dual-gate transistor includes a first active layer and a first gate and a second gate located on opposite sides of the first active layer. The first gate of the first dual-gate transistor receives a first control signal, and the second gate of the first dual-gate transistor receives a second control signal. Both the first and second control signals are pulse signals, and the pulse widths of the first and second control signals are different. This application can improve the driving capability of the first dual-gate transistor.

Description

Technical Field

[0001] This application belongs to the field of display technology, and in particular relates to a pixel circuit, a display panel, and a display device. Background Technology

[0002] With the continuous improvement of display technology, people's requirements for display devices are also constantly increasing. Among various display technologies, self-emissive display devices have been widely used in various electronic devices, including computers, mobile phones and other electronic products, due to their advantages such as self-emissiveness, thinness, low power consumption, high contrast, high color gamut and flexible display.

[0003] The self-emissive elements in a self-emissive display device can include, for example, organic light-emitting diodes (OLEDs), quantum dot light-emitting diodes (QLEDs), and micro light-emitting diodes (Micro LEDs). In actual displays, the light-emitting elements are typically driven by a driving current output from a pixel circuit, enabling the display device to display an image.

[0004] A dual-gate transistor can be set in a pixel circuit. However, the inventors of this application have found that dual-gate transistors cannot currently ensure the stability of current transmission and the current output capability. Summary of the Invention

[0005] This application provides a pixel circuit, a display panel, and a display device that can improve the current output capability of dual-gate transistors.

[0006] In a first aspect, embodiments of this application provide a pixel circuit, which includes a transistor. At least one transistor in the pixel circuit is a first dual-gate transistor. The first dual-gate transistor includes a first active layer and a first gate and a second gate located on opposite sides of the first active layer. The first gate of the first dual-gate transistor is used to receive a first control signal, and the second gate of the first dual-gate transistor is used to receive a second control signal. Both the first control signal and the second control signal are pulse signals, and the pulse width of the first control signal is different from the pulse width of the second control signal.

[0007] Secondly, embodiments of this application provide a display panel, which includes pixel circuits as provided in the first aspect.

[0008] Thirdly, embodiments of this application provide a display device, which includes a display panel as provided in the second aspect.

[0009] The pixel circuit, display panel, and display device of this application embodiment include a pixel circuit in which at least one transistor is a first dual-gate transistor. The first dual-gate transistor includes a first active layer and a first gate and a second gate located on opposite sides of the first active layer. The first gate of the first dual-gate transistor is used to receive a first control signal, and the second gate of the first dual-gate transistor is used to receive a second control signal. Both the first and second control signals are pulse signals, and the pulse widths of the first and second control signals are different. On one hand, since the first gate of the first dual-gate transistor is used to receive the first control signal, and the second gate of the first dual-gate transistor is used to receive the second control signal, and both the first and second control signals are pulse signals, the first dual-gate transistor can be turned on under the combined control of the first and second control signals, increasing the conduction degree of the first dual-gate transistor, increasing the number of charge carriers flowing through the first dual-gate transistor, thereby increasing the current output capability of the first dual-gate transistor. On the other hand, since the pulse width of the first control signal is different from that of the second control signal, even if the first control signal and / or the second control signal are delayed, the overlap time of the enable level of the first control signal and the enable level of the second control signal can be guaranteed to be the same or similar to the pulse width of the enable level with the shortest pulse width among the enable levels of the first control signal and the second control signal. This is beneficial to ensure that the conduction time of the first dual-gate transistor of the pixel circuit at different positions is the same or similar, thereby improving the uniformity of the display. Attached Figure Description

[0010] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a cross-sectional schematic diagram of a dual-gate transistor;

[0012] Figure 2 A waveform diagram showing a portion of the first control signal and a portion of the second control signal;

[0013] Figure 3 A cross-sectional schematic diagram of a first dual-gate transistor in a pixel circuit provided in an embodiment of this application;

[0014] Figure 4 This is a schematic diagram of another waveform, showing a partial waveform of the first control signal and a partial waveform of the second control signal.

[0015] Figure 5 This is a schematic diagram illustrating the relationship between the enable level of the first control signal and the enable level of the second control signal under different time delay conditions.

[0016] Figure 6 This is a schematic diagram illustrating another relationship between the enable level of the first control signal and the enable level of the second control signal under different time delay conditions.

[0017] Figure 7 This is another waveform diagram showing a partial waveform of the first control signal and a partial waveform of the second control signal;

[0018] Figure 8 This is another waveform diagram showing a partial waveform of the first control signal and a partial waveform of the second control signal;

[0019] Figure 9 This is another waveform diagram showing a partial waveform of the first control signal and a partial waveform of the second control signal;

[0020] Figure 10 Another cross-sectional schematic diagram of the first dual-gate transistor in the pixel circuit provided in the embodiments of this application;

[0021] Figure 11 A schematic diagram of a pixel circuit provided in an embodiment of this application;

[0022] Figure 12 Another circuit diagram of the pixel circuit provided in the embodiments of this application;

[0023] Figure 13 A cross-sectional schematic diagram of a second dual-gate transistor in a pixel circuit provided in an embodiment of this application;

[0024] Figure 14 Another circuit diagram of the pixel circuit provided in the embodiments of this application;

[0025] Figure 15 Another circuit diagram of the pixel circuit provided in the embodiments of this application;

[0026] Figure 16 A timing diagram showing the enable level of the first scan signal and the enable level of the second control signal;

[0027] Figure 17 A schematic diagram of a connection of the second dual-gate transistor in a pixel circuit provided in an embodiment of this application;

[0028] Figure 18 A waveform diagram illustrating the enable levels of a Class A scan signal and a Class B scan signal;

[0029] Figure 19 Another circuit diagram of the pixel circuit provided in the embodiments of this application;

[0030] Figure 20A timing diagram showing the enable level of the first Class A scan signal and the enable level of the second control signal;

[0031] Figure 21 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0032] Figure 22 Another structural schematic diagram of the display panel provided in the embodiments of this application;

[0033] Figure 23 A schematic diagram of yet another structure of the display panel provided in an embodiment of this application;

[0034] Figure 24 This is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0035] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0036] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0037] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0038] It should be noted that the transistors in the embodiments of this application can be either N-type or P-type transistors. Unless otherwise specified, the embodiments of this application will be described using a P-type transistor as an example. For an N-type transistor, the on-state level is high and the off-state level is low. That is, when the gate of an N-type transistor is high, its first and second terminals are connected; when the gate of an N-type transistor is low, its first and second terminals are off. For a P-type transistor, the on-state level is low and the off-state level is high. That is, when the control terminal of a P-type transistor is low, its first and second terminals are connected; when the control terminal of a P-type transistor is high, its first and second terminals are off. In specific implementation, the gate of each transistor is used as its control electrode. Furthermore, depending on the signal and type of the gate of each transistor, its first electrode can be used as the source and its second electrode as the drain, or its first electrode can be used as the drain and its second electrode as the source. No distinction is made here. In addition, the on-level and off-level in the embodiments of the present invention are general terms. The on-level refers to any level that can turn on the transistor, and the off-level refers to any level that can turn off / turn off the transistor.

[0039] In the embodiments of this application, the term "electrical connection" can refer to a direct electrical connection between two components, or it can refer to an electrical connection between two components via one or more other components.

[0040] In the embodiments of this application, the first node is defined only for the convenience of describing the circuit structure, and the first node is not an actual circuit unit.

[0041] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this application can be combined with each other without contradiction.

[0042] Before describing the technical solutions provided in the embodiments of this application, in order to facilitate understanding of the embodiments of this application, this application first specifically explains the problems existing in the related technologies:

[0043] Figure 1 This is a schematic cross-sectional view of a dual-gate transistor. (Example) Figure 1As shown, a dual-gate transistor may include an active layer 11' and a top gate a' and a bottom gate b' located on opposite sides (i.e., different sides) of the active layer 11'. In related technologies, the top gate a' is typically used to receive a control signal, and the bottom gate b' is used to receive a constant voltage signal. The top gate a' can control the on / off state of the dual-gate transistor under the control of the control signal. That is, only the top gate a' is active when the dual-gate transistor is turned on, while the bottom gate b' is inactive. This makes it impossible to induce additional charge carriers in the dual-gate transistor, resulting in a lower degree of conduction and consequently a weaker current output capability, i.e., a smaller output current.

[0044] In view of this, this application considers that one of the top gate and the bottom gate of the dual-gate transistor may receive a first control signal and the other may receive a second control signal, so that the dual-gate transistor can be turned on under the joint control of the first control signal and the second control signal, thereby increasing the conduction degree of the dual-gate transistor, increasing the number of charge carriers flowing through the first dual-gate transistor, and thus increasing the current output capability of the first dual-gate transistor.

[0045] Figure 2 This is a waveform diagram showing a portion of the waveforms of the first control signal and a portion of the waveforms of the second control signal. Figure 2 In the diagram, K1 represents a portion of the waveform of the first control signal, and K2 represents a portion of the waveform of the first control signal. Figure 2 The example is illustrated by having both the enable levels of the first and second control signals low. For instance, a dual-gate transistor is turned on when both the first and second control signals are enabled. Figure 2 As shown, the inventors of this application further realized that the first control signal and / or the second control signal may experience time delays during transmission due to load effects. Figure 2 For example, if the pulse width of the first control signal is the same as the pulse width of the second control signal (e.g., the pulse width of the enable level of the first control signal is the same as the pulse width of the enable level of the second control signal), then when neither the first nor the second control signal experiences a time delay, the overlap time between the enable levels of the first and second control signals is t1. However, when the first and / or second control signals experience a time delay (e.g., the overlap time between the enable levels of the first and second control signals is t2), t2 < t1. Furthermore, the overlap time t2 will change depending on the time delay.

[0046] The loads corresponding to pixel circuits at different locations may differ, so the time delays of the first and / or second control signals received by pixel circuits at different locations may also differ. If the pulse width of the first control signal is the same as the pulse width of the second control signal—for example, if the pulse width of the enable level of the first control signal is the same as the pulse width of the enable level of the second control signal—a time delay in the first and / or second control signals will cause significant differences in the conduction duration (i.e., the aforementioned overlap time t2) of the dual-gate transistors in pixel circuits at different locations. For example, some pixel circuits may have their dual-gate transistors turn on earlier, while others may have them turn on later, resulting in poor display uniformity.

[0047] In view of the inventors’ above-mentioned research findings, the embodiments of this application provide a pixel circuit, a display panel and a display device, which can solve the above-mentioned technical problems existing in the related art.

[0048] The technical concept of this application embodiment is as follows: at least one transistor in the pixel circuit is a first dual-gate transistor. The first dual-gate transistor includes a first active layer and a first gate and a second gate located on opposite sides of the first active layer. The first gate of the first dual-gate transistor is used to receive a first control signal, and the second gate of the first dual-gate transistor is used to receive a second control signal. Both the first control signal and the second control signal are pulse signals, and the pulse width of the first control signal is different from that of the second control signal. On the one hand, since the first gate of the first dual-gate transistor is used to receive the first control signal, and the second gate of the first dual-gate transistor is used to receive the second control signal, and both the first control signal and the second control signal are pulse signals, the first dual-gate transistor can be turned on under the joint control of the first control signal and the second control signal, thereby increasing the conduction degree of the first dual-gate transistor, increasing the number of charge carriers flowing through the first dual-gate transistor, and thus increasing the driving capability of the first dual-gate transistor. On the other hand, since the pulse width of the first control signal is different from that of the second control signal, even if the first control signal and / or the second control signal are delayed, the overlap time of the enable level of the first control signal and the enable level of the second control signal can be guaranteed to be the same or similar to the pulse width of the enable level with the shortest pulse width among the enable levels of the first control signal and the second control signal. This is beneficial to ensure that the conduction time of the first dual-gate transistor of the pixel circuit at different positions is the same or similar, thereby improving the uniformity of the display.

[0049] The pixel circuit provided in the embodiments of this application will be described below.

[0050] In this embodiment, the pixel circuit may include a transistor. The transistor may include a thin-film transistor (TFT).

[0051] Figure 3 This is a cross-sectional schematic diagram of a first dual-gate transistor in a pixel circuit provided in an embodiment of this application. For example... Figure 3 As shown, at least one transistor in the pixel circuit is a first dual-gate transistor ST1. The first dual-gate transistor ST1 may include a first active layer 31 and a first gate g11 and a second gate g12 located on opposite sides of the first active layer 31. The first active layer 31 may, for example, include a channel region CHD and source regions s and drain regions d located on opposite sides of the channel region CHD. The doping concentration of the channel region CHD may be lower than the doping concentration of the source regions s and drain regions d. Figure 3 The example shown is based on the configuration of the first gate g11 located on the first side A1 of the first active layer 31 and the second gate g12 located on the second side A2 of the first active layer 31. However, in other embodiments, the positions of the first gate g11 and the second gate g12 can be interchanged, i.e., the first gate g11 is located on the second side A2 of the first active layer 31, and the second gate g12 is located on the first side A1 of the first active layer 31. The first side A1 of the first active layer 31 can be, for example, the side of the first active layer 31 facing away from the substrate 01, and the second side A2 of the first active layer 31 can be, for example, the side of the first active layer 31 facing the substrate 01.

[0052] The first gate g11 of the first dual-gate transistor ST1 can be used to receive a first control signal, and the second gate g12 of the first dual-gate transistor ST1 can be used to receive a second control signal. The first control signal and the second control signal can be different signals. The first dual-gate transistor ST1 can be turned on under the joint control of the first control signal and the second control signal. For example, when both the first control signal and the second control signal are at the enable level, the first dual-gate transistor ST1 is turned on.

[0053] Figure 4 This is a schematic diagram showing a partial waveform of the first control signal and a partial waveform of the second control signal. (See diagram below.) Figure 4 As shown, both the first control signal K1 and the second control signal K2 can be pulse signals, and the pulse width of the first control signal K1 is different from that of the second control signal K2. Specifically, the pulse width of the enable level p1 of the first control signal K1 is different from the pulse width of the enable level p2 of the second control signal K2. Figure 4 The example shown is based on the premise that the enable level p1 of the first control signal K1 and the enable level p2 of the second control signal K2 are both low. However, in other embodiments, the enable level p1 of the first control signal K1 and the enable level p2 of the second control signal K2 may also be high. This application does not limit this.

[0054] The pulse width of the enable level p2 of the second control signal K2 can be greater than the pulse width of the enable level p1 of the first control signal K1, or the pulse width of the enable level p2 of the second control signal K2 can be less than the pulse width of the enable level p1 of the first control signal K1. This application embodiment does not limit this.

[0055] Figure 5 This diagram illustrates the relationship between the enable levels of the first and second control signals under different time delays. Figure 5 In the diagram, K1-1 represents the first control signal without delay, K2-1 represents the second control signal without delay, K1-2 and K1-3 both represent the first control signal with delay, and K2-2 and K2-3 both represent the second control signal with delay. Figure 5 In the illustrated embodiment, the pulse width of the enable level p2 of the second control signal K2 can be greater than the pulse width of the enable level p1 of the first control signal K1. For example... Figure 5 As shown, regardless of whether the first control signal is delayed, the second control signal is delayed, or both the first and second control signals are delayed, the overlap time between the enable level p1 of the first control signal and the enable level p2 of the second control signal can be equal to t1, that is, the enable level with the shortest pulse width among the enable levels p1 and p2 of the first and second control signals (e.g., t1). Figure 5 The pulse widths of the enable levels p1 shown are the same or similar. This helps to ensure that the conduction duration of the first dual-gate transistors in pixel circuits at different locations is the same or similar, thereby improving display uniformity.

[0056] Figure 6 This diagram illustrates another relationship between the enable level of the first control signal and the enable level of the second control signal under different time delays. Figure 5 The difference between the illustrated embodiment and the one shown is that, in Figure 6 In the illustrated embodiment, the pulse width of the enable level p2 of the second control signal K2 can be smaller than the pulse width of the enable level p1 of the first control signal K1. For example... Figure 6 As shown, regardless of whether the first control signal is delayed, the second control signal is delayed, or both the first and second control signals are delayed, the overlap time between the enable level p1 of the first control signal and the enable level p2 of the second control signal can be equal to t1, that is, the enable level with the shortest pulse width among the enable levels p1 and p2 of the first and second control signals (e.g., t1). Figure 6 The pulse widths of the enable levels (p2) shown are the same or similar. This helps ensure that the conduction durations of the first dual-gate transistors in pixel circuits at different locations are the same or similar, thereby improving display uniformity.

[0057] In the pixel circuit of this application embodiment, at least one transistor in the pixel circuit is a first dual-gate transistor. The first dual-gate transistor includes a first active layer and a first gate and a second gate located on opposite sides of the first active layer. The first gate of the first dual-gate transistor is used to receive a first control signal, and the second gate of the first dual-gate transistor is used to receive a second control signal. Both the first control signal and the second control signal are pulse signals, and the pulse width of the first control signal is different from that of the second control signal. On the one hand, since the first gate of the first dual-gate transistor is used to receive the first control signal, and the second gate of the first dual-gate transistor is used to receive the second control signal, and both the first control signal and the second control signal are pulse signals, the first dual-gate transistor can be turned on under the joint control of the first control signal and the second control signal, thereby increasing the conduction degree of the first dual-gate transistor, increasing the number of charge carriers flowing through the first dual-gate transistor, and thus increasing the driving capability of the first dual-gate transistor. On the other hand, since the pulse width of the first control signal is different from that of the second control signal, even if the first control signal and / or the second control signal are delayed, the overlap time of the enable level of the first control signal and the enable level of the second control signal can be guaranteed to be the same or similar to the pulse width of the enable level with the shortest pulse width among the enable levels of the first control signal and the second control signal. This is beneficial to ensure that the conduction time of the first dual-gate transistor of the pixel circuit at different positions is the same or similar, thereby improving the uniformity of the display.

[0058] Figure 7 This is another waveform diagram showing a portion of the waveforms of the first control signal and a portion of the waveforms of the second control signal. For example... Figure 7 As shown, according to some embodiments of this application, optionally, the start edge of the enable level p2 of the second control signal K2 may be at the same or similar time as the start edge of the enable level p1 of the first control signal K1, and the end edge of the enable level p2 of the second control signal K2 may be later than the end edge of the enable level p1 of the first control signal K1.

[0059] For example, when neither the first control signal K1 nor the second control signal K2 experiences a time delay, the overlap time between the enable levels p1 and p2 of the first and second control signals is t1. Since the end edge of the enable level p2 of the second control signal K2 is later than the end edge of the enable level p1 of the first control signal K1, when the first control signal K1 experiences a time delay, the overlap time between the enable levels p1 and p2 of the first and second control signals can still be the same as or close to t1, i.e., the overlap time between the enable level with the shortest pulse width among the enable levels p1 and p2 of the first and second control signals (e.g., the enable level with the shortest pulse width). Figure 7The pulse widths of the enable levels p1 shown are the same or similar. This helps to ensure that the conduction duration of the first dual-gate transistors in pixel circuits at different locations is the same or similar, thereby improving display uniformity.

[0060] Figure 8 This is another waveform diagram showing a portion of the waveforms of the first control signal and a portion of the waveforms of the second control signal. For example... Figure 8 As shown, according to some embodiments of this application, optionally, the start edge of the enable level p2 of the second control signal K2 may be earlier than the start edge of the enable level p1 of the first control signal K1, and the end edge of the enable level p2 of the second control signal K2 may be at the same or similar time as the end edge of the enable level p1 of the first control signal K1.

[0061] For example, when neither the first control signal K1 nor the second control signal K2 experiences a time delay, the overlap time between the enable levels p1 and p2 of the first and second control signals is t1. Since the start edge of the enable level p2 of the second control signal K2 is earlier than the start edge of the enable level p1 of the first control signal K1, when the second control signal K2 experiences a time delay, the overlap time between the enable levels p1 and p2 of the first and second control signals can still be the same as or close to t1, i.e., the overlap time between the enable level with the shortest pulse width among the enable levels p1 and p2 (e.g., the first control signal K1 and the second control signal K2). Figure 8 The pulse widths of the enable levels p1 shown are the same or similar. This helps to ensure that the conduction duration of the first dual-gate transistors in pixel circuits at different locations is the same or similar, thereby improving display uniformity.

[0062] Combination Figure 4 and Figure 5 As shown, according to some embodiments of this application, optionally, the start edge of the enable level p2 of the second control signal K2 may be earlier than the start edge of the enable level p1 of the first control signal K1, and the end edge of the enable level p2 of the second control signal K2 may be later than the end edge of the enable level p1 of the first control signal K1.

[0063] For example, when neither the first control signal K1 nor the second control signal K2 experiences a time delay, the overlap time between the enable levels p1 and p2 of the first and second control signals is t1. Since the start edge of the enable level p2 of the second control signal K2 is earlier than the start edge of the enable level p1 of the first control signal K1, and the end edge of the enable level p2 of the second control signal K2 is later than the end edge of the enable level p1 of the first control signal K1, the overlap time between the enable levels p1 and p2 of the first and second control signals can still be the same as or close to t1, regardless of whether the first control signal K1, the second control signal K2, or both are delayed. That is, the overlap time is the shortest pulse width enable level between the first and second control signals (e.g., the one with the shortest pulse width). Figure 5 The pulse widths of the enable levels p1 shown are the same or similar. This helps to ensure that the conduction duration of the first dual-gate transistors in pixel circuits at different locations is the same or similar, thereby improving display uniformity.

[0064] As mentioned earlier, the delay of the first control signal received by pixel circuits at different locations may vary. The inventors of this application have discovered that the maximum delay of the first control signal received by pixel circuits at different locations is, for example, less than 0.5 microseconds. Therefore, as... Figure 4 or Figure 7 As shown, in some specific embodiments, the interval ΔH1 between the end edge of the enable level p2 of the second control signal K2 and the end edge of the enable level p1 of the first control signal K1 can be greater than or equal to 0.5 microseconds.

[0065] Thus, since the interval ΔH1 between the end edge of the enable level p2 of the second control signal K2 and the end edge of the enable level p1 of the first control signal K1 is greater than or equal to 0.5 microseconds, i.e., the interval ΔH1 is greater than or equal to the maximum delay of the first control signal, it can be guaranteed that when the first control signal K1 experiences a delay, the overlap time between the enable levels p1 and p2 of the first control signal received by the pixel circuits at different positions is t1, i.e., the shortest pulse width enable level among the enable levels p1 and p2 of the first and second control signals (e.g., the one with the shortest pulse width). Figure 4 or Figure 7 The pulse widths of the enable levels (p1) shown are the same. This ensures that the conduction duration of the first dual-gate transistors in pixel circuits at different locations is the same, greatly improving display uniformity.

[0066] Further research by the inventors of this application revealed that the maximum delay in the delay of the second control signal received by the pixel circuits at different locations is, for example, less than 0.5 microseconds. In view of this, as... Figure 4or Figure 8 As shown, in some specific embodiments, the interval ΔH2 between the starting edge of the enable level p2 of the second control signal K2 and the starting edge of the enable level p1 of the first control signal K1 can be greater than or equal to 0.5 microseconds.

[0067] Thus, since the interval ΔH2 between the starting edge of the enable level p2 of the second control signal K2 and the starting edge of the enable level p1 of the first control signal K1 is greater than or equal to 0.5 microseconds, i.e., the interval ΔH2 is greater than or equal to the maximum delay of the second control signal, it can be guaranteed that when the second control signal K2 experiences a delay, the overlap time of the enable levels p1 and p2 of the first control signal received by the pixel circuits at different positions is t1, i.e., the shortest pulse width enable level among the enable levels p1 and p2 of the first and second control signals (e.g., the one with the shortest pulse width). Figure 4 or Figure 8 The pulse widths of the enable levels (p1) shown are the same. This ensures that the conduction duration of the first dual-gate transistors in pixel circuits at different locations is the same, greatly improving display uniformity.

[0068] like Figure 4 As shown, in some specific embodiments, optionally, the interval ΔH1 between the end edge of the enable level p2 of the second control signal K2 and the end edge of the enable level p1 of the first control signal K1 can be greater than or equal to 0.5 microseconds, and the interval ΔH2 between the start edge of the enable level p2 of the second control signal K2 and the start edge of the enable level p1 of the first control signal K1 can be greater than or equal to 0.5 microseconds.

[0069] Thus, regardless of whether the first control signal K1, the second control signal K2, or both are delayed, the overlap time between the enable levels p1 and p2 of the first and second control signals received by the pixel circuits at different locations is always t1, which is the shortest pulse width enable level between the first and second control signals (e.g., the enable level of the first control signal K1 and the enable level of the second control signal K2). Figure 4 The pulse widths of the enable levels (p1) shown are the same. This ensures that the conduction duration of the first dual-gate transistors in pixel circuits at different locations is the same, greatly improving display uniformity.

[0070] See also Figure 4 According to some embodiments of this application, optionally, the pulse width of the enable level p1 of the first control signal K1 is the first time interval ΔT1.

[0071] The interval ΔH2 between the start edge of the enable level p2 of the second control signal K2 and the start edge of the enable level p1 of the first control signal K1 is less than the first time interval ΔT1, and / or the interval ΔH1 between the end edge of the enable level p2 of the second control signal K2 and the end edge of the enable level p1 of the first control signal K1 is less than the first time interval ΔT1.

[0072] In this way, since ΔH1 and / or ΔH2 are less than the first time interval ΔT1, it can be ensured that the pulse width of the enable level p2 of the second control signal K2 will not be too long, thereby ensuring that the time occupied by each row of pixel circuits will not be too long, which is beneficial to achieving a high refresh rate.

[0073] See also Figure 4 According to some embodiments of this application, optionally, the first dual-gate transistor can be a P-type transistor, and the enable level p1 of the first control signal K1 and the enable level p2 of the second control signal K2 can both be low. Accordingly, the start edge of the enable level can be a falling edge, and the end edge of the enable level can be a rising edge.

[0074] In some specific embodiments, when the first dual-gate transistor is a P-type transistor, the falling edge of the low level of the second control signal K2 can be earlier than the falling edge of the low level of the first control signal K1, and / or, the rising edge of the low level of the second control signal K2 can be later than the rising edge of the low level of the first control signal K1. This helps ensure that the conduction duration of the first dual-gate transistor in pixel circuits at different locations is the same or similar, thereby improving display uniformity.

[0075] Figure 9 This is another waveform diagram showing a portion of the waveforms of the first control signal and a portion of the waveforms of the second control signal. For example... Figure 9 As shown, according to some embodiments of this application, optionally, the first dual-gate transistor can be an N-type transistor, and the enable level p1 of the first control signal K1 and the enable level p2 of the second control signal K2 can both be high. Accordingly, the start edge of the enable level can be a rising edge, and the end edge of the enable level can be a falling edge.

[0076] In some specific embodiments, when the first dual-gate transistor is an N-type transistor, the rising edge of the high level of the second control signal K2 can be earlier than the rising edge of the high level of the first control signal K1, and / or, the falling edge of the high level of the second control signal K2 can be later than the falling edge of the high level of the first control signal K1. This helps ensure that the conduction duration of the first dual-gate transistor in pixel circuits at different locations is the same or similar, thereby improving display uniformity.

[0077] See also Figure 3According to some embodiments of this application, optionally, the display panel where the pixel circuit is located may include at least a substrate 01, a first metal layer M1, an active layer 02, and a second metal layer M2 stacked together. Along the thickness direction Z of the display panel, the first metal layer M1 may be located between the substrate 01 and the active layer 02, and the second metal layer M2 may be located on the side of the active layer 02 away from the substrate 01. The first active layer 31 may be located on the active layer 02. It should be noted that... Figure 3 Other membrane layers may also be included in the cross-sectional structure shown, but they are not shown here for the sake of simplicity.

[0078] The first gate g11 of the first dual-gate transistor ST1 can be located in the second metal layer M2, and the second gate g12 of the first dual-gate transistor ST1 can be located in the first metal layer M1. That is, the first gate g11 can be a top gate, and the second gate g12 can be a bottom gate.

[0079] Figure 10 Another cross-sectional schematic diagram of the first dual-gate transistor in the pixel circuit provided in an embodiment of this application. (See attached diagram.) Figure 10 As shown, with Figure 3 The difference in the illustrated embodiment is that the first gate g11 of the first dual-gate transistor ST1 can be located in the first metal layer M1, and the second gate g12 of the first dual-gate transistor ST1 can be located in the second metal layer M2. That is, the first gate g11 can be the bottom gate, and the second gate g12 can be the top gate.

[0080] Figure 11 This is a schematic diagram of a pixel circuit provided in an embodiment of this application. Figure 11 As shown, according to some embodiments of this application, the pixel circuit 10 may optionally include a light-emitting branch FL connected to the light-emitting element D. The light-emitting branch FL can be used to provide a driving current to the light-emitting element D to drive the light-emitting element D to emit light. At least one transistor in the light-emitting branch FL may be a first dual-gate transistor ST1.

[0081] The first dual-gate transistor ST1 can be turned on under the combined control of the first and second control signals, and the output current of the first dual-gate transistor ST1 is relatively large. Therefore, by placing at least one first dual-gate transistor ST1 in the light-emitting branch FL, the driving current provided by the light-emitting branch FL can be increased, that is, the driving current output by the pixel circuit can be increased, thereby increasing the driving capability of the pixel circuit.

[0082] See also Figure 11According to some embodiments of this application, optionally, the light-emitting branch FL may include a driving transistor T1 and a light-emitting control transistor T2. The gate of the driving transistor T1 is electrically connected to the first node N1, the first electrode of the driving transistor T1 is electrically connected to the first power supply voltage signal line PVDD, and the second electrode of the driving transistor T1 is electrically connected to the first electrode of the light-emitting element D. The second electrode of the light-emitting element D is electrically connected to the second power supply voltage signal line PVEE. The first electrode of the light-emitting element D may include the anode of the light-emitting element D, and the second electrode of the light-emitting element D may include the cathode of the light-emitting element D.

[0083] The first gate of the light-emitting control transistor T2 is electrically connected to the first light-emitting control signal line EM1, and the second gate of the light-emitting control transistor T2 is electrically connected to the second light-emitting control signal line EM2. The first light-emitting control signal line EM1 can be used to transmit a first control signal, and the second light-emitting control signal line EM2 can be used to transmit a second control signal. The light-emitting control transistor T2 can be connected in series between the first electrode of the driving transistor T1 and the first power supply voltage signal line PVDD and / or connected in series between the second electrode of the driving transistor T1 and the first electrode of the light-emitting element D. Figure 11 The example shown is that the light-emitting control transistor T2 is connected in series between the second electrode of the driving transistor T1 and the first electrode of the light-emitting element D. Figure 11 As shown, the first electrode of the light-emitting control transistor T2 can be electrically connected to the second electrode of the driving transistor T1, and the second electrode of the light-emitting control transistor T2 can be electrically connected to the first electrode of the light-emitting element D.

[0084] The first dual-gate transistor ST1 may include a light-emitting control transistor T2.

[0085] Thus, since the light-emitting control transistor T2 in the light-emitting branch FL is the first dual-gate transistor ST1, the driving current provided by the light-emitting branch FL can be increased, that is, the driving current output by the pixel circuit can be increased, thereby increasing the driving capability of the pixel circuit.

[0086] Figure 12 This is another circuit diagram of the pixel circuit provided in an embodiment of this application. For example... Figure 12 As shown, according to some embodiments of this application, optionally, the light-emitting control transistor T2 may include a first light-emitting control transistor T21 and a second light-emitting control transistor T22.

[0087] The first gate of the first light-emitting control transistor T21 is electrically connected to the first light-emitting control signal line EM1, the second gate of the first light-emitting control transistor T21 is electrically connected to the second light-emitting control signal line EM2, the first terminal of the first light-emitting control transistor T21 is electrically connected to the first power supply voltage signal line PVDD, and the second terminal of the first light-emitting control transistor T21 is electrically connected to the first terminal of the driving transistor T1.

[0088] The first gate of the second light-emitting control transistor T22 is electrically connected to the first light-emitting control signal line EM1, the second gate of the second light-emitting control transistor T22 is electrically connected to the second light-emitting control signal line EM2, the first electrode of the second light-emitting control transistor T22 is electrically connected to the second electrode of the driving transistor T1, and the second electrode of the first light-emitting control transistor T22 is electrically connected to the first electrode of the light-emitting element D.

[0089] The first light-emitting control transistor T21 can be turned on under the combined control of the first control signal provided by the first light-emitting control signal line EM1 and the second control signal provided by the second light-emitting control signal line EM2, thereby increasing the output current of the first light-emitting control transistor T21. The second light-emitting control transistor T22 can also be turned on under the combined control of the first control signal provided by the first light-emitting control signal line EM1 and the second control signal provided by the second light-emitting control signal line EM2, thereby increasing the output current of the second light-emitting control transistor T22. Therefore, the driving current provided by the light-emitting branch can be increased, that is, the driving current output by the pixel circuit can be increased, thus increasing the driving capability of the pixel circuit.

[0090] The inventors of this application further realized that the pixel circuit also includes transistors that are turned on / off under the control of the scan signal line. The enable level of the scan signal provided by the scan signal line has a short pulse width, meaning the transistors connected to the scan signal line have short conduction times. If the transistors connected to the scan signal line are turned on under the combined control of the first and second control signals, the enable levels of the first and second control signals need to overlap and be slightly offset. This lengthens the initialization and / or data writing time for each row of pixel circuits, thus increasing the time occupied by each row of pixel circuits, which is detrimental to achieving a high refresh rate.

[0091] The transistors connected to the light emission control signal lines (such as the first light emission control signal line EM1 and the second light emission control signal line EM2) have long conduction times. Therefore, increasing the pulse width of the enable level of one of the first and second control signals by a certain duration (such as a few microseconds) has little impact on the overall effect and can better improve the output current of the pixel circuit.

[0092] In view of this, this application considers that some dual-gate transistors in the pixel circuit (such as dual-gate transistors connected to the light emission control signal line) are turned on under the joint control of the first control signal and the second control signal, while other dual-gate transistors in the pixel circuit (such as dual-gate transistors connected to the scan signal line) are connected to a constant potential at one of their gates, which can be applied, for example, to high refresh rate scenarios.

[0093] Figure 13This is a cross-sectional schematic diagram of the second dual-gate transistor in the pixel circuit provided in an embodiment of this application. For example... Figure 13 As shown, specifically, according to some embodiments of this application, optionally, at least one transistor in the pixel circuit can be a second dual-gate transistor ST2. The second dual-gate transistor ST2 may include a second active layer 32 and a first gate g13 and a second gate g14 located on opposite sides of the second active layer 32. (Combined with...) Figure 3 and Figure 13 As shown, the structure of the second active layer 32 is similar to that of the first active layer 31, and will not be described again here. In some examples, both the second active layer 32 and the first active layer 31 may be located in active layer 02. Figure 13 The example shown is based on the premise that the first gate g13 is located on the first side B1 of the second active layer 33, and the second gate g14 is located on the second side B2 of the second active layer 33. However, in other embodiments, the positions of the first gate g13 and the second gate g14 can be interchanged, that is, the first gate g13 is located on the second side B2 of the second active layer 33, and the second gate g14 is located on the first side B1 of the second active layer 33. The first side B1 of the second active layer 33 can be, for example, the side of the second active layer 33 facing away from the substrate 01, and the second side B2 of the second active layer 33 can be, for example, the side of the second active layer 33 facing the substrate 01.

[0094] In some specific embodiments, the first gate g13 of the second dual-gate transistor ST2 can be located in the second metal layer M2, and the second gate g14 of the second dual-gate transistor ST2 can be located in the first metal layer M1. That is, the first gate g13 can be a top gate, and the second gate g14 can be a bottom gate.

[0095] In some other specific embodiments, the first gate g13 of the second dual-gate transistor ST2 can be located in the first metal layer M1, and the second gate g14 of the second dual-gate transistor ST2 can be located in the second metal layer M2. That is, the first gate g13 can be the bottom gate, and the second gate g14 can be the top gate.

[0096] One of the first gate g13 and the second gate g14 of the second dual-gate transistor ST2 is used to receive a constant voltage signal, and the other can be connected to the scan signal line or the target node (such as...). Figure 14 or Figure 15 The first node N1 shown is electrically connected. In this way, the first gate g13 or the second gate g14 can control the second dual-gate transistor ST2 to be turned on or off under the control of the scan signal line or the target node.

[0097] Thus, since the second dual-gate transistor ST2 is turned on under the control of a single signal, there is no need to misalign the two control signals, thereby reducing the time occupied by the pixel circuit in each row and facilitating the achievement of a high refresh rate.

[0098] Figure 14 This is another circuit diagram of the pixel circuit provided in an embodiment of this application. For example... Figure 14 As shown, according to some embodiments of this application, optionally, the second dual-gate transistor ST2 may include a switching transistor Tn. The first gate of the switching transistor Tn is electrically connected to the scan signal line S, and the second gate of the switching transistor Tn is electrically connected to the first constant voltage signal line V1. The first constant voltage signal line V1 can be used to transmit a first constant voltage signal. The first constant voltage signal is a voltage signal with a constant voltage value. The voltage value of the first constant voltage signal can be flexibly adjusted according to actual conditions, and this application does not limit this. Figure 14 Taking the switching transistor Tn as an example of the data writing transistor T3, in other embodiments, the switching transistor Tn may also include other transistors, and this application does not limit this. Figure 14 In the illustrated embodiment, the first gate of the data writing transistor T3 is electrically connected to the scan signal line S, the second gate of the data writing transistor T3 is electrically connected to the first constant voltage signal line V1, the first terminal of the data writing transistor T3 is electrically connected to the data signal line data, and the second terminal of the data writing transistor T3 is electrically connected to the first terminal of the driving transistor T1. The data writing transistor T3 is used to write the data signal from the data signal line data to the first gate (i.e., the first node N1) of the driving transistor T1 under the control of the scan signal line S.

[0099] And / or, the second dual-gate transistor includes ST2 which can drive transistor T1. The first gate of driving transistor T1 is electrically connected to the first node N1, and the second gate of driving transistor T1 is electrically connected to the second constant voltage signal line V2. The second constant voltage signal line V2 is used to transmit a second constant voltage signal, and driving transistor T1 is used to turn on or off under the control of the first node N1. The voltage value of the second constant voltage signal can be flexibly adjusted according to actual conditions, and this application embodiment does not limit it in this regard. The voltage value of the second constant voltage signal can be the same as or different from the voltage value of the first constant voltage signal, and this application embodiment does not limit it in this regard.

[0100] exist Figure 14 In the illustrated embodiment, the pixel circuit 10 may further include a storage capacitor Cst. The first plate of the storage capacitor Cst is electrically connected to the first node N1, and the second plate of the storage capacitor Cst is electrically connected to the first power supply voltage signal line PVDD. The storage capacitor Cst is used to maintain the potential of the first node N1. The first dual-gate transistor ST1 may include a light-emitting control transistor T2.

[0101] Thus, since the data writing transistor T3 is turned on under the control of the scan signal provided by the scan signal line S, there is no need to misalign the two control signals, thereby reducing the time occupied by each row of pixel circuits and facilitating the achievement of a high refresh rate. Furthermore, since the light-emitting control transistor T2 in the light-emitting branch is the first dual-gate transistor ST1, the driving current provided by the light-emitting branch can be increased, i.e., the driving current output by the pixel circuit can be increased, thereby increasing the driving capability of the pixel circuit.

[0102] Figure 15 This is another circuit diagram of the pixel circuit provided in an embodiment of this application. For example... Figure 15 As shown, according to some embodiments of this application, optionally, the scan signal line S may include a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, and / or a fourth scan signal line S4. The first constant voltage signal line V1 includes a first sub-constant voltage signal line V11, a second sub-constant voltage signal line V12, a third sub-constant voltage signal line V13, and / or a fourth sub-constant voltage signal line V14. The voltage values ​​of the constant voltage signals transmitted by the first sub-constant voltage signal line V11, the second sub-constant voltage signal line V12, the third sub-constant voltage signal line V13, and / or the fourth sub-constant voltage signal line V14 may be the same or different.

[0103] The second dual-gate transistor ST2 may include a switching transistor Tn, which may include a data writing transistor T3, a threshold compensation transistor T4, a first reset transistor T5, and / or a second reset transistor T6.

[0104] The first gate of the data writing transistor T3 is electrically connected to the first scan signal line S1, the second gate of the data writing transistor T3 is electrically connected to the first sub-constant voltage signal line V11, the first terminal of the data writing transistor T3 is electrically connected to the data signal line data, and the second terminal of the data writing transistor T3 is electrically connected to the first terminal of the driving transistor T1. The data writing transistor T3 is used to write the data signal of the data signal line data to the first terminal of the driving transistor T1 under the control of the first scan signal line S1.

[0105] The first gate of the threshold compensation transistor T4 is electrically connected to the second scan signal line S2, the second gate of the threshold compensation transistor T4 is electrically connected to the second sub-constant voltage signal line V12, the first terminal of the threshold compensation transistor T4 is electrically connected to the first terminal of the driving transistor T1, and the second terminal of the threshold compensation transistor T4 is electrically connected to the second terminal of the driving transistor T1. The threshold compensation transistor T4 is used to connect the first terminal of the driving transistor T1 and the second terminal of the driving transistor T1 under the control of the second scan signal line S2.

[0106] The first gate of the first reset transistor T5 is electrically connected to the third scan signal line S3, the second gate of the first reset transistor T5 is electrically connected to the third sub-constant voltage signal line V13, the first terminal of the first reset transistor T5 is electrically connected to the first reset signal line Vref1, and the second terminal of the first reset transistor T5 is electrically connected to the first node N1. The first reset transistor T5 is used to conduct under the control of the third scan signal line S3 to transmit the first reset signal of the first reset signal line Vref1 to the first node N1 to reset the first node N1.

[0107] The first gate of the second reset transistor T6 is electrically connected to the fourth scan signal line S4, the second gate of the second reset transistor T6 is electrically connected to the fourth constant voltage signal line V14, the first electrode of the second reset transistor T6 is electrically connected to the second reset signal line Vref2, and the second electrode of the second reset transistor T6 is electrically connected to the first electrode of the light-emitting element D. The second reset transistor T6 is used to conduct under the control of the fourth scan signal line S4, transmitting the second reset signal of the second reset signal line Vref2 to the first electrode of the light-emitting element D to reset the first electrode of the light-emitting element D. Exemplarily, the second reset signal line Vref2 may reuse the first reset signal line Vref1, or it may not reuse the first reset signal line Vref1; this application embodiment does not limit this.

[0108] The pixel circuit 10 may also include a storage capacitor Cst, the first plate of which is electrically connected to the first node N1, and the second plate of which is electrically connected to the first power supply voltage signal line PVDD. The storage capacitor Cst is used to maintain the potential of the first node N1.

[0109] exist Figure 15 In the illustrated embodiment, the first dual-gate transistor ST1 may include a first light-emitting control transistor T21 and a second light-emitting control transistor T22. The connection method of the first light-emitting control transistor T21 and the second light-emitting control transistor T22 has been described above and will not be repeated here.

[0110] Thus, since the data writing transistor T3, threshold compensation transistor T4, first reset transistor T5, and / or second reset transistor T6 are turned on under the control of the scan signal provided by the scan signal line S, there is no need to misalign the two control signals, thereby reducing the time occupied by each row of pixel circuits and facilitating the achievement of a high refresh rate. Furthermore, since the first light-emitting control transistor T21 and the second light-emitting control transistor T22 in the light-emitting branch are first dual-gate transistors ST1, the driving current provided by the light-emitting branch can be increased, i.e., the driving current output by the pixel circuit can be increased, thereby increasing the driving capability of the pixel circuit.

[0111] Figure 16This is a timing diagram showing the enable level of the first scan signal and the enable level of the second control signal. Figure 16 The example is illustrated with both the enable level of the first scan signal and the enable level of the second control signal being low. Figure 16 As shown, according to some embodiments of this application, optionally, considering the leakage current characteristic of the transistor itself, the start edge of the enable level p2 of the second control signal K2 can be later than the end edge of the enable level p3 of the first scan signal transmitted by the first scan signal line S1. That is, the second control signal K2 can be switched to the enable level only after the data signal is written, so as to better ensure the successful writing of the data signal and avoid the light-emitting element emitting light prematurely.

[0112] According to some embodiments of this application, optionally, in some cases, such as low refresh rate cases, or when the time per line is relatively sufficient, some dual-gate transistors in the pixel circuit (such as dual-gate transistors connected to the light emission control signal line) can also be driven in a similar manner to the first dual-gate transistor ST1, thereby increasing the driving capability of the dual-gate transistors.

[0113] Figure 17 This is a schematic diagram illustrating a connection of the second dual-gate transistor in a pixel circuit provided in an embodiment of this application. Figure 17 As shown, specifically, according to some embodiments of this application, optionally, at least one transistor in the pixel circuit can be a third dual-gate transistor ST3. The third dual-gate transistor ST3 may include a third active layer (not shown in the figure) and a first gate g15 and a second gate g16 located on opposite sides of the third active layer. The structure of the third dual-gate transistor ST3 is the same as or similar to the structure of the second dual-gate transistor ST2; please refer to the description of the structure of the second dual-gate transistor ST2 above, which will not be repeated here. The difference is that: the first gate g15 of the third dual-gate transistor ST3 is electrically connected to the Class A scan signal line Sa, and the first gate g15 of the third dual-gate transistor ST3 is used to receive the Class A scan signal transmitted by the Class A scan signal line Sa; the second gate g16 of the third dual-gate transistor ST3 is electrically connected to the Class B scan signal line Sc, and the second gate g16 of the third dual-gate transistor ST3 is used to receive the Class B scan signal transmitted by the Class B scan signal line Sc. Both the Class A and Class B scan signals are pulse signals.

[0114] Figure 18 This is a waveform diagram illustrating the enable levels of a Class A scan signal and a Class B scan signal. For example... Figure 18As shown, in some embodiments, the pulse width of the enable level p4 of the Class A scan signal K3 is different from the pulse width of the enable level p5 of the Class B scan signal K3. For example, the pulse width of the enable level p4 of the Class A scan signal K3 can be greater than the pulse width of the enable level p5 of the Class B scan signal K3.

[0115] The pulse width of the enable level p4 of the Class A scan signal K3 can be less than the pulse width of the enable level p1 of the first control signal K1. Similarly, the pulse width of the enable level p5 of the Class B scan signal K3 can also be less than the pulse width of the enable level p1 of the first control signal K1. For example, the first and second control signals K1 can control the light-emitting control transistor to turn on / off, while the Class A and Class B scan signals K3 can control the data writing transistor, threshold compensation transistor, and / or reset transistor to turn on / off.

[0116] In some embodiments, the start edge of the enable level p4 of the class A scan signal K3 may be earlier than the start edge of the enable level p5 of the class B scan signal K3, and / or the end edge of the enable level p4 of the class A scan signal K3 may be later than the end edge of the enable level p5 of the class B scan signal K3.

[0117] Thus, when a delay occurs in the Class A scan signal K3 and / or a delay occurs in the Class B scan signal K4, the overlap time between the enable level p4 of the Class A scan signal K3 and the enable level p5 of the Class B scan signal K3, and the enable level with the shortest pulse width among the enable levels p4 and p5 of the Class A scan signal K3 (e.g., Figure 18 The pulse widths of the enable levels (p5) shown are the same or similar. This helps ensure that the conduction duration of the third dual-gate transistors in pixel circuits at different locations is the same or similar, further improving display uniformity.

[0118] See also Figure 18 According to some embodiments of this application, optionally, the interval ΔH3 between the start edge of the enable level p4 of the Class A scan signal K3 and the enable level p5 of the Class B scan signal K3 can be less than or equal to the interval ΔH2 between the start edge of the enable level p2 of the second control signal K2 and the start edge of the enable level p1 of the first control signal K1.

[0119] And / or, the interval ΔH4 between the end edge of the enable level p4 of the Class A scan signal K3 and the end edge of the enable level p5 of the Class B scan signal K3 can be less than or equal to the interval ΔH1 between the end edge of the enable level p2 of the second control signal K2 and the end edge of the enable level p1 of the first control signal K1.

[0120] Thus, since the interval ΔH3 between the start edge of the enable level p4 of the Class A scan signal K3 and the enable level p5 of the Class B scan signal K3 is small, and / or the interval ΔH4 between the end edge of the enable level p4 of the Class A scan signal K3 and the end edge of the enable level p5 of the Class B scan signal K3 is small, it can be ensured that the time for initializing and / or writing data signals for each row of pixel circuits will not be too long, that is, it can be ensured that the time occupied by each row of pixel circuits will not be too long, which is beneficial to improving the refresh rate.

[0121] Figure 19 This is another circuit diagram of the pixel circuit provided in an embodiment of this application. For example... Figure 19 As shown, according to some embodiments of this application, optionally, a Class A scan signal line Sa may include a first Class A scan signal line Sa1, a second Class A scan signal line Sa2, a third Class A scan signal line Sa3, and / or a fourth Class A scan signal line Sa4. A Class B scan signal line Sc may include a first Class B scan signal line Sc1, a second Class B scan signal line Sc2, a third Class B scan signal line Sc3, and / or a fourth Class B scan signal line Sc4.

[0122] The third dual-gate transistor ST3 may include a data write transistor T3, a threshold compensation transistor T4, a first reset transistor T5, and / or a second reset transistor T6.

[0123] The first gate of the data writing transistor T3 is electrically connected to the first Class A scan signal line Sa1, the second gate of the data writing transistor T3 is electrically connected to the first Class B scan signal line Sc1, the first terminal of the data writing transistor T3 is electrically connected to the data signal line data, and the second terminal of the data writing transistor T3 is electrically connected to the first terminal of the driving transistor T1. The data writing transistor T3 is turned on under the control of the first Class A scan signal line Sa1 and the first Class B scan signal line Sc1 to write the data signal of the data signal line data to the first terminal of the driving transistor T1.

[0124] The first gate of the threshold compensation transistor T4 is electrically connected to the second Class A scan signal line Sa2, the second gate of the threshold compensation transistor T4 is electrically connected to the second Class B scan signal line Sc2, the first terminal of the threshold compensation transistor T4 is electrically connected to the first terminal of the driving transistor T1, and the second terminal of the threshold compensation transistor T4 is electrically connected to the second terminal of the driving transistor T1. The threshold compensation transistor T4 is used to connect the first terminal of the driving transistor T1 and the second terminal of the driving transistor T1 under the control of the second Class A scan signal line Sa2 and the second Class B scan signal line Sc2.

[0125] The first gate of the first reset transistor T5 is electrically connected to the third Class A scan signal line Sa3, the second gate of the first reset transistor T5 is electrically connected to the third Class B scan signal line Sc3, the first terminal of the first reset transistor T5 is electrically connected to the first reset signal line Vref1, and the second terminal of the first reset transistor T5 is electrically connected to the first node N1. The first reset transistor T5 is used to conduct under the control of the third Class A scan signal line Sa3 and the third Class B scan signal line Sc3, and transmit the first reset signal of the first reset signal line Vref1 to the first node N1 to reset the first node N1.

[0126] The first gate of the second reset transistor T6 is electrically connected to the fourth Class A scan signal line Sa4, the second gate of the second reset transistor T6 is electrically connected to the fourth Class B scan signal line Sc4, the first electrode of the second reset transistor T6 is electrically connected to the second reset signal line Vref2, and the second electrode of the second reset transistor T6 is electrically connected to the first electrode of the light-emitting element D. The second reset transistor T6 is used to conduct under the control of the fourth Class A scan signal line Sa4 and the fourth Class B scan signal line Sc4, transmitting the second reset signal of the second reset signal line Vref2 to the first electrode of the light-emitting element D to reset the first electrode of the light-emitting element D. Exemplarily, the second reset signal line Vref2 may reuse the first reset signal line Vref1, or it may not reuse the first reset signal line Vref1; this application embodiment does not limit this.

[0127] The pixel circuit 10 may also include a storage capacitor Cst, the first plate of which is electrically connected to the first node N1, and the second plate of which is electrically connected to the first power supply voltage signal line PVDD. The storage capacitor Cst is used to maintain the potential of the first node N1.

[0128] exist Figure 19 In the illustrated embodiment, the first dual-gate transistor ST1 may include a first light-emitting control transistor T21 and a second light-emitting control transistor T22. The connection method of the first light-emitting control transistor T21 and the second light-emitting control transistor T22 has been described above and will not be repeated here.

[0129] Thus, since the data writing transistor T3, threshold compensation transistor T4, first reset transistor T5, and / or second reset transistor T6 are the third dual-gate transistor ST3, the driving capability of these transistors is significantly increased. Furthermore, since the first light-emitting control transistor T21 and the second light-emitting control transistor T22 in the light-emitting branch are the first dual-gate transistor ST1, the driving current provided by the light-emitting branch can be increased, i.e., the driving current output by the pixel circuit can be increased, thereby increasing the driving capability of the pixel circuit.

[0130] See also Figure 19 According to some embodiments of this application, optionally, the first Class A scan signal line Sa1 and the second Class A scan signal line Sa2 can be multiplexed, and the first Class B scan signal line Sc1 and the second Class B scan signal line Sc2 can be multiplexed.

[0131] And / or, the third Class A scan signal line Sa3 and the fourth Class A scan signal line Sa4 can be multiplexed, and the third Class B scan signal line Sc3 and the fourth Class B scan signal line Sc4 can be multiplexed.

[0132] This reduces the number of traces in the display panel, which is beneficial for wiring design, reduces production costs, and enables narrow bezels.

[0133] Figure 20 This is a timing diagram showing the enable level of the first Class A scan signal and the enable level of the second control signal. Figure 20 The example is illustrated by having both the enable level of the first Class A scan signal and the enable level of the second control signal at a low level. Figure 20 As shown, according to some embodiments of this application, optionally, considering the leakage current characteristic of the transistor itself, the start edge of the enable level p2 of the second control signal K2 can be later than the end edge of the enable level p31 of the first class A scan signal K31 transmitted by the first class A scan signal line. That is, the second control signal K2 can be switched to the enable level only after the data signal is written, so as to better ensure the successful writing of the data signal and avoid the light-emitting element emitting light prematurely.

[0134] Based on the pixel circuit provided in the above embodiments, this application also provides a display panel. Please refer to the following embodiments.

[0135] Figure 21 This is a schematic diagram of a display panel provided in an embodiment of this application. Figure 21 As shown, the display panel 20 provided in this application embodiment may include the pixel circuit 10 as provided in the above embodiment.

[0136] In the display panel of this application embodiment, at least one transistor in the pixel circuit is a first dual-gate transistor. The first dual-gate transistor includes a first active layer and a first gate and a second gate located on opposite sides of the first active layer. The first gate of the first dual-gate transistor is used to receive a first control signal, and the second gate of the first dual-gate transistor is used to receive a second control signal. Both the first control signal and the second control signal are pulse signals, and the pulse width of the first control signal is different from that of the second control signal. On the one hand, since the first gate of the first dual-gate transistor is used to receive the first control signal, and the second gate of the first dual-gate transistor is used to receive the second control signal, and both the first control signal and the second control signal are pulse signals, the first dual-gate transistor can be turned on under the joint control of the first control signal and the second control signal, thereby increasing the conduction degree of the first dual-gate transistor, increasing the number of charge carriers flowing through the first dual-gate transistor, and thus increasing the driving capability of the first dual-gate transistor. On the other hand, since the pulse width of the first control signal is different from that of the second control signal, even if the first control signal and / or the second control signal are delayed, the overlap time of the enable level of the first control signal and the enable level of the second control signal can be guaranteed to be the same or similar to the pulse width of the enable level with the shortest pulse width among the enable levels of the first control signal and the second control signal. This is beneficial to ensure that the conduction time of the first dual-gate transistor of the pixel circuit at different positions is the same or similar, thereby improving the uniformity of the display.

[0137] Figure 22 This is another structural schematic diagram of the display panel provided in an embodiment of this application. For example... Figure 22 As shown, according to some embodiments of this application, optionally, the display panel 20 may include a first gate driving circuit 221, a second gate driving circuit 222, a first control signal line L1, and a second control signal line L2. The first gate driving circuit 221 can be electrically connected to the first gate g11 of the first dual-gate transistor ST1 in the pixel circuit 10 via the first control signal line L1, and the first gate driving circuit 221 is used to provide a first control signal. The second gate driving circuit 222 is electrically connected to the second gate g12 of the first dual-gate transistor ST1 in the pixel circuit 10 via the second control signal line L2, and the second gate driving circuit 222 is used to provide a second control signal.

[0138] Thus, the first gate driving circuit 221 and the second gate driving circuit 222 can respectively provide the first control signal and the second control signal to the first dual-gate transistor ST1 in the pixel circuit 10. The first dual-gate transistor can be turned on under the joint control of the first control signal and the second control signal, thereby increasing the number of charge carriers flowing through the first dual-gate transistor and increasing the driving capability of the first dual-gate transistor.

[0139] See also Figure 22According to some embodiments of this application, optionally, the display panel 20 may include a display area AA, which includes a plurality of pixel circuits 10. The first gate driving circuit 221 may include a plurality of cascaded first shift registers 221a, one of which can be electrically connected via a first control signal line L1 to the first gate g11 of a first dual-gate transistor ST1 in the plurality of pixel circuits 10 arranged along a first direction X. Exemplarily, the first direction X may be the row direction of the display panel. That is, one first shift register 221a can provide a first control signal to the first dual-gate transistor ST1 in the plurality of pixel circuits 10 arranged along the first direction X.

[0140] The second gate drive circuit 222 may include a plurality of cascaded second shift registers 222a. One second shift register 222a may be electrically connected to the second gate g12 of the first dual-gate transistor ST1 in the plurality of pixel circuits 10 arranged along the first direction X via the second control signal line L2. That is, one second shift register 222a may provide a second control signal to the first dual-gate transistor ST1 in the plurality of pixel circuits 10 arranged along the first direction X.

[0141] In some examples, the circuit structures of the first shift register 221a and the second shift register 222a can be the same, but the pulse width of the first trigger signal STV1 received by the first-stage first shift register 221a can be different from the pulse width of the second trigger signal STV2 received by the first-stage second shift register 222a, so that the pulse width of the first control signal output by the first shift register 221a is different from the pulse width of the second control signal output by the second shift register 222a.

[0142] See also Figure 22 According to some embodiments of this application, optionally, the display panel 20 may further include a first non-display area NA1 and a second non-display area NA2. Along the first direction X, the first non-display area NA1, the display area NA1, and the second non-display area NA2 may be arranged sequentially.

[0143] The first gate driving circuit 221 may be located in the first non-display area NA1 and / or the second non-display area NA2. The second gate driving circuit 222 may be located in the first non-display area NA1 and / or the second non-display area NA2. For example, in Figure 22 In the embodiment shown, both the first gate driving circuit 221 and the second gate driving circuit 222 can be located in the first non-display area NA1.

[0144] Figure 23 This is another schematic diagram of the structure of a display panel provided in an embodiment of this application. For example... Figure 23As shown, for example, the first gate driving circuit 221 can be located in the first non-display area NA1 and the second non-display area NA2, and the second gate driving circuit 222 can also be located in the first non-display area NA1 and the second non-display area NA2. In other embodiments, one of the first gate driving circuit 221 and the second gate driving circuit 222 can be located in the first non-display area NA1, and the other can be located in the second non-display area NA2. In other embodiments, one of the first gate driving circuit 221 and the second gate driving circuit 222 can be located in both the first non-display area NA1 and the second non-display area NA2, and the other can be located only in the first non-display area NA1 or the second non-display area NA2. This application does not limit this aspect.

[0145] Based on the display panel provided in the above embodiments, this application also provides a display device, including the display panel provided in this application. Please refer to... Figure 24 , Figure 24 This is a schematic diagram of a display device provided in an embodiment of this application. Figure 24 The provided display device 1000 includes the display panel 20 provided in any of the above embodiments of this application. Figure 24 The embodiments use a mobile phone as an example to describe the display device 1000. It is understood that the display device provided in the embodiments of this application can be other display devices with display functions, such as wearable products, computers, televisions, and in-vehicle display devices. This application does not impose specific limitations on these. The display device provided in the embodiments of this application has the beneficial effects of the display panel 20 provided in the embodiments of this application. For details, please refer to the specific descriptions of the display panel 20 in the above embodiments. These descriptions will not be repeated here.

[0146] It should be understood that the specific circuit structures and cross-sectional structures of the display panels provided in the accompanying drawings of the embodiments of this application are merely examples and are not intended to limit this application. Furthermore, the above embodiments provided in this application can be combined with each other unless there is contradiction.

[0147] It should be clarified that the various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. According to the embodiments described above, these embodiments do not exhaustively describe all details, nor do they limit this application to only the specific embodiments described. Obviously, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to make good use of this application and modifications based on it. This application is limited only by the claims and their full scope and equivalents.

[0148] Those skilled in the art will understand that the above embodiments are exemplary and not restrictive. Different technical features appearing in different embodiments can be combined to achieve beneficial effects. Based on a study of the drawings, specification, and claims, those skilled in the art should be able to understand and implement other variations of the disclosed embodiments. In the claims, the term "comprising" does not exclude other structures; the quantity refers to "one" but does not exclude multiple; the terms "first" and "second" are used to identify names and not to indicate any particular order. Any reference numerals in the claims should not be construed as limiting the scope of protection. The appearance of certain technical features in different dependent claims does not mean that these technical features cannot be combined to achieve beneficial effects.

Claims

1. A pixel circuit, characterized in that, The pixel circuit includes transistors, wherein at least one transistor in the pixel circuit is a first dual-gate transistor. The first dual-gate transistor includes a first active layer and a first gate and a second gate located on opposite sides of the first active layer. The first gate of the first dual-gate transistor is used to receive a first control signal, and the second gate of the first dual-gate transistor is used to receive a second control signal. Both the first control signal and the second control signal are pulse signals, and the pulse width of the first control signal is different from that of the second control signal; The start edge of the enable level of the second control signal is earlier than the start edge of the enable level of the first control signal, and the end edge of the enable level of the second control signal is later than the end edge of the enable level of the first control signal.

2. The pixel circuit according to claim 1, characterized in that, The interval between the start edge of the enable level of the second control signal and the start edge of the enable level of the first control signal is greater than or equal to 0.5 microseconds, and / or the interval between the end edge of the enable level of the second control signal and the end edge of the enable level of the first control signal is greater than or equal to 0.5 microseconds.

3. The pixel circuit according to claim 1, characterized in that, The pulse width of the enable level of the first control signal is the first time interval; The interval between the start edge of the enable level of the second control signal and the start edge of the enable level of the first control signal is less than the first time interval, and / or the interval between the end edge of the enable level of the second control signal and the end edge of the enable level of the first control signal is less than the first time interval.

4. The pixel circuit according to claim 1, characterized in that, The first dual-gate transistor is a P-type transistor, the enable level is low, the start edge is a falling edge, and the end edge is a rising edge; Alternatively, the first dual-gate transistor is an N-type transistor, the enable level is high, the start edge is a rising edge, and the end edge is a falling edge.

5. The pixel circuit according to claim 1, characterized in that, The display panel where the pixel circuit is located includes at least a substrate, a first metal layer, an active layer, and a second metal layer stacked together. The first metal layer is located between the substrate and the active layer, and the second metal layer is located on the side of the active layer away from the substrate. The first active layer is located on the active layer. The first gate of the first dual-gate transistor is located in the first metal layer, and the second gate of the first dual-gate transistor is located in the second metal layer; or, the first gate of the first dual-gate transistor is located in the second metal layer, and the second gate of the first dual-gate transistor is located in the first metal layer.

6. The pixel circuit according to claim 1, characterized in that, The pixel circuit includes a light-emitting branch connected to a light-emitting element, the light-emitting branch being used to provide a driving current to the light-emitting element; At least one transistor in the light-emitting branch is the first dual-gate transistor.

7. The pixel circuit according to claim 6, characterized in that, The light-emitting branch includes: A driving transistor, wherein the gate of the driving transistor is electrically connected to a first node, the first electrode of the driving transistor is electrically connected to a first power supply voltage signal line, and the second electrode of the driving transistor is electrically connected to the first electrode of the light-emitting element; A light-emitting control transistor, wherein the first gate of the light-emitting control transistor is electrically connected to a first light-emitting control signal line, and the second gate of the light-emitting control transistor is electrically connected to a second light-emitting control signal line. The first light-emitting control signal line is used to transmit the first control signal, and the second light-emitting control signal line is used to transmit the second control signal. The light-emitting control transistor is connected in series between the first electrode of the driving transistor and the first power supply voltage signal line and / or connected in series between the second electrode of the driving transistor and the first electrode of the light-emitting element. The first dual-gate transistor includes the light-emitting control transistor.

8. The pixel circuit according to claim 7, characterized in that, The light-emitting control transistor includes a first light-emitting control transistor and a second light-emitting control transistor. The first gate of the first light-emitting control transistor is electrically connected to the first light-emitting control signal line, the second gate of the first light-emitting control transistor is electrically connected to the second light-emitting control signal line, the first electrode of the first light-emitting control transistor is electrically connected to the first power supply voltage signal line, and the second electrode of the first light-emitting control transistor is electrically connected to the first electrode of the driving transistor. The first gate of the second light-emitting control transistor is electrically connected to the first light-emitting control signal line, the second gate of the second light-emitting control transistor is electrically connected to the second light-emitting control signal line, the first electrode of the second light-emitting control transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the first light-emitting control transistor is electrically connected to the first electrode of the light-emitting element.

9. The pixel circuit according to claim 7, characterized in that, At least one transistor in the pixel circuit is a second dual-gate transistor. The second dual-gate transistor includes a second active layer and a first gate and a second gate located on opposite sides of the second active layer. One of the first gate and the second gate of the second dual-gate transistor is used to receive a constant voltage signal.

10. The pixel circuit according to claim 9, characterized in that, The second dual-gate transistor includes a switching transistor, wherein the first gate of the switching transistor is electrically connected to a scan signal line, and the second gate of the switching transistor is electrically connected to a first constant voltage signal line, the first constant voltage signal line being used to transmit a first constant voltage signal; And / or, the second dual-gate transistor includes the driving transistor, the first gate of the driving transistor is electrically connected to the first node, the second gate of the driving transistor is electrically connected to a second constant voltage signal line, the second constant voltage signal line is used to transmit a second constant voltage signal, and the driving transistor is used to turn on or off under the control of the first node.

11. The pixel circuit according to claim 10, characterized in that, The scanning signal line includes a first scanning signal line, a second scanning signal line, a third scanning signal line, and / or a fourth scanning signal line. The first constant voltage signal line includes a first sub-constant voltage signal line, a second sub-constant voltage signal line, a third sub-constant voltage signal line, and / or a fourth sub-constant voltage signal line. The voltage values ​​of the constant voltage signals transmitted by the first sub-constant voltage signal line, the second sub-constant voltage signal line, the third sub-constant voltage signal line, and / or the fourth sub-constant voltage signal line are the same or different. The switching transistor includes a data writing transistor. The first gate of the data writing transistor is electrically connected to the first scan signal line, the second gate of the data writing transistor is electrically connected to the first sub-constant voltage signal line, the first terminal of the data writing transistor is electrically connected to the data signal line, and the second terminal of the data writing transistor is electrically connected to the first terminal of the driving transistor. The data writing transistor is used to write the data signal of the data signal line into the first terminal of the driving transistor under the control of the first scan signal line. And / or, the switching transistor includes a threshold compensation transistor, the first gate of the threshold compensation transistor being electrically connected to the second scan signal line, the second gate of the threshold compensation transistor being electrically connected to the second sub-constant voltage signal line, the first terminal of the threshold compensation transistor being electrically connected to the first terminal of the driving transistor, and the second terminal of the threshold compensation transistor being electrically connected to the second terminal of the driving transistor. The threshold compensation transistor is used to connect the first terminal of the driving transistor and the second terminal of the driving transistor under the control of the second scan signal line. And / or, the switching transistor includes a first reset transistor, the first gate of the first reset transistor being electrically connected to the third scan signal line, the second gate of the first reset transistor being electrically connected to the third sub-constant voltage signal line, the first terminal of the first reset transistor being electrically connected to the first reset signal line, and the second terminal of the first reset transistor being electrically connected to the first node. The first reset transistor is used to be turned on under the control of the third scan signal line to transmit a first reset signal from the first reset signal line to the first node to reset the first node. And / or, the switching transistor includes a second reset transistor, the first gate of the second reset transistor being electrically connected to the fourth scan signal line, the second gate of the second reset transistor being electrically connected to the fourth sub-constant voltage signal line, the first electrode of the second reset transistor being electrically connected to the second reset signal line, and the second electrode of the second reset transistor being electrically connected to the first electrode of the light-emitting element. The second reset transistor is used to be turned on under the control of the fourth scan signal line to transmit the second reset signal of the second reset signal line to the first electrode of the light-emitting element to reset the first electrode of the light-emitting element.

12. The pixel circuit according to claim 11, characterized in that, The start edge of the enable level of the second control signal is later than the end edge of the enable level of the first scan signal transmitted by the first scan signal line.

13. The pixel circuit according to claim 7, characterized in that, At least one transistor in the pixel circuit is a third dual-gate transistor. The third dual-gate transistor includes a third active layer and a first gate and a second gate located on opposite sides of the third active layer. The first gate of the third dual-gate transistor is electrically connected to a Class A scan signal line and is used to receive a Class A scan signal transmitted by the Class A scan signal line. The second gate of the third dual-gate transistor is electrically connected to a Class B scan signal line and is used to receive a Class B scan signal transmitted by the Class B scan signal line. Both the Class A scan signal and the Class B scan signal are pulse signals. Wherein, the pulse width of the enable level of the Class A scanning signal is less than the pulse width of the enable level of the first control signal; The start edge of the enable level of the Class A scan signal is earlier than the start edge of the enable level of the Class B scan signal, and / or the end edge of the enable level of the Class A scan signal is later than the end edge of the enable level of the Class B scan signal.

14. The pixel circuit according to claim 13, characterized in that, The interval between the start edge of the enable level of the Class A scan signal and the start edge of the enable level of the Class B scan signal is less than or equal to the interval between the start edge of the enable level of the second control signal and the start edge of the enable level of the first control signal. And / or, the interval between the end edge of the enable level of the Class A scan signal and the end edge of the enable level of the Class B scan signal is less than or equal to the interval between the end edge of the enable level of the second control signal and the end edge of the enable level of the first control signal.

15. The pixel circuit according to claim 13, characterized in that, The Class A scan signal lines include a first Class A scan signal line, a second Class A scan signal line, a third Class A scan signal line, and / or a fourth Class A scan signal line; the Class B scan signal lines include a first Class B scan signal line, a second Class B scan signal line, a third Class B scan signal line, and / or a fourth Class B scan signal line. The third dual-gate transistor includes a data writing transistor. The first gate of the data writing transistor is electrically connected to the first Class A scan signal line, the second gate of the data writing transistor is electrically connected to the first Class B scan signal line, the first terminal of the data writing transistor is electrically connected to the data signal line, and the second terminal of the data writing transistor is electrically connected to the first terminal of the driving transistor. The data writing transistor is used to conduct under the control of the first Class A scan signal line and the first Class B scan signal line to write the data signal of the data signal line into the first terminal of the driving transistor. And / or, the third dual-gate transistor includes a threshold compensation transistor, the first gate of the threshold compensation transistor being electrically connected to the second Class A scan signal line, the second gate of the threshold compensation transistor being electrically connected to the second Class B scan signal line, the first terminal of the threshold compensation transistor being electrically connected to the first terminal of the driving transistor, and the second terminal of the threshold compensation transistor being electrically connected to the second terminal of the driving transistor. The threshold compensation transistor is used to conduct under the control of the second Class A scan signal line and the second Class B scan signal line, connecting the first terminal of the driving transistor and the second terminal of the driving transistor. And / or, the third dual-gate transistor includes a first reset transistor, the first gate of the first reset transistor being electrically connected to the third Class A scan signal line, the second gate of the first reset transistor being electrically connected to the third Class B scan signal line, the first terminal of the first reset transistor being electrically connected to the first reset signal line, and the second terminal of the first reset transistor being electrically connected to the first node. The first reset transistor is used to conduct under the control of the third Class A scan signal line and the third Class B scan signal line, transmitting a first reset signal from the first reset signal line to the first node to reset the first node. And / or, the third dual-gate transistor includes a second reset transistor, the first gate of the second reset transistor being electrically connected to the fourth Class A scan signal line, the second gate of the second reset transistor being electrically connected to the fourth Class B scan signal line, the first electrode of the second reset transistor being electrically connected to the second reset signal line, and the second electrode of the second reset transistor being electrically connected to the first electrode of the light-emitting element. The second reset transistor is used to conduct under the control of the fourth Class A scan signal line and the fourth Class B scan signal line, transmitting the second reset signal of the second reset signal line to the first electrode of the light-emitting element to reset the first electrode of the light-emitting element.

16. The pixel circuit according to claim 15, characterized in that, The first Class A scan signal line is multiplexed with the second Class A scan signal line, and the first Class B scan signal line is multiplexed with the second Class B scan signal line; And / or, the third Class A scan signal line is multiplexed with the fourth Class A scan signal line, and the third Class B scan signal line is multiplexed with the fourth Class B scan signal line.

17. The pixel circuit according to claim 15, characterized in that, The start edge of the enable level of the second control signal is later than the end edge of the enable level of the first Class A scan signal transmitted by the first Class A scan signal line.

18. A display panel, characterized in that, Includes the pixel circuit as described in any one of claims 1 to 17.

19. The display panel according to claim 18, characterized in that, The display panel includes a first gate driving circuit, a second gate driving circuit, a first control signal line, and a second control signal line. The first gate driving circuit is electrically connected to the first gate of the first dual-gate transistor in the pixel circuit through the first control signal line. The first gate driving circuit is used to provide the first control signal. The second gate driving circuit is electrically connected to the second gate of the first dual-gate transistor in the pixel circuit through the second control signal line. The second gate driving circuit is used to provide the second control signal.

20. The display panel according to claim 19, characterized in that, The display panel includes a display area, which includes a plurality of pixel circuits. The first gate driving circuit includes a plurality of cascaded first shift registers. One of the first shift registers is electrically connected to the first gate of the first dual-gate transistor in the plurality of pixel circuits arranged along the first direction through the first control signal line. The second gate drive circuit includes a plurality of cascaded second shift registers, one of which is electrically connected to the second gate of the first dual-gate transistor in a plurality of pixel circuits arranged along the first direction via the second control signal line.

21. The display panel according to claim 20, characterized in that, The display panel further includes a first non-display area and a second non-display area, and the first non-display area, the display area and the second non-display area are arranged sequentially along the first direction; The first gate driving circuit is located in the first non-display area and / or the second non-display area, and the second gate driving circuit is located in the first non-display area and / or the second non-display area.

22. A display device, characterized in that, Includes a display panel as claimed in any one of claims 18 to 21.

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