A vertical launch EML chip

Abstract

The application discloses a vertical emission type EML chip, and belongs to the technical field of EML chips.The vertical emission type EML chip comprises a substrate and an emission column, an oxidation layer is arranged above the substrate, an EAM-MQW layer is arranged above the oxidation layer, a DFB-MQW layer is arranged above the EAM-MQW layer, a grating layer is arranged above the DFB-MQW layer, an InP cladding layer is arranged above the grating layer, an electrode layer is arranged above the InP cladding layer, an EA pin and an SOA plate are arranged on the electrode layer, a vertical cavity is arranged between the EAM-MQW layer and the electrode layer, the emission column is arranged on the inner side wall of the vertical cavity, and an LD laser is arranged on the emission column.The EAM-MQW layer and the DFB-MQW layer are arranged, the complexity of EML chip manufacturing is reduced, the EML chip manufacturing speed is improved, the EML wafer yield and stability are improved, the EML chip consistency is ensured, the processing is easier, the manufacturing cost is reduced, meanwhile, the vertical cavity and the EA pin are arranged, the EML chip can be flexibly adapted to internal and external storage, the chip applicability is improved, and the wavelength stability and uniformity are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of EML chip, and particularly relates to a vertical emission type EML chip. BACKGROUND

[0002] In cloud computing, mobile Internet, video and other new business and application modes, optical communication technology will be used. In optical communication, the optical module is a tool for converting optical and electrical signals, and is one of the key devices in optical communication equipment. The intensity of the optical signal input into the external optical fiber by the optical module directly affects the quality of the optical fiber communication. With the rapid development of 5G network, the optical module, which is in the core position of optical communication, has developed rapidly and various forms of optical modules have been produced.

[0003] With the rapid development of the data communication era, vertical cavity surface emitting laser chips are widely used in the field of optical communication, such as optical interconnection, optical sensing, optical storage, application scenarios such as data center short distance communication, 5G base station, HDMI ultra-high definition video transmission and the like, due to their excellent characteristics, such as small chip size, output circular spot, low operating threshold, high coupling efficiency, and easy integration.

[0004] The existing EML chip still adopts a horizontal edge-emitting laser, which makes the wavelength stability poor and uneven, and the traditional EML chip is complex in processing and needs to adapt to the heat dissipation of a high-power array, so that the preparation cost is relatively high. SUMMARY

[0005] The present application relates to the technical field of EML chip, and particularly relates to a vertical emission type EML chip.

[0006] In order to achieve the above-mentioned purpose, the technical scheme adopted by the present application is as follows:

[0007] A vertical emission type EML chip, comprising a substrate and an emission column, wherein an oxidation layer is arranged above the substrate, an EAM-MQW layer is arranged above the oxidation layer, a DFB-MQW layer is arranged above the EAM-MQW layer, a grating layer is arranged above the DFB-MQW layer, an InP cladding layer is arranged above the grating layer, an electrode layer is arranged above the InP cladding layer, an EA pin and an SOA plate are arranged on the electrode layer, a vertical cavity is arranged between the EAM-MQW layer and the electrode layer, the emission column is arranged on the inner wall of the vertical cavity, and an LD laser is arranged on the emission column.

[0008] Preferably, the substrate is the first layer of the chip, a negative electrode contact is arranged on the lower surface of the substrate, the substrate is a Si-doped GaAs bottom layer, and the doping concentration is 1.5e 18 cm-3 .

[0009] Preferably, the oxidation layer is the second layer of the chip, the oxidation layer material is Al2O3, which is oxidized by a wet oxidation process, wherein the material is Al x Ga 1-x As, wherein x is greater than or equal to 0.5, and the DFB-MQW layer and the EAM-MQW layer are stacked with each other.

[0010] Preferably, the EAM-MQW layer is the third layer of the chip, a high-reflection coating layer is arranged at the left end surface of the EML chip, and an anti-reflection coating layer is arranged at the right end surface of the EML chip; the leading end of the EAM-MQW layer is aligned to the high-reflection coating layer, and the trailing end of the EAM-MQW layer is aligned to the anti-reflection coating layer.

[0011] Preferably, the DFB-MQW layer is the fourth layer of the chip, and a first SiO layer and a second TiO layer are sequentially arranged in the direction away from the DFB-MQW layer.

[0012] Preferably, the grating layer is the fifth layer of the chip, the trailing end of the grating layer is aligned to the trailing end of the DFB-MQW layer, and the length ratio of the grating layer to the DFB-MQW layer is greater than 0.5.

[0013] Preferably, the InP cladding layer is the sixth layer of the chip, and the InP cladding layer is arranged above the grating layer.

[0014] Preferably, the electrode layer is the seventh layer of the chip, the electrode layer is etched and arranged on the upper surface of the InP cladding layer, the electrode layer includes a DFB positive electrode, an EAM positive electrode, and an EML negative electrode, an electrical isolation region is arranged between the DFB positive electrode and the EAM positive electrode, and the DFB positive electrode is located above the DFB-MQW layer.

[0015] Preferably, a positive electrode contact is arranged on the upper surface of the electrode layer, the EA pin is located on the same horizontal line as the LD laser, and positive electrode contacts are arranged on the LD laser, the EA pin, and the SOA board.

[0016] Compared with the prior art, the present application has the following beneficial effects:

[0017] 1. In the present application, by arranging the EAM-MQW layer and the DFB-MQW layer and stacking the DFB-MQW layer and the EAM-MQW layer with each other, the complexity of EML chip manufacturing is reduced, the manufacturing speed of the EML chip is improved, the yield and stability of the EML chip are improved, the consistency of the EML chip is ensured, the processing is easier, and the manufacturing cost is reduced.

[0018] 2、The scheme, through the vertical cavity and the setting of EA pin, can make the EML chip can be flexible to adapt to internal and external storage, improve the applicability of the chip, improve the stability and uniformity of the wavelength.

[0019] 3、The scheme, through the setting of LD laser and SOA plate, the LD laser can be reversibly reduced after the absorption spectrum of the external electric field is cancelled, and the SOA plate uses a lens to transform the light beam to achieve the effect of concentrated collection of optical signals. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 A structure diagram of a vertical emission type EML chip is provided for the present application.

[0021] Figure 2 A structure diagram of a laser in a vertical emission type EML chip is provided for the present application.

[0022] Figure 3 A structure diagram of an emission column in a vertical emission type EML chip is provided for the present application.

[0023] Figure 4 A structure diagram of a substrate in a vertical emission type EML chip is provided for the present application.

[0024] Figure 5 A structure diagram of a vertical emission type EML chip is provided for the present application. Figure 3 An enlarged view of A in the structure diagram.

[0025] Figure 6 An enlarged view of B in the structure diagram. Figure 2 An enlarged view of B in the structure diagram.

[0026] In the figure: 1, substrate; 2, emission column; 3, LD laser; 4, EA pin; 5, SOA plate; 6, oxidation layer; 7, EAM-MQW layer; 8, DFB-MQW layer; 9, grating layer; 10, InP cladding layer; 11, electrode layer. DETAILED DESCRIPTION

[0027] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0028] EMBODIMENT

[0029] Referring to Figures 1-6A vertical emission type EML chip, comprising a substrate 1 and an emission column 2, wherein an oxidation layer 6 is arranged above the substrate 1, an EAM-MQW layer 7 is arranged above the oxidation layer 6, a DFB-MQW layer 8 is arranged above the EAM-MQW layer 7, a grating layer 9 is arranged above the DFB-MQW layer 8, an InP cladding layer 10 is arranged above the grating layer 9, and an electrode layer 11 is arranged above the InP cladding layer 10;

[0030] Further, the substrate 1 is the first layer of the chip, a negative electrode contact is arranged on the lower surface of the substrate 1, the substrate is a Si-doped GaAs bottom layer, and the doping concentration is 1.5e 18 cm -3 The oxidation layer 6 is the second layer of the chip, the material of the oxidation layer 6 is Al2O3, which is formed by wet oxidation process of a prefabricated layer with Al x Ga 1-x As as the material, wherein x is greater than or equal to 0.97, the EAM-MQW layer 7 is the third layer of the chip, a high-reflection coating layer is arranged on the left end surface of the EML chip, and an anti-reflection coating layer is arranged on the right end surface of the EML chip; the first end of the EAM-MQW layer 7 is aligned to the high-reflection coating layer, and the last end of the EAM-MQW layer 7 is aligned to the anti-reflection coating layer; the DFB-MQW layer 8 is the fourth layer of the chip, the high-reflection coating layer is sequentially provided with a first SiO2 layer and a second TiO2 layer in the direction away from the DFB-MQW layer 8; the grating layer 9 is the fifth layer of the chip, the last end of the grating layer 9 is aligned to the last end of the DFB-MQW layer 8, and the length ratio of the grating layer 9 to the DFB-MQW layer 8 is 0.5; the DFB-MQW layer 8 and the EAM-MQW layer 7 are stacked with each other; the InP cladding layer 10 is the sixth layer of the chip, and the InP cladding layer 10 is deposited above the grating layer 9;

[0031] It should be noted that the oxidation layer 6 is deposited on the substrate 1, and a laser structure is made on the semiconductor substrate 1 by using etching technology; the etching is a technology of microfabrication on a wafer by taking a photoresist pattern formed by a photolithography technology as a mask; the etching is divided into dry etching and wet etching in terms of technology; a good current-limiting aperture and optical-limiting window can be formed by oxidizing an AI GaAs layer with a high aluminum component; the EAM-MQW layer 7 is formed on the oxidation layer 6, the DFB-MQW layer 8 is formed on the EAM-MQW layer 7, and the grating layer 9 is formed above the DFB-MQW layer 8; the InP cladding layer 10 is deposited above the grating layer 9 and the EAM-MQW layer 7, and then the InP cladding layer 10 is deposited above the grating layer 9; the electrode layer 11 is etched and arranged on the upper surface of the InP cladding layer 10; the DFB-MQW layer 8 and the EAM-MQW layer 7 are stacked with each other;

[0032] The further benefits of the above are: the mutual stacking of the DFB-MQW layer 8 and the EAM-MQW layer 7 reduces the complexity of the EML chip manufacturing, improves the EML manufacturing speed, improves the EML die yield and stability, facilitates the consistency of the EML chip, and thus makes the processing easier and reduces the manufacturing cost.

[0033] The EA pin 4 and the SOA plate 5 are arranged on the electrode layer 11, and the vertical cavity is arranged between the EAM-MQW layer 7 and the electrode layer 11, the emission column 2 is arranged on the inner wall of the vertical cavity, and the LD laser 3 is arranged on the emission column 2;

[0034] Further, the electrode layer 11 is the seventh layer of the chip, the electrode layer 11 is etched and arranged on the upper surface of the InP cladding layer 10, the electrode layer 11 includes a DFB positive electrode, an EAM positive electrode and an EML negative electrode, an electrical isolation region is arranged between the DFB positive electrode and the EAM positive electrode, the DFB positive electrode is located above the DFB-MQW layer 8, a positive electrode contact is arranged on the upper surface of the electrode layer 11, the EA pin 4 is located on the same horizontal line as the LD laser 3, and the LD laser 3, the EA pin 4 and the SOA plate 5 are all provided with a positive electrode contact;

[0035] It should be noted that the absorption edge of the LD laser 3 is steep, the thermal stability is good, and when a suitable reverse electric field is added, the exciton absorption peak will obviously move to the long-wave direction, and the absorption spectrum can be reversibly restored after the external electric field is removed. When the EA pin 4 on the electrode layer 11 is connected to a high level, the internal program memory is accessed first, and when the addressing range exceeds the maximum addressing space of the internal program memory, it automatically jumps to the external program memory. When the EA pin 4 is connected to a low level, it directly jumps to the external memory. The SOA plate 5 is a semiconductor optical amplifier, which uses a lens to transform the light beam to achieve the effect of concentrated collection of optical signals. The vertical cavity of the EML chip makes the chip lasing wavelength very stable, and improves the standard deviation of less than one cavity wavelength of 2nm;

[0036] The further benefits of the above are: in this way, the EML chip can flexibly adapt to internal and external storage, improve the applicability of the chip, and improve the stability and uniformity of the wavelength.

[0037] The application is prepared and used, and the oxide layer 6 is deposited on the substrate 1, the laser structure is made on the semiconductor substrate 1 by using etching technology, the etching is a technology of micro-processing on a wafer by taking a photoresist pattern formed by a photoetching technology as a mask, the etching is divided into dry etching and wet etching in a technical aspect, a good current limiting aperture and optical limiting window can be formed by oxidizing the AIGaAs layer with high aluminum component, the EAM-MQW layer 7 is formed on the oxide layer 6, the DFB-MQW layer 8 is formed on the EAM-MQW layer 7, the grating layer 9 is formed above the DFB-MQW layer 8; the InP cladding layer 10 is deposited above the grating layer 9 and the EAM-MQW layer 7, then the InP cladding layer 10 is deposited above the grating layer 9, the electrode layer 11 is etched and arranged on the upper surface of the InP cladding layer 10, the DFB-MQW layer 8 and the EAM-MQW layer 7 are stacked with each other, the complexity of EML chip manufacturing is reduced, the manufacturing speed of the EML is improved, the yield and stability of the EML wafer are improved, the consistency of the EML chip is facilitated, and then the processing is easier, and the manufacturing cost is reduced.

[0038] The absorption edge of the LD laser 3 is steep, the thermal stability is good, and when a suitable reverse electric field is added, the exciton absorption peak will obviously move to the long-wave direction, and the absorption spectrum can be reversibly restored after the external electric field is cancelled, when the EA pin 4 on the electrode layer 11 is connected to a high level, the internal program memory is accessed first, when the addressing range exceeds the maximum addressing space of the internal program memory, the external program memory is automatically jumped to, when the EA pin 4 is connected to a low level, the external memory is directly jumped to, the SOA board 5 is a semiconductor optical amplifier, the lens is used for light beam transformation to achieve the effect of concentrated collection of optical signals, the vertical cavity of the EML chip is arranged, so that the chip lasing wavelength is very stable, and the standard deviation of less than one cavity wavelength is improved to 2nm, so that the EML chip can flexibly adapt to internal and external storage, the applicability of the chip is improved, and the wavelength stability and uniformity are improved.

[0039] The above is only a preferred specific embodiment of the application, but the protection scope of the application is not limited to this, any person skilled in the art can make equivalent replacement or change according to the technical scheme and the inventive concept of the application within the technical range disclosed by the application, which should be covered in the protection scope of the application.

Claims

1. A vertical emitting EML chip comprising a substrate (1) and an emitting pillar (2), characterized in that, The substrate (1) is provided with an oxidation layer (6) above it, the EAM-MQW layer (7) is provided above the oxidation layer (6), the DFB-MQW layer (8) is provided above the EAM-MQW layer (7), the grating layer (9) is provided above the DFB-MQW layer (8), the InP cladding layer (10) is provided above the grating layer (9), the electrode layer (11) is provided above the InP cladding layer (10), the EA pin (4) and the SOA plate (5) are provided on the electrode layer (11), the vertical cavity is opened between the EAM-MQW layer (7) to the electrode layer (11), the emission column (2) is arranged on the inner side wall of the vertical cavity, and the LD laser (3) is arranged on the emission column (2). 2.The vertical emitting EML chip of claim 1, wherein, The substrate (1) is the first layer of the chip, the lower surface of the substrate (1) is provided with a negative electrode contact, the substrate (1) is a Si-doped GaAs bottom layer, and the doping concentration is 1.5e 18 cm -3 . 3.The vertical emitting EML chip of claim 1, wherein, The oxide layer (6) is the second layer of the chip, the oxide layer (6) material is Al2O3, which is formed by wet oxidation process of the material Al x Ga 1-x a preformed layer of As, where x > 0.

97. 4.The vertical emitting EML chip of claim 1, wherein, The EAM-MQW layer (7) is the third layer of the chip, the high-reflection coating layer is arranged on the left end face of the EML chip, and the anti-reflection film layer is arranged on the right end face of the EML chip; the leading end of the EAM-MQW layer (7) is aligned to the high-reflection coating layer, and the trailing end of the EAM-MQW layer (7) is aligned to the anti-reflection film layer.

5. The vertical transmitting EML chip of claim 4, wherein, The DFB-MQW layer (8) is the fourth layer of the chip, the high-reflection coating layer is sequentially provided with a first SiO2 layer and a second TiO2 layer in the direction away from the DFB-MQW layer (8). 6.The vertical transmitting EML chip of claim 1, wherein, The grating layer (9) is the fifth layer of the chip, the trailing end of the grating layer (9) is aligned to the trailing end of the DFB-MQW layer (8), the length ratio of the grating layer (9) to the DFB-MQW layer (8) is 0.5, and the DFB-MQW layer (8) and the EAM-MQW layer (7) are stacked with each other. 7.The vertical transmitting EML chip of claim 1, wherein, The InP cladding layer (10) is the sixth layer of the chip, and the InP cladding layer (10) is deposited above the grating layer (9). 8.The vertical emitting EML chip of claim 1, wherein, The electrode layer (11) is the seventh layer of the chip, the electrode layer (11) is etched on the upper surface of the InP cladding layer (10), the electrode layer (11) comprises a DFB positive electrode, an EAM positive electrode and an EML negative electrode, an electrical isolation region is arranged between the DFB positive electrode and the EAM positive electrode, and the DFB positive electrode is located above the DFB-MQW layer (8). 9.The vertical emitting EML chip of claim 1, wherein, The upper surface of the electrode layer (11) is provided with a positive electrode contact, the EA pin (4) is located on the same horizontal line as the LD laser (3), and the positive electrode contact is arranged on the LD laser (3), the EA pin (4) and the SOA plate (5).

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