Clock reset control apparatus and method for integrated circuit system, electronic device

Abstract

A clock reset control device and method of integrated circuit system, and an electronic device. The clock reset control device comprises a clock reset configuration circuit, a reset signal detection circuit, a reset control circuit and a clock control circuit. The clock reset configuration circuit is configured to configure a reset trigger signal in response to a reset configuration instruction; the reset signal detection circuit is configured to detect the reset trigger signal and provide the reset trigger signal to the reset control circuit; the reset control circuit is configured to send a clock control signal to the clock control circuit and send a reset signal or a reset release signal to the integrated circuit system in response to the reset trigger signal; and the clock control circuit is configured to control a clock signal provided to the integrated circuit system in response to the clock control signal. The clock reset control device can automatically realize the reset and reset release functions through the hardware circuit while avoiding the timing convergence problem of the reset signal caused by the high-frequency reset.

Description

[0001] This application claims priority to Chinese Patent Application No. 202210137956.0, filed on February 15, 2022, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Embodiments of this disclosure relate to a clock reset control device, a clock reset control method, and an electronic device for an integrated circuit system. Background Technology

[0003] Digital integrated circuits (ICs) are integrated circuits designed and operated based on digital logic (Boolean algebra) and used to process digital signals. According to the definition of an integrated circuit, a digital IC can also be defined as a digital logic circuit or system made by integrating components and interconnects onto the same semiconductor chip. Based on the number of gates or components contained in a digital IC, it can be classified into small-scale integration (SSI) circuits, medium-scale integration (MSI) circuits, large-scale integration (LSI) circuits, very-large-scale integration (VLSI) circuits, ultra-large-scale integration (ULSI) circuits, and giant-scale integration (GSI) circuits, etc. Summary of the Invention

[0004] At least one embodiment of this disclosure provides a clock reset control device for an integrated circuit system, comprising: a clock reset configuration circuit, a reset signal detection circuit, a reset control circuit, and a clock control circuit; the clock reset configuration circuit is configured to configure a reset trigger signal in response to a reset configuration command, the reset trigger signal including a first signal identifier for triggering a reset operation and a second signal identifier for triggering a de-reset operation; the reset signal detection circuit is configured to detect the reset trigger signal and provide the reset trigger signal to the reset control circuit; the reset control circuit is configured to, in response to the reset trigger signal, send a clock control signal to the clock control circuit and send a reset signal to the integrated circuit system to perform the reset operation on the integrated circuit system, or send a de-reset signal to perform the de-reset operation on the integrated circuit system; and the clock control circuit is configured to, in response to the clock control signal, control the clock signal provided to the integrated circuit system to correspond to the reset operation or the de-reset operation.

[0005] For example, in a clock reset control device provided in at least one embodiment of this disclosure, the clock reset configuration circuit includes a register whose value is set to record the reset trigger signal.

[0006] For example, in a clock reset control device provided in at least one embodiment of this disclosure, the frequency of the clock signal includes a first frequency and a second frequency, wherein the first frequency is greater than the second frequency. The control provided to the integrated circuit system includes: switching the frequency of the clock signal from the first frequency to the second frequency to transmit the clock signal to the integrated circuit system at the second frequency, or stopping the transmission of the clock signal to the integrated circuit system to perform a reset operation or a de-reset operation on the integrated circuit system; and switching the frequency of the clock signal from the second frequency to the first frequency, or switching from stopping the transmission of the clock signal to starting the transmission of the clock signal at the first frequency to transmit the clock signal to the integrated circuit system at the first frequency to drive the integrated circuit system to operate.

[0007] For example, in a clock reset control device provided in at least one embodiment of this disclosure, the clock control signal includes a first clock control sub-signal and a second clock control sub-signal, and the reset control circuit includes a first control sub-circuit. The first control sub-circuit is configured to send the first clock control sub-signal to the clock control circuit in response to a first trigger command, and to send the second clock control sub-signal to the clock control circuit in response to a second trigger command.

[0008] For example, in a clock reset control device provided in at least one embodiment of this disclosure, the clock control circuit includes a first multiplexing circuit, which is configured to switch the frequency of the clock signal from the first frequency to the second frequency in response to the first clock control sub-signal, and to switch the frequency of the clock signal from the second frequency to the first frequency in response to the second clock control sub-signal.

[0009] For example, in a clock reset control device provided in at least one embodiment of this disclosure, the clock control circuit includes a second multiplexing circuit, which is configured to stop transmitting the clock signal in response to the first clock control sub-signal, and to switch from stopping transmitting the clock signal to starting transmitting the clock signal of the first frequency in response to the second clock control sub-signal.

[0010] For example, in a clock reset control device provided in at least one embodiment of this disclosure, the clock control circuit includes a first multiplexer circuit, a second multiplexer circuit, a third multiplexer circuit, and a fourth multiplexer circuit. The first multiplexer circuit is configured to select and output a clock signal of the first frequency and a clock signal of the second frequency. The second multiplexer circuit is configured to select and output the clock signal of the first frequency or control an enable signal to stop or start transmitting the clock signal. The third multiplexer circuit is configured to select and output the output of the first multiplexer circuit or the output of the second multiplexer circuit. The fourth multiplexer circuit is configured to select and output the output of the third multiplexer circuit or the clock signal of the first frequency, thereby switching the frequency of the clock signal from the first frequency to the second frequency or stopping the transmission of the clock signal in response to the first clock control sub-signal, and switching the frequency of the clock signal from the second frequency to the first frequency or switching from stopping the transmission of the clock signal to starting the transmission of the clock signal of the first frequency in response to the second clock control sub-signal.

[0011] For example, in a clock reset control device provided in at least one embodiment of this disclosure, the reset control circuit further includes a second control sub-circuit, the second control sub-circuit being configured to output the reset signal to the integrated circuit system in response to a third trigger instruction to perform the reset operation on the integrated circuit system.

[0012] For example, in a clock reset control device provided in at least one embodiment of this disclosure, the second control sub-circuit is further configured to output the de-reset signal to the integrated circuit system in response to a fourth trigger instruction to perform the de-reset operation on the integrated circuit system.

[0013] For example, in the clock reset control device provided in at least one embodiment of this disclosure, the reset configuration circuit is further configured to configure the reset trigger signal as a second signal identifier for triggering the de-reset operation in response to the reset configuration command; the reset signal detection circuit is further configured to send the reset trigger signal to the third control sub-circuit when the second signal identifier of the reset trigger signal is detected; the second control sub-circuit is further configured to output the de-reset signal to the integrated circuit system in response to the second signal identifier of the reset trigger signal to perform the de-reset operation on the integrated circuit system.

[0014] For example, at least one embodiment of the clock reset control device provided in this disclosure further includes a timing circuit, which is configured to: start timing in response to detecting the first signal identifier of the reset trigger signal and send the first trigger command to the first control sub-circuit when the timing reaches a first threshold; start timing in response to detecting that the frequency of the clock signal changes from the first frequency to the second frequency or in response to detecting that the clock control circuit stops outputting the clock signal, and send the third trigger command to the second control sub-circuit when the timing reaches a second threshold; start timing in response to detecting that the reset operation of the integrated circuit system has been completed, and send the fourth trigger command to the second control sub-circuit when the timing reaches a third threshold; or start timing in response to detecting that the de-reset operation of the integrated circuit system has been completed, and send the second trigger command to the first control sub-circuit when the timing reaches a fourth threshold.

[0015] At least one embodiment of this disclosure also provides an electronic device, including a clock reset control device and an integrated circuit system provided in any embodiment of this disclosure, wherein the integrated circuit system is configured to perform the reset operation or the de-reset operation under the control of the clock reset control device.

[0016] At least one embodiment of this disclosure also provides a clock reset control method for an integrated circuit system, comprising: in response to a reset configuration command, configuring a reset trigger signal through a clock reset configuration circuit, the reset trigger signal including a first signal identifier for triggering a reset operation and a second signal identifier for triggering a de-reset operation; detecting the reset trigger signal through a reset signal detection circuit and providing the reset trigger signal to a reset control circuit; in response to the reset trigger signal, sending a clock control signal to a clock control circuit and a reset signal to the integrated circuit system through the reset control circuit to perform the reset operation on the integrated circuit system, or sending a de-reset signal to perform the de-reset operation on the integrated circuit system; and in response to the clock control signal, controlling a clock signal provided to the integrated circuit system through the clock control circuit to correspond to the reset operation or the de-reset operation.

[0017] For example, in a clock reset control method provided in at least one embodiment of this disclosure, the clock signal provided to the integrated circuit system is controlled by the clock control circuit, including: in response to the reset configuration command, configuring the reset trigger signal as a first signal identifier for triggering the reset operation by the clock reset configuration circuit; when the reset signal detection circuit detects the reset trigger signal, sending the reset trigger signal to a first control sub-circuit of the reset control circuit; in response to the first signal identifier of the reset trigger signal, timing is performed by a timing circuit, and when the timing reaches a first threshold, the first trigger command is sent to the first control sub-circuit; in response to the first trigger command, the first clock control sub-signal is sent to the clock control circuit by the first control sub-circuit; in response to the first clock control sub-signal, the frequency of the clock signal is switched from a first frequency to a second frequency by the clock control circuit to provide the clock signal of the second frequency to the integrated circuit system or to stop transmitting the clock signal, wherein the first frequency is greater than the second frequency.

[0018] For example, in a clock reset control method provided in at least one embodiment of this disclosure, the reset control circuit sends a reset signal to the integrated circuit system to perform the reset operation on the integrated circuit system, or sends a de-reset signal to perform the de-reset operation on the integrated circuit system, comprising: in response to detecting that the frequency of the clock signal has switched from the first frequency to the second frequency or in response to detecting that the clock control circuit has stopped outputting the clock signal, timing is performed by the timing circuit, and a third trigger command is sent to the second control sub-circuit of the reset control circuit when the timing reaches a second threshold; in response to the third trigger command, the second control sub-circuit outputs the reset signal to the integrated circuit system to perform the reset operation on the integrated circuit system; in response to detecting that the reset operation on the integrated circuit system has been completed, timing is performed by the timing circuit, and a fourth trigger command is sent to the second control sub-circuit when the timing reaches a third threshold; in response to the fourth trigger command, the second control sub-circuit outputs the de-reset signal to the integrated circuit system to perform the de-reset operation on the integrated circuit system.

[0019] For example, in a clock reset control method provided in at least one embodiment of this disclosure, the clock signal provided to the integrated circuit system is controlled by the clock control circuit, and the method further includes: in response to detecting that the integrated circuit system has completed the reset operation, timing is performed by the timing circuit, and a second trigger command is sent to the first control sub-circuit when the timing reaches a fourth threshold; in response to the second trigger command, the first control sub-circuit sends a second clock control sub-signal to the clock control circuit; in response to the second clock control sub-signal, the clock control circuit switches the frequency of the clock signal from the second frequency to the first frequency or switches from stopping the transmission of the clock signal to starting the transmission of the clock signal at the first frequency, so as to provide the clock signal at the first frequency to the integrated circuit system. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure, and are not intended to limit this disclosure.

[0021] Figure 1 A schematic diagram of an electronic device provided in at least one embodiment of the present disclosure is shown;

[0022] Figure 2 A timing diagram of a clock reset control device provided in at least one embodiment of this disclosure;

[0023] Figure 3 A schematic block diagram of a reset signal detection circuit provided for at least one embodiment of this disclosure;

[0024] Figure 4 A schematic diagram of the state machine of a clock reset control device provided in at least one embodiment of the present disclosure is shown;

[0025] Figure 5 This is a schematic diagram of the structure of a timing circuit provided in at least one embodiment of the present disclosure;

[0026] Figure 6A A schematic diagram of the structure of a clock control circuit provided in at least one embodiment of this disclosure;

[0027] Figure 6B A schematic diagram of another clock control circuit provided in at least one embodiment of this disclosure;

[0028] Figure 6C A schematic diagram of another clock control circuit provided in at least one embodiment of the present disclosure;

[0029] Figure 7A for Figure 6CThe diagram shown illustrates a clock control circuit using an on-chip reference clock.

[0030] Figure 7B for Figure 6C The diagram shown illustrates a clock control circuit using a clock-off mode.

[0031] Figure 8 A schematic diagram of the structure of a first control sub-circuit provided in at least one embodiment of this disclosure;

[0032] Figure 9 This is a schematic diagram of another timing circuit provided in at least one embodiment of the present disclosure;

[0033] Figure 10 A schematic diagram of the structure of a second control sub-circuit provided for at least one embodiment of this disclosure; and

[0034] Figure 11 A flowchart of a clock reset control method provided in at least one embodiment of the present disclosure is shown. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0036] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0037] In large-scale digital integrated circuit design, as chip area increases, transistor count increases, and operating frequency rises, timing for resetting integrated circuit systems becomes increasingly difficult to converge.

[0038] The inventors noted that, to address the issue of convergent reset timing, software programming is needed during chip startup and operation to control the reset and de-reset operations of the integrated circuit system when the clock signal frequency is low. This requires strictly configuring the clock reset register to switch the clock signal frequency and reset operation in a specific order, ensuring that the reset and de-reset operations are performed on the integrated circuit system when the clock signal is low, and then switching the clock signal frequency from low to the operating frequency (e.g., high) to drive the integrated circuit system to work normally. Therefore, if the software programming configuration order is unreasonable, it can easily lead to the chip malfunctioning.

[0039] Furthermore, this requirement for the clock reset sequence is not for functional purposes, but rather to address timing issues during backend reset implementation. Making software program these non-functional requirements significantly increases the complexity of software programming, making it unfriendly to software programmers.

[0040] At least one embodiment of this disclosure provides a clock reset control device for an integrated circuit system, including: a clock reset configuration circuit, a reset signal detection circuit, a reset control circuit, and a clock control circuit. The clock reset configuration circuit is configured to configure a reset trigger signal in response to a reset configuration command. The reset trigger signal includes a first signal identifier for triggering a reset operation and a second signal identifier for triggering a de-reset operation. The reset signal detection circuit is configured to detect the reset trigger signal and provide it to the reset control circuit. The reset control circuit is configured to, in response to the reset trigger signal, send a clock control signal to the clock control circuit and a reset signal to the integrated circuit system to perform a reset operation on the integrated circuit system, or send a de-reset signal to perform a de-reset operation on the integrated circuit system. The clock control circuit is configured to, in response to the clock control signal, control the clock signal provided to the integrated circuit system to correspond to the reset operation or the de-reset operation.

[0041] At least one embodiment of this disclosure also provides a clock reset control method and electronic device corresponding to the above-described clock reset control device.

[0042] The clock reset control device provided in at least one embodiment of this disclosure can automatically switch the clock signal frequency during reset or de-reset in the chip design through hardware circuitry (e.g., switch to a low-frequency clock or turn off the clock). After the reset is completed, it automatically switches to the operating frequency or turns on the clock. This avoids problems such as timing convergence of the reset signal caused by high-frequency reset, while automatically realizing the reset and de-reset functions through hardware circuitry. This reduces the involvement of software programming, simplifies the operation, reduces the complexity of software programming, and helps ensure the normal operation of the chip.

[0043] The embodiments and some examples of this disclosure will now be described in detail with reference to the accompanying drawings.

[0044] Figure 1 A schematic diagram of an electronic device provided in at least one embodiment of the present disclosure is shown. For example... Figure 1 As shown, the electronic device 1 includes a clock reset control device 100 and an integrated circuit system 200. For example, the integrated circuit system 200 is configured to perform a reset operation or a de-reset operation under the control of the clock reset control device 100.

[0045] For example, in some examples, the clock reset control device 100 can perform a reset operation on the integrated circuit system 200 under a low-frequency clock signal, thereby enabling the integrated circuit system to achieve a low-frequency reset and avoiding problems such as timing convergence of the reset signal caused by high-frequency reset.

[0046] For example, such as Figure 1 As shown, the clock reset control device 100 includes a clock reset configuration circuit 110, a reset signal detection circuit 120, a reset control circuit 130, and a clock control circuit 140.

[0047] For example, the clock reset configuration circuit 110 is configured to configure a reset trigger signal in response to a reset configuration command. For example, the reset trigger signal includes a first signal identifier for triggering a reset operation and a second signal identifier for triggering a de-reset operation. For example, in some examples, the first signal identifier can be set to 0, and the second signal identifier can be set to 1; for example, 0 indicates reset, and 1 indicates de-reset. Alternatively, in other examples, the first signal identifier can be set to 00 and / or 01, and the second signal identifier can be set to 10; for example, 00 indicates clock off, 01 indicates low frequency, and 10 indicates de-reset. Both clock off (00) and low frequency clock (01) can be used for the reset operation, as long as they can identify both the reset and de-reset operations. The embodiments of this disclosure do not limit this.

[0048] For example, the clock reset configuration circuit 110 includes a register whose value is set to record a reset trigger signal and can be read by other components, i.e., in response to software configuration for setting reset and de-reset operations. For example, in response to a reset configuration instruction requiring a reset operation, the register value can be set to 0 to indicate the start of a reset operation, and in response to a reset configuration instruction requiring a de-reset operation, it can be set to 1 to indicate the start of a de-reset operation; or the register value can be set to 00 or 01 to indicate the start of a reset operation, or set to 10 to indicate the start of a de-reset operation, depending on the actual situation, and the embodiments of this disclosure do not limit this.

[0049] For example, when the upper-level system needs to perform a reset or de-reset operation on the integrated circuit system, or when a problem occurs in the operation of the integrated circuit system and the data needs to be reset, a reset configuration command can be sent to the clock reset configuration circuit at any time through the upper-level software (such as application program or system program).

[0050] In the embodiments of this disclosure, the reset operation or de-reset operation is enabled only through software configuration as needed, without involving specific frequency switching or other operations, thereby greatly reducing the involvement and complexity of software and helping to ensure the normal operation of the integrated circuit system.

[0051] For example, the reset signal detection circuit 120 is configured to detect the reset trigger signal and provide the reset trigger signal to the reset control circuit 130.

[0052] For example, when the reset trigger signal is configured to 0, it indicates that a reset operation has begun. Taking the reset operation being active low as an example, when the reset signal detection circuit 120 detects the falling edge of the reset trigger signal, it indicates that the reset operation has been enabled, and sends this reset trigger signal, which indicates that the reset operation has been enabled, to the reset control circuit 130. That is, the reset signal detection circuit 120 is used to detect whether the software has configured a reset operation or a de-reset operation.

[0053] Figure 3 This is a schematic block diagram of a reset signal detection circuit provided for at least one embodiment of the present disclosure. For example, as... Figure 3 As shown, the reset signal detection circuit 120 includes a 1-step delay circuit, an inverter 11, an inverter 12, a two-input AND gate 01, and a two-input AND gate 02.

[0054] For example, such as Figure 3As shown, after the software configures the clock reset configuration circuit, it passes through a 2-step synchronization circuit. Then, the synchronized signal is delayed by one clock cycle (e.g., one clock cycle). Next, a two-input AND gate and an inverter are used to identify the rising and falling edges of the reset trigger signal, i.e., to identify reset release (i.e., de-reset operation) and reset activation (i.e., reset operation). Once reset activation and reset release are identified, the signal is transmitted to the subsequent reset control circuit 130 to trigger the state machine (e.g.,...). Figure 4 (As shown) Jump to the next page.

[0055] For example, the reset control circuit 130 is configured to, in response to a reset trigger signal, send a clock control signal clk_sel to the clock control circuit and a reset signal RST (e.g., low level) to the integrated circuit system to perform a reset operation on the integrated circuit system, or send a de-reset signal (e.g., high level) to perform a de-reset operation on the integrated circuit system.

[0056] Figure 2 This is a timing diagram of a clock reset control device provided for at least one embodiment of the present disclosure.

[0057] like Figure 2 As shown, the reset operation is first initiated by the reset trigger signal sent by the reset signal detection circuit 120. After waiting for a certain period of time (this time interval is configurable by the software and can be implemented through the timing circuit described later), the circuit automatically starts switching to a low-frequency clock (i.e., the first frequency clock signal) or turns off the clock (i.e., stops transmitting the clock signal to the integrated circuit system). After the frequency switching is completed and a certain period of time is waited (this time interval is configurable by the software and can be implemented through the timing circuit described later), the circuit automatically resets, i.e., sends a reset signal to the integrated circuit system to perform the reset operation. After the reset operation is completed, a certain period of time is waited (this time interval is configurable by the software and can be implemented through the timing circuit described later). During this period of time, the system can determine whether to switch (toggle) a certain number of clock cycles at a low frequency according to the pre-configured software. The circuit uses a period (e.g., 32 cycles) to transfer the state of the reset register to the non-reset register after switching between 32 cycles, thus ensuring that the non-reset register is in a stable, i.e., definite state. After waiting for this certain time interval, the circuit automatically enters the de-reset operation (of course, the de-reset operation can also be implemented through software configuration, i.e., triggered by the rising edge of the reset trigger signal; the embodiments of this disclosure do not limit this), i.e., automatically sends a de-reset signal to the integrated circuit system to perform the de-reset operation on the integrated circuit system. After the de-reset operation is completed, after waiting for a certain time (this time interval is configurable by software and can be implemented through the timing circuit described later), the circuit automatically switches to the clock of the operating frequency (i.e., the second frequency clock signal) or turns on the clock (i.e., transmits the clock signal of the operating frequency to the integrated circuit system).

[0058] It should be noted that in the above process, when the reset operation is implemented through software configuration, that is, when the reset operation is triggered by the rising edge of the reset trigger signal, after the reset control circuit triggers the reset operation by the rising edge of the reset trigger signal, the circuit will automatically reset after a certain period of time.

[0059] It should be noted that the time interval controlled by the timing circuit mentioned above (i.e., as...) Figure 5 The counting waterline shown can be configured, for example, in the firmware as a microcontroller unit (MCU). Of course, the timing circuit may not be set in the clock reset control device mentioned above, as long as the reset and de-reset operations of the circuit can be realized. The embodiments disclosed herein do not limit this.

[0060] For example, in some examples, the reset control circuit 130 includes a first control sub-circuit and a second control sub-circuit, the specific functions of which will be described in detail later. For example, it may also include more control sub-circuits; the embodiments of this disclosure do not limit this.

[0061] For example, clock control circuit 140 is configured to control the clock signal provided to the integrated circuit system in response to clock control signal clk_sel, corresponding to a reset operation or a de-reset operation.

[0062] For example, the frequency of a clock signal includes a first frequency and a second frequency. The first frequency is greater than the second frequency, meaning the first frequency indicates a high frequency, i.e., the operating frequency, while the second frequency indicates a low frequency, i.e., the clock frequency used when performing a reset or de-reset operation.

[0063] For example, controlling the clock signal provided to the integrated circuit system 200 includes: switching the frequency of the clock signal from a first frequency to a second frequency to transmit the clock signal to the integrated circuit system 200 at the second frequency, or stopping the transmission of the clock signal to the integrated circuit system 200 to perform a reset operation or a de-reset operation on the integrated circuit system 200; and switching the frequency of the clock signal from the second frequency to the first frequency, or switching from stopping the transmission of the clock signal to starting the transmission of the clock signal at the first frequency to transmit the clock signal to the integrated circuit system at the first frequency to drive the integrated circuit system to operate.

[0064] For example, such as Figure 1 As shown, a low-frequency clock (i.e., a second-frequency clock signal) and a working clock (i.e., a first-frequency clock signal) can be provided to the clock control circuit 140 through an on-chip phase-locked loop (PLL).

[0065] Therefore, the clock signal frequency can be switched automatically during the reset or de-reset process using the aforementioned hardware circuit (e.g., switching to a low-frequency clock or turning off the clock). After the reset is completed, the clock signal can be automatically switched back to the operating frequency or turned on. This avoids problems such as timing convergence of the reset signal caused by high-frequency reset, while automatically implementing the reset and de-reset functions through hardware circuit. This reduces the involvement of software programming, simplifies the operation, lowers the complexity of software programming, and helps ensure the normal operation of the integrated circuit system.

[0066] For example, in some examples, the clock reset control device 100 further includes a timing circuit (not shown) for configuring the clock reset configuration circuit 110 (e.g., through which the timing circuit is used to implement...). Figure 3 The timing of the time interval in the 2-step synchronization (or the interval in the reset control circuit) or the interval in the reset control circuit (e.g., Figure 2 The configurable time interval can be achieved through this timing circuit.

[0067] For example, the timing circuit is configured to: start timing in response to the detection of a first signal identifier of a reset trigger signal and send a first trigger command to a first control sub-circuit when the timing reaches a first threshold; start timing in response to the detection that the frequency of the clock signal has switched from a first frequency to a second frequency or in response to the detection that the clock control circuit has stopped outputting the clock signal, and send a third trigger command to a second control sub-circuit when the timing reaches a second threshold; start timing in response to the detection that a reset operation has been performed on the integrated circuit system, and send a fourth trigger command to the second control sub-circuit when the timing reaches a third threshold; or start timing in response to the detection that a reset operation has been performed on the integrated circuit system, and send a second trigger command to the first control sub-circuit when the timing reaches a fourth threshold.

[0068] Figure 4 This is a schematic diagram of the state machine of a reset control circuit provided in at least one embodiment of the present disclosure. The following is in conjunction with... Figure 1 and Figure 3 The process of automatically switching the frequency of the clock signal during reset or de-reset by the clock reset control device is described in detail.

[0069] The reset control circuit 130 receives the reset trigger signal from the reset signal detection circuit 120, performs appropriate state machine transitions, and then controls the frequency switching of the clock signal and the activation (i.e., reset operation) and deactivation (i.e., reset release operation) of the reset. For example, Figure 4 As shown, the state machine of this exemplary reset control circuit includes 9 states.

[0070] For example, after a chip (i.e., an integrated circuit system) is powered on and reset, its state machine is in an idle state.

[0071] After the software configuration is reset, when the reset control circuit 130 detects the falling edge of the reset trigger signal through the reset signal detection circuit 120, the trigger state machine jumps from the IDLE state to the first timing state CNT0.

[0072] Figure 5 This is a schematic diagram of a timing circuit provided in at least one embodiment of the present disclosure. For example, in the counting states CNT0, CNT1, CNT2, and CNT3, a timing circuit can be used... Figure 5 The timing circuit shown performs the timing. For example, as... Figure 5 As shown, the timing circuit includes a counter and a comparator to implement the timing function. It only jumps to the next state after counting to a software-configured threshold (e.g., a first threshold, a second threshold, a third threshold, or a fourth threshold). During the jump, the counter is automatically reset to zero. This counter can be, for example, an 8-bit counter, but it can also be a 32-bit or 64-bit counter, depending on the actual situation. The embodiments disclosed herein do not impose any limitations on this.

[0073] For example, when the CNT0 counter reaches a specified value (e.g., a first threshold) in the first timing state, it jumps to the CLK_DOWN state. That is, in this first timing state, the timing circuit starts timing in response to the detection of a first signal identifier of a reset trigger signal, and sends a first trigger command to the first control sub-circuit when the timing reaches the first threshold.

[0074] For example, the clock control signal includes a first clock control sub-signal CLK_DOWN and a second clock control sub-signal CLK_UP, and the reset control circuit 130 includes a first control sub-circuit (not shown in the figure).

[0075] For example, the first control sub-circuit is configured to send a first clock control sub-signal CLK_DOWN to the clock control circuit 140 in response to a received first trigger command, thereby jumping to... Figure 4 The CLK_DOWN state is shown.

[0076] Figure 6A A schematic diagram of the structure of a clock control circuit provided in at least one embodiment of this disclosure; Figure 6B A schematic diagram of another clock control circuit provided in at least one embodiment of this disclosure; Figure 6C This is a schematic diagram of another clock control circuit provided in at least one embodiment of the present disclosure. The following is in conjunction with... Figures 6A-6C A detailed description of the CLK_DOWN state in the state machine is provided.

[0077] For example, in some cases, when entering the CLK_DOWN state, the clock signal is switched to a second frequency, that is, switched to a low frequency, for example, 25 MHz.

[0078] For example, in this example, such as Figure 6A As shown, the clock control circuit 140 includes a first multiplexer circuit 141. For example, this first multiplexer circuit 141 is configured to change the frequency of the clock signal from a first frequency (operating frequency, i.e., the clock signal at the operating frequency) in response to a first clock control sub-signal CLK_DOWN. Figure 6A The operating clock shown is switched to the second frequency (25MHz on-chip reference clock).

[0079] For example, such as Figure 6A As shown, in the CLK_DOWN state, the first multiplexer circuit 141 switches the clock signal from the working clock to the on-chip reference clock, thereby switching the frequency of the clock signal from the first frequency to the second frequency.

[0080] For example, in other examples, the clock is turned off (i.e., the clock signal is stopped) when the CLK_DOWN state is entered.

[0081] For example, in this example, such as Figure 6B As shown, the clock control circuit 140 includes a second multiplexer circuit 142. For example, this second multiplexer circuit 142 is configured to stop transmitting a clock signal in response to a first clock control sub-signal CLK_DOWN.

[0082] For example, such as Figure 6B As shown, in the CLK_DOWN state, the first multiplexer circuit 141 switches the clock signal from a working clock to a stop transmitting clock signal. For example, the enable signal clk_en is controlled by a state machine, and remains 0 after entering the CLK_DOWN state (0 indicates that the clock signal is stopped), and remains 1 after entering the CLK_UP state (1 indicates that the transmission of the first frequency clock signal is enabled).

[0083] For example, in some other examples, once the CLK_DOWN state is entered, the clock signal can be switched to a second frequency, i.e., switched to a low frequency, for example, 25 MHz, or the clock can be turned off (i.e., the clock signal transmission can be stopped).

[0084] For example, in this example, such as Figure 6C As shown, the clock control circuit 140 includes a first multiplexer circuit 141, a second multiplexer circuit 142, a third multiplexer circuit 143, and a fourth multiplexer circuit 144.

[0085] For example, the first multiplexing circuit 141 is configured to select and output a clock signal of a first frequency (the clock signal of the operating frequency, i.e., Figure 6CThe second multiplexer circuit 142 is configured to select the first frequency clock signal (i.e., the operating clock shown) and the second frequency clock signal (e.g., an on-chip reference clock of 25MHz); the second multiplexer circuit 142 is configured to select the output clock signal of the first frequency (i.e., the operating clock shown). Figure 6C The working clock shown) or the enable signal that controls the stop or start of the transmission clock signal (i.e., after entering the CLK_DOWN state) will... Figure 6C The enable signal shown is set to 0); the third multiplexer circuit 143 is configured to select either the output of the first multiplexer circuit 141 or the output of the second multiplexer circuit 142; the fourth multiplexer circuit 144 is configured to select either the output of the third multiplexer circuit or a clock signal of the first frequency (i.e., ...). Figure 6C (as shown in the working clock), thereby in the CLK_DOWN state, in response to the first clock control sub-signal, switching the frequency of the clock signal from the first frequency to the second frequency or stopping the transmission of the clock signal.

[0086] For example, such as Figure 6C As shown, the enable signal clk_en is controlled by the state machine. After entering the CLK_DOWN state, it is always 0 (0 means stop transmitting the clock signal), and after entering the CLK_UP state, it is always 1 (1 means start transmitting the clock signal of the first frequency).

[0087] Figure 7A for Figure 6C The diagram shown illustrates a clock control circuit using an on-chip reference clock. Figure 7B for Figure 6C The diagram shown illustrates a clock control circuit using a clock-off mode. The choice between switching to a low-frequency clock or shutting down the clock depends on business requirements.

[0088] For example, in some examples, such as Figure 7A As shown, in the CLK_DOWN state, if the on-chip reference clock is used, then Figure 6C The clock control circuit shown can perform the following functions: Step S1: Switch the first multiplexer circuit 141 to the working clock; Step S2: Switch the third multiplexer circuit 143 to the output of the first multiplexer circuit 141; Step S3: Switch the fourth multiplexer circuit 144 to the output of the third multiplexer circuit 143; Step S4: Switch the first multiplexer circuit 141 to the on-chip reference clock, thereby enabling the clock signal frequency to be switched from the first frequency to the second frequency.

[0089] For example, such as Figure 7A As shown, sel0 is the selection signal of the first multiplexer circuit 141, sel1 is the selection signal of the third multiplexer circuit 143, and sel2 is the selection signal of the fourth multiplexer circuit 144.

[0090] For example, in some examples, such as Figure 7B As shown, in the CLK_DOWN state, if the clock is turned off, then Figure 6C The clock control circuit shown can perform the following functions: Step S1: Pull the enable signal clk_en high to make it valid; Step S2: Switch the third multiplexer circuit 143 to the output of the second multiplexer circuit 142; Step S3: Switch the fourth multiplexer circuit 144 to the output of the third multiplexer circuit 143; Step S4: Pull the enable signal clk_en low to perform clock gating to turn off the clock, thereby turning off the clock.

[0091] For example, such as Figure 7B As shown, sel1 is the selection signal of the third multiplexer circuit 143, and sel2 is the selection signal of the fourth multiplexer circuit 144.

[0092] For example, as shown in the figure Figures 6A-6C As shown, a first multiplexer circuit 141 can be used to switch the on-chip reference clock and the operating clock, and a second multiplexer circuit 142 can be used to switch the enable signal and the operating clock. The on-chip reference clock is the reference clock of the on-chip phase-locked loop (PLL).

[0093] For example, when the frequency of the clock signal switches from a first frequency to a second frequency (e.g., a 25MHz on-chip reference clock) or the clock is turned off, the timing circuit responds to detecting that the clock signal frequency has switched from the first frequency to the second frequency or responds to detecting that the clock control circuit has stopped outputting the clock signal (i.e., the clock is turned off) by, for example... Figure 3 The timing circuit shown performs timing (i.e., enters the second timing state CNT1), and sends a third trigger command to the second control sub-circuit of the reset control circuit 130 when the timing reaches the second threshold.

[0094] For example, after the CLK_DOWN state is processed, it automatically jumps to the second timing state CNT1.

[0095] For example, after entering the second timing state CNT1, it starts counting from 0, stops counting when it reaches the software-specified waterline (i.e., the second threshold), and then sends a third trigger instruction to trigger the state machine to jump to the next state (reset state), while the counter is automatically cleared to zero.

[0096] For example, the next state after the second timing state CNT1 is the reset state, the main function of which is to pull the reset signal low and transmit it to the integrated circuit system 200, thereby making the reset effective.

[0097] For example, the second control sub-circuit of the reset control circuit 130 is configured to output a reset signal to the integrated circuit system 200 in response to a third trigger command to perform a reset operation on the integrated circuit system. That is, entering Figure 4 The reset state is shown.

[0098] Figure 8 This is a schematic diagram of the structure of a first control sub-circuit provided in at least one embodiment of the present disclosure.

[0099] like Figure 8 As shown, after the state machine transitions to the reset state, the state machine indicator signal initially selects path 1'b0 to send to the subsequent reset synchronization circuit to output a reset signal. Only after the state machine transitions to the de-reset state does it select path 1'b1 to send to the subsequent reset synchronization circuit to output a de-reset signal.

[0100] The reset synchronization circuit, for example, uses a two-stage D flip-flop for synchronization. The signal after the fifth multiplexer circuit (MUX) is connected to the reset terminal of the two-stage D flip-flop, and the D terminal of the first-stage flip-flop has a fixed input of 1'b1. In the embodiments of this disclosure, a low-level active reset is implemented, while asynchronous reset and synchronous de-reset are also supported. It should be noted that the detailed structure of the two-stage D flip-flop is not shown in the figure. For specific structure and working principle, please refer to the descriptions in this field, which will not be repeated here.

[0101] For example, after the integrated circuit system 200 completes the reset operation, the timing circuit starts timing in response to detecting that the integrated circuit system 200 has completed the reset operation, and sends a fourth trigger command to the second control sub-circuit when the timing reaches the third threshold.

[0102] That is, after the reset state process is completed, it will automatically jump to the third timer CNT2.

[0103] For example, after entering the third timing state CNT2, the counter starts counting from 0, stops counting when it reaches the software-specified threshold (e.g., the third threshold), and then sends a fourth trigger instruction to trigger the state machine to jump to the next state (i.e., the reset state), while the counter is automatically cleared to zero.

[0104] For example, the timing circuit used in the third timing state CNT2 can be the same as the timing circuit used in the first timing state CNT1 and the second timing state CNT2; for example, both can use... Figure 5 The timing circuit shown can also be different, for example, using... Figure 9 The timing circuit shown.

[0105] Figure 9 This is a schematic diagram of another timing circuit provided in at least one embodiment of the present disclosure.

[0106] For example, such as Figure 9 As shown, in the third timing state, CNT2 also supports automatically switching the clock from 1 to 256 beats in clock gating mode.

[0107] like Figure 9 As shown, by determining whether the state machine is in the third timing state CNT2 and whether clock gating mode is used, if both conditions are met, the 8-bit counter is triggered to start counting from 0 and stops after counting to the software-configured counting level. During the counting process, the enable signal clk_en is turned on, thereby obtaining the clock switching of the number of software-configured counting levels.

[0108] For example, the next state after the third timing state CNT2 is the reset state, which is triggered by the fourth trigger instruction to pull the reset signal high (i.e., the reset signal) and input it to the integrated circuit system, thereby releasing the reset.

[0109] For example, in one example, the second control sub-circuit is also configured to output a reset signal to the integrated circuit system 200 in response to the aforementioned fourth trigger instruction to perform a reset operation on the integrated circuit system 200. That is, the reset is performed automatically through this hardware circuit, thereby further reducing software involvement and lowering the complexity of software programming.

[0110] For example, the second control sub-circuit in this example can be... Figure 8 The circuit shown is implemented.

[0111] For example, in another example, the reset can also be implemented through software configuration. For example, in this example, the reset configuration circuit 110 is further configured to configure the reset trigger signal as a second signal identifier 1 or 10 for triggering the reset operation in response to a reset configuration command; for example, the reset signal detection circuit 120 is further configured to send the reset trigger signal to the third control sub-circuit when the second signal identifier 1 or 10 of the reset trigger signal is detected (e.g., a rising edge of the reset trigger signal is detected); the second control sub-circuit is further configured to output a reset signal to the integrated circuit system in response to the second signal identifier (e.g., a rising edge) of the reset trigger signal to perform a reset operation on the integrated circuit system.

[0112] Figure 10 This is a schematic diagram of the structure of a second control sub-circuit provided for at least one embodiment of the present disclosure. For example, such as... Figure 10 As shown, the second control sub-circuit can be configured via software to achieve reset.

[0113] like Figure 10 As shown, after the state machine jumps to the de-reset state, the state machine indicator signal selects the 1'b1 path, and then outputs the de-reset signal to the integrated circuit system 200 after being processed by the reset synchronization circuit.

[0114] This completes the reset and release of the integrated circuit system 200, i.e., the reset is completed.

[0115] In addition, Figure 10 The hardware circuit shown supports software-configurable reset mode. Whether to use automatic reset mode or software-configurable reset mode can be selected as a static parameter, which can be configured in the software. Figure 10 The release mode (deassert_mode) is a static parameter. When it is equal to 0, it means that the software configuration de-reset method is used, and when it is equal to 1, it means that the hardware automatic de-reset method is used.

[0116] It should be noted that the first control sub-circuit can also be adopted. Figure 10 The circuit structure shown can be implemented as long as it achieves the reset function; the embodiments disclosed herein are not limited in this regard. For example, when through... Figure 10 The circuit shown implements the function of the first control sub-circuit as follows: after the state machine jumps to the reset state, the state machine indicator signal selects the 1'b0 path, and then outputs a de-reset signal to the integrated circuit system 200 after being processed by the reset synchronization circuit.

[0117] For example, after the integrated circuit system completes the reset operation, the timing circuit (e.g.) Figure 5 The timing circuit shown responds to the detection that the integrated circuit system 200 has completed the reset operation and starts timing. When the timing reaches the fourth threshold, it sends a second trigger command to the first control sub-circuit. The first control sub-circuit responds to the second trigger command and sends a second clock control sub-signal to the clock control circuit.

[0118] For example, once the reset state process is complete, it automatically jumps to the fourth timing state CNT3.

[0119] For example, after entering the fourth timing state CNT3, the counter starts counting from 0, stops counting after counting to the software-specified threshold (e.g., the fourth threshold), and then sends a second trigger instruction value to reset the control circuit 130 to trigger the state machine to jump to the next state (i.e., the CLK_UP state), while the counter is automatically cleared.

[0120] For example, after the fourth timing state CNT3 ends, it enters the CLK_UP state, whose main function is to switch the clock to the working clock. Whether the on-chip reference clock is used or the clock gating method is used, it is only necessary to switch the fourth multiplexer circuit 144 to the working clock channel to drive the integrated circuit system 200 to operate normally.

[0121] For example, when using Figure 6AWhen the circuit shown is implemented, the first multiplexer circuit 141, in the CLK_UP state, switches the frequency of the clock signal from the second frequency (e.g., 25MHz on-chip reference clock) to the first frequency (operating clock) in response to the second clock control sub-signal CLK_UP, that is, outputs the operating clock to the integrated circuit system 200.

[0122] For example, when using Figure 6B When the circuit shown is implemented, the second multiplexer circuit 142, in the CLK_UP state, switches from stopping the transmission of the clock signal to starting the transmission of the clock signal (working clock) at the first frequency in response to the second clock control sub-signal CLK_UP.

[0123] For example, when using Figure 6C When the circuit shown is implemented, the second multiplexing circuit 142, in the CLK_UP state, responds to the second clock control sub-signal by switching the frequency of the clock signal from the second frequency to the first frequency or from stopping the transmission of the clock signal to starting the transmission of the clock signal at the first frequency.

[0124] After the CLK_UP state ends, the process enters the IDLE state, and the entire process is complete.

[0125] At this point, the clock reset control device implemented by the above hardware automatically completes the reset or de-reset operation of the integrated circuit system under low frequency or clock off conditions, and then switches back to the working clock to allow the integrated circuit system to work normally.

[0126] It should be noted that the decision Figure 2 The values ​​of the first threshold, second threshold, third threshold, and fourth threshold of the time interval shown can be set to be the same (i.e., the time intervals of each stage are the same) or different (i.e., the time intervals of each stage are different), depending on the specific circumstances. The embodiments of this disclosure do not limit this.

[0127] It should be noted that the components and structure of the clock reset control device are exemplary and not limiting. As needed, the clock reset control device may also include other components and structures, and the embodiments disclosed herein are not limited in this regard.

[0128] Figure 11 A flowchart of a clock reset control method provided in at least one embodiment of the present disclosure is shown.

[0129] like Figure 11 As shown, the method may include steps S110 to S140.

[0130] Step S110: In response to the reset configuration command, configure the reset trigger signal through the clock reset configuration circuit.

[0131] Step S120: Detect the reset trigger signal through the reset signal detection circuit and provide the reset trigger signal to the reset control circuit.

[0132] Step S130: In response to the reset trigger signal, the reset control circuit sends a clock control signal to the clock control circuit and a reset signal to the integrated circuit system to perform a reset operation on the integrated circuit system, or sends a de-reset signal to perform a de-reset operation on the integrated circuit system.

[0133] Step S140: In response to the clock control signal, the clock signal provided to the integrated circuit system is controlled by the clock control circuit to correspond to the reset operation or the de-reset operation.

[0134] For step S110, for example, the reset trigger signal includes a first signal identifier for triggering the reset operation and a second signal identifier for triggering the de-reset operation. For details, please refer to the description of the clock reset configuration circuit in the above-described clock reset control device; it will not be repeated here.

[0135] For step S120, please refer to the description of the reset signal detection circuit in the above reset control device, which will not be repeated here.

[0136] For example, in at least one example, step S140 may include: in response to a reset configuration instruction, configuring a reset trigger signal as a first signal identifier for triggering a reset operation via a clock reset configuration circuit; sending the reset trigger signal to a first control sub-circuit of a reset control circuit when the reset signal detection circuit detects the reset trigger signal; in response to the first signal identifier of the reset trigger signal, timing is performed via a timing circuit, and the first trigger instruction is sent to the first control sub-circuit when the timing reaches a first threshold; in response to the first trigger instruction, sending the first clock control sub-signal to a clock control circuit via the first control sub-circuit; and in response to the first clock control sub-signal, switching the frequency of the clock signal from a first frequency to a second frequency via the clock control circuit to provide the clock signal of the second frequency to the integrated circuit system or to stop transmitting the clock signal, wherein the first frequency is greater than the second frequency.

[0137] For example, in at least one example, step S130 may include: in response to detecting that the frequency of the clock signal has switched from a first frequency to a second frequency or in response to detecting that the clock control circuit has stopped outputting the clock signal, timing is performed by a timing circuit, and a third trigger command is sent to the second control sub-circuit of the reset control circuit when the timing reaches a second threshold; in response to the third trigger command, a reset signal is output to the integrated circuit system through the second control sub-circuit to perform a reset operation on the integrated circuit system; in response to detecting that the reset operation on the integrated circuit system has been completed, timing is performed by a timing circuit, and a fourth trigger command is sent to the second control sub-circuit when the timing reaches a third threshold; in response to the fourth trigger command, a de-reset signal is output to the integrated circuit system through the second control sub-circuit to perform a de-reset operation on the integrated circuit system.

[0138] For example, in at least one example, step S140 may further include: in response to detecting that the integrated circuit system has completed the reset operation, timing is performed by a timing circuit, and a second trigger command is sent to the first control sub-circuit when the timing reaches a fourth threshold; in response to the second trigger command, the first control sub-circuit sends a second clock control sub-signal to the clock control circuit; in response to the second clock control sub-signal, the clock control circuit switches the frequency of the clock signal from a second frequency to a first frequency or switches from stopping the transmission of the clock signal to starting the transmission of the clock signal at the first frequency, so as to provide the clock signal at the first frequency to the integrated circuit system.

[0139] For detailed information on steps S130 and S140, please refer to the specific descriptions of the reset control circuit and clock control circuit in the clock reset control device documentation. They will not be repeated here.

[0140] It should be noted that the execution order of the various steps of the clock reset control method in the various embodiments of this disclosure is not limited. Although the execution process of each step has been described in a specific order above, this does not constitute a limitation on the embodiments of this disclosure. The various steps in this clock reset control method can be executed serially or in parallel, which can be determined according to actual needs. The clock reset control method may also include more or fewer steps, and the embodiments of this disclosure do not limit this.

[0141] The clock reset control method provided in at least one embodiment of this disclosure can automatically switch the clock signal frequency during reset or de-reset in chip design through hardware circuitry (e.g., switch to a low-frequency clock or turn off the clock). After the reset is completed, it automatically switches to the operating frequency or turns on the clock. This avoids problems such as timing convergence of the reset signal caused by high-frequency reset, while automatically implementing the reset and de-reset functions through hardware circuitry. This reduces the involvement of software programming, simplifies the operation, reduces the complexity of software programming, and helps ensure the normal operation of the chip.

[0142] Regarding the aforementioned publicly disclosed information, the following points need to be clarified:

[0143] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0144] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0145] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims.

Claims

1. A clock reset control device for an integrated circuit system, comprising: The circuit includes a clock reset configuration circuit, a reset signal detection circuit, a reset control circuit, and a clock control circuit. The clock reset configuration circuit is configured to configure a reset trigger signal in response to a reset configuration command, wherein the reset trigger signal includes a first signal identifier for triggering a reset operation and a second signal identifier for triggering a de-reset operation. The reset signal detection circuit is configured to detect the reset trigger signal and provide the reset trigger signal to the reset control circuit; The reset control circuit is configured to, in response to the reset trigger signal, send a clock control signal to the clock control circuit and a reset signal to the integrated circuit system to perform the reset operation on the integrated circuit system, or send a de-reset signal to perform the de-reset operation on the integrated circuit system; and The clock control circuit is configured to control the clock signal provided to the integrated circuit system in response to the clock control signal, corresponding to the reset operation or the de-reset operation.

2. The clock reset control device according to claim 1, wherein, The clock reset configuration circuit includes a register. The value of the register is set to record the reset trigger signal.

3. The clock reset control device according to claim 1, wherein, The clock signal has a first frequency and a second frequency, wherein the first frequency is greater than the second frequency. The control provides the clock signal to the integrated circuit system, including: Switching the frequency of the clock signal from the first frequency to the second frequency to transmit the clock signal to the integrated circuit system at the second frequency, or stopping the transmission of the clock signal to the integrated circuit system to perform a reset operation or a de-reset operation on the integrated circuit system; and The frequency of the clock signal is switched from the second frequency to the first frequency, or the transmission of the clock signal is switched from stopping to starting the transmission of the clock signal at the first frequency, so as to transmit the clock signal to the integrated circuit system at the first frequency to drive the integrated circuit system to operate.

4. The clock reset control device according to claim 3, wherein, The clock control signal includes a first clock control sub-signal and a second clock control sub-signal, and the reset control circuit includes a first control sub-circuit, wherein... The first control sub-circuit is configured to send the first clock control sub-signal to the clock control circuit in response to a first trigger command, and to send the second clock control sub-signal to the clock control circuit in response to a second trigger command.

5. The clock reset control device according to claim 4, wherein, The clock control circuit includes a first multiplexer circuit. The first multiplexing circuit is configured to switch the frequency of the clock signal from the first frequency to the second frequency in response to the first clock control sub-signal, and to switch the frequency of the clock signal from the second frequency to the first frequency in response to the second clock control sub-signal.

6. The clock reset control device according to claim 4, wherein, The clock control circuit includes a second multiplexer circuit. The second multiplexing circuit is configured to stop transmitting the clock signal in response to the first clock control sub-signal, and to switch from stopping transmitting the clock signal to starting transmitting the clock signal of the first frequency in response to the second clock control sub-signal.

7. The clock reset control device according to claim 4, wherein, The clock control circuit includes a first multiplexer circuit, a second multiplexer circuit, a third multiplexer circuit, and a fourth multiplexer circuit. The first multiplexing circuit is configured to select and output a clock signal of the first frequency and a clock signal of the second frequency; The second multiplexing circuit is configured to select either the output of a clock signal at the first frequency or to control the stop or start of the transmission of the clock signal. The third multiplexing circuit is configured to select the output of the first multiplexing circuit or the output of the second multiplexing circuit; The fourth multiplexing circuit is configured to select the output of the third multiplexing circuit or the clock signal of the first frequency, thereby switching the frequency of the clock signal from the first frequency to the second frequency or stopping the transmission of the clock signal in response to the first clock control sub-signal, and switching the frequency of the clock signal from the second frequency to the first frequency or switching from stopping the transmission of the clock signal to starting the transmission of the clock signal of the first frequency in response to the second clock control sub-signal.

8. The clock reset control device according to claim 4, wherein, The reset control circuit also includes a second control sub-circuit. The second control sub-circuit is configured to output the reset signal to the integrated circuit system in response to a third trigger command to perform the reset operation on the integrated circuit system.

9. The clock reset control device according to claim 8, wherein, The second control sub-circuit is further configured to output the reset signal to the integrated circuit system in response to a fourth trigger instruction to perform the reset operation on the integrated circuit system.

10. The clock reset control device according to claim 8, wherein, The clock reset configuration circuit is further configured to, in response to the reset configuration command, configure the reset trigger signal as a second signal identifier for triggering the de-reset operation; The reset signal detection circuit is further configured to send the reset trigger signal to the second control sub-circuit when the second signal identifier of the reset trigger signal is detected. The second control sub-circuit is further configured to output the de-reset signal to the integrated circuit system in response to a second signal identifier of the reset trigger signal to perform the de-reset operation on the integrated circuit system.

11. The clock reset control device according to claim 9 further includes a timing circuit, wherein, The timing circuit is configured as follows: In response to the detection of the first signal identifier of the reset trigger signal, timing is started, and when the timing reaches a first threshold, the first trigger command is sent to the first control sub-circuit. The timing begins in response to detecting a switch in the frequency of the clock signal from the first frequency to the second frequency, or in response to detecting that the clock control circuit stops outputting the clock signal, and the third trigger command is sent to the second control sub-circuit when the timing reaches a second threshold. In response to detecting that the reset operation on the integrated circuit system has been completed, a timer is started, and when the timer reaches a third threshold, the fourth trigger command is sent to the second control sub-circuit, or In response to the detection that the reset operation has been performed on the integrated circuit system, a timing is started, and when the timing reaches a fourth threshold, a second trigger command is sent to the first control sub-circuit.

12. An electronic device comprising the clock reset control device and integrated circuit system as described in any one of claims 1-11, in, The integrated circuit system is configured to perform the reset operation or the de-reset operation under the control of the clock reset control device.

13. A clock reset control method for an integrated circuit system, comprising: In response to a reset configuration command, a reset trigger signal is configured via a clock reset configuration circuit, wherein the reset trigger signal includes a first signal identifier for triggering a reset operation and a second signal identifier for triggering a de-reset operation; The reset trigger signal is detected by the reset signal detection circuit and provided to the reset control circuit. In response to the reset trigger signal, the reset control circuit sends a clock control signal to the clock control circuit and a reset signal to the integrated circuit system to perform the reset operation on the integrated circuit system, or sends a de-reset signal to perform the de-reset operation on the integrated circuit system; and In response to the clock control signal, the clock signal provided to the integrated circuit system is controlled by the clock control circuit to correspond to the reset operation or the de-reset operation.

14. The clock reset control method according to claim 13, wherein, The clock signal provided to the integrated circuit system by the clock control circuit includes: In response to the reset configuration command, the reset trigger signal is configured as a first signal identifier for triggering the reset operation via the clock reset configuration circuit; When the reset signal detection circuit detects the reset trigger signal, it sends the reset trigger signal to the first control sub-circuit of the reset control circuit. A first signal identifier responding to the reset trigger signal is used to time the event via a timing circuit, and a first trigger command is sent to the first control sub-circuit when the time reaches a first threshold. In response to the first trigger command, a first clock control sub-signal is sent to the clock control circuit through the first control sub-circuit; In response to the first clock control sub-signal, the clock control circuit switches the frequency of the clock signal from a first frequency to a second frequency to provide the clock signal of the second frequency to the integrated circuit system or to stop transmitting the clock signal, wherein the first frequency is greater than the second frequency.

15. The clock reset control method according to claim 14, wherein, In response to detecting that the frequency of the clock signal has switched from the first frequency to the second frequency or in response to detecting that the clock control circuit has stopped outputting the clock signal, the timing circuit performs timing, and when the timing reaches the second threshold, a third trigger command is sent to the second control sub-circuit of the reset control circuit. In response to the third trigger command, the second control sub-circuit outputs the reset signal to the integrated circuit system to perform the reset operation on the integrated circuit system; In response to detecting that the reset operation on the integrated circuit system has been completed, the timing circuit starts timing, and when the timing reaches the third threshold, a fourth trigger command is sent to the second control sub-circuit. In response to the fourth trigger command, the second control sub-circuit outputs the reset signal to the integrated circuit system to perform the reset operation on the integrated circuit system.

16. The clock reset control method according to claim 15, wherein, The clock signal provided to the integrated circuit system by the clock control circuit further includes: In response to detecting that the integrated circuit system has completed the reset operation, the timing circuit starts timing, and when the timing reaches the fourth threshold, a second trigger command is sent to the first control sub-circuit. In response to the second trigger command, the first control sub-circuit sends a second clock control sub-signal to the clock control circuit; In response to the second clock control sub-signal, the clock control circuit switches the frequency of the clock signal from the second frequency to the first frequency or switches from stopping the transmission of the clock signal to starting the transmission of the clock signal at the first frequency, so as to provide the clock signal at the first frequency to the integrated circuit system.

Images