A pixel electrode circuit and a control method thereof

Abstract

The application provides a pixel electrode circuit and a control method thereof. The pixel electrode circuit comprises a first switch, a second switch, a bootstrap unit, a first gate signal line, a second gate signal line, a data signal line, a first voltage signal line, a second voltage signal line and a third voltage signal line. The bootstrap unit comprises a third switch, a fourth switch, a fifth switch and a first capacitor. In the charging process of the bootstrap unit, the data signal line is not required to participate in the charging process, but is used to control the output voltage of the pixel electrode circuit to obtain a desired output voltage. Therefore, the voltage on the data signal line does not need to remain unchanged during the charging process of the bootstrap unit, so that the pulse duration of the signal on the data signal line can be shortened, and the time for the data signal line to perform data writing on each row of pixels in the display panel is shortened, which is helpful to realize high resolution of the display panel.

Description

Technical Field

[0001] This application relates to the field of display device technology, and in particular to a pixel electrode boost circuit and a control method for the boost circuit. Background Technology

[0002] With the rapid development of display technology, display panels are widely used in people's daily lives, such as in various electronic devices like televisions, computers, and mobile phones, and are playing an increasingly important role.

[0003] For display panels, resolution is a crucial performance indicator. High-resolution display panels provide users with an excellent experience and significantly enhance market competitiveness. Therefore, improving the resolution of display panels is a very important research topic for those skilled in the art. Summary of the Invention

[0004] In view of this, this application provides a pixel electrode circuit, the solution of which is as follows:

[0005] A pixel electrode circuit is used in a display panel and is electrically connected to the pixel electrodes in the display panel, comprising: a first switch, a second switch, a bootstrap unit, a first gate signal line, a second gate signal line, a data signal line, a first voltage signal line, a second voltage signal line, and a third voltage signal line.

[0006] The control terminal of the first switch is electrically connected to the data signal line, the input terminal of the first switch is electrically connected to the first voltage signal line, the output terminal of the first switch is electrically connected to the control terminal of the second switch, the input terminal of the second switch is electrically connected to the second voltage signal line, the output terminal of the second switch is electrically connected to the first node, and the first node is electrically connected to the pixel electrode.

[0007] The bootstrap unit includes a third switch, a fourth switch, a fifth switch, and a first capacitor. The control terminals of the third and fourth switches are electrically connected to the first gate signal line, and the control terminal of the fifth switch is electrically connected to the second gate signal line. The input terminals of the third and fifth switches are electrically connected to the third voltage signal line, and the input terminal of the fourth switch is electrically connected to the second voltage signal line. The first plate of the first capacitor is electrically connected to the output terminal of the third switch and the first node, and the second plate of the first capacitor is electrically connected to the output terminals of the fourth and fifth switches.

[0008] Compared with the prior art, the beneficial effects of the technical solution of this application are as follows:

[0009] The pixel electrode circuit provided in this application includes: a first switch, a second switch, a bootstrap unit, a first gate signal line, a second gate signal line, a data signal line, a first voltage signal line, a second voltage signal line, and a third voltage signal line. The bootstrap unit includes a third switch, a fourth switch, a fifth switch, and a first capacitor. The first plate of the first capacitor in the bootstrap unit is electrically connected to the third voltage signal line via the third switch. The second plate of the first capacitor is electrically connected to the second voltage signal line via the fourth switch. The second plate of the first capacitor is also electrically connected to the second voltage signal line via the fifth switch. Furthermore, the control terminals of the third and fifth switches are electrically connected to the first gate signal line, and the control terminal of the fifth switch is electrically connected to the second gate signal line. Therefore, by controlling the third, fourth, and fifth switches to open sequentially via the first and second gate signal lines, the voltages on the second and third voltage signal lines are sequentially charged into the first and second plates of the first capacitor, thus charging the bootstrap unit. This does not require the participation of the data signal line, and the final output bootstrap voltage is independent of the voltage value of the signal on the data signal line.

[0010] Furthermore, the data signal line is electrically connected to the control terminal of the first switch, controlling the opening of the first switch. When the data signal line controls the first switch to open, the first voltage signal line is connected to the control terminal of the second switch, opening the second switch. At this time, the voltage signal provided by the second voltage signal line is transmitted to the first node and the first plate of the first capacitor, making the output voltage of the pixel electrode circuit the voltage value of the signal on the second voltage signal line 2. When the data signal line controls the first switch to close, the second switch closes. At this time, the voltage value at the first node is the bootstrap voltage output by the bootstrap unit, that is, the output voltage of the pixel electrode circuit is the bootstrap voltage. Therefore, in this pixel electrode circuit, the data signal line Source does not participate in the charging of the bootstrap unit, but is used to control the output voltage of the pixel electrode circuit to obtain the desired output voltage.

[0011] As can be seen from the above, during the charging process of the bootstrap unit, the data signal line is not required. Instead, it is used to control the output voltage of the pixel electrode circuit. Therefore, the voltage on the data signal line Source does not need to remain constant during the charging process of the bootstrap unit. This can shorten the pulse duration of the signal on the data signal line, thereby shortening the time for the data signal line to write data to each row of pixels in the display panel, which helps to achieve a high resolution in the display panel. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0013] The structures, proportions, sizes, etc., shown in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size should still fall within the scope of the technical content disclosed in this application, provided that they do not affect the effects and purposes that this application can produce.

[0014] Figure 1 A circuit diagram of a pixel electrode circuit provided in this application;

[0015] Figure 2 This is a timing diagram of the signals on the first gate signal line, the second gate signal line, and the data signal line.

[0016] Figure 3 A circuit diagram of another pixel electrode circuit provided in this application;

[0017] Figure 4 This is a signal timing diagram of a first gate signal line, a second gate signal line, a data signal line, and a switch signal line;

[0018] Figure 5 This is another signal timing diagram for the first gate signal line, the second gate signal line, the data signal line, and the switch signal line;

[0019] Figure 6 A circuit diagram of yet another pixel electrode circuit provided in this application;

[0020] Figure 7 A circuit diagram of yet another pixel electrode circuit provided in this application;

[0021] Figure 8 A circuit diagram of yet another pixel electrode circuit provided in this application;

[0022] Figure 9 A circuit diagram of yet another pixel electrode circuit provided in this application;

[0023] Figure 10 A circuit diagram of yet another pixel electrode circuit provided in this application;

[0024] Figure 11 A circuit diagram of yet another pixel electrode circuit provided in this application;

[0025] Figure 12 A circuit diagram of yet another pixel electrode circuit provided in this application;

[0026] Figure 13 A circuit diagram of yet another pixel electrode circuit provided in this application;

[0027] Figure 14 This is another signal timing diagram of the first gate signal line, the second gate signal line, the data signal line, and the switch signal line;

[0028] Figure 15 The voltage change curve of the pixel electrode data voltage signal when the data signal line Source provides the first data voltage signal line.

[0029] Figure 16 The voltage change curve of the pixel electrode versus the data voltage signal when the second data voltage signal is provided to the data signal line Source.

[0030] Figure 17 A flowchart of a control method for a pixel electrode circuit provided in this application;

[0031] Figure 18 A flowchart illustrating the charging of the bootstrap unit in a control method for a pixel electrode circuit provided in this application;

[0032] Figure 19 A flowchart of another control method for a pixel electrode circuit provided in this application;

[0033] Figure 20 A flowchart of another control method for a pixel electrode circuit provided in this application;

[0034] Figure 21 A flowchart illustrating the charging of the bootstrap unit in another control method for a pixel electrode circuit provided in this application. Detailed Implementation

[0035] The embodiments of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are merely one area of ​​this application, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0036] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0037] Display panels typically include boost circuits to provide higher voltages to the pixel electrodes. Furthermore, to ensure the final bootstrap voltage remains constant throughout the boost circuit's operation, the data voltage signal on the data signal line must remain constant until the bootstrap voltage is output. Therefore, when writing data to each row of pixels in the display panel, the writing time must be at least as long as the time it takes for the boost circuit to generate one bootstrap voltage. This longer data writing time is detrimental to achieving high resolution in the display panel.

[0038] Based on this, this application provides a pixel electrode circuit, which is applied in a display panel and electrically connected to the pixel electrode 100 in the display panel to provide operating voltage to the pixels in the display panel. Figure 1 As shown, Figure 1 This application provides a schematic diagram of a pixel electrode circuit, which includes: a first switch T1, a second switch T2, a bootstrap unit 200, a first gate signal line Gate1, a second gate signal line Gate2, a data signal line Source, a first voltage signal line 1, a second voltage signal line 2, and a third voltage signal line 3. The first gate signal line Gate1, the second gate signal line Gate2, and the data signal line Source are pulse signal lines, while the second voltage signal line 2 and the third voltage signal line 3 are constant voltage signal lines.

[0039] The control terminal of the first switch T1 is electrically connected to the data signal line Source. The input terminal of the first switch T1 is electrically connected to the first voltage signal line 1. The output terminal of the first switch T1 is electrically connected to the control terminal of the second switch T2. The input terminal of the second switch T2 is electrically connected to the second voltage signal line 2. The output terminal of the second switch T2 is electrically connected to the first node P1. The first node P1 is the output port of the pixel electrode circuit and is electrically connected to the pixel electrode 300.

[0040] The bootstrap unit includes a third switch T3, a fourth switch T4, a fifth switch T5, and a first capacitor C1. The control terminals of the third switch T3 and the fourth switch T4 are electrically connected to the first gate signal line Gate1, and the control terminal of the fifth switch T5 is electrically connected to the second gate signal line Gate2. The input terminals of the third switch T3 and the fifth switch T5 are both electrically connected to the third voltage signal line 3, and the input terminal of the fourth switch T4 is electrically connected to the second voltage signal line 2. The first plate of the first capacitor C1 is electrically connected to the output terminal of the third switch T3 and also to the first node P1. The second plate of the first capacitor C1 is electrically connected to the output terminals of both the fourth switch T4 and the fifth switch T5.

[0041] Specifically, in the bootstrap unit 200 of the pixel electrode circuit, the first plate of the first capacitor C1 is electrically connected to the third voltage signal line 3 via the third switch T3, the second plate of the first capacitor C1 is electrically connected to the second voltage signal line 2 via the fourth switch T4, and the second plate of the first capacitor C1 is also electrically connected to the second voltage signal line 2 via the fifth switch T5. Furthermore, the control terminals of the third switches T3 and T4 are electrically connected to the first gate signal line Gate1, and the control terminal of the fifth switch T5 is electrically connected to the second gate signal line Gate2. Therefore, by controlling the third switches T3, T4, and T5 to open sequentially via the first gate signal line Gate1 and the second gate signal line Gate2, the voltages on the second voltage signal line 2 and the third voltage signal line 3 are sequentially charged into the first and second plates of the first capacitor C1, thereby achieving the charging of the first capacitor C1 and thus the charging of the bootstrap unit 200. Therefore, the charging process of the bootstrap unit 100 does not require the participation of the data signal line Source, and the final output bootstrap voltage value is related to the voltage values ​​of the signals on the second voltage signal line 2 and the third voltage signal line 3, but is independent of the voltage value of the signal on the data signal line Source.

[0042] Furthermore, the data signal line Source is electrically connected to the control terminal of the first switch T1, enabling it to control the opening of the first switch T1. When the data signal line Source controls the first switch T1 to open, the first voltage signal line 1 connects to the control terminal of the second switch T2, opening the second switch T2. At this time, the voltage signal provided by the second voltage signal line 2 is transmitted to the first node P1 and the first plate of the first capacitor C1, making the output voltage of the pixel electrode circuit the voltage value of the signal on the second voltage signal line 2. When the data signal line Source controls the first switch T1 to close, the second switch T2 closes, and the voltage signal provided by the second voltage signal line 2 is not transmitted to the first node P1 and the first plate of the first capacitor C1. At this time, the voltage value at the first node P1 is the bootstrap voltage output by the bootstrap unit 200, i.e., the output voltage of the pixel electrode circuit is the bootstrap voltage. Therefore, different signals on the data signal line Source result in different output voltages for the pixel electrode circuit. Thus, in this pixel electrode circuit, the data signal line Source does not participate in the charging of the bootstrap unit 200, but is used to control the output voltage of the pixel electrode circuit to obtain the desired output voltage.

[0043] As described above, during the charging process of the bootstrap unit 100, the data signal line Source is not required. Instead, it is used to control the output voltage of the pixel electrode circuit to obtain the desired output voltage. Therefore, the voltage on the data signal line Source does not need to remain constant throughout the charging process of the bootstrap unit 200. This shortens the pulse duration of the signal on the data signal line Source, thereby reducing the time it takes for the data signal line Source to write data to each row of pixels in the display panel, which helps to achieve a high resolution for the display panel. It should be noted that the duration of the signal pulse on the data signal line Source here refers to the time during which the signal on the data signal line Source remains at a high level. Subsequent descriptions of the duration of the signal pulse refer to the time during which the signal remains at a high level.

[0044] Based on the above embodiments, in one embodiment of this application, such as Figure 2 As shown, Figure 2 This application provides a timing diagram of the signals provided by the first gate signal line Gate1, the second gate signal line Gate2, and the data signal line Source in the pixel electrode circuit. The data signal line Source provides a data voltage signal, which includes a first data voltage signal and a second data voltage signal. The voltage value of the first data voltage signal is greater than that of the second data voltage signal. The first data voltage signal is used to open the first switch T1, and the second data voltage signal is used to close the first switch T1. The first voltage signal line 1 provides a first voltage signal, which is used to open the second switch T2. When the data voltage signal is the first data voltage signal VGH, the control terminal of the second switch T2 is connected to the first voltage signal line 1, so that the first voltage signal on the first voltage signal line 1 is transmitted to the control terminal of the second switch T2, opening the second switch T2. The second voltage signal line 2 provides a second voltage signal, and the third voltage signal line 3 provides a third voltage signal, the voltage value of which is greater than that of the second voltage signal. The first gate signal line Gate1 provides a first control signal, which is used to open the third switch T3 and the fourth switch T4. The second gate signal line, Gate2, provides a second control signal when the third switch T3 and the fourth switch T4 are closed and the data signal line Source provides a data voltage. This second control signal is used to open the fifth switch T5. It should be noted that the first gate signal line, Gate1, the second gate signal line, and the data signal line Source are all pulse signal lines, and the first control signal, the second control signal, and the data voltage signal are all pulse signals. Furthermore, the first data voltage signal is typically the turn-on voltage VGH of the switching transistor, and the second data voltage signal is typically the turn-off voltage VGL of the switching transistor.

[0045] Specifically, as described above, when the pixel electrode circuit is working, the first gate signal line Gate1 first provides a first control signal, opening the third switch T3 and the fourth switch T4, so that the first plate of the first capacitor C1 is connected to the third voltage signal line 3, and the second plate of the first capacitor C1 is connected to the second voltage signal line 2, thereby charging the first plate of the first capacitor C1 with the voltage of the third voltage signal and the voltage of the second voltage signal respectively. The signal pulses on the second voltage signal line 2 and the third voltage signal line 3 end, and the third switch T3 and the fourth switch T4 close. After the third switch T3 and the fourth switch T4 are closed, the second gate signal line Gate2 provides the second control signal to open the fifth switch T5, so that the second plate of the first capacitor C1 is connected to the third voltage signal line 3, so as to charge the second plate of the first capacitor C1 with the voltage of the third voltage signal. At this time, the voltage on the first plate of the first capacitor C1 is coupled up, generating a bootstrap voltage. The voltage value of the bootstrap voltage is twice the difference between the voltage value of the third voltage signal and the voltage value of the second voltage signal. If the second voltage signal provided by the second voltage signal line 2 is denoted as V2 and the third voltage signal provided by the third voltage signal line is denoted as V3, the voltage value of the bootstrap voltage is 2V3-V2.

[0046] When the data signal line Source provides the data voltage, the second gate signal line Gate2 simultaneously provides the second control signal. If the data voltage signal is the first data voltage signal, the first switch T1 is open, the second switch T2 is open, and the second voltage signal on the second voltage signal line 2 is transmitted to the first node P1 and the first plate of the first capacitor C1. Since the data voltage signal and the second control signal are provided simultaneously, while the voltage of the third voltage signal is being applied to the second plate of the first capacitor C1, the voltage of the second voltage signal is also being applied to the first plate of the first capacitor C1. This results in the voltages on the first and second plates of the first capacitor C1 being the same, both being the second voltage signal superimposed on the third voltage signal. The bootstrap unit 200 generates no bootstrap voltage, and the voltage at the first node P1 is pulled to a low potential, which is the voltage of the second voltage signal. The output voltage of this pixel electrode circuit is the voltage value of the second voltage signal provided by the second voltage signal line 2.

[0047] If the data signal line Source provides the second data voltage signal, the first switch T1 is closed, the second switch T2 is closed, the second voltage signal cannot be transmitted to the first plate of the first capacitor C1, the voltage at the first node P1 remains at a high potential, which is the value of the bootstrap voltage. At this time, the output voltage of the pixel electrode circuit is the bootstrap voltage mentioned above.

[0048] As can be seen from the above, during the operation of the bootstrap unit 200, the participation of the data signal line Source is not required. The data signal line Source only needs to provide the corresponding first data voltage signal or second data voltage signal according to the different operating voltages required by the pixel electrodes when the second control signal is provided by the second gate signal line Gate2. Thus, the holding time of the data voltage signal on the data signal line Source is only the duration of the second control signal provided by the second gate signal line Gate2, which shortens the pulse duration of the data voltage signal on the data signal line Source, thereby shortening the time for the data signal line Source to write data to each row of pixels in the display panel, which helps to achieve a high resolution of the display panel.

[0049] It should be noted that during the operation of the display panel, at the start of each frame of data writing, the control terminal of the second switch T2 may have residual charge from the previous frame, causing the second switch T2 to not close completely, thus affecting the normal operation of the pixel electrode circuit. Therefore, in one embodiment of this application, as... Figure 3 As shown, Figure 3 This application provides a schematic diagram of another pixel electrode circuit, which further includes a sixth switch T6, a switch signal line Gate3, and a fourth voltage signal line 4. The control terminal of the sixth switch T6 is electrically connected to the switch signal line Gate3, the input terminal of the sixth switch T6 is electrically connected to the fourth voltage signal line 4, and the output terminal of the sixth switch T6 is electrically connected to the control terminal of the second switch T2. Specifically, the control terminal of the sixth switch T6 is electrically connected to the switch signal line Gate3, causing the switch signal line Gate3 to open the sixth switch T6. The input terminal of the sixth switch T6 is electrically connected to the fourth voltage signal line 4, and the output terminal of the sixth switch T6 is electrically connected to the control terminal of the second switch T2. This ensures that when the sixth switch T6 is open, the control terminal of the second switch T2 is connected to the fourth voltage signal line 4, thereby closing the second switch T2 and preventing incomplete closure of the second switch T2, thus improving the reliability of the pixel electrode circuit.

[0050] Based on the above embodiments, in one embodiment of this application, such as Figure 4 As shown, Figure 4This application provides a timing diagram of the signals provided by the first gate signal line Gate1, the second gate signal line Gate2, the switch signal line Gate3, and the data signal line Source in a pixel electrode circuit. The switch signal line Gate3 provides a third control signal before the third switch T3 and the fourth switch T4 are opened, opening the sixth switch T6. This connects the fourth voltage signal line 4 to the control terminal of the second switch T2. The fourth voltage signal line 4 provides a fourth voltage signal to close the second switch T2, preventing incomplete closure of the second switch T2. Alternatively, as... Figure 5 As shown, Figure 5 This application provides a timing diagram for the signals provided by the first gate signal line Gate1, the second gate signal line Gate2, the switch signal line Gate3, and the data signal line Source in another pixel electrode circuit. The switch signal line Gate3 provides a third control signal to open the sixth switch when the third switch T3 and the fourth switch T4 are open (i.e., when the third switch T3 and the fourth switch T4 are in a switched state). This opens the sixth switch, connecting the fourth voltage signal line 4 to the control terminal of the second switch T2. The fourth voltage signal line 4 provides a fourth voltage signal to close the second switch T2, preventing incomplete closure of the second switch T2. It should be noted that the fourth voltage signal line 4 is a constant voltage signal line, and the voltage value of the fourth voltage signal is a constant voltage value.

[0051] Based on the sixth switch T6, switch signal line Gate3, and fourth voltage signal line 4 of the pixel electrode circuit, in one embodiment of this application, such as Figure 6 As shown, Figure 6 This is a circuit diagram of a pixel electrode circuit provided in this application. The switch signal line Gate3 is used to provide a third control signal when the third switch T3 and the fourth switch T4 are turned on. That is, the switch signal line Gate3 and the first gate signal line Gate provide control signals simultaneously, and both control signals are used to turn on the switches. Thus, the switch signal line Gate3 can be electrically connected to the first gate signal line Gate1, that is, the first gate signal line Gate1 and the switch signal line Gate3 are combined into one. This allows the control signal provided by the first gate signal line Gate1 to be used to turn on both the third switch T3 and the fourth switch T4, as well as to turn on the sixth switch T6. This reduces the number of signal lines in the pixel electrode circuit and helps to simplify the pixel electrode circuit.

[0052] Based on the sixth switch T6, switch signal line Gate3, and fourth voltage signal line 4 of the pixel electrode circuit, in one embodiment of this application, as shown... Figure 7 As shown, Figure 7This is a circuit diagram of a pixel electrode circuit provided in this application. The second voltage signal line 2 is used to provide a second voltage signal. The voltage value of the fourth voltage signal provided by the fourth voltage signal line 4 is equal to the voltage value of the second voltage signal provided by the second voltage signal line 2. That is, the voltage signal provided by the fourth voltage signal line 4 is the same as the voltage signal provided by the second voltage signal line 2. Therefore, the fourth voltage signal line 4 and the second voltage signal line 2 can be electrically connected, thereby merging the fourth voltage signal line 4 and the second voltage signal line 2 into one signal line, reducing the number of signal lines in the pixel electrode circuit and helping to simplify the pixel electrode circuit.

[0053] Based on any of the above embodiments, in one embodiment of this application, such as Figure 8 As shown, Figure 8 This is a circuit diagram of a pixel electrode circuit provided in this application. If the voltage value of the first voltage signal provided by the first voltage signal line 1 is equal to the voltage value of the first data voltage signal provided by the data signal line Source, and the signal transmission direction of the data signal line Source is the same as the channel direction of the first switch T1, that is, the first data voltage signal is the same as the first voltage signal, then the first voltage signal line 1 and the data signal line Source can be electrically connected, thereby merging the first voltage signal line 1 and the data signal line Source into one signal line, reducing the number of signal lines in the pixel electrode circuit and helping to simplify the pixel electrode circuit.

[0054] In another embodiment of this application, such as Figure 9 As shown, Figure 9 This is a circuit diagram of a pixel electrode circuit provided in this application. The third voltage signal line 3 is used to provide a third voltage signal. If the voltage value of the first voltage signal provided by the first voltage signal line 1 is equal to the voltage value of the third voltage signal provided by the third voltage signal line 3, the first voltage signal line 1 and the third voltage signal line 3 are electrically connected. Specifically, at this time, both the first voltage signal line 1 and the third voltage signal line 3 are constant voltage signal lines. Both the first voltage signal and the third voltage signal are constant voltage signals, and the voltage values ​​of the first voltage signal and the third voltage signal are equal. Therefore, the first voltage signal and the third voltage signal are the same and can be the same voltage signal. Thus, in this embodiment, the first voltage signal line 1 and the third voltage signal line 3 are electrically connected, thereby merging the first voltage signal line 1 and the third voltage signal line 3 into a single signal line, reducing the number of signal lines in the pixel electrode circuit and helping to simplify the pixel electrode circuit.

[0055] In one embodiment of this application, such as Figure 10 As shown, Figure 10This application provides a schematic diagram of a pixel electrode circuit, which further includes a seventh switch T7. The control terminal of the seventh switch T7 is electrically connected to the second gate signal line Gate2, the input terminal of the seventh switch T7 is electrically connected to the output terminal of the first switch T1, and the output terminal of the seventh switch T7 is electrically connected to the control terminal of the second switch T2. Specifically, as described above, the electrical connection between the input terminal of the seventh switch T7 and the output terminal of the first switch T1, and the electrical connection between the output terminal and the control terminal of the second switch T2, prevents the charge at the control terminal of the second switch T2 from flowing to the first switch T1, thus avoiding leakage current in the second switch T2 and preventing abnormal shutdown of the second switch T2, ensuring the reliability of the pixel electrode circuit.

[0056] Furthermore, the control terminal of the seventh switch T7 is electrically connected to the second gate signal line Gate2, and is opened via the second gate signal line Gate2. It is known that the second gate signal line Gate2 provides a second control signal when the data signal line Source provides a data voltage signal, with the timing being identical. Therefore, the seventh switch T7 and the first switch T1 open simultaneously, preventing leakage current from the second switch T2 without affecting the signal transmission between the first switch T1 and the second switch T2.

[0057] It should be noted that, for the bootstrap unit in this pixel electrode circuit, the capacitance on the second plate side of the first capacitor C1 affects the bootstrap effect of the output voltage of the first capacitor C1, i.e., the bootstrap voltage. The larger the capacitance on the second plate side of the first capacitor C1, the better the bootstrap effect. Therefore, in one embodiment of this application, as... Figure 11 As shown, Figure 11 The circuit diagram of a pixel electrode circuit provided in this application shows that the bootstrap unit 200 further includes a second capacitor C2. The first plate of the second capacitor C2 is electrically connected to the second plate of the first capacitor C1, the output terminal of the fourth switch T4, and the output terminal of the fifth switch T5. The second plate of the second capacitor C2 is also electrically connected to the second voltage signal line 2. Specifically, the first plate of the second capacitor C2 is electrically connected to the second plate of the second capacitor C1, thereby connecting a second capacitor in series on one side of the first plate of the first capacitor C1, which helps to increase the capacitance on the second plate side of the first capacitor C1. Furthermore, the first plate of the second capacitor C2 is also electrically connected to the output terminal of the fourth switch T4 and the output terminal of the fifth switch T5. Thus, when the second plate of the first capacitor C1 is charged with the voltage of the second voltage signal, the first plate of the second capacitor C2 is also charged with the voltage of the second voltage signal. When the second plate of the first capacitor C1 is charged with the voltage of the third voltage signal, the first plate of the second capacitor C2 is also charged with the voltage of the third voltage signal line, which is the same as the charging process of the second plate of the first capacitor C1. Therefore, it does not affect the voltage of the second plate of the first capacitor C1.

[0058] To prevent charge loss from the control terminal of the second switch T2 or external charge from flowing to the control terminal of the second switch T2, such as Figure 1 As shown, the pixel electrode circuit also includes a third capacitor C3. The first plate of the third capacitor C2 is electrically connected to the control terminal of the second switch T2, and the second plate is electrically connected to the second voltage signal line 2.

[0059] The pixel electrode circuit provided in this application can be applied to electronic paper display panels. Therefore, in one embodiment of this application, such as Figure 12 As shown, the display panel includes an electrophoretic film 300. The second voltage signal is the first driving voltage of the electrophoretic film 300, and the third voltage signal is the second driving voltage of the electrophoretic film 300. The voltage value of the second voltage signal is less than the voltage value of the third voltage signal; that is, the second voltage signal is the low driving voltage DL of the electrophoretic film 300, and the third voltage signal is the high driving voltage DH of the electrophoretic film 300. It should be noted that this pixel electrode circuit can also be applied to other types of display panels, depending on the specific application.

[0060] Optionally, all seven switches are MOSFETs with the same channel type; specifically, all seven switches are either PMOS or NMOS. It should be noted that in the above embodiments, the first to seventh switches are NMOS, such as... Figure 13 and Figure 14 As shown, Figure 13 This is a circuit diagram showing that all seven switches in the pixel electrode circuit are PMOS. Figure 14 This is a timing diagram of the signals provided by the first gate signal line Gate1, the second gate signal line Gate2, the switch signal line Gate3, and the data signal line Source when all the first to seventh switches in the pixel electrode circuit are PMOS. The working principle of the pixel electrode circuit is the same when all the first to seventh switches are PMOS, and will not be described again here.

[0061] Optionally, in one specific embodiment of this application, the width-to-length ratios of the first to seventh switches are the same, all being 4μm / 6μm, and the capacitance values ​​of the first and second capacitors are equal, both being 300fF. The above values ​​are only values ​​of one specific embodiment and are not limitations on the width-to-length ratios and capacitance values.

[0062] like Figure 15 and 16 As shown, Figure 15 When the first data voltage signal line (Source) is provided to the data signal line (Source), i.e., when a high-potential data voltage signal is provided, the voltage change curve of the pixel electrode (pixel) and the data voltage signal (Source) is shown in the graph. Figure 16The graph shows the voltage change of the pixel electrode data line voltage signal Source when a second data voltage signal is provided to the data signal line Source, and the data voltage signal is at a low potential. Figure 15 and Figure 16 It can be seen that when the data signal line Source provides a high-potential first data voltage signal line, the voltage of the pixel electrode will be pulled to a low-potential DL, and when the data signal line Source provides a low-potential second data voltage signal line, the voltage of the pixel electrode will remain at a high potential.

[0063] Accordingly, this application also provides a control method for pixel electrode circuits, such as... Figure 1 As shown, the pixel electrode circuit includes: a first switch T1, a second switch T2, a bootstrap unit 200, a first gate signal line Gate1, a second gate signal line Gate2, a data signal line Source, a first voltage signal line 1, a second voltage signal line 2, and a third voltage signal line 3. The control terminal of the first switch T1 is electrically connected to the data signal line Source, the input terminal of the first switch T1 is electrically connected to the first voltage signal line 1, the output terminal of the first switch T1 is electrically connected to the control terminal of the second switch T2, the input terminal of the second switch T2 is electrically connected to the second voltage signal line 2, and the output terminal of the second switch T2 is electrically connected to the first node P1, which is the output port of the pixel electrode circuit and is electrically connected to the pixel electrode 300. The bootstrap unit includes a third switch T3, a fourth switch T4, a fifth switch T5, and a first capacitor C1. The control terminals of the third switch T3 and the fourth switch T4 are electrically connected to the first gate signal line Gate1, and the control terminal of the fifth switch T5 is electrically connected to the second gate signal line Gate2. The input terminals of the third switch T3 and the fifth switch T5 are electrically connected to the second voltage signal line 2, and the input terminal of the fourth switch T4 is also electrically connected to the second voltage signal line 2. The first plate of the first capacitor C1 is electrically connected to the output terminal of the third switch T3 and also to the first node P1. The second plate of the first capacitor C1 is electrically connected to the output terminals of the fourth switch T4 and the fifth switch T5.

[0064] Based on the above, such as Figure 17 As shown, Figure 17 A flowchart of a pixel electrode circuit control method provided in this application is included, the control method comprising:

[0065] S1: Charge the bootstrap unit 200, wherein, for example... Figure 18 As shown, Figure 18 The flowchart for charging the bootstrap unit 200 includes the following steps:

[0066] S11: Using the first gate signal line Gate1 to provide a first control signal, the third switch T3 and the fourth switch T4 are turned on, and the voltage of the third voltage signal provided by the third voltage signal line 3 is charged to the first plate of the first capacitor C1, and the voltage of the second voltage signal provided by the second voltage signal line 2 is charged to the second plate of the first capacitor C1.

[0067] S12: The second control signal Gate2 is provided using the second gate signal line to open the fifth switch T5, charging the second plate of the first capacitor C1 with the voltage of the third voltage signal, generating a bootstrap voltage. It should be noted that the first gate signal line Gate1 and the second gate signal line Gate2 are pulse signal lines. When the control signal pulse on them ends, the third switch T3, the fourth switch T4, and the fifth switch T5 will be closed.

[0068] After charging the bootstrap unit 200, the control method includes:

[0069] S2: While providing the second control signal using the second gate signal line Gate2, a data voltage signal is also provided using the data signal line Source. The pixel electrode circuit generates a corresponding output voltage based on the data voltage signal. The data voltage signal includes a first data voltage signal and a second data voltage signal. If the data signal line provides the first data voltage signal, the output voltage is the voltage of the second voltage signal. If the data signal line provides the second data voltage signal, the output voltage is the bootstrap voltage.

[0070] Specifically, as described above, this control method sequentially controls the first gate signal line Gate1 and the second gate signal line Gate2 to provide the first control signal and the second control signal respectively. The first gate signal line Gate1 and the second gate signal line Gate2 control the opening of the third switch T3, the fourth switch T4, and the fifth switch T5, thereby charging the first plate and the second plate of the first capacitor C1 in sequence using the voltages on the second voltage signal line 2 and the third voltage signal line 3. This achieves the charging of the bootstrap unit 200. Therefore, the charging process of the bootstrap unit 200 does not require the participation of the data signal line Source. The data voltage signal on the data signal line Source is only used to control the output voltage. Thus, the voltage on the data signal line Source does not need to remain constant throughout the operation of the bootstrap unit 200, thereby shortening the pulse duration of the signal on the data signal line Source and consequently shortening the time it takes for the data signal line Source to write data to each row of pixels in the display panel, which helps to achieve a high resolution for the display panel.

[0071] It should be noted that during the operation of the display panel, at the beginning of each frame, the control terminal of the second switch T2 may have residual charge from the previous frame, causing the second switch T2 to not close completely, thus affecting the normal operation of the pixel electrode circuit. Therefore, in one embodiment of this application, as... Figure 3 As shown, there is a sixth switch T6, a switch signal line Gate3, and a fourth voltage signal line 4. The control terminal of the sixth switch T6 is electrically connected to the switch signal line Gate3, the input terminal of the sixth switch T6 is electrically connected to the fourth voltage signal line 4, and the output terminal of the sixth switch T6 is electrically connected to the control terminal of the second switch T2. Figure 19 As shown, the control method also includes:

[0072] S01: Before the third switch T3 and the fourth switch T4 are opened, the third control signal is provided by the switch signal line Gate3 to open the sixth switch T6 so as to transmit the fourth voltage signal provided by the fourth voltage signal line 4 to the control terminal of the second switch T2 and close the second switch T2.

[0073] Or, such as Figure 20 As shown, when the third switch T3 and the fourth switch T4 are opened, the third control signal is provided by the switch signal line Gate3 to open the sixth switch T6, so as to transmit the fourth voltage signal provided by the fourth voltage signal line 4 to the control terminal of the second switch T2 and close the second switch T2.

[0074] It should be noted that when the bootstrap unit 200 is charged, the capacitance on the second plate side of the first capacitor C1 affects the bootstrap effect of the output voltage of the first capacitor C1, i.e., the bootstrap voltage. The larger the capacitance on the second plate side of the first capacitor C1, the better the bootstrap effect. Therefore, in one embodiment of this application, as... Figure 11 As shown, the bootstrap unit 200 also includes a second capacitor C2. The first plate of the second capacitor C2 is electrically connected to the second plate of the first capacitor C1, the output terminal of the fourth switch T4, and the output terminal of the fifth switch T5. The second plate of the second capacitor C2 is electrically connected to the second voltage signal line 2. That is, a second capacitor is connected in series on one side of the first plate of the first capacitor C1, which helps to increase the capacitance on the second plate side of the first capacitor C1. Figure 21 As shown, charging the bootstrap unit 200 also includes:

[0075] S111: While charging the first plate of the first capacitor C1 with the voltage of the third voltage signal and the second plate of the first capacitor C1 with the voltage of the second voltage signal, the first plate of the second capacitor C2 with the voltage of the second voltage signal is charged, and the second plate of the second capacitor C2 with the voltage of the second voltage signal is charged.

[0076] S121: While charging the second plate of the first capacitor C1 with the voltage of the third voltage signal, the first plate of the second capacitor C2 is also charged with the voltage of the third voltage signal.

[0077] In summary, this application provides a pixel electrode circuit and a control method. The pixel electrode circuit includes: a first switch, a second switch, a bootstrap unit, a first gate signal line, a second gate signal line, a data signal line, a first voltage signal line, a second voltage signal line, and a third voltage signal line. The bootstrap unit includes a third switch, a fourth switch, a fifth switch, and a first capacitor. During the charging process of the bootstrap unit, the data signal line is not required; instead, it is used to control the output voltage of the pixel electrode circuit to obtain the desired output voltage. Therefore, the voltage on the data signal line does not need to remain constant during the charging process of the bootstrap unit, thereby shortening the pulse duration of the signal on the data signal line and consequently shortening the time for the data signal line to write data to each row of pixels in the display panel, which helps to achieve a high resolution in the display panel.

[0078] The various embodiments in this specification are described in a progressive, parallel, or combined manner. Each embodiment focuses on its differences from other embodiments, and similar or identical areas between embodiments can be referred to interchangeably. For the apparatuses disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant details can be found in the description of the method area.

[0079] It should be noted that, in the description of this application, the terms "upper," "lower," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be a component centrally located at the same time.

[0080] It should also be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes the aforementioned element.

[0081] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A pixel electrode circuit, characterized by comprising: A display panel, comprising: a first switch, a second switch, a bootstrap unit, a first gate signal line, a second gate signal line, a data signal line, a first voltage signal line, a second voltage signal line and a third voltage signal line; The control end of the first switch is electrically connected with the data signal line, the input end of the first switch is electrically connected with the first voltage signal line, the output end of the first switch is electrically connected with the control end of the second switch, the input end of the second switch is electrically connected with the second voltage signal line, the output end of the second switch is electrically connected with a first node, and the first node is electrically connected with the pixel electrode; The bootstrap unit comprises a third switch, a fourth switch, a fifth switch and a first capacitor, the control ends of the third switch and the fourth switch are electrically connected with the first gate signal line, the control end of the fifth switch is electrically connected with the second gate signal line, the input ends of the third switch and the fifth switch are electrically connected with the third voltage signal line, and the input end of the fourth switch is electrically connected with the second voltage signal line; the first plate of the first capacitor is electrically connected with the output end of the third switch and the first node, and the second plate of the first capacitor is electrically connected with the output end of the fourth switch and the output end of the fifth switch.

2. The pixel electrode circuit according to claim 1, characterized by The data signal line is used for providing a data voltage signal, the data voltage signal comprises a first data voltage signal and a second data voltage signal, the first data voltage signal is used for opening the first switch, and the second data voltage signal is used for closing the first switch; The first voltage signal line is used for providing a first voltage signal, when the first switch is opened, the control end of the second switch is in communication with the first voltage signal line, and the second switch is opened; The first gate signal line is used for providing a first control signal, the third switch and the fourth switch are opened, the second gate signal line is used for providing a second control signal when the third switch and the fourth switch are closed and the data signal line provides the data signal, and the fifth switch is opened.

3. The pixel electrode circuit of claim 1, wherein, Further comprising: a sixth switch, a switch signal line and a fourth voltage signal line; The control end of the sixth switch is electrically connected with the switch signal line, the input end of the sixth switch is electrically connected with the fourth voltage signal line, and the output end of the sixth switch is electrically connected with the control end of the second switch.

4. The pixel electrode circuit according to claim 3, characterized by The switch signal line is used for providing a third control signal to open the sixth switch before the third switch and the fourth switch are opened, or the switch signal line is used for providing a third control signal to open the sixth switch when the third switch and the fourth switch are opened; The fourth voltage signal line is used for providing a fourth voltage signal to close the second switch.

5. The pixel electrode circuit of claim 4, wherein, If the switch signal line is used for providing a third control signal to open the sixth switch when the third switch and the fourth switch are opened, the switch signal line is electrically connected with the first gate signal line.

6. The pixel electrode circuit of claim 4, wherein, The second voltage signal line is used for providing a second voltage signal, and the fourth voltage signal line is electrically connected with the second voltage signal line if the voltage of the fourth voltage signal is equal to the voltage of the second voltage signal.

7. The pixel electrode circuit of claim 2, wherein, The first voltage signal line is electrically connected with the data signal line if the voltage value of the first voltage signal is equal to the voltage value of the first data voltage signal and the signal transmission direction of the data signal line is the same as the conduction direction of the first switch.

8. The pixel electrode circuit of claim 2, wherein, The third voltage signal line is used for providing a third voltage signal, and the first voltage signal line is electrically connected with the third voltage signal line if the voltage value of the first voltage signal is equal to the voltage value of the third voltage signal.

9. The pixel electrode circuit of claim 1, wherein, Further comprising: The seventh switch has its control end electrically connected with the second gate signal line, its input end electrically connected with the output end of the first switch, and its output end electrically connected with the control end of the second switch.

10. The pixel electrode circuit of claim 1, wherein, The bootstrap unit further comprises a second capacitor, the first plate of the second capacitor is electrically connected with the second plate of the first capacitor, the output end of the fourth switch and the output end of the fifth switch, and the second plate of the second capacitor is electrically connected with the second voltage signal line. The capacitance of the first capacitor is equal to the capacitance of the second capacitor.

11. The pixel electrode circuit of claim 1, wherein, The display panel comprises an electrophoretic film, the second voltage signal is a first driving voltage of the electrophoretic film, the third voltage signal is a second driving voltage of the electrophoretic film, and the voltage value of the second voltage signal is less than the voltage value of the third voltage signal.

12. The pixel electrode circuit of claim 1, 4, or 9, wherein, The switches in the pixel electrode circuit are all MOS tubes, and have the same channel type.

13. The pixel electrode circuit of claim 1, 4, or 9, wherein, The width-length ratios of the switches in the pixel electrode circuit are equal.

14. A control method of a pixel electrode circuit, characterized by, The pixel electrode circuit is electrically connected with a pixel electrode in a display panel, comprising: a first switch, a second switch, a bootstrap unit, a first gate signal line, a second gate signal line, a data signal line, a first voltage signal line, a second voltage signal line and a third voltage signal line; the control end of the first switch is electrically connected with the data signal line, the input end of the first switch is electrically connected with the first voltage signal line, and the output end of the first switch is electrically connected with the control end of the second switch; the input end of the second switch is electrically connected with the second voltage signal line, the output end of the second switch is electrically connected with a first node, the first node is an output port of the pixel electrode circuit and is electrically connected with the pixel electrode; the bootstrap unit comprises a third switch, a fourth switch, a fifth switch and a first capacitor, the control ends of the third switch and the fourth switch are electrically connected with the first gate signal line, and the control end of the fifth switch is electrically connected with the second gate signal line; the input ends of the third switch and the fifth switch are electrically connected with the third voltage signal line, and the input end of the fourth switch is electrically connected with the second voltage signal line; the first plate of the first capacitor is electrically connected with the output end of the third switch and the first node respectively, and the second plate of the first capacitor is electrically connected with the output end of the fourth switch and the output end of the fifth switch; and the control method comprises: Charging the bootstrap unit, wherein charging the bootstrap unit comprises: providing a first control signal by using the first gate signal line to open the third switch and the fourth switch, to charge the first plate of the first capacitor with the voltage of the third voltage signal provided by the third voltage signal line, and to charge the second plate of the first capacitor with the voltage of the second voltage signal provided by the second voltage signal line; providing a second control signal by using the second gate signal line to open the fifth switch, to charge the second plate of the first capacitor with the voltage of the third voltage signal, to generate a bootstrap voltage; after charging the bootstrap unit, providing a data voltage signal by using the data signal line while providing a second control signal by using the second gate signal line, wherein the data voltage signal comprises a first data voltage signal and a second data voltage signal, and wherein the output voltage is the voltage of the second voltage signal if the data signal line provides the first data voltage signal, and the output voltage is the bootstrap voltage if the data signal line provides the second data voltage signal.

15. The control method according to claim 14, characterized by The pixel electrode circuit further comprises a sixth switch, a switch signal line and a fourth voltage signal line, wherein the control end of the sixth switch is electrically connected with the switch signal line, the input end of the sixth switch is electrically connected with the fourth voltage signal line, and the output end of the sixth switch is electrically connected with the control end of the second switch. The control method further comprises: before the third switch and the fourth switch are opened, providing a third control signal by using the switch signal line to open the sixth switch, to transmit the fourth voltage signal provided by the fourth voltage signal line to the control end of the second switch, and to close the second switch; or simultaneously with the third switch and the fourth switch being opened, providing a third control signal by using the switch signal line to open the sixth switch, to transmit the fourth voltage signal provided by the fourth voltage signal line to the control end of the second switch, and to close the second switch.

16. The control method according to claim 14, characterized by The bootstrap unit further comprises a second capacitor, wherein the first plate of the second capacitor is electrically connected with the second plate of the first capacitor, the output end of the fourth switch and the output end of the fifth switch respectively, and the second plate of the second capacitor is electrically connected with the second voltage signal line; and charging the bootstrap unit further comprises: simultaneously with charging the first plate of the first capacitor with the voltage of the third voltage signal and charging the second plate of the first capacitor with the voltage of the second voltage signal, charging the first plate of the second capacitor with the voltage of the second voltage signal and charging the second plate of the second capacitor with the voltage of the second voltage signal; simultaneously with charging the second plate of the first capacitor with the voltage of the third voltage signal, charging the first plate of the second capacitor with the voltage of the third voltage signal.

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