Signal generation circuitry layout in a memory device

Abstract

The present application relates to signal generation circuitry layout in a memory device. A memory device may include signal generation circuitry positioned in multiple levels of a memory die relative to a substrate. For example, a first set of transistors for generating access signals may be positioned on a first level of a memory die, and a second set of transistors for generating the access signals may be positioned on a second level of the memory die. The formation of the first set of transistors and the second set of transistors may involve processing operations common to the formation of other transistors on the respective levels, such as cell select transistors, plane select transistors, shunt transistors, and other transistors of the respective levels.

Description

[0001] Cross Reference

[0002] This patent application claims priority to U.S. patent application No. 17 / 680,006 filed by VIMERCATI on February 24, 2022, entitled "SIGNAL DEVELOPMENT CIRCUITRY LAYOUTS IN AMEMORY DEVICE," which is assigned to its assignee and is expressly incorporated herein by reference.

[0003] The technical field relates to signal generation circuitry layout in memory devices. Background Art

[0004] Memory devices are widely used to store information in various electronic devices, such as computers, user devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, typically corresponding to a logical 1 or a logical 0. In some examples, a single memory cell can support more than two possible states, any of which can be stored by the memory cell. To access information stored by a memory device, a component can read (e.g., sense, detect, retrieve, identify, determine, evaluate) the state of one or more memory cells within the memory device. To store information, a component can write (e.g., program, set, assign) one or more memory cells within the memory device to a corresponding state.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), 3-dimensional cross point memory (3D cross point), NOR and NAND (NAND memory devices), and others. Memory devices may be described in terms of volatile configurations or non-volatile configurations. Volatile memory cells (e.g., DRAM) may lose their programmed state over time unless they are periodically refreshed by an external power source. Non-volatile memory cells (e.g., NAND) may maintain their programmed state for extended periods of time even in the absence of external power. Summary of the invention

[0006] An apparatus is described. The apparatus may include: a first digit line associated with a first level of a memory die above a substrate, the first digit line coupled to a first group of memory cells of the memory die; a second digit line associated with a second level of the memory die above the substrate, the second digit line coupled to a second group of memory cells of the memory die; a first transistor associated with the first level of the memory die and operable to couple the first digit line to a first conductor coupled to a sense amplifier of the memory die; a second transistor associated with the second level of the memory die and operable to couple the second digit line to the first conductor; a third transistor associated with the first level of the memory die and operable to couple the first conductor to a voltage source; and a fourth transistor associated with the second level of the memory die and having a channel portion coupled between the first conductor and the second conductor.

[0007] A method is described. The method may include: isolating a conductor of a first level of a memory die above a substrate from a voltage source based at least in part on deactivating a first transistor associated with the memory die; generating a first voltage at a conductor of the memory die based at least in part on coupling a storage element of a memory cell with a digit line and coupling the digit line with the conductor; shifting the conductor from the first voltage to a second voltage based at least in part on shifting a bias applied to a gate of a second transistor associated with a second level of the memory die above the substrate from a third voltage to a fourth voltage, the second transistor having a channel portion coupled between a first portion of the conductor and a second portion of the conductor; and determining a logic state based at least in part on shifting the conductor from the first voltage to the second voltage.

[0008] An apparatus is described. The apparatus may include: a memory die including a first level above a substrate and a second level above the substrate; and circuitry of the memory die operable to cause the apparatus to: isolate a conductor of the memory die from a voltage source based at least in part on deactivating a first transistor associated with the first level of the memory die; generate a first voltage at a conductor of the memory die based at least in part on coupling a storage element of a memory cell with a digit line and coupling the digit line with the conductor; shift the conductor from the first voltage to a second voltage based at least in part on shifting a bias applied to a gate of a second transistor associated with the second level of the memory die from a third voltage to a fourth voltage, the second transistor having a channel portion coupled between a first portion of the conductor and a second portion of the conductor; and determine a logic state based at least in part on shifting the conductor from the first voltage to the second voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 An example of a memory device supporting signal generation circuitry layout according to examples as disclosed herein is illustrated.

[0010] Figure 2 Examples of circuits supporting topology of signal generation circuitry in a memory device according to examples as disclosed herein are illustrated.

[0011] Figure 3A and 3B Examples of non-linear electrical properties of ferroelectric memory cells according to examples as disclosed herein are illustrated.

[0012] Figure 4 Examples of transistor structures supporting layout of signal generation circuitry in a memory device according to examples as disclosed herein are illustrated.

[0013] Figure 5 Examples of circuits supporting topology of signal generation circuitry in a memory device according to examples as disclosed herein are illustrated.

[0014] Figure 6 A timing diagram illustrating the operation of an example access process supporting a signal generation circuitry layout in a memory device according to examples as disclosed herein is shown.

[0015] Figure 7 Examples of memory structures supporting layout of signal generation circuitry in a memory device according to examples as disclosed herein are illustrated.

[0016] Figure 8 A block diagram of a memory device is shown supporting a layout of signal generation circuitry in the memory device according to examples as disclosed herein.

[0017] Fig. 9

[0013] Flowcharts are shown illustrating one or several methods of supporting signal generation circuitry layout in a memory device according to examples as disclosed herein. DETAILED DESCRIPTION

[0018] Memory devices may include various arrangements of memory arrays formed above a substrate, and memory cells of the memory array may be organized (e.g., addressed) according to rows and columns. In some examples, at least some circuitry supporting operation (e.g., access) of the memory array may be located below the memory array, which may refer to a location at least partially between the memory array and the substrate. For example, decoding or multiplexing circuitry, signal generation circuitry, or sensing circuitry, as well as other types of circuitry, may be located below the memory array and may include transistors formed at least in part by doping portions of the substrate (e.g., substrate-based transistors, such as transistors having channels formed of doped crystalline silicon or other semiconductors) in some examples. As memory devices expand to have a greater number of levels (e.g., layers, levels) above a substrate, the area of ​​the substrate used for such support circuitry may increase, which may lead to scaling limitations (e.g., related to the limited area of ​​the substrate to support the growing number of levels, and thereby to the ever-increasing number and area of ​​such support circuitry).

[0019] According to examples as disclosed herein, a memory device may include signal generation circuitry positioned in multiple levels of a memory die relative to a substrate. For example, a set of one or more first transistors of the signal generation circuitry for generating access signals may be positioned on a first level of the memory die, and a set of one or more second transistors of the signal generation circuitry for generating access signals may be positioned on a second level of the memory die. In some examples, the set of first transistors may be coupled to a set of access lines (e.g., at the first level) and may be associated with coupling the set of access lines to a voltage source (e.g., a ground voltage source). In some examples, the set of second transistors may be coupled to the set of access lines (e.g., at the second level) and may be associated with providing a voltage shift along the access lines, which may support a sense amplifier to compare the access signal relative to a voltage (e.g., a ground voltage). Such operation of the second set of transistors may utilize capacitance of the second set of transistors (e.g., between a gate of the second transistor and a channel of the second transistor, between a gate of the second transistor and a corresponding access line), and may involve coupling of both ends of the channel of the second transistor to the corresponding access line (e.g., directly, indirectly). The formation of the set of first transistors and the set of second transistors may involve common processing operations with forming other transistors on the corresponding levels (e.g., cell select transistors, level select transistors, shunt transistors, and other transistors of the corresponding levels). By configuring the signal generation circuitry, which may include signal generation transistors, to be located on multiple levels of a memory die, and utilizing common manufacturing operations, the memory die may support a higher density of memory cells (e.g., in each level), improved access operations (e.g., due to shorter access lines, due to closer proximity between memory cells and signal generation circuitry), and greater scalability (e.g., by supporting a greater number of levels above a substrate), among other advantages.

[0020] Originally in reference Figures 1 to 4 Features of the present disclosure are described in the context of the described memory devices and associated circuitry. Figures 5 to 7 Features of the present disclosure are described in the context of the described exemplary circuits, timing diagrams, and memory structures. Figure 8 and 9 These and other features of the present disclosure are further illustrated and described with reference to device diagrams and flow charts associated with the layout of signal generation circuitry in a described memory device.

[0021] Figure 1An example of a memory device 100 that supports a signal generation circuitry layout in a memory device according to an example as disclosed herein is illustrated. The memory device 100 may also be referred to as a memory die or an electronic memory device. The memory device 100 may include memory cells 105 that are programmable to store different logic states. In some cases, the memory cells 105 may be programmable to store two logic states, represented as logic 0 and logic 1. In some cases, the memory cells 105 may be programmable to store more than two logic states (e.g., as multi-level cells). A group of memory cells 105 may be part of a memory array 110 of the memory device 100, where in some examples, the memory array 110 may refer to a contiguous tile of memory cells 105 (e.g., a group of contiguous elements of a semiconductor chip).

[0022] In some examples, the memory cell 105 may store a charge representing a programmable logic state (e.g., in a capacitor, in a capacitive memory element, or in a capacitive storage element). In some examples, a charged and uncharged capacitor may represent two logic states, respectively. In some other examples, a positively charged (e.g., first polarity, positive polarity) and a negatively charged (e.g., second polarity, negative polarity) capacitor may represent two logic states, respectively. A DRAM or FeRAM architecture may use such a design, and the capacitor employed may include a dielectric material having a linear or quasi-electric polarization property as an insulator. In some examples, different charge levels of the capacitor may represent different logic states, which in some examples may support more than two logic states in the corresponding memory cell 105. In some examples such as the FeRAM architecture, the memory cell 105 may include a ferroelectric capacitor having a ferroelectric material as an insulating (e.g., non-conductive, dielectric) layer between the terminals of the capacitor. Different levels or polarities of polarization of the ferroelectric capacitor may represent different logic states (e.g., supporting two or more logic states in the corresponding memory cell 105).

[0023] In the example of memory device 100, each row of memory cells 105 may be associated with one or more word lines 120 (eg, WL1 through WL2). M ) are coupled, and each column of memory cells 105 can be coupled to one or more digit lines 130 (eg, DL1 to DL N) are coupled. Each of the word line 120 and the digit line 130 may be an example of an access line of the memory device 100. In general, one memory cell 105 may be located at (e.g., coupled to, coupled between) a word line 120 and a digit line 130. This intersection may be referred to as an address of the memory cell 105. A selected memory cell 105 (e.g., a target memory cell 105) may be a memory cell 105 located at an intersection of a selected word line 120 (e.g., an activated word line 120, a powered word line 120) and a selected digit line 130 (e.g., an activated digit line 130, a powered digit line 130).

[0024] In some architectures, the storage components of the memory cells 105 may be electrically isolated (e.g., selectively isolated) from the digit lines 130 by a cell selection component, which in some examples may be referred to as a switch component or selector device of or otherwise associated with the memory cells 105. The word lines 120 may be coupled to the cell selection components (e.g., via control nodes of the cell selection components) and may control the cell selection components of the memory cells 105. For example, the cell selection components may be transistors and the word lines 120 may be coupled to the gates of the transistors (e.g., where the gate nodes of the transistors may be the control nodes of the transistors). Activating the word lines 120 may result in an electrical connection or closed circuit between the respective logical storage components of one or more memory cells 105 and the one or more corresponding digit lines 130, which may be referred to as activating the one or more memory cells 105 or coupling the one or more memory cells 105 with the respective one or more digit lines 130. The digit lines 130 may then be accessed to read from or write to the respective memory cells 105.

[0025] In some examples, memory cell 105 may also be coupled to one or more plate lines 140 (eg, PL1 to PL N) are coupled. In some examples, each of the plate lines 140 may be independently addressable (e.g., to support individual selection or biasing). In some examples, the plurality of plate lines 140 may represent a common plate or other common node (e.g., a plate node common to each of the memory cells 105 in the memory array 110) or otherwise be functionally equivalent thereto. For configurations in which the memory cells 105 employ capacitors for storing logic states, the digit lines 130 may provide access to a first node (e.g., a first terminal, a first plate) of the capacitor, and the plate lines 140 may provide access to a second node (e.g., a second terminal, a second plate) of the capacitor. Although the plurality of plate lines 140 of the memory device 100 are shown as being substantially parallel to the plurality of digit lines 130, in other examples, the plurality of plate lines 140 may be substantially parallel to the plurality of word lines 120, or in any other configuration (e.g., a common planar conductor, a common plate layer, a common plate node).

[0026] Access operations such as reading, writing, rewriting, and refreshing may be performed on the memory cell 105 by selecting (e.g., activating) a word line 120, a digit line 130, or a plate line 140 coupled to the memory cell 105, which may include applying a voltage, charge, or current to the corresponding access line. When a memory cell 105 is selected (e.g., in a read operation), the resulting signal may be used to determine the logic state stored by the memory cell 105. For example, a memory cell 105 having a capacitive memory element storing a logic state may be selected, and the resulting charge flow through the access line or the resulting voltage of the access line may be detected to determine the programmed logic state stored by the memory cell 105.

[0027] Access to memory cells 105 may be controlled using row component 125 (e.g., row decoder), column component 135 (e.g., column decoder), or plate component 145 (e.g., plate decoder), or a combination thereof. For example, row component 125 may receive a row address from memory controller 170 and activate corresponding word line 120 based on the received row address. Similarly, column component 135 may receive a column address from memory controller 170 and activate corresponding digit line 130. In some examples, such access operations may be accompanied by plate component 145 biasing one or more of plate lines 140 (e.g., biasing one of plate lines 140, biasing some or all of plate lines 140, biasing a common plate).

[0028] In some examples, the memory controller 170 may use one or more components (e.g., row components 125, column components 135, plate components 145, sense components 150) to control the operation of the memory cell 105 (e.g., read operation, write operation, rewrite operation, refresh operation). In some cases, one or more of the row components 125, column components 135, plate components 145, and sense components 150 may be co-located or otherwise included with the memory controller 170. The memory controller 170 may generate row and column address signals to activate the desired word lines 120 and digit lines 130. The memory controller 170 may also generate or control various voltages or currents used during operation of the memory device 100.

[0029] When the memory cell 105 is accessed (e.g., in cooperation with the memory controller 170) to determine the logic state written to or stored by the memory cell 105, the memory cell 105 may be read (e.g., sensed) by the sensing component 150. For example, the sensing component 150 may be configured to evaluate, in response to the read operation, a current or charge transfer through or from the memory cell 105, or a voltage resulting from coupling the memory cell 105 with the sensing component 150. The sensing component 150 may provide an output signal indicative of the logic state read from the memory cell 105 to one or more components (e.g., to the column component 135, the input / output component 160, the memory controller 170).

[0030] The sensing component 150 may include various switching components, selection components, transistors, amplifiers, capacitors, resistors, or voltage sources to detect or amplify the difference of the sense signal (e.g., the difference between the read voltage and the reference voltage, the difference between the read current and the reference current, the difference between the read charge and the reference charge), which may be referred to as latching in some examples. In some examples, the sensing component 150 may include a set of components (e.g., circuit elements) that are repeated for each of a set or subset of digit lines 130 coupled to the sensing component 150. For example, the sensing component 150 may include a separate sensing circuit (e.g., a respective sense amplifier, a respective signal generating component) for each of a set of digit lines 130 coupled to the sensing component 150, so that a logic state can be separately detected for a respective memory cell 105 coupled to a respective one of the set of digit lines 130.

[0031] Memory cell 105 may be written to by activating an associated word line 120, digit line 130, or plate line 140 (e.g., via memory controller 170). In other words, a logic state may be stored in memory cell 105. Row component 125, column component 135, or plate component 145 may accept data to be written to memory cell 105, for example, via input / output component 160. The write operation may be performed at least in part by sense component 150, or the write operation may be configured to bypass sense component 150.

[0032] In a configuration implementing a capacitive memory element, the memory cell 105 may be written by applying a voltage to (e.g., across) the capacitor, and then isolating the capacitor (e.g., isolating the capacitor from the voltage source used to write the memory cell 105, floating the capacitor) to store the charge associated with the desired logic state in the capacitor. In the case of ferroelectric memory, the ferroelectric memory element (e.g., a ferroelectric capacitor) of the memory cell 105 may be written by applying a voltage of a magnitude high enough to polarize the ferroelectric memory element with the polarization associated with the desired logic state (e.g., applying a saturation voltage), and the ferroelectric memory element may be isolated (e.g., floating), or a zero net voltage or bias may be applied to the ferroelectric memory element (e.g., ground, virtual ground, or equalizing the voltage across the ferroelectric memory element).

[0033] According to examples as disclosed herein, the memory device 100 may include signal generation circuitry (e.g., associated with the sensing component 150) positioned in multiple levels of a memory die (e.g., a semiconductor die) relative to a substrate. For example, a set of one or more first transistors for generating access signals may be positioned on a first level of the memory die, and a set of one or more second transistors for generating access signals may be positioned on a second level of the memory die. The formation of the set of first transistors and the set of second transistors may involve processing operations (e.g., patterning operations, material deposition operations, material removal operations) common to forming other transistors (e.g., cell select transistors, layer select transistors, shunt transistors, and other transistors of the respective levels) on the respective levels. By locating signal generating transistors on multiple levels of a memory die and utilizing common manufacturing operations, the memory device 100 can support a higher density of memory cells 105 (e.g., in each level), improved access operations (e.g., due to shorter access lines, due to closer proximity between the memory cells 105 and the signal generating circuitry), and greater scalability (e.g., by supporting a greater number of levels above the substrate), among other advantages.

[0034] Figure 2An example of a circuit 200 supporting a signal generation circuit system layout in a memory device according to an example as disclosed herein is illustrated. The circuit 200 includes a memory cell 105-a and a sensing element 150-a, which may be as described in reference to Figure 1 Circuit 200 also includes word line 120-a, digit line 130-a, and plate line 140-a, which may be referenced Figure 1 105 -a. In various examples, plate line 140 -a may illustrate an independently addressable plate line 140 -a or a common plate node (e.g., of a memory array 110 including memory cells 105 -a). In some memory architectures (e.g., DRAM), plate line 140 -a may be an example of a ground node, such as Vss. In some other memory architectures (e.g., FeRAM), plate line 140 -a may be biased to different voltage levels during different portions of an operation performed using memory cells 105 -a.

[0035] The memory cell 105-a may include a logical storage component (e.g., a memory element, a storage element, a memory storage element), such as a capacitor 220 having a first plate (cell plate 221) and a second plate (cell bottom 222). The cell plate 221 and the cell bottom 222 may be capacitively coupled by a dielectric material positioned therebetween (e.g., in DRAM applications), or by a ferroelectric material positioned therebetween (e.g., in FeRAM applications). The cell plate 221 may be capacitively coupled to a voltage V plate is associated with, and the cell bottom 222 can be connected to the voltage V bottom 2 and 3. As illustrated in circuit 200, cell plate 221 is accessible via plate line 140-a and cell bottom 222 is accessible via digit line 130-a. As described herein, various logic states may be stored by charging, discharging, or polarizing capacitor 220.

[0036] Capacitor 220 may be electrically connected to digit line 130-a, and a stored logic state of capacitor 220 may be read or sensed by operating the various elements represented in circuit 200. For example, memory cell 105-a may also include a cell selection component 230, which in some examples may be referred to as a switch component or selector device coupled to or between an access line (e.g., digit line 130-a) and capacitor 220. In some examples, cell selection component 230 may be considered to be outside the illustrative boundaries of memory cell 105-a, and cell selection component 230 may be referred to as a switch component or selector device coupled to or between an access line (e.g., digit line 130-a) and memory cell 105-a.

[0037] When the cell selection component 230 is activated (e.g., by activating a logic signal), the capacitor 220 can be coupled (e.g., selectively) with the digit line 130-a, and when the cell selection component 230 is deactivated (e.g., by deactivating a logic signal), the capacitor 220 can be isolated (e.g., selectively) from the digit line 130-a. A logic signal or other selection signal or voltage can be applied to a control node 235 of the cell selection component 230 (e.g., via the word line 120-a). In other words, the cell selection component 230 can be configured to couple or decouple the capacitor 220 with the digit line 130-a based on a logic signal or voltage applied to the control node 235 via the word line 120-a.

[0038] Activating cell selection component 230 may be referred to as selecting or activating memory cell 105-a, and deactivating cell selection component 230 may be referred to as deselecting or deactivating memory cell 105-a. In some examples, cell selection component 230 is a transistor and its operation may be controlled by applying an activation voltage to a transistor gate (e.g., a control or selection node or terminal). The voltage used to activate the transistor (e.g., a voltage between a transistor gate terminal and a transistor source terminal) may be a voltage greater than the magnitude of a threshold voltage of the transistor. In some examples, activating cell selection component 230 may be referred to as coupling (e.g., selectively) memory cell 105-a with digit line 130-a.

[0039] Biasing plate line 140-a or digit line 130-a may result in a voltage difference across capacitor 220 (e.g., the voltage of digit line 130-a minus the voltage of plate line 140-a). The voltage difference may be accompanied by a change in the charge stored by capacitor 220 (e.g., due to charge sharing between capacitor 220 and digit line 130-a, due to charge sharing between capacitor 220 and plate line 140-a), and the magnitude of the change in stored charge may depend on the initial state of capacitor 220 (e.g., whether the initial charge or logic state stores a logic 1 or a logic 0).

[0040] The digit line 130-a may be coupled to an additional memory cell 125 (not shown), and the digit line 130-a may have properties that result in a non-negligible intrinsic capacitance 240 (e.g., on the order of picofarads (pF)), which may couple the digit line 130-a with a voltage source 250-a. The voltage source 250-a may represent a common ground or virtual ground voltage, or the voltage of an adjacent access line of the circuit 200 (not shown). Although illustrated as Figure 2 , but intrinsic capacitance 240 may be associated with a property distributed throughout digit line 130 - a.

[0041] Sensing component 150-a may include a signal generating component 260 and a sense amplifier 270 coupled to signal generating component 260 via signal line 265. In various examples, signal generating component 260 may include circuitry configured to amplify or otherwise modify the signal of digit line 130-a prior to a logic state detection operation (e.g., by sense amplifier 270). Signal generating component 260 may include, for example, a transistor, an amplifier, a cascode, or any other circuitry configured to generate a signal for sensing a logic state stored by memory cell 105-a. In some examples, signal generating component 260 may include a charge transfer sense amplifier, which may include one or more transistors in a cascode or voltage controlled configuration.

[0042] Although digit line 130-a and signal line 265 are identified as separate lines, digit line 130-a, signal line 265, and any other lines connecting memory cell 105 with sense amplifier 270 may be referred to as a single access line (e.g., of or associated with memory cell 105). The components of this access line may be identified separately for purposes of illustrating intervening components and intervening signals in various example configurations.

[0043] Sense amplifier 270 may include a first node 271 and a second node 272, which in some examples may be coupled to different access lines of a circuit (e.g., signal line 265 and reference line 285 of circuit 200, respectively), or in other examples may be coupled to a common access line of a different circuit (not shown). In some examples, first node 271 may be referred to as a signal node, and second node 272 may be referred to as a reference node. However, other configurations of access lines or reference lines may be used to support the techniques described herein.

[0044] The sense amplifier 270 may include various transistors or amplifiers to detect, convert, or amplify the difference in the signal, which may be referred to as latching. For example, the sense amplifier 270 may include a sense signal voltage (e.g., V of the signal line 265) received and compared at the first node 271. sig ) and the reference signal voltage at the second node 272 (eg, V ref) circuit element. The voltage of the first node 271 can be based on accessing the memory cell 105-a, such as at least in part based on the voltage of the charge transfer of the capacitor 220 when the cell selection component 230 is activated. In some examples, the voltage of the second node 272 can be provided by a reference component 280 (e.g., a reference voltage source). In some other examples, the reference voltage can be provided, for example, by accessing the memory cell 105-a to generate the reference voltage (e.g., in a self-referenced access operation) or by accessing a different memory cell 105 (e.g., a complementary memory cell 105) to generate the reference voltage (e.g., in a paired or complementary memory cell access operation), in which case at least a portion of the reference component 280 can be included as part of the signal generation component 260, or at least a portion of the reference component 280 can be omitted. For example, the second node 272 may be (e.g., selectively) coupled to the signal line 265, the signal generating component 260, and the digital line 130-a (e.g., for a self-reference configuration), or the second node 272 may be coupled to a different signal line 265 and a different signal generating component 260 of the sensing component 150, wherein the signal generating component may be coupled to a different digital line 130 coupled to a different memory cell 105 (e.g., for a complementary reference configuration).

[0045] The output of the sense amplifier 270 may be driven to a relatively higher voltage (e.g., a positive voltage) or a relatively lower voltage (e.g., a negative voltage, a ground voltage) based on the comparison at the sense amplifier 270. For example, the sense amplifier 270 may output the detected logic state via one or more I / O lines 275 based on the comparison of the signals at the first node 271 and the second node 272. For example, if the first node 271 has a voltage lower than the second node 272, the output of the sense amplifier 270 may be driven to a relatively lower voltage (e.g., V L If the first node 271 has a voltage higher than the second node 272, the output of the sense amplifier 270 may be driven to the voltage of the second sense amplifier voltage source 250-c (e.g., V H The sensing component 150-a may latch the output of the sense amplifier 270 to determine the logic state stored in the memory cell 105-a (e.g., latching or determining a logic 0 when the first node 271 has a voltage lower than the second node 272, and latching or determining a logic 1 when the first node 271 has a voltage higher than the second node 272). The latched output of the sense amplifier 270 corresponding to the detected logic state of the memory cell 105-a may be output via one or more input / output (I / O) lines (e.g., I / O line 275), which may include a sense amplifier 270 outputted via a reference signal. Figure 1The outputs of the column component 135 or the input / output component 160 are described. In some examples, one or more I / O channels can share a common electrical node or path with the first node 271 or the second node 272.

[0046] To perform a write operation on memory cell 105-a, a voltage may be applied across capacitor 220 by controlling the voltages of cell plate 221 (e.g., through plate line 140-a) and cell bottom 222 (e.g., through digit line 130-a). For example, to write a logic 0, cell plate 221 may be made low (e.g., grounding plate line 140-a, virtually grounding plate line 140-a, applying a negative voltage to plate line 140-a), and cell bottom 222 may be made high (e.g., applying a positive voltage to digit line 130-a). The reverse process may be performed to write a logic 1, where cell plate 221 is made high and cell bottom 222 is made low. In some cases, the voltage applied across capacitor 220 during a write operation may have a magnitude equal to or greater than the saturation voltage of the ferroelectric material in capacitor 220, such that capacitor 220 is polarized and thereby maintains a charge even when the magnitude of the applied voltage is reduced or when a net zero voltage is applied across capacitor 220.

[0047] The circuit 200 including the sense amplifier 270, the cell selection component 230, the signal generation component 260, or the reference component 280 may include various types of transistors. For example, the circuit 200 may include an n-type transistor, where applying a relatively positive voltage (e.g., an applied voltage having a positive magnitude relative to the source terminal, which is greater than the threshold voltage) above the threshold voltage of the n-type transistor to the gate of the n-type transistor enables a conduction path to be formed between other terminals (e.g., the drain terminal and the source terminal, across the conduction channel) of the n-type transistor.

[0048] In some examples, an n-type transistor may function as a switch component, wherein the applied voltage is a logic signal used to enable conduction through the transistor by applying a relatively high logic signal voltage (e.g., a voltage corresponding to a logic 1 state, which may be associated with a positive logic signal voltage supply), or to disable conduction through the transistor by applying a relatively low logic signal voltage (e.g., a voltage corresponding to a logic 0 state, which may be associated with a ground or virtual ground voltage). In some examples employing an n-type transistor as a switch component, the voltage of the logic signal applied to the gate terminal may be selected to operate the transistor at a particular operating point (e.g., in a saturation region or in an active region).

[0049] In some examples, the behavior of an n-type transistor may be more complex than logic switching, and the selective conductivity across the transistor may also vary with varying drain and source voltages. For example, the applied voltage at the gate terminal may have a certain voltage level (e.g., a clamping voltage) that is used to enable conductivity between the drain terminal and the source terminal when the source terminal voltage is below a certain level (e.g., below the gate terminal voltage minus a threshold voltage). When the voltage of the source terminal rises above a certain level, the n-type transistor may be deactivated such that the conduction path between the drain terminal and the source terminal is broken.

[0050] Additionally or alternatively, circuit 200 may include a p-type transistor, wherein applying a relatively negative voltage (e.g., an applied voltage having a negative magnitude relative to the source terminal, which is greater than the threshold voltage) above a threshold voltage of the p-type transistor to a gate of the p-type transistor enables a conduction path to be formed between other terminals (e.g., a drain terminal and a source terminal, across a conductive channel) of the p-type transistor.

[0051] In some examples, the p-type transistor may function as a switch component, where the applied voltage is a logic signal used to enable conductivity by applying a relatively low logic signal voltage (e.g., a voltage corresponding to a logic "1" state, which may be associated with a negative logic signal voltage supply), or to disable conductivity by applying a relatively high logic signal voltage (e.g., a voltage corresponding to a logic "0" state, which may be associated with a ground or virtual ground voltage). In some examples employing a p-type transistor as a switch component, the voltage of the logic signal applied to the gate terminal may be selected to operate the transistor at a particular operating point (e.g., in a saturation region or in an active region).

[0052] In some examples, the behavior of a p-type transistor may be more complex than logical switching by a gate voltage, and the selective conductivity across the transistor may also vary with varying drain and source voltages. For example, the applied voltage at the gate terminal may have a specific voltage level that is used to enable conductivity between the drain terminal and the source terminal as long as the source terminal voltage is above a certain level (e.g., above the gate terminal voltage plus a threshold voltage). When the voltage of the source terminal voltage drops below a certain level, the p-type transistor may be deactivated such that the conduction path between the drain terminal and the source terminal is broken.

[0053] The transistors of circuit 200 may be field effect transistors (FETs), including metal oxide semiconductor FETs, which may be referred to as MOSFETs. In some examples, these and other types of transistors may be formed from doped regions of a material of a substrate. In some examples, transistors may be formed on a substrate dedicated to a particular component of circuit 200 (e.g., a substrate for sense amplifier 270, a substrate for signal generating component 260, a substrate for reference component 280, a substrate for memory cell 105-a), or transistors may be formed on a substrate common to particular components of circuit 200 (e.g., a substrate common to two or more of sense amplifier 270, signal generating component 260, reference component 280, or memory cell 105-a). Some FETs may have a metal portion including aluminum or other metals, but some FETs may implement other non-metallic materials such as polysilicon, including FETs that may be referred to as MOSFETs. Further, although an oxide portion may be used as a dielectric portion of a FET, other non-oxide materials may be used in the dielectric material in a FET, including FETs that may be referred to as MOSFETs.

[0054] Although circuit 200 illustrates one set of components relative to a single memory cell 105, various components of circuit 200 may be replicated in memory device 100 to support various operations. For example, to support row access or page access operations, sensing component 150 may be configured with multiples of one or more of signal generating components 260, signal lines 265, reference components 280, reference lines 285, sense amplifiers 270, or other components, where the multiples may be configured according to the number of memory cells 105 that may be accessed in a row access or page access operation (e.g., in concurrent operations).

[0055] According to examples as disclosed herein, the circuit 200 may include signal generating circuitry (e.g., circuitry of the signal generating component 260, circuitry of the reference component 280) positioned in multiple levels of the memory die relative to the substrate. For example, a set of one or more first transistors for generating access signals may be positioned on a first level of the memory die, and a set of one or more second transistors for generating access signals may be positioned on a second level of the memory die. In some examples, the set of first transistors may be coupled to a set of access lines (e.g., coupled to a set of signal lines 265 at the first level), and may be associated with coupling the set of access lines to a voltage source (e.g., a ground voltage source). In some examples, the set of second transistors may be coupled to the set of access lines (e.g., coupled to the set of signal lines 265 at the second level), and may be associated with providing a voltage shift along the access lines, which may support a sense amplifier 270 that compares the access signal relative to a voltage (e.g., a ground voltage).

[0056] In some examples, the first transistor and the second transistor may include respective channel portions formed of doped semiconductor material that has been deposited over a semiconductor substrate (e.g., using thin film material deposition techniques), and the transistor of the sense amplifier 270 may include respective channel portions formed of doped regions of a semiconductor substrate (e.g., doped regions of a crystalline silicon wafer). The formation of the set of first transistors and the set of second transistors may involve common processing operations with the formation of other transistors on respective levels (e.g., cell select transistors, layer select transistors, shunt transistors, and other transistors of respective levels). By locating signal generating transistors on multiple levels of a memory die, and utilizing common manufacturing operations, the memory die may support higher density memory cells (e.g., in each level), improved access operations (e.g., due to shorter access lines, due to closer proximity between memory cells and signal generating circuitry), and greater scalability (e.g., by supporting a greater number of levels over a substrate), among other advantages.

[0057] Figure 3A and 3B An example of nonlinear electrical properties of a ferroelectric memory cell with hysteresis plots 300-a and 300-b according to an example disclosed herein. The hysteresis plots 300-a and 300-b may respectively illustrate the nonlinear electrical properties of a ferroelectric memory cell using a hysteresis plot 300-a and 300-b as described in reference to FIG. Figure 2 1 and 2. The hysteresis plots 300-a and 300-b depict the hysteresis of the memory cell 105 as the voltage difference V between the terminals of the ferroelectric capacitor 220 varies. cap The charge Q stored on the ferroelectric capacitor 220 (for example, when the voltage difference V cap When charge is allowed to flow into or out of the ferroelectric capacitor 220). For example, the voltage difference V cap It can represent the voltage difference between the cell bottom 222 and the cell plate 221 (for example, V bottom –V plate 、V DL –V PL ). However, in some other examples, V cap Alternatively, it can be understood as the difference between the cell plate 221 and the cell bottom 222 (eg, V plate –V bottom 、V PL –V DL ).

[0058] Ferroelectric materials are characterized by electrical polarization, where the material can maintain a non-zero charge in the absence of an electric field. Examples of ferroelectric materials include barium titanate (BaTiO3), lead titanate (PbTiO3), lead zirconium titanate (PZT), and strontium bismuth tantalate (SBT). The ferroelectric capacitor 220 described herein may include these or other ferroelectric materials. The electrical polarization within the ferroelectric capacitor 220 creates a net charge at the surface of the ferroelectric material and attracts opposite charges through the terminals of the ferroelectric capacitor 220. Therefore, charge can be stored at the interface of the ferroelectric material and the capacitor terminals.

[0059] As depicted in the hysteresis plot 300-a, the ferroelectric material used in the ferroelectric capacitor 220 can remain positively or negatively polarized during a state in which there is no net voltage difference between the terminals of the ferroelectric capacitor 220. For example, the hysteresis plot 300-a illustrates two possible polarization states, namely, a charge state 305-a and a charge state 310-a, which can represent a negative saturation polarization state and a positive saturation polarization state, respectively. The charge states 305-a and 310-a can be in a physical state that illustrates a residual polarization (Pr) value, which can refer to the polarization (or charge) that remains when an external bias (e.g., voltage) is removed. According to the example of the hysteresis plot 300-a, the charge state 305-a can represent a logical 1 when a voltage difference is not applied across the ferroelectric capacitor 220, and the charge state 310-a can represent a logical 0 when a voltage difference is not applied across the ferroelectric capacitor 220. In some examples, the logical values ​​of the corresponding charge states or polarization states can be reversed or interpreted in an opposite manner to accommodate other schemes for operating the memory cell 105.

[0060] A logical 0 or 1 may be written to the memory cell 105 by controlling the electrical polarization of the ferroelectric material and, therefore, the charge on the capacitor terminals, by applying a net voltage difference across the ferroelectric capacitor 220. For example, the voltage 315 may be a voltage equal to or greater than the positive saturation voltage, and applying the voltage 315 across the ferroelectric capacitor 220 may cause charge to accumulate until a charge state 305-b is reached (e.g., writing a logical 1). When the voltage 315 is removed from the ferroelectric capacitor 220 (e.g., a zero net voltage is applied across the terminals of the ferroelectric capacitor 220), the charge state of the ferroelectric capacitor 220 may follow a path 320 shown between the charge state 305-b at zero voltage across the capacitor and the charge state 305-a. In other words, the charge state 305-a may represent a logical 1 state at the equilibrium voltage across the ferroelectric capacitor 220 that is already positively saturated.

[0061] Similarly, voltage 325 may be a voltage equal to or less than the negative saturation voltage, and applying voltage 325 across ferroelectric capacitor 220 may cause charge to accumulate until charge state 310-b is reached (e.g., a logical 0 is written). When voltage 325 is removed from ferroelectric capacitor 220 (e.g., a zero net voltage is applied across the terminals of ferroelectric capacitor 220), the charge state of ferroelectric capacitor 220 may follow path 330 shown between charge state 310-b and charge state 310-a at zero voltage across the capacitor. In other words, charge state 310-a may represent a logical 0 state at an equilibrium voltage across ferroelectric capacitor 220 that has been negatively saturated. In some examples, voltage 315 representing the saturation voltage and voltage 325 may have the same magnitude across ferroelectric capacitor 220, but have opposite polarities. Although the example of hysteresis plot 300-a illustrates a logic 0 corresponding to charge state 310-a and a logic 1 corresponding to charge state 305-a, in some examples the logical states may correspond to different charge states, such as a logic 0 corresponding to charge state 305-a and a logic 1 corresponding to charge state 310-a, as well as other examples.

[0062] To read or sense the stored state of ferroelectric capacitor 220, a voltage may also be applied across ferroelectric capacitor 220. In response to the applied voltage, the subsequent charge Q stored by the ferroelectric capacitor changes, and the degree of change may depend on the initial polarization state, the applied voltage, the intrinsic or other capacitance on the access line, and other factors. In other words, the charge state or access line voltage resulting from the read operation may depend on whether charge state 305-a or charge state 310-a or some other charge state was initially stored, as well as other factors.

[0063] Hysteresis plot 300-b illustrates an example of reading stored charge states 305-a and 310-a. Read voltage 335 may be applied, for example, via digit line 130-a and plate line 140-a as a voltage difference, as shown in FIG. Figure 2 The hysteresis plot 300 - b may illustrate a read operation, where the read voltage 335 is a positive voltage difference V cap (For example, where V bottom –V plate is positive, where V DL Greater than V PL ). A positive read voltage across ferroelectric capacitor 220 may be referred to as a “plate low” read operation, where digit line 130-a is initially placed at a high voltage and plate line 140-a is initially at a low voltage (e.g., ground voltage). Although read voltage 335 is shown as a positive voltage across ferroelectric capacitor 220, in an alternative access operation, the read voltage may be a negative voltage across ferroelectric capacitor 220, which may be referred to as a “plate high” read operation.

[0064] When a memory cell 105 is selected (eg, by activating the cell selection component 230 via the word line 120-a, as shown in FIG. Figure 2 ), a read voltage 335 may be applied across ferroelectric capacitor 220. When read voltage 335 is applied to ferroelectric capacitor 220, charge may flow into or out of ferroelectric capacitor 220 via associated digit line 130-a and plate line 140-a, and in some examples, different charge states or access line voltages may be produced depending on whether ferroelectric capacitor 220 is in charge state 305-a (e.g., storing a logical 1) or in charge state 310-a (e.g., storing a logical 0), or some other charge state.

[0065] When a read operation is performed on ferroelectric capacitor 220 in charge state 305-a (e.g., logic 1), additional positive charge may accumulate across ferroelectric capacitor 220, and the charge state may follow path 340 until the charge and voltage of charge state 305-c are reached. The amount of charge flowing through capacitor 220 may be related to the intrinsic or other capacitance of digit line 130-a or other access lines. In a "plate low" read configuration, read operations associated with charge states 305-a and 305-c, or more generally, read operations associated with a logic 1 state, may be associated with a relatively small amount of charge transfer (e.g., compared to read operations associated with charge states 310-a and 310-c, or more generally, a logic 0 state).

[0066] As shown by the transitions between charge state 305-a and charge state 305-c, the resulting voltage 350 across ferroelectric capacitor 220 may be a relatively large positive value due to the relatively large voltage change at capacitor 220 for a given charge change. Thus, when reading a logic 1 in a “plate low” read operation, the voltage 350 is equal to V in charge state 305-c. PL With V cap (For example, V bottom –V plate ) may be a relatively high voltage. This read operation may not change the remnant polarization of the ferroelectric capacitor 220 storing the charge state 305-a, and thus after performing the read operation, the ferroelectric capacitor 220 may return to the charge state 305-a via path 340 when the read voltage 335 is removed (e.g., by applying a zero net voltage across the ferroelectric capacitor 220, by equalizing the voltage across the ferroelectric capacitor 220). Therefore, performing a read operation with a positive read voltage on the ferroelectric capacitor 220 having the charge state 305-a may be considered a non-destructive read process.

[0067] When performing a read operation on ferroelectric capacitor 220 in charge state 310-a (e.g., logic 0), as a net positive charge accumulates across ferroelectric capacitor 220, the stored charge may reverse polarity and the charge state may follow path 360 until the charge and voltage of charge state 310-c are reached. The amount of charge flowing through ferroelectric capacitor 220 may again be related to the intrinsic or other capacitance of digit line 130-a or other access lines. In a "plate low" read configuration, read operations associated with charge states 310-a and 310-c, or more generally with a logic 0 state, may be associated with a relatively large amount of charge transfer (e.g., compared to read operations associated with charge states 305-a and 305-c, or more generally with a logic 1 state).

[0068] As shown by the transitions between charge state 310-a and charge state 310-c, in some cases, the resulting voltage 355 can be a relatively small positive value due to the relatively small change in voltage at capacitor 220 for a given charge change. Thus, when reading a logical 0 in a "plate low" read operation, the charge state 310-c is equal to V PL and V cap (For example, V bottom –V plate ) can be a relatively low voltage.

[0069] The transition from charge state 310-a to charge state 310-d may illustrate a sensing operation associated with a partial reduction or partial reversal of the polarization or charge of ferroelectric capacitor 220 of memory cell 105 (e.g., a decrease in the magnitude of charge Q from charge state 310-a to charge state 310-d). In other words, depending on the properties of the ferroelectric material, after performing a read operation, when read voltage 335 is removed (e.g., by applying a net zero voltage across ferroelectric capacitor 220, by equalizing the voltage across ferroelectric capacitor 220), ferroelectric capacitor 220 may not return to charge state 310-a. In contrast, when a net zero voltage is applied across ferroelectric capacitor 220 after a read operation of charge state 310-a with read voltage 335, the charge state may follow path 365 from charge state 310-c to charge state 310-d, illustrating a net decrease in polarization magnitude (e.g., a charge state that is less positively polarized than initial charge state 310-a, illustrated by the charge difference between charge state 310-a and charge state 310-d). Thus, performing a read operation with a positive read voltage on ferroelectric capacitor 220 with charge state 310-a may be described as a destructive read process.

[0070] The position of charge state 305-c and charge state 310-c after initiating a read operation may depend on various factors, including the particular sensing scheme and circuitry. In some cases, the final charge may depend on the net capacitance of digit line 130-a coupled to memory cell 105, which may include intrinsic capacitance 240, an integrator capacitor (e.g., of sensing component 150), and others. For example, if ferroelectric capacitor 220 is electrically coupled to plate line 140-a at 0V and read voltage 335 is applied to digit line 130-a, then when memory cell 105 is selected, the voltage of digit line 130-a may drop due to charge flowing from the net capacitance of digit line 130-a to ferroelectric capacitor 220. Thus, in some examples, the voltage measured at sensing component 150 may not be equal to read voltage 335 or the resulting voltages 350 or 355, and may instead depend on the voltage of digit line 130-a or other access lines after a charge sharing period.

[0071] The voltage of the digit line 130 - a or the signal line 265 (where applicable) resulting from the read operation may be compared to a reference voltage (eg, via a reference voltage such as Figure 2 The reference line 285 described above) is used to determine the initial state (e.g., charge state, logic state) of the ferroelectric capacitor 220. In some instances, the digital line voltage may be the sum of the plate line voltage and the final voltage across the ferroelectric capacitor 220 (e.g., voltage 350 when reading a ferroelectric capacitor 220 having a storage charge state 305-a, or voltage 355 when reading a ferroelectric capacitor 220 having a storage charge state 310-a). In some instances, the digital line voltage may be the difference between the read voltage 335 and the final voltage across the capacitor 220 (e.g., (read voltage 335-voltage 350) when reading a ferroelectric capacitor 220 having a storage charge state 305-a, (read voltage 335-voltage 355) when reading a ferroelectric capacitor 220 having a storage charge state 310-a).

[0072] In some examples, a read operation of memory cell 105 may be associated with a fixed voltage of digit line 130-a, wherein the charge state of ferroelectric capacitor 220 after initiating the read operation may be the same regardless of its initial charge state. For example, in a read operation in which digit line 130-a is maintained at fixed read voltage 335, ferroelectric capacitor 220 may enter charge state 370 for both the case in which ferroelectric capacitor initially stored charge state 305-a and the case in which ferroelectric capacitor initially stored charge state 310-a. Thus, instead of using a voltage difference of digit line 130-a to detect an initial charge state or logic state, in some examples, the initial charge state or logic state of ferroelectric capacitor 220 may be determined based at least in part on a charge difference associated with the read operation. For example, as illustrated by hysteresis plot 300-b, a logical 1 can be detected based on a charge difference Q between charge state 305-a and charge state 370 (e.g., a relatively small amount of charge transfer), and a logical 0 can be detected based on a charge difference Q between charge state 310-a and charge state 370 (e.g., a relatively large amount of charge transfer).

[0073] In some examples, such detection may be supported by a charge transfer sense amplifier, a cascode (e.g., a transistor operating in a cascode configuration, which may also support decoding functionality according to examples as disclosed herein), or other circuitry of a signal generating component 260 between digit line 130-a and signal line 265, and the voltage of signal line 265 may be based at least in part on the amount of charge transferred from capacitor 220 after initiating a read operation. In such examples, while digit line 130-a remains at a fixed voltage level, the voltage of signal line 265 may be compared to a reference voltage (e.g., at sense amplifier 270) to determine the logic state initially stored by ferroelectric capacitor 220.

[0074] In some instances where digit line 130-a is held at a fixed read voltage 335, capacitor 220 may be positively saturated after a read operation, regardless of whether capacitor 220 was initially in charge state 305-a (e.g., a logic 1) or initially in charge state 310-a (e.g., a logic 0). Thus, after such a read operation, capacitor 220 may be at least temporarily charged according to a logic 1 state, regardless of its initial or intended logic state. Thus, at least when capacitor 220 is intended to store a logic 0 state, a rewrite operation may be performed, and such a rewrite operation may include applying a write voltage 325 to store a logic 0 state, as described with reference to hysteresis plot 300-a. Such a rewrite operation may be configured or otherwise described as a selective rewrite operation, as it may not be necessary to apply a rewrite voltage when capacitor 220 is intended to store a logic 1 state. In some instances, this access scheme may be referred to as a "2Pr" scheme, in which the charge difference used to distinguish between logic 0 and logic 1 may be equal to twice the remanent polarization of memory cell 105 (e.g., the charge difference between charge state 305-a (positive saturation charge state) and charge state 310-a (negative saturation charge state)).

[0075] Figure 4 An example of a transistor structure 400 supporting a signal generation circuitry layout in a memory device according to an example as disclosed herein is illustrated. The transistor structure 400 illustrates an example of a transistor formed at least in part by a portion of a substrate 420 (e.g., a doped portion 440 of the substrate 420), and may illustrate an arrangement of features of the transistor configured as a planar transistor arrangement. The substrate 420 may be a portion of a semiconductor wafer, such as a silicon chip (e.g., crystalline silicon, single crystal silicon) of a memory die. For illustrative purposes, aspects of the transistor structure 400 may be described with reference to the x-direction, y-direction, and z-direction (e.g., height direction) of a coordinate system 410. In some examples, the z-direction may illustrate a direction perpendicular to a surface of the substrate 420 (e.g., a surface in an xy plane, a surface on or above which other materials may be deposited), and each of the structures illustrated by their respective cross-sections in the xz plane may extend a distance (e.g., length) along the y-direction.

[0076] Transistor structure 400 illustrates an example of a transistor channel electrically coupled between terminal 470-a-1 and terminal 470-a-2, which may include one or more doped portions 440 of substrate 420. In various examples, one of terminals 470-a-1 or 470-a-2 may be referred to as a source terminal, and the other of terminals 470-a-1 or 47-a-2 may be referred to as a drain terminal, where such designation may be based on a configuration or relative biasing of a circuit that includes transistor structure 400. A channel (e.g., a channel portion) of a transistor may include or refer to one or more portions of a transistor structure that are operable to open or close a conduction path (e.g., modulate conductivity, form a channel, open a channel, close a channel) between a source and a drain (e.g., between terminal 470-a-1 and terminal 470-a-2) based at least in part on a voltage of a gate (e.g., gate terminal, gate portion 450) of the transistor. In other words, the channel of the transistor can be configured to be activated (e.g., become conductive) or deactivated (e.g., become non-conductive) based at least in part on a voltage of a gate (e.g., gate portion 450). In some examples of transistor structure 400 (e.g., a planar transistor arrangement), the channel portion formed by one or more doped portions 440 of substrate 420 can support a conduction path in a generally horizontal direction (e.g., an "in-plane" direction, along the x-direction, in an xy plane, within a surface of substrate 420, or in a direction parallel to the surface).

[0077] The gate portion 450 can be physically separated from the channel portion (e.g., separated from the substrate 420, separated from one or more of the doped portions 440) by a gate insulating portion 460 (e.g., a gate dielectric). Each of the terminals 470 can be in contact with or otherwise coupled to a corresponding doped portion 440-a (e.g., electrically, physically), and each of the terminals 470 and the gate portion 450 can be formed of a conductive material (e.g., a metal or metal alloy, or a polycrystalline semiconductor (e.g., polysilicon), as well as other conductor or semiconductor arrangements formed above the substrate 420).

[0078] In some examples, transistor structure 400 can be operated as an n-type (e.g., n-channel) transistor, where a relatively positive voltage above a threshold voltage (e.g., an applied voltage having a positive magnitude relative to the source terminal that is greater than the threshold voltage) applied to gate voltage 450 activates a channel portion or otherwise enables a conduction path between terminals 470-a-1 and 470-a-2 (e.g., in a direction substantially aligned with the x-direction within substrate 420). In some such examples, doped portion 440-a can refer to a portion having an n-type doping or an n-type semiconductor, and doped portion 440-b can refer to a portion having a p-type doping or a p-type semiconductor (e.g., a channel portion having an NPN configuration along the x-direction or channel direction).

[0079] In some examples, transistor structure 400 can be operated as a p-type (e.g., p-channel) transistor, where a relatively negative voltage above a threshold voltage (e.g., an applied voltage having a negative magnitude relative to the source terminal that is greater than the threshold voltage) applied to gate portion 450 activates a channel portion or otherwise enables a conduction path between terminals 470-a-1 and 470-a-2. In some such examples, doped portion 440-a can refer to a portion having a p-type doping or a p-type semiconductor, and doped portion 440-b can refer to a portion having an n-type doping or an n-type semiconductor (e.g., a channel portion having a PNP configuration along the x-direction or channel direction).

[0080] In some examples, circuitry operable to support access operations to memory cells 105 (e.g., at least a portion of row component 125, column component 135, plate component 145, sense component 150, or memory controller 170, or various combinations thereof) may be formed to include several sets of respective transistors each having an arrangement of transistor structure 400, wherein each of the transistors may have a channel portion formed by a respective doped portion 440 of substrate 420. In some examples, such transistors may utilize the crystalline semiconductor material of substrate 420 to achieve various performance characteristics or manufacturing characteristics of such material or such arrangement. Some examples of such an arrangement may be implemented in a complementary metal oxide semiconductor (CMOS) configuration, which may refer to various examples of complementary and symmetric pairs of p-type transistors and n-type transistors (e.g., for logic functions). However, such a structure or arrangement of substrate-based transistors may be limited by the available area of ​​substrate 420 (e.g., below memory array 110 or a level or stack of layers of memory array 110).

[0081] According to examples as disclosed herein, various aspects of the signal generation component 260 and other circuitry (e.g., addressing circuitry, shunt circuitry) may be located separate from or remote from (e.g., above) the substrate 420, including having various components or circuitry at different levels of one or more memory arrays 110. For example, some circuitry (e.g., transistors supporting aspects of signal generation associated with the signal generation component 260) may be formed in multiple levels above the substrate 420, where such transistors may include or be referred to as thin film transistors or vertical transistors, among other configurations or terms.

[0082] Figure 5 An example of a circuit 500 supporting a signal generation circuit system layout in a memory device according to an example as disclosed herein is illustrated. The circuit 500 includes a memory cell 105-b (e.g., a pair of memory cells 105-b) configured to be coupled to a sensing component 150-b, which may be as described in reference to Figures 1 to 4An example of aspects of the memory cell 105 and the sensing component 150 are described. The circuit 500 illustrates an example of a complementary memory cell arrangement (eg, a complementary reference configuration).

[0083] The sensing component 150-b includes a sense amplifier 270-a coupled to circuitry (e.g., of the signal generating component 260) for sensing a logic state based on accessing the memory cell 105-b (e.g., based on latching a signal difference between an access of the memory cell 105-b-1 and an access of the memory cell 105-b-2). Signals may be communicated between the memory cell 105-b and the sense amplifier 270-a via respective digit lines 130-b and signal lines 265-a, which may be referred to in combination with any other constituent signal paths as respective access lines between the memory cell 105-b and the sense amplifier 270a. The operation of the circuit 500 may also be supported by various configurations of the word lines 120 and the plate lines 140. For example, as illustrated, at least memory cells 105-b-1 and 105-b-2 may be coupled to common plate line 140-b, and memory cells 105-b-1 and 105-b-2 may be coupled to word lines 120-b-1 and 120-b-2, respectively, which may be driven together or independently. sig1 , the voltage V on the signal line 265-a-2 sig2 and the voltage V on the plate line 140-b PL To illustrate the signals of the access lines, as shown.

[0084] The circuit 500 may include a ground node 510, which may represent a node coupled to a common ground point (e.g., chassis ground, neutral point, virtual ground, ground voltage source). The ground node 510 may be associated with a common reference voltage having a voltage V0, from which other voltages are defined or otherwise related. The circuit 500 also includes a voltage source 520, which may represent a node coupled to various voltage supplies of the memory device 100 including the example circuit 500. The respective voltage sources 520 may be coupled to a voltage supply that is regulated at the memory device 100 including the circuit 500, or is not regulated at the memory device 100 (e.g., regulated or otherwise supplied by a host device coupled to the memory device 100). In some examples, two or more voltage sources 520 may be coupled to the same voltage supply (e.g., a common voltage source), and in some implementations may be associated with the same voltage level.

[0085] Circuit 500 may include a switch component 530 that may be coupled with the components (e.g., coupled between the components, electrically coupled with the components) to provide selective coupling or decoupling functionality. In some examples, switch component 530 may be a transistor (e.g., an n-type transistor, a p-type transistor), and a logic signal (e.g., SW#) may be applied to the gate of the transistor to enable or disable a conduction path (e.g., a channel) through the transistor. As described herein, enabling a logic signal at switch component 530 (e.g., as a logic 1) may enable the conduction path through switch component 530 (e.g., close the circuit path), and disabling a logic signal at switch component 530 (e.g., as a logic 0) may disable the conduction path through switch component 530 (e.g., open the circuit path). The control logic signal may be provided by a memory controller (not shown) (e.g., reference Figure 1 The memory controller 170 described herein or any other component of the memory device 100 that supports access operation timing provides the logic signal SW# and other logic signals.

[0086] Circuit 500 may include a variable voltage source 540, which may include various configurations of voltage source 520 and a selection component 545 controlled via a logic signal VV. The voltage source 540 may be controlled by a memory controller (not shown) (e.g., see Figure 1 The memory controller 170 described herein or any other component of the memory device 100 that supports the access operation timing provides the logic signal VV. Although the variable voltage source 540 is illustrated as including two voltage sources 520 and a selection component 545, the variable voltage source 540 that supports the operations described herein may include other configurations, such as including more than two voltage sources 520, or including a voltage buffer that provides a variable voltage in other ways. In some examples, the variable voltage source 540 may include two or more switch components 530 in place of the selection component 545, which may support a floating voltage condition.

[0087] Circuit 500 may include transistors 550, 555, 560, and 565, which may support various aspects of accessing memory cell 105-b. According to examples as disclosed herein, the set of transistors 550, 555, 560, and 565 may be implemented at two or more levels of a memory die, which may involve various implementations of thin film transistor (TFT) technology (e.g., where one or more of transistors 550, 555, 560, or 565 are implemented as thin film transistors, such as vertical transistors). In some examples, any combination of transistors 550, 555, 560, and 565 may be positioned in two or more levels of a memory die above a substrate.

[0088] Transistor 550 may support decoding functionality (e.g., level selection, layer selection) of circuit 500. For example, each digit line 130-b of a multi-level memory array that includes circuit 500 (e.g., having digit lines 130-b on multiple levels) may be associated with a corresponding transistor 550-a, and the corresponding transistor 550-a may support coupling of the digit line 130-b of a given level with a sense amplifier 270-a (e.g., via signal line 265-a). Transistor 550-a-1 may support coupling of digit line 130-b-1 with signal line 265-a-1 (e.g., based on input signal SEL1, which may be associated with a layer selection signal), etc. A digit line 130-b of one or more levels that are not associated with an access operation may be isolated from signal line 265-b by deactivating the corresponding transistor 550-a.

[0089] Transistors 555 may support shunting functionality of circuit 500. For example, each digit line 130-b may be associated with a respective transistor 555-a, and the respective transistor 555-a may support coupling the digit line 130-b with the plate line 140-b. This coupling may equalize the voltage across a group of memory cells 105-b (e.g., a column of memory cells) between the digit line 130-b and the plate line 140-b, which may reduce the accumulation of leakage charge (e.g., at capacitor 220) that may otherwise corrupt the logic state stored by the group of memory cells 105-b. Transistor 555-a-1 may support shunting the digit line 130-b-1 with the plate line 140-b (e.g., based on input signal SH1), etc. The shunt path of the digit line 130-b associated with an access operation may be opened by deactivating the respective transistor 555-a. In some examples, circuit 500 may be implemented without such current shunting functionality, and accordingly transistor 555 may be omitted.

[0090] Transistor 560 may support grounding functionality of circuit 500. For example, each signal line 265-a may be associated with a respective transistor 560-a, and the respective transistor 560-a may support coupling of the signal line 265-a with a ground node 510-a. This coupling may reset the voltage of the signal line 265-a (e.g., to zero), which may be performed before, after, or as part of an access operation (e.g., before coupling the memory cell 105-b with the signal line 265-a, after latching by the sense amplifier 270-a). Transistor 560-a-1 may support coupling of the signal line 265-a-1 with the ground node 510-a-1 (e.g., based on an input signal EN1), etc. The ground path of the signal line 265-a associated with an access operation may be opened by deactivating the respective transistor 560-a.

[0091] Transistor 565 can support voltage shifting functionality (e.g., voltage offset functionality, voltage shifting functionality) of the circuit. For example, each signal line 265-a can be associated with a corresponding transistor 565-a, and the corresponding transistor 565-a can support generating a signal on the signal line according to a first voltage (e.g., when the first voltage (e.g., V G1 ) biases the gate of the corresponding transistor 565-a), and based on changing the voltage applied to the gate of the corresponding transistor 565-a (e.g., based on converting the gate of the corresponding transistor 565-a to a second voltage (e.g., V G2 ) bias voltage, which can be initiated based on the input signal VV) to shift (e.g., shift, offset) to a second voltage.

[0092] In some examples, such operations can utilize the capacitance of the respective transistor 565-a (e.g., between the gate and the channel of the respective transistor 565-a, between the gate of the respective transistor 565-a and the signal line 265-a). In some examples, the transistor 565 can be referred to as a capacitor, where the respective capacitance is provided between structures of the circuit 500 that are generally formed with other transistors of the circuit 500 (e.g., one or more of the transistors 550, 555, or 560). For example, the transistor 565 can alternatively be referred to as a gate silicon oxide capacitor (e.g., a capacitor implemented in a metal oxide semiconductor arrangement).

[0093] In some examples, both ends of the channel associated with transistor 565-a may be directly connected to the corresponding signal line 265-a (e.g., via a metal connection). In some other examples, one or both ends of the channel associated with transistor 565-a may be connected to the corresponding signal line 265-a via an optional connection (e.g., another transistor (not shown)). Transistor 565-a-1 may support the voltage of shift signal line 265-a-1, and transistor 565-a-2 may support the voltage of shift signal line 265-a-2, and so on. As described, the gates of at least a corresponding pair of transistors 565-a (e.g., where transistors 565-a-1 and 565-a-2 may be an example of this pair) may be biased in common (e.g., using a shared variable voltage source 540, via a voltage V GL associated gate line 570).

[0094] Sense amplifier 270-a illustrates an example of a circuit system configured to detect a logic state based at least in part on comparing a first sense signal (e.g., of signal line 265-a-1) to a second sense signal (e.g., of signal line 265-a-a). Sense amplifier 270-a includes: a first node (node ​​A) configured to couple with first signal line 265-a-1, which may be an example of first node 271; and a second node (node ​​B) configured to couple with second signal line 265-a-2, which may be an example of second node 272. Sense amplifier 270-a also includes: a third node (node ​​C), which may be referred to as a high sense amplifier supply node; and a fourth node (node ​​D), which may be referred to as a low sense amplifier supply node. The example of sense amplifier 270-a illustrates a configuration having a pair of cross-coupled p-type transistors and a pair of cross-coupled n-type transistors. However, other configurations of sense amplifier 270 may be used in accordance with the described techniques, including a pair of relative differential amplifiers coupled between the first node and the second node. In some examples, doped portions of a substrate (eg, substrate 420 ) may be used to implement transistors of sense amplifier 270 - a and other transistors that support operation of circuit 500 .

[0095] Figure 6 A timing diagram 600 is shown illustrating the operation of an example access operation in support of a signal generation circuitry topology in a memory device according to examples as disclosed herein. Figure 5 The components of circuit 500 are depicted to describe an example access operation.

[0096] Prior to the access operation of timing diagram 600 (e.g., prior to 601), components of circuit 500 may be in various states that may include an initial state. For example, each of switch components 530-a and 530-b may be open or deactivated (e.g., via deactivated logic signals SW1 and SW2 to deactivate sense amplifier 270-a). In some examples, transistor 550-a may be deactivated (e.g., via deactivated logic signals SEL1 and SEL2 to isolate digital line 130-b from signal line 265-a to deselect the level of memory cell 105-b), transistor 555-a may be activated (e.g., via activated logic signals SH1 and SH2 to support shunting between digital line 130-b and plate line 140-b), transistor 560-a may be activated (e.g., via activated logic signals EN1 and EN2 to support grounding of signal line 265-a), and the gate of transistor 565-a may be activated with an initial voltage (e.g., V G1 , which may be a ground voltage, biased via a deactivated logic signal VV). In some examples, digit line 130-b and plate line 140-b may be grounded (eg, at a voltage of 0V).

[0097] Further, prior to the access operation of timing diagram 600, memory cells 105-b-1 and 105-b-2 may be written according to a logic state (e.g., a shared logic state). For example, one of memory cells 105-b may be written with a negative polarization (e.g., charge state 305-a, by applying voltage 315) and the other of memory cells 105-b may be written with a positive polarization (e.g., charge state 310-a, by applying voltage 325), where the relative polarization difference between memory cells 105-b-1 and 105-b-2 may be associated with the written logic state. The operation of timing diagram 600 may illustrate aspects of a read operation that determines the written logic state based on differential signaling from accessing memory cells 105-b-1 and 105-b-2.

[0098] At 601, an access operation may include disabling shunting of digit line 130-b. For example, logic signals SH1 and SH2 may be deactivated, which may isolate digit lines 130-b-1 and 130-b-2 from plate line 140-b (e.g., based on deactivating transistors 555-a-1 and 555-a-2, respectively).

[0099] At 602, the access operation may include shifting (eg, boosting) the voltage applied to the gate of transistor 565-a. For example, logic signal VV may be activated, which may shift variable voltage source 540 from a voltage V G1 The bias gate line 570 is converted to a voltage V G2 Gate line 570 is biased. In some examples, the voltage of signal line 265-a may not be affected (eg, may remain at 0V during operation of 602) (eg, due to grounding via transistor 560-a).

[0100] At 603, the access operation may include disabling grounding of signal line 265-a. For example, logic signals EN1 and EN2 may be deactivated, which may isolate signal lines 265-a-1 and 265-a-2 from ground nodes 510-a-1 and 510-a-2, respectively (e.g., based on deactivating transistors 560-a-1 and 560-a-2, respectively). In some examples, after the operation of 603, signal lines 265-a-1 and 265-a-2 may be in a floating state, but may be maintained at or near 0V.

[0101] At 604, the access operation may include selecting digit lines 130-b-1 and 130-b-2, which may involve a level selection operation. For example, logic signals SEL1 and SEL2 may be activated, which may couple digit line 130-b-1 with signal line 265-a-1 and digit line 130-b-2 with signal line 265-a-2 (e.g., based on activating transistors 550-a-1 and 550-a-2, respectively).

[0102] At 605, the access operation may include selecting memory cells 105-b-1 and 105-b-2, which may involve a cell selection operation. For example, logic signals WL1 and WL2 may be activated, which may couple the storage element (e.g., capacitor 220) of memory cell 105-b-1 with digit line 130-b-1 and the storage element of memory cell 105-b-2 with digit line 130-b-2 (e.g., based on activating cell selection components, such as cell selection components 230 of memory cells 105-b-1 and 105-b-2, respectively). In some examples, the operation of 605 may also include transitioning plate line 140-b from a low voltage (e.g., a ground voltage) to a voltage that supports reading memory cells 105-b-1 and 105-b-2. However, in some other examples, such biasing of plate line 140-b may be performed before or after the operation of 605 (e.g., before the operation of 606).

[0103] In some examples, a bias (eg, V PL The difference between the voltage of the reference node 510-a and the voltage of the ground node 510-a may correspond to Figure 3B 335 is depicted. In some examples, this biasing by plate line 140-b may correspond to a "plate high" read bias on memory cell 105-b. In response to the biasing of 605, and the selection of memory cells 105-b-1 and 105-b-2, charge may flow between the storage elements of memory cells 105-b-1 and 105-b-2 and signal lines 265-a-1 and 265-a-2, respectively, thereby generating different voltages on signal lines 265-a-1 and 265-a-2 (e.g., due to different polarizations of memory cells 105-b-1 and 105-b-2).

[0104] In the example of timing diagram 600, memory cell 105-b-1 may be associated with storage charge state 305-a such that V sig,1 may rise to a relatively high level (e.g., associated with charge state 305-c), and memory cell 105-b-2 may be associated with storage charge state 310-a, such that V sig,2may rise to a relatively low level (eg, associated with charge state 310-c). V sig,1 With V sig,2 However, in some examples (e.g., due to the transistor configuration of sense amplifier 270-a), it may be beneficial to perform the evaluation when one of signal lines 265-a is above a reference voltage (e.g., ground voltage) and the other signal line 265-a is below the reference voltage.

[0105] At 606, the access operation may include shifting (eg, lowering, shifting, offsetting) the voltage applied to the gate of transistor 565-a. For example, logic signal VV may be deactivated, which may switch variable voltage source 540 from using voltage V G2 The bias gate line 570 is converted to a voltage V G1 The gate line 570 is biased. In response, the voltages of the signal lines 265-a-1 and 265-a-2 may each shift (e.g., drop) due to the shift in the voltage applied to the gate of the transistor 565-a and the capacitance between the gate and the channel of the transistor 565. Thus, the capacitance between the structures of the transistor 565 may be utilized (e.g., as a capacitor) to pull down the voltages of the signal lines 265-a-1 and 265-a-2, such that after the operation of 606, the voltage of one of the signal lines 265-a (e.g., signal line 265-a-1) may be higher than the reference voltage (e.g., higher than 0V) and the voltage of the other of the signal lines 265-a (e.g., signal line 265-a-2) may be lower than the reference voltage (e.g., higher than 0V).

[0106] At 607, the access operation may include determining the logic states stored by memory cells 105-b-1 and 105-b-2, which may include V sig,1 With V sig,2 520-b and node D of sense amplifier 270-a with voltage source 520-a (e.g., based on activating switch components 530-b and 530-a, respectively). In some examples, this latching may be performed after isolating node C from signal line 265-a-1 and node D from signal line 265-a-2 (e.g., via isolation transistors, not shown).

[0107] The access operation may include or be followed by various subsequent operations at 608. In some examples (where operations 605 through 607 involve disturbing the polarization state of any of memory cells 105-b), after the logic state is determined, the logic state may be written back to memory cells 105-b-1 and 105-b-2, which may involve applying a write bias to one of memory cells 105-b (e.g., memory cell 105-b-2, which may have been at least partially depolarized during operation of 605, but not memory cell 105-b-1, which may not have been depolarized during operation of 605) or applying a write bias to both memory cells 105-b. In some instances, at 608, the access operation may include or be followed by various operations that return circuit 500 to one or more initial conditions (e.g., deactivating logic signals SW1 and SW2, deactivating transistor 550-a, activating transistor 555-a, activating transistor 560-a, biasing the gate of transistor 565-a with an initial voltage).

[0108] The order of operations shown in the timing diagram 600 is for illustrative purposes, and various other orders and combinations of steps (e.g., in concurrent operations) may be performed to support the described techniques. Further, the timing of the operations of the timing diagram 600 is also for illustrative purposes and is not intended to indicate a specific relative duration between one operation and another operation. Various operations according to the examples disclosed herein may be performed over a relatively shorter or relatively longer duration than the durations described in the various examples of the present disclosure. Further, the various operations illustrated in the timing diagram 600 may be performed over overlapping or concurrent durations to support the techniques described herein.

[0109] The transitions of the logic signals of timing diagram 600 illustrate transitions from one state to another, and generally reflect transitions between an enabled or activated state (e.g., state "0") and a disabled or deactivated state (e.g., state "1") as associated with a particular numbered operation. In various examples, a state may be associated with a particular voltage of a logic signal (e.g., a logic input voltage applied to the gate of a transistor operating as a switch), and a voltage change from one state to another may not be instantaneous. Instead, in some examples, a voltage associated with a logic signal may follow a curve from one logic state to another over time. Thus, the transitions shown in timing diagram 600 do not necessarily indicate instantaneous transitions. Further, the initial state of a logic signal associated with a transition at a numbered operation may be reached during various times prior to the numbered operation while still supporting the described transition and associated operations.

[0110] Figure 7An example of a memory structure 700 supporting a layout of signal generation circuitry in a memory device according to an example as disclosed herein is illustrated. The memory structure 700 may illustrate a portion of a memory device 100 or a memory die that may be formed with or over a substrate 420-a, which may be a reference Figure 4 4. The memory structure 700 may be used to implement the reference Figure 5 500. For example, memory structure 700 may illustrate an example of a structure for implementing circuitry associated with a first signal line 265 (e.g., signal line 265-a-1 of circuit 500), which may be associated with signal line conductor 735-a-1. In some examples, a similar structure (e.g., a structure that is substantially symmetrical across the yz plane) may be implemented for circuitry associated with a second signal line 265 (e.g., signal line 265-a-2 of circuit 500), which may be associated with signal line conductor 735-b-1 and column decoder 745-b, although such similar structure is omitted for illustrative clarity.

[0111] For illustrative purposes, aspects of memory structure 700 may be described with reference to the x-, y-, and z-directions of coordinate system 701. The z-direction may describe a direction relative to (e.g., perpendicular to) a surface of substrate 420-a (e.g., a surface in an xy plane, a surface on or over which other materials may be deposited), and each of the related structures illustrated by their respective cross-sections in the xz plane may extend a distance or repeat a certain amount (e.g., according to a pitch dimension), or both, along the y-direction. In some examples, for illustrative purposes, the x-direction may be aligned with or referred to as a column direction (e.g., along a column of memory cells), and the y-direction may be aligned with or referred to as a row direction (e.g., along a row of memory cells 105).

[0112] Memory structure 700 illustrates an example of memory arrays 110 associated with different levels 705 (e.g., different layers, a stack of layers, a stack of levels). For example, memory array 110-c-1 may be associated with level 705-a-1 at a first position (e.g., height) relative to substrate 420-a, and memory array 110-c-2 may be associated with level 705-a-2 at a second (e.g., different) position relative to substrate 420-a (e.g., above level 705-a-1 relative to substrate 420-a). Although memory structure 700 illustrates an example with two levels 705-a, the techniques described herein may be applied to memory structures with any number of one or more levels 705.

[0113] At least some, if not all, of the memory arrays 110-c may include a set of respective memory cells 105-c arranged according to rows (e.g., aligned in the y-direction, addressed according to positions in the x-direction) and columns (e.g., aligned in the x-direction, addressed according to positions in the y-direction). For example, a column of memory cells 110-c-1 may include n memory cells 105-c-11 through 105-c-1n and may be associated with (e.g., formed on, formed in contact with, coupled to) a digit line conductor 710-a-11 (e.g., an instance of digit line 130). In some examples, a column of memory array 110-c-2 may include the same number of memory cells 105-c, which may or may not be physically aligned (e.g., in the z-direction) or overlap (e.g., when viewed in the xy plane) with the memory cells 105-c of the memory array 110-c-1. A certain number (m) of columns may be formed by repeating the illustrated memory cells 105-c and digit line conductors 710-c, as well as other features, along the y-direction.

[0114] At least some, if not each, of the memory cells 105-c in the memory structure 700 may include a respective capacitor 220-b and a respective cell select component 230-b (e.g., a transistor). In the example of the memory structure 700, each of the cell select components 230-b may be formed as a vertical transistor that may include a channel portion (e.g., a vertical channel) formed at least in part by the respective pillar 715-a or a portion thereof (e.g., along the z-direction), and a gate portion formed at least in part by the respective word line conductor 720-a (e.g., an example of word line 120). In some examples, the gate portion of the cell select component 230-b may be a portion or region of the word line 120 or word line conductor 720-a operable to activate the channel portion of the cell select component 230-b (e.g., modulate the conductivity of the channel portion). The word line conductor 720-a may extend from one memory cell 105-c to another memory cell 105-c along a direction, for example, the y-direction (e.g., the row direction, along a row of memory cells 105-c), and may be coupled to a row component 125 (not shown) for selecting (e.g., activating) the row of memory cells 105-c (e.g., by biasing the word line conductor 720-a).

[0115] In some examples, the word line conductor 720-a of one memory cell 110-c (e.g., memory array 110-c-1) may be coupled with the word line conductor 720-a of another memory array 110-c (e.g., memory array 110-c-2, memory array 110-c operable to couple with signal line conductor 735-b) so that a row of memory cells 105-c may be activated in common across multiple memory arrays 110-c or multiple levels 705-a (e.g., by sharing a common node or output of row component 125, not shown). In some examples, the interconnections between the word line conductors 720-a of different levels 705-a may be formed at least in part along the z-direction by one or more vias, trenches, or TSVs, which may be positioned at or near a boundary of the memory array 110-c (e.g., along the y-direction), as well as other locations relative to the memory array 110-c.

[0116] Each capacitor 220-b of a memory cell 105-c may include a respective dielectric portion 725-a formed between a pillar 715-a associated with the memory cell 105-c or a portion otherwise aligned with the pillar (e.g., a portion aligned in the z-direction, an inner portion of the capacitor 220-b) and a plate conductor 730-a (e.g., a plate line 140, a plate node or a common plate, an outer portion of the capacitor 220-b). For example, each capacitor 220-b may include a respective inner portion aligned in the z-direction or otherwise coincident with the pillar 715-a, and a respective outer portion separated from the inner portion by a respective dielectric portion 725-a (e.g., at least partially concentric around the inner portion). In some examples, the outer portions of two or more capacitors 220-b may be a continuous material, such as a continuous metal or other conductor of a plate line or a common plate node (e.g., of the plate conductor 730-a). In some examples, a portion of the pillar 715-a of the capacitor 220-b may be the same material or material combination as a portion of the pillar 715-a of the corresponding cell selection component 230-b (e.g., a doped semiconductor material, a polycrystalline semiconductor). In some examples, a portion of the pillar 715-a of the capacitor 220-b may be or include a different material or material combination than a portion of the pillar 715-a of the corresponding cell selection component 230-b (e.g., a metal or conductor portion, a metal layer deposited on or above the surface of the pillar 715-a). In some examples, the dielectric portion 725-a may be formed of a ferroelectric material that is operable to maintain a non-zero charge or polarization (e.g., corresponding to a stored logic state) in the absence of an electric field.

[0117] In the example of memory structure 700, memory array 110-c-1 can be associated with (e.g., coupled with, including, accessed using) plate conductor 730-a-1 and memory array 110-c-2 can be associated with plate conductor 730-a-2. Each of plate conductors 730-a can be coupled with plate component 145 (not shown) for biasing plate conductor 730-a. In the example of memory structure 700, each plate conductor 730-a can be associated with at least one column of memory cells 105-c. In some examples, each of plate conductors 730-a can also extend along the row of memory cells 105-c in the y-direction, in which case each of plate conductors 730-a can be associated with all memory cells 105-c of the respective memory array 110-c. In some examples, the plate conductor 730-a may be a metal or other conductor formed over or between the dielectric portions 725-a of the memory cells 105-c of the corresponding memory array 110-c.

[0118] In the example of memory structure 700, each column of memory cells 105-c of each memory array 110-c can be associated with a corresponding transistor 550-b (e.g., a layer select transistor), which can also be formed as a vertical transistor. Each transistor 550-b can be operable to couple a corresponding digit line conductor 710-a with a corresponding signal line conductor 735-a (e.g., an example of signal line 265). In the example of memory structure 700, each signal line conductor 735-a can be a combination of a horizontal metal layer formed in contact with a pillar 740-a (e.g., above, opposite to the digit line conductor 710-a) and a vertical portion coupled to a column decoder 745-a, which can be formed by one or more vias, slots, or TSVs. In the example of the memory structure 700, to support m columns of each memory array 110-c, m signal line conductors 735-a can be formed along the y direction, and each signal line conductor 735-a can be coupled to the transistor 550-b of each memory array 110-c or each level 705-a (for example, the signal line conductor 735-a-1 is coupled to the transistors 550-b-11 and 550-b-21).

[0119] At least some, if not every, transistor 550-b may include a channel portion (e.g., a vertical channel) formed at least in part by one or more respective pillars 740-a and a gate portion formed at least in part by one or more respective conductors 741-a (e.g., examples of level select lines, one of which may convey a logic signal SEL1). In some examples, the gate portion of transistor 550-b may be a portion or region of a level select line operable to activate (e.g., modulate the conductivity of) the channel portion of transistor 550-b. Conductor 741-a may extend from one column of memory cells 105-c to another column, or from one transistor 550-b to another transistor, in a direction such as the y-direction (e.g., in a row direction, parallel to the rows of memory cells 105-c), and may be coupled with a level decoder (not shown) for selecting or activating memory array 110-c (e.g., by biasing conductor 741-a, by activating the row of transistor 550-b).

[0120] A set of m signal line conductors 735-a may be coupled to a column decoder 745-a, which in turn may be coupled to a sensing component 150-c. Thus, a combination of a plane decoder (not shown) and a column decoder 745-a may be used to multiplex, address, or otherwise selectively couple the digit line conductors 710-a of the memory arrays 110-c-1 and 110-c-2 with the sensing component 150-c or its sense amplifier 270 to support various access operations. In some examples, the column decoder 745 may be omitted so that the signal line conductors 735-a may be coupled directly to the sensing component 150-c.

[0121] In the example of memory structure 700, each column of memory cells 105-c of each memory array 110-c may also be associated with a corresponding transistor 555-b (e.g., a shunt transistor), which may also be formed as a vertical transistor. Each transistor 555-b may be operable to couple a corresponding digit line conductor 710-a with a conductor portion 750-a (e.g., a corresponding conductor portion 750-a of digit line conductor 710-a, a conductor portion 750-a common to digit line conductors 710-a of memory array 110-c, or a plate connection), which conductor portion 750-a may connect or shunt the corresponding digit line conductor 710-a with plate conductor 730-a.

[0122] At least some, if not every, transistor 555-b may include a channel portion (e.g., a vertical channel) formed at least in part by one or more respective pillars 755-a (e.g., between respective digit line conductors 710-a and conductor portion 750-a) and a gate portion formed at least in part by one or more respective conductors 756-a (e.g., examples of level shunt lines, one of which may transmit logic signal SH1). In some examples, the gate portion of transistor 555-b may be a portion or region of a level shunt line operable to activate the channel portion of transistor 555-b (e.g., to modulate the conductivity of the channel portion). Conductor 756-a may extend from one column of memory cells 105-c to another column, or from one transistor 555-b to another transistor, in a direction such as the y-direction (e.g., in a row direction, parallel to the rows of memory cells 105-c), and may be coupled to a layer decoder (not shown) for shunting the memory array 110-c (e.g., by biasing conductor 756-a, by activating rows of transistors 555-b).

[0123] Conductor portion 750-a or its functionality may be provided by various types of structures. In an example of memory structure 700, each of conductor portions 750-a may include a horizontal conductor portion (e.g., a metal layer, at least a portion aligned along the x-direction) formed in contact with one or more pillars 755-a (e.g., above, opposite to digit line conductor 710-a) and in contact with one or more plate conductors 730-a. In various examples, conductor portion 750-a may be formed using one or more common processes or materials as the formation of signal line conductor 735-a or the formation of plate conductor 730-a, or both. In some examples, conductor portion 750-a may include multiple horizontal conductor portions, one or more vertical conductor portions (e.g., slots, vias), or any combination thereof.

[0124] In some examples, the functionality of conductor portion 750 may be provided by a "short" or dummy cell or capacitor (not shown). For example, conductor portion 750 may include a portion that is aligned with and in contact with one or more pillars 755-a, or a material portion or extension of pillar 755-a, which may have similar materials, similar dimensions, or other aspects similar to the inner portion of capacitor 220-b. Additionally or alternatively, conductor portion 750 may include a portion having similar materials, similar dimensions, or other aspects similar to the outer portion of capacitor 220. In such cases, conductor portion 750 may be formed with one or more processes also used to form capacitor 220-b, but dielectric portion 725 may be omitted.

[0125] In the example of memory structure 700, each signal line conductor 735-a can be associated with a corresponding transistor 560-b (e.g., a grounding transistor), which can also be formed as a vertical transistor. Each transistor 560-b can be operable to couple the corresponding signal line conductor 735-a with a ground conductor 765-a (e.g., a corresponding ground conductor 765-a of the signal line conductor 735-a, a common ground conductor 765-a of the signal line conductor 735-a, a ground plane associated with the ground node 510), which can support grounding the corresponding signal line conductor 735-a (e.g., through one or more vias or other intermediate conductors).

[0126] At least some, if not every, transistor 560-b may include a channel portion (e.g., a vertical channel) formed at least in part by one or more respective pillars 760-a (e.g., between signal line conductor 735-a and ground conductor 765-a) and a gate portion formed at least in part by one or more respective conductors 761-a (e.g., an example of a ground activation line that may transmit logic signal EN1). In some examples, the gate portion of transistor 560-b may be a portion or region of a ground activation line operable to activate a channel portion of transistor 560-b (e.g., modulate the conductivity of the channel portion). Conductor 761-a may extend from one transistor 560-b to another transistor in a direction such as the y-direction (e.g., in a row direction) and may be coupled with row component 125, column component 135, sensing component 150, or other components (not shown) for grounding signal line conductor 735-a (e.g., through bias conductor 761-a, through activating a row of transistors 560-b).

[0127] In the example of memory structure 700, each signal line conductor 735-a may also be associated with a corresponding transistor 565-b (e.g., a deflection transistor, a deflection capacitor), which may also be formed as a vertical transistor. Each transistor 565-b may be operable to shift (e.g., boost, reduce, shift, deflect) the voltage of the corresponding signal line conductor 735-a (e.g., based on biasing through a variable voltage source 540, not shown, based on operating the transistor 565-b as a capacitor). At least some (if not each) transistor 565-b may include a channel portion (e.g., a vertical channel) formed at least in part by one or more corresponding pillars 770-a (e.g., between the signal line conductor 735-a and the intermediate conductor 775-a) and a channel portion (e.g., a vertical channel) formed at least in part by one or more corresponding conductors 771-a (e.g., an example of a gate line that can transmit a voltage V GL) The gate portion formed by the conductor 771-a. The conductor 771-a can extend from one transistor 565-b to another transistor in a direction such as the y-direction (e.g., in the row direction) and can be coupled to a variable voltage source 540 (not shown) for shifting the voltage of the signal line conductor 735-a (e.g., through the bias conductor 771-a).

[0128] In the example of memory structure 700, each signal line conductor 735-a may also be associated with a corresponding transistor 780-b, which may also be formed as a vertical transistor. Each transistor 780-b may be operable to couple the corresponding signal line conductor 735-a with the corresponding intermediate conductor 775-a, which may support the voltage deflection capability of the transistor 565-b coupled with the corresponding intermediate conductor 775-a. At least some (if not each) transistor 780-a may include a channel portion (e.g., a vertical channel) at least partially formed by one or more corresponding pillars 785-a (e.g., between the signal line conductor 735-a and the intermediate conductor 775-a) and a gate portion at least partially formed by one or more corresponding conductors 786-a. The conductor 786-a may extend from one transistor 780-a to another transistor along a direction such as the y-direction (e.g., along the row direction). In some examples, pillars 770-a and 785-a may collectively relate to the same pattern as pillar 760-a (e.g., along the x-direction, along the y-direction), but are positioned on different levels 705 (e.g., along the z-direction) and implemented according to different gate arrangements and biases. Although transistors 565-b and 780-a are illustrated as being associated with a level 705-a that is higher than the level 705-a associated with transistor 560-b, this relative arrangement may be swapped in some other examples.

[0129] In some examples, transistor 780-a may be activated according to various techniques to support operation of memory structure 700. In some examples, the transistor may be configured in an "always on" configuration, wherein conductor 786-a may be activated whenever power or voltage is applied or provided to memory structure 700, or whenever memory structure 700 is operable to support an access operation (e.g., operating in an active mode). In some examples, transistor 780-a may be configured to be activated during access of memory array 110-c-1 or memory array 110-c-2, or both. In some examples, transistor 780-a may be activated when the corresponding memory array 110-c is selected for an access operation, in which case the corresponding transistor 550-b and the corresponding transistor 780-a may be activated (e.g., during access of memory array 110-c-1, transistor 550-b-11 and 780-a-1, and the corresponding repeating transistors, are activated in the y direction). In some examples, a layer decoder and other circuitry may be used to perform this combination or concurrent activation. Although the example of memory structure 700 includes transistor 780-a, in some examples, transistor 780-a may be replaced with a metal conductor (e.g., via, slot, TSV) that electrically connects signal line conductor 735-a to corresponding intermediate conductor 775-a, or intermediate conductor 775-a may extend (e.g., in the x-direction) to connect directly with signal line conductor 735-a (e.g., where signal line conductor 735-a may include horizontal portions that coincide with top and bottom ends of pillar 770-a).

[0130] In various examples, each of the pillars 715, 740, 755, 760, 770, and 785 is operable to support at least a portion of a channel of a corresponding transistor (e.g., a channel aligned along the z-direction or an operable conduction path that supports electrical coupling or a conduction path between source and drain terminals based at least in part on a voltage of a corresponding gate portion, gate terminal, or gate conductor), and may include one or more doped semiconductor portions. For example, to support an n-type transistor, such pillars may include at least a p-type semiconductor portion, or may include a stack (e.g., along the z-direction) of an n-type semiconductor, a p-type semiconductor, and an n-type semiconductor (e.g., in an NPN arrangement along the z-direction), as well as other constituent materials or arrangements. To support a p-type transistor, such pillars may include at least an n-type semiconductor portion, or may include a stack (e.g., along the z-direction) of a p-type semiconductor, an n-type semiconductor, and a p-type semiconductor (e.g., in a PNP arrangement along the z-direction), as well as other constituent materials or arrangements. In some examples, a pillar as described herein can include one or more electrode portions, such as electrodes at one or both ends (eg, the top end, the bottom end, or both) of the pillar.

[0131] Each of the pillars 715, 740, 755, 760, 770, and 785 may be associated with a height or height dimension relative to the substrate (e.g., a lower range in the z-direction, an upper range in the z-direction, a span in the z-direction) that may be defined as part of balancing various performance criteria of the memory array 110. In some examples, the height dimension or range of the pillars associated with the same level 705 along the z-direction may be equal or at least partially overlap. For example, the pillars 715, 740, 755, or 760 associated with level 705-a-1 or the pillars 715, 740, 755, 770, or 785 associated with level 705-a-2, or various combinations of both, may have a common height dimension relative to the substrate (e.g., a common upper range, a common lower range, or both). In some examples, a pillar 715 may have a height or height dimension that is different from other pillars (e.g., a pillar 715 having an extended height along the z-direction to support one or more features of the capacitor 220). Pillars 715, 740, 755, 760, 770 and 785 can be formed to have various cross-sectional shapes (e.g., in the xy plane), such as square, rectangular, circular, elliptical or polygonal, among others, wherein pillars 715, 740, 755, 760, 770 and 785 can have common or different shapes, or common or different sizes.

[0132] Pillars 715, 740, 755, 760, 770, and 785 may be formed according to various techniques. In some examples, one or more layers or layer stacks of doped semiconductor material may be deposited on or over a substrate (e.g., on or in contact with digit line conductor 710, ground conductor 765, or intermediate conductor 775, or a corresponding metal layer), and portions of the deposited layers positioned between respective pillars (e.g., along the x-direction, along the y-direction) may be etched away or grooved to form respective pillars. In some examples, combinations of pillars 715, 740, 755, 760, 770, and 785 of the same level 705 may be formed of the same material or combination of materials (e.g., formed of the same layer or layer stack to support a common type of transistor channel). In some examples, such layers may include one or more electrode layers (e.g., an electrode layer above a stack of doped semiconductor material layers, an electrode layer below a stack of doped semiconductor material layers, or both), and such electrode layers may or may not be etched or grooved along with the pillar formation process. Additionally or alternatively, in some examples, holes or trenches may be etched through the material (e.g., in the z-direction, through the dielectric material, through the gate dielectric material) and the material of the pillars 715, 740, 755, 760, 770, and 785 (e.g., one or more doped semiconductor materials, one or more electrode materials) may be deposited in the etched holes or trenches. In examples where the pillar material is deposited into the holes, trenches, or other recesses, the pillars 715, 740, 755, 760, 770, and 785 of the same level 705 may be formed of the same material or combination of materials (e.g., using a common material deposition operation), or may be formed of different materials or combinations of materials (e.g., using different material deposition operations, which may support transistors with different channel types).

[0133] In various examples, the number or configuration of pillars 715, 740, 755, 760, 770, and 785 for the respective transistors may be defined or selected for particular characteristics, such as the associated drive strength (e.g., drive current), impedance, activation threshold, or leakage characteristics of a particular transistor or group of transistors. In some examples, multiple pillars may be described or configured as parallel physical structures (e.g., parallel channels) of a common transistor or transistor component. For example, as illustrated, each of transistors 550-b may include or otherwise be formed to have two pillars 740-a, each of transistors 555-b may include or otherwise be formed to have two pillars 755-a, and so on. However, in other examples, each of such transistors may respectively include or otherwise be formed to have any number of one or more pillars. Similarly, in various examples, capacitor 220 may be formed with or formed over any number of one or more pillars 715. In some instances, each pillar of a group configured in parallel (e.g., activated together) may be described or configured as a component of a single transistor, such that the corresponding cell selection, level selection, or level shunt may be described or configured as having multiple transistors arranged in parallel.

[0134] In some examples, various combinations of gate conductors (e.g., word line conductors 720-a, conductors 741-a, conductors 756-a, conductors 761-a, conductors 771-a, conductors 786-a) of a given level 705-a may be formed using one or more common operations, one or more common materials, or otherwise share various aspects of formation or configuration. For example, such gate conductors may be formed using one or more common conductor formation processes (e.g., a common masking process, a common etching process, a common deposition process, or various combinations thereof). In some examples, such gate conductors may be formed to have a height dimension that is within or overlaps a height dimension of the pillar corresponding to at least the doped semiconductor portion of the pillar.

[0135] In various examples, gate conductors (e.g., word line conductor 720-a, conductor 741-a, conductor 756-a, conductor 761-a, conductor 771-a, conductor 786-a) may be formed of a metal or metal alloy (e.g., copper, tungsten, gold, silver, tin, aluminum, or alloys thereof). Such conductors may be separated from corresponding pillars (in the x-direction, in the y-direction, in the x-direction and y-direction, in the radial direction) by a gate dielectric that contacts portions of the conductors and the corresponding pillars. In some examples, the gate conductors may be positioned alongside the corresponding pillars (e.g., as lateral gates, as bypass gates, as a pair of gate conductors on either or both sides of the pillars), including conductors that extend between the pillars in the y-direction and are separated from the pillars in the x-direction by a gate dielectric. In some examples, the gate conductor may include at least a portion that is wrapped (e.g., partially, completely) around a respective pillar (e.g., as a wrap-around gate, as a circumferential gate, as a concentric gate, as a fully wrap-around gate), wherein at least the respective pillar may be wrapped (e.g., partially wrapped, completely wrapped) with a circumferential gate dielectric that is in contact with the pillar and the conductor. In various examples, the digit line conductor 710-a, signal line conductor 735-a, ground conductor 765-a, and intermediate conductor 775-a, as well as other components such as conductors, may be formed of a metal or metal alloy, which may be the same material or a different material than the conductor used to support the gate portion of the transistor (e.g., the gate conductor).

[0136] In some examples, the circuitry of the level decoder (not shown), column decoder 745-a, or sensing component 150-c, or any combination thereof, may be substrate-based, such as including transistors formed at least in part from doped portions of substrate 420-a (e.g., transistors configured in a CMOS arrangement according to transistor structure 400). By including transistors 550-b, 555-b, 560-b, and 565-b in locations above substrate 420-a (e.g., in multiple levels 705-a), memory structure 700 may support improved flexibility for distributing signal generation circuitry throughout the memory die, which may improve area utilization or semiconductor substrate material utilization, among other advantages.

[0137] Figure 8 A block diagram 800 of a memory device 820 is shown that supports a signal generation circuitry layout in a memory device according to an example as disclosed herein. The memory device 820 may be a memory device as described in reference to Figures 1 to 7820, or various components thereof, may be examples of means for performing various aspects of the signal generation circuitry layout as described herein. For example, the memory device 820 may include a voltage source coupling component 825, a voltage generation component 830, a voltage deflection component 835, a sensing component 840, a cell select transistor 845, a level select transistor 850, a deflection shunt component 855, a voltage select transistor 860, a voltage deflection transistor 865, or any combination thereof. Each of these components may communicate with each other, directly or indirectly (e.g., via one or more buses).

[0138] The voltage source coupling component 825 may be configured as or otherwise support means for isolating a conductor of the memory die from a voltage source based at least in part on deactivating a first transistor associated with a first level of the memory die above the substrate. The voltage generating component 830 may be configured as or otherwise support means for generating a first voltage at a conductor of the memory die based at least in part on coupling a storage element of a memory cell with a digit line and coupling the digit line with the conductor. The voltage deflecting component 835 may be configured as or otherwise support means for shifting the conductor from a first voltage to a second voltage based at least in part on shifting a bias voltage applied to a gate of a second transistor associated with a second level of the memory die above the substrate from a third voltage to a fourth voltage, the second transistor having a channel portion coupled between a first portion of the conductor and a second portion of the conductor. The sensing component 840 may be configured as or otherwise support means for determining a logic state based at least in part on the voltage deflecting component 835 shifting the conductor from a first voltage to a second voltage.

[0139] In some examples, coupling a storage element of the memory cell with a digit line can be based at least in part on voltage generation component 830 activating a first channel associated with one or more first semiconductor pillars of the memory die coupled between the storage element and the digit line. In some examples, coupling the digit line with a conductor can be based at least in part on voltage generation component 830 activating a second channel associated with one or more second semiconductor pillars of the memory die coupled between the digit line and the conductor, wherein the one or more second semiconductor pillars overlap the one or more first semiconductor pillars along a height dimension relative to the substrate.

[0140] In some instances, deactivating the first transistor may be based at least in part on deactivating a third channel associated with one or more third semiconductor pillars of the memory die coupled between the conductor and the voltage source based on the voltage source coupling component 825, wherein the one or more third semiconductor pillars overlap with the one or more first semiconductor pillars along a height dimension relative to the substrate.

[0141] In some examples, a channel portion of the second transistor is associated with one or more fourth semiconductor pillars of the memory die that overlap the one or more first semiconductor pillars along a height dimension relative to the substrate.

[0142] In some examples, a first end of the channel portion of the second transistor is coupled to the first conductor, and the deflection shunt component 855 can be configured as or otherwise support means for activating a fifth transistor associated with the second level of the memory die, the fifth transistor having a channel portion coupled between the second end of the channel portion of the second transistor and the conductor. In some examples, the first end of the channel portion of the second transistor can be coupled to the conductor and the second end of the channel portion of the second transistor can be coupled to the conductor.

[0143] In some examples, the voltage source is associated with a ground voltage.

[0144] In some examples, the voltage source coupling component 825 may be configured as or otherwise support means for isolating a second conductor of the memory die from a voltage source based at least in part on deactivating a third transistor associated with the first level of the memory die. In some examples, the voltage generating component 830 may be configured as or otherwise support means for generating a fifth voltage at a second conductor of the memory die based at least in part on coupling a storage element of a second memory cell to a second digit line and coupling the second digit line to a second conductor. In some examples, the voltage deflecting component 835 may be configured as or otherwise support means for shifting the second conductor from a fifth voltage to a sixth voltage based at least in part on shifting a bias voltage applied to a gate of a fourth transistor associated with the second level of the memory die from a seventh voltage to an eighth voltage, the fourth transistor having a channel portion coupled between a first portion of the second conductor and a second portion of the second conductor. In some examples, the sensing component 840 may be configured as or otherwise support means for determining a logic state based at least in part on the voltage deflecting component 835 shifting the second conductor from the fifth voltage to the sixth voltage.

[0145] In some examples, determining the logic state is based at least in part on comparing the second voltage to the sixth voltage.

[0146] Fig. 9 A flowchart illustrating a method 900 for supporting a signal generation circuit system layout in a memory device according to an example as disclosed herein is shown. The operations of the method 900 may be implemented by a memory device or components thereof as described herein. For example, the operations of the method 900 may be implemented by a memory device or components thereof as described herein. Figures 1 to 8 The memory device described herein may be used to perform the functions described herein. In some examples, the memory device may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0147] At 905, the method may include isolating a conductor of the memory die from a voltage source based at least in part on deactivating a first transistor associated with a first level of the memory die above the substrate. The operation of 905 may be performed according to examples as disclosed herein. In some examples, the memory die may be isolated from a voltage source as described in reference to Figure 8 The voltage source coupling component 825 is described to perform aspects of the operation of 905 .

[0148] At 910, the method may include generating a first voltage at a conductor of the memory die based at least in part on coupling a storage element of the memory cell to a digit line and coupling the digit line to a conductor. The operation of 910 may be performed according to examples as disclosed herein. In some examples, the operation may be performed as described in reference to Figure 8 The voltage generating component 830 is described to perform aspects of the operation of 910 .

[0149] At 915, the method may include shifting the conductor from a first voltage to a second voltage based at least in part on shifting a bias voltage applied to a gate of a second transistor associated with a second level of a memory die above the substrate from a third voltage to a fourth voltage, the second transistor having a channel portion coupled between a first portion of the conductor and a second portion of the conductor. The operation of 915 may be performed according to examples as disclosed herein. In some examples, the operation may be performed by Figure 8 Aspects of the operations of voltage deflection assembly 835 performing 915 are described.

[0150] At 920, the method may include determining a logic state based at least in part on shifting the conductor from a first voltage to a second voltage. The operation of 920 may be performed according to examples as disclosed herein. In some examples, the logic state may be determined by Figure 8 Aspects of the operations of sensing component 840 performing 920 are described.

[0151] In some examples, an apparatus as described herein may perform one or several methods, such as method 900. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0152] Aspect 1: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuit systems, logic, means, or instructions for: isolating a conductor of a first level of a memory die above a substrate from a voltage source based at least in part on deactivating a first transistor associated with the memory die above a substrate; generating a first voltage at the conductor of the memory die based at least in part on coupling a storage element of a memory cell to a digit line and coupling the digit line to the conductor; shifting the conductor from the first voltage to a second voltage based at least in part on shifting a bias applied to a gate of a second transistor associated with a second level of the memory die above the substrate from a third voltage to a fourth voltage, the second transistor having a channel portion coupled between a first portion of the conductor and a second portion of the conductor; and determining a logic state based at least in part on shifting the conductor from the first voltage to the second voltage.

[0153] Aspect 2: A method, apparatus, or non-transitory computer-readable medium according to Aspect 1, wherein coupling the storage element of the memory cell to the digital line is based at least in part on activating a first channel associated with one or more first semiconductor pillars of the memory die coupled between the storage element and the digital line, and coupling the digital line to the conductor is based at least in part on activating a second channel associated with one or more second semiconductor pillars of the memory die coupled between the digital line and the conductor, wherein the one or more second semiconductor pillars overlap with the one or more first semiconductor pillars along a height dimension relative to the substrate.

[0154] Aspect 3: A method, apparatus, or non-transitory computer-readable medium according to Aspect 2, wherein deactivating the first transistor is based at least in part on deactivating a third channel associated with one or more third semiconductor pillars of the memory die coupled between the conductor and the voltage source, wherein the one or more third semiconductor pillars overlap with the one or more first semiconductor pillars along the height dimension relative to the substrate.

[0155] Aspect 4: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 2 to 3, wherein the channel portion of the second transistor is associated with one or more fourth semiconductor pillars of the memory die that overlap with the one or more first semiconductor pillars along the height dimension relative to the substrate.

[0156] Aspect 5: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 4, wherein a first end of the channel portion of the second transistor is coupled to the first conductor and the method, apparatus, and non-transitory computer-readable medium further include operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for activating a fifth transistor associated with the second level of the memory die, the fifth transistor having a channel portion coupled between a second end of the channel portion of the second transistor and the conductor.

[0157] Aspect 6: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 4, wherein a first end of the channel portion of the second transistor is coupled to the conductor and a second end of the channel portion of the second transistor is coupled to the conductor.

[0158] Aspect 7: The method, apparatus, or non-transitory computer-readable medium of any one of Aspects 1 to 6, wherein the voltage source is associated with a ground voltage.

[0159] Aspect 8: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 7, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: isolating a second conductor of the memory die from the voltage source based at least in part on deactivating a third transistor associated with the first level of the memory die; generating a fifth voltage at the second conductor of the memory die based at least in part on coupling a storage element of a second memory cell to a second digital line and coupling the second digital line to the second conductor; shifting the second conductor from the fifth voltage to a sixth voltage based at least in part on shifting a bias applied to a gate of a fourth transistor associated with the second level of the memory die from a seventh voltage to an eighth voltage, the fourth transistor having a channel portion coupled between a first portion of the second conductor and a second portion of the second conductor; and wherein determining the logic state is based at least in part on shifting the second conductor from the fifth voltage to the sixth voltage.

[0160] Aspect 9: The method, apparatus, or non-transitory computer-readable medium of aspect 8, wherein determining the logic state is based at least in part on comparing the second voltage to the sixth voltage.

[0161] It should be noted that the methods described herein are possible implementations, and that the operations and steps may be rearranged or otherwise modified and other implementations are possible. Furthermore, portions from two or more of the methods may be combined.

[0162] An apparatus is described. The following provides an overview of aspects of the apparatus as described herein:

[0163] Aspect 10: An apparatus comprising: a first digit line associated with a first level of a memory die above a substrate, the first digit line being associated with a first group of memory cells of the memory die (e.g., coupled thereto, coupled to a cell selection component thereof); a second digit line associated with a second level of the memory die above the substrate, the second digit line being associated with a second group of memory cells of the memory die (e.g., coupled thereto, coupled to a cell selection component thereof); a first transistor associated with the first level of the memory die and operable to couple the first digit line to a first conductor coupled to a sense amplifier of the memory die; a second transistor associated with the second level of the memory die and operable to couple the second digit line to the first conductor; a third transistor associated with the first level of the memory die and operable to couple the first conductor to a voltage source; and a fourth transistor associated with the second level of the memory die and having a channel portion coupled to (e.g., coupled between, electrically, physically coupled to) the first conductor and a second conductor.

[0164] Aspect 11: The apparatus of aspect 10, further comprising: a fifth transistor associated with the second level of the memory die and operable to couple the first conductor with the second conductor.

[0165] Aspect 12: The apparatus of aspect 10, wherein the second conductor is connected to the first conductor via a metal portion associated with the second level of the memory die.

[0166] Aspect 13: The apparatus of any of Aspects 10 to 12, wherein the second conductor and the second digit line overlap along a height dimension relative to the substrate.

[0167] Aspect 14: An apparatus according to any one of Aspects 10 to 13, wherein: a channel portion of the first transistor includes a group of one or more first semiconductor pillars in contact with the first digital line and the first conductor; and a channel portion of the second transistor includes a group of one or more second semiconductor pillars in contact with the second digital line and the first conductor.

[0168] Aspect 15: An apparatus according to Aspect 14, wherein: the channel portion of the third transistor includes a group of one or more third semiconductor pillars in contact with the first conductor and overlapping with the group of one or more first semiconductor pillars along a height dimension relative to the substrate; and the channel portion of the fourth transistor includes a group of one or more fourth semiconductor pillars in contact with the first conductor and overlapping with the group of one or more second semiconductor pillars along the height dimension relative to the substrate.

[0169] Aspect 16: An apparatus according to any one of Aspects 14 to 15, wherein: each first memory cell of the first group of memory cells is associated with a corresponding first cell selection transistor, wherein a channel portion of each first cell selection transistor includes a group of corresponding one or more fifth semiconductor pillars in contact with the first digital line and overlapping with the group of one or more first semiconductor pillars along a height dimension relative to the substrate; and each second memory cell of the second group of memory cells is associated with a corresponding second cell selection transistor, wherein a channel portion of each second cell selection transistor includes a group of corresponding one or more sixth semiconductor pillars in contact with the second digital line and overlapping with the group of one or more second semiconductor pillars along the height dimension relative to the substrate.

[0170] Aspect 17: An apparatus according to any one of Aspects 10 to 16, further comprising: a third digital line associated with the first level of the memory die, the third digital line coupled to a third group of memory cells of the memory die; a fourth digital line associated with the second level of the memory die, the fourth digital line coupled to a fourth group of memory cells of the memory die; a fifth transistor associated with the first level of the memory die and operable to couple the third digital line to a third conductor coupled to the sense amplifier; a sixth transistor associated with the second level of the memory die and operable to couple the fourth digital line to the second conductor; a seventh transistor associated with the first level of the memory die and operable to couple the second conductor to a second voltage source; and an eighth transistor associated with the second level of the memory die and having a channel portion coupled between the third conductor and the fourth conductor.

[0171] Aspect 18: The apparatus of aspect 17, wherein the sense amplifier is operable to detect a logic state based at least in part on a voltage of the first conductor and a voltage of the third conductor.

[0172] Aspect 19: The apparatus of any of Aspects 10 to 18, wherein the sense amplifier comprises a plurality of transistors, each transistor of the plurality of transistors comprising a respective channel portion formed at least in part by a doped portion of the substrate.

[0173] Aspect 20: The apparatus of any one of aspects 10 to 19, wherein the voltage source is associated with a ground voltage.

[0174] An apparatus is described. The following provides an overview of aspects of the apparatus as described herein:

[0175] Aspect 21: A device comprising: a memory die comprising a first level above a substrate and a second level above the substrate; and a circuit system of the memory die that is operable to cause the device to: isolate a conductor of the memory die from a voltage source based at least in part on deactivating a first transistor associated with the first level of the memory die; generate a first voltage at the conductor of the memory die based at least in part on coupling a storage element of a memory cell to a digit line and coupling the digit line to the conductor; shift the conductor from the first voltage to a second voltage based at least in part on shifting a bias applied to a gate of a second transistor associated with the second level of the memory die from a third voltage to a fourth voltage, the second transistor having a channel portion coupled to (e.g., coupled between, electrically and physically coupled to) a first portion of the conductor and a second portion of the conductor; and determine a logic state based at least in part on shifting the conductor from the first voltage to the second voltage.

[0176] Aspect 22: An apparatus according to Aspect 21, wherein the circuit system is operable to cause the apparatus to: couple the storage element of the memory cell with the digital line based at least in part on activating a first channel associated with one or more first semiconductor pillars of the memory die coupled between the storage element and the digital line; and couple the digital line with the conductor based at least in part on activating a second channel associated with one or more second semiconductor pillars of the memory die coupled between the digital line and the conductor, wherein the one or more second semiconductor pillars overlap with the one or more first semiconductor pillars along a height dimension relative to the substrate.

[0177] Aspect 23: An apparatus according to Aspect 22, wherein the circuit system is operable to cause the apparatus to: deactivate the first transistor based at least in part on deactivating a third channel associated with one or more third semiconductor pillars of the memory die coupled between the conductor and the voltage source, wherein the one or more third semiconductor pillars overlap with the one or more first semiconductor pillars along the height dimension relative to the substrate.

[0178] Aspect 24: An apparatus according to any one of Aspects 22 to 23, wherein: the channel portion of the second transistor is associated with one or more fourth semiconductor pillars of the memory die that overlap with the one or more first semiconductor pillars along the height dimension relative to the substrate.

[0179] Aspect 25: An apparatus according to any one of Aspects 22 to 24, wherein the circuit system is operable to cause the apparatus to: isolate a second conductor of the memory die from the voltage source based at least in part on deactivating a third transistor associated with the first level of the memory die; generate a fifth voltage at the second conductor of the memory die based at least in part on coupling a storage element of a second memory cell to a second digital line and coupling the second digital line to the second conductor; shift the second conductor from the fifth voltage to a sixth voltage based at least in part on shifting a bias applied to a gate of a fourth transistor associated with the second level of the memory die from a seventh voltage to an eighth voltage, the fourth transistor having a channel portion coupled between a first portion of the second conductor and a second portion of the second conductor; and determine the logic state based at least in part on shifting the second conductor from the fifth voltage to the sixth voltage.

[0180] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, the signal may represent a signal bus, where the bus may have various bit widths.

[0181] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication with each other (or in conductive contact or connected or coupled to each other) if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, based on the operation of the device that includes the connected components, the conductive path between the components that are in electronic communication with each other (or in conductive contact or connected or coupled to each other) may be an open circuit or a closed circuit. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some examples, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0182] The term "coupled" refers to a state of moving from an open circuit relationship between components (where signals cannot currently be transmitted between components via a conductive path) to a closed circuit relationship between components (where signals can be transmitted between components via a conductive path). When a component, such as a controller, couples other components together, the component causes a change that allows signals to flow between the other components via a conductive path that previously did not allow signal flow.

[0183] The term "isolation" refers to a relationship between components where a signal cannot currently flow between the components. Components are isolated from one another if an open circuit exists between them. For example, when a switch positioned between two components is open, the components separated by the switch are isolated from one another. When a controller isolates two components from one another, the controller effects a change that prevents a signal from flowing between the components using a conduction path that previously permitted the signal to flow.

[0184] As used herein, the term "layer" or "level" refers to a layer or sheet of a geometric structure (e.g., relative to a substrate). Each layer or level may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer or level may be a three-dimensional structure in which two dimensions are greater than the third dimension, such as a film. A layer or level may include different elements, components, or materials. In some examples, a layer or level may be composed of two or more sub-layers or sub-levels.

[0185] The devices discussed herein, including memory arrays, may be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping using various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping may be performed by ion implantation during the initial formation or growth of the substrate or by any other doping method.

[0186] The switch components or transistors discussed herein may represent field effect transistors (FETs) and include three-terminal devices, including a source, a drain, and a gate. The terminals may be connected to other electronic components by conductive materials (e.g., metals). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., most carriers are electrons), then the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most carriers are holes), then the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "on" or "activated." A transistor may be “off” or “deactivated” when a voltage less than the transistor's threshold voltage is applied to the transistor gate.

[0187] The description set forth herein in conjunction with the drawings describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein is intended to mean "serving as an example, instance, or illustration" rather than "preferred" or "advantageous over other examples." The detailed description includes specific details for providing an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0188] In the drawings, similar components or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label without regard to the second reference label.

[0189] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on a computer-readable medium or transmitted via a computer-readable medium as one or more instructions or codes. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described herein may be implemented using software executed by a processor, hardware, firmware, hard wiring, or a combination of any of these. Features that implement the functions may also be physically located at various locations, including portions that are distributed so that the functions are implemented at different physical locations.

[0190] For example, the various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed using a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0191] As used herein, including in the claims, "or" as used in a list of items (for example, a list of items preceded by a phrase such as "at least one of" or "one or more of") indicates an inclusive list such that (for example) a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). In addition, as used herein, the phrase "based on" should not be understood as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" can be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be understood in the same manner as the phrase "based at least in part on".

[0192] The description herein is provided to enable persons skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but should conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device comprising: a first digit line associated with a first level of a memory die above a substrate, the first digit line coupled to a first set of memory cells of the memory die; a second digit line associated with a second level of the memory die above the substrate, the second digit line coupled to a second set of memory cells of the memory die; a first transistor associated with the first level of the memory die and operable to couple the first digit line to a first conductor coupled to a sense amplifier of the memory die; a second transistor associated with the second level of the memory die and operable to couple the second digit line with the first conductor; a third transistor associated with the first level of the memory die and operable to couple the first conductor to a voltage source; as well as A fourth transistor is associated with the second level of the memory die and has a channel portion coupled between the first conductor and a second conductor.

2. The apparatus according to claim 1, further comprising: A fifth transistor is associated with the second level of the memory die and is operable to couple the first conductor with the second conductor.

3. The apparatus of claim 1, wherein the second conductor is connected to the first conductor via a metal portion associated with the second level of the memory die.

4. The apparatus of claim 1, wherein the second conductor and the second digit line overlap along a height dimension relative to the substrate.

5. The apparatus of claim 1, wherein: A channel portion of the first transistor includes a set of one or more first semiconductor pillars in contact with the first digit line and the first conductor; and A channel portion of the second transistor includes a set of one or more second semiconductor pillars in contact with the second digit line and the first conductor.

6. The apparatus according to claim 5, wherein: a channel portion of the third transistor including a set of one or more third semiconductor pillars in contact with the first conductor and overlapping the set of one or more first semiconductor pillars along a height dimension relative to the substrate; and The channel portion of the fourth transistor includes a set of one or more fourth semiconductor pillars in contact with the first conductor and overlapping the set of one or more second semiconductor pillars along the height dimension relative to the substrate.

7. The apparatus of claim 5, wherein: each first memory cell of the first group of memory cells is associated with a respective first cell select transistor, wherein a channel portion of each first cell select transistor includes a respective set of one or more fifth semiconductor pillars in contact with the first digit line and overlapping the set of one or more first semiconductor pillars along a height dimension relative to the substrate; and Each second memory cell in the second group of memory cells is associated with a corresponding second cell select transistor, wherein a channel portion of each second cell select transistor includes a set of corresponding one or more sixth semiconductor pillars that are in contact with the second digit line and overlap with the set of one or more second semiconductor pillars along the height dimension relative to the substrate.

8. The apparatus of claim 1, further comprising: a third digit line associated with the first level of the memory die, the third digit line coupled to a third group of memory cells of the memory die; a fourth digit line associated with the second level of the memory die, the fourth digit line coupled to a fourth group of memory cells of the memory die; a fifth transistor associated with the first level of the memory die and operable to couple the third digit line to a third conductor coupled to the sense amplifier; a sixth transistor associated with the second level of the memory die and operable to couple the fourth digit line with the second conductor; a seventh transistor associated with the first level of the memory die and operable to couple the second conductor to a second voltage source; and An eighth transistor is associated with the second level of the memory die and has a channel portion coupled between the third conductor and a fourth conductor.

9. The apparatus of claim 8, wherein the sense amplifier is operable to detect a logic state based at least in part on a voltage of the first conductor and a voltage of the third conductor.

10. The apparatus of claim 1, wherein the sense amplifier comprises a plurality of transistors, each transistor of the plurality of transistors comprising a respective channel portion formed at least in part by a doped portion of the substrate.

11. The apparatus of claim 1, wherein the voltage source is associated with a ground voltage.

12. A method comprising: isolating a conductor of the memory die from a voltage source based at least in part on deactivating a first transistor associated with a first level of the memory die above the substrate; generating a first voltage at the conductor of the memory die based at least in part on coupling a storage element of a memory cell with a digit line and coupling the digit line with the conductor; shifting the conductor from the first voltage to a second voltage based at least in part on shifting a bias voltage applied to a gate of a second transistor associated with a second level of the memory die above the substrate from a third voltage to a fourth voltage, the second transistor having a channel portion coupled between a first portion of the conductor and a second portion of the conductor; and A logic state is determined based at least in part on shifting the conductor from the first voltage to the second voltage.

13. The method according to claim 12, wherein: coupling the storage element of the memory cell with the digit line is based at least in part on activating a first channel associated with one or more first semiconductor pillars of the memory die coupled between the storage element and the digit line; and Coupling the digit line with the conductor is based at least in part on activating a second channel associated with one or more second semiconductor pillars of the memory die coupled between the digit line and the conductor, wherein the one or more second semiconductor pillars overlap the one or more first semiconductor pillars along a height dimension relative to the substrate.

14. The method of claim 13, wherein deactivating the first transistor is based at least in part on deactivating a third channel associated with one or more third semiconductor pillars of the memory die coupled between the conductor and the voltage source, wherein the one or more third semiconductor pillars overlap with the one or more first semiconductor pillars along the height dimension relative to the substrate.

15. The method of claim 13, wherein the channel portion of the second transistor is associated with one or more fourth semiconductor pillars of the memory die that overlap the one or more first semiconductor pillars along the height dimension relative to the substrate.

16. The method of claim 12, wherein a first end of the channel portion of the second transistor is coupled to the conductor, the method further comprising: A fifth transistor associated with the second level of the memory die is activated, the fifth transistor having a channel portion coupled between a second end of the channel portion of the second transistor and the conductor.

17. The method of claim 12, wherein a first end of the channel portion of the second transistor is coupled to the conductor and a second end of the channel portion of the second transistor is coupled to the conductor. The method of claim 12 , wherein the voltage source is associated with a ground voltage.

19. The method of claim 12, further comprising: isolating a second conductor of the memory die from the voltage source based at least in part on deactivating a third transistor associated with the first level of the memory die; generating a fifth voltage at the second conductor of the memory die based at least in part on coupling a storage element of a second memory cell with a second digit line and coupling the second digit line with the second conductor; and shifting the second conductor from the fifth voltage to a sixth voltage based at least in part on shifting a bias voltage applied to a gate of a fourth transistor associated with the second level of the memory die from a seventh voltage to an eighth voltage, the fourth transistor having a channel portion coupled between a first portion of the second conductor and a second portion of the second conductor, Wherein determining the logic state is based at least in part on shifting the second conductor from the fifth voltage to the sixth voltage.

20. The method of claim 19, wherein determining the logic state is based at least in part on comparing the second voltage to the sixth voltage.

21. An apparatus comprising: a memory die comprising a first level above a substrate and a second level above the substrate; and circuitry of the memory die operable to cause the apparatus to: isolating a conductor of the memory die from a voltage source based at least in part on deactivating a first transistor associated with the first level of the memory die; generating a first voltage at the conductor of the memory die based at least in part on coupling a storage element of a memory cell with a digit line and coupling the digit line with the conductor; shifting the conductor from the first voltage to a second voltage based at least in part on shifting a bias voltage applied to a gate of a second transistor associated with the second level of the memory die from a third voltage to a fourth voltage, the second transistor having a channel portion coupled between a first portion of the conductor and a second portion of the conductor; and A logic state is determined based at least in part on shifting the conductor from the first voltage to the second voltage.

22. The apparatus of claim 21, wherein the circuit system is operable to cause the apparatus to: coupling the storage element of the memory cell with the digit line based at least in part on activating a first channel associated with one or more first semiconductor pillars of the memory die coupled between the storage element and the digit line; and The digit line is coupled to the conductor based at least in part on activating a second channel associated with one or more second semiconductor pillars of the memory die coupled between the digit line and the conductor, wherein the one or more second semiconductor pillars overlap the one or more first semiconductor pillars along a height dimension relative to the substrate.

23. The apparatus of claim 22, wherein the circuit system is operable to cause the apparatus to: The first transistor is deactivated based at least in part on deactivating a third channel associated with one or more third semiconductor pillars of the memory die coupled between the conductor and the voltage source, wherein the one or more third semiconductor pillars overlap the one or more first semiconductor pillars along the height dimension relative to the substrate.

24. The apparatus of claim 22, wherein: The channel portion of the second transistor is associated with one or more fourth semiconductor pillars of the memory die that overlap the one or more first semiconductor pillars along the height dimension relative to the substrate.

25. The apparatus of claim 22, wherein the circuit system is operable to cause the apparatus to: isolating a second conductor of the memory die from the voltage source based at least in part on deactivating a third transistor associated with the first level of the memory die; generating a fifth voltage at the second conductor of the memory die based at least in part on coupling a storage element of a second memory cell with a second digit line and coupling the second digit line with the second conductor; shifting the second conductor from the fifth voltage to a sixth voltage based at least in part on shifting a bias voltage applied to a gate of a fourth transistor associated with the second tier of the memory die from a seventh voltage to an eighth voltage, the fourth transistor having a channel portion coupled between a first portion of the second conductor and a second portion of the second conductor; and The logic state is determined based at least in part on shifting the second conductor from the fifth voltage to the sixth voltage.

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