A biologically plausible neuron computing circuit and computing method

Abstract

The application provides a biologically plausible neuron computing circuit and a computing method, which operates the membrane potential of the previous moment and the neural network pulse signal through a synaptic integration module, a leaky integration module, a threshold comparison and a pulse emission module, obtains the membrane potential of the current moment, and generates a pulse signal according to the membrane potential of the current moment. Compared with the traditional digital-analog hybrid design which excessively pursues the accurate neuromorphic behavior and the traditional digital design which excessively pursues the extremely low computing complexity, the biologically plausible neuron computing circuit of the application makes a better trade-off between the biological plausibility and the computing complexity, so that more abundant neuron dynamic behaviors can be realized at a smaller hardware cost, the maximum scale of the reinforced LIF neuron integration and the synaptic integration are realized, and the biologically plausible neuron computing circuit can be deployed in more complex and more diverse neuromorphic brain-like applications.

Description

Technical Field

[0001] This invention relates to the field of microprocessor technology, and in particular to a biologically reliable neuronal computing circuit and computing method. Background Technology

[0002] Neuromorphic brain-inspired platforms ultimately handle neuromorphic computation. Under the current development trend of brain-inspired computing, neuromorphic applications place demands on neuromorphic hardware in terms of both model adaptability and computational efficiency. Regarding model adaptability, the wide range of application scenarios requires neuromorphic processors to be more general-purpose computing platforms. In terms of computational efficiency, the internal processing cores need to carefully consider the complexity of the computational models and adopt more hardware-friendly design methodologies to achieve the expected computational functions with minimal hardware computation and storage overhead.

[0003] Existing neuronal circuit designs do not strike a good balance between biological confidence and computational complexity. Analog circuits, in their pursuit of precise neuromorphic behavior, suffer from high energy consumption, making large-scale scalability difficult and thus less acceptable for various applications. Digital circuits, on the other hand, prioritize extremely low computational complexity, employing the overly simplistic LIF neuron model, which severely limits the neuromorphic behaviors and functions that neurons can perform, thereby restricting the widespread application of neuromorphic platforms in various scenarios. Summary of the Invention

[0004] This invention provides a biologically reliable neuronal computing circuit and computing method to address the imbalance between biological reliability and computational complexity in existing technologies.

[0005] This invention provides a biologically reliable neuronal computing circuit, comprising a synaptic integration module, a leakage integration module, and a threshold comparison and pulse firing module connected in sequence;

[0006] The synaptic integration module is used to calculate the current membrane level based on the membrane level at the previous moment and the input neural network pulse signal, and send the current membrane level to the leakage integration module;

[0007] The leakage integration module is used to perform a leakage operation on the membrane level at the current moment, and send the membrane level after the leakage operation to the threshold comparison and pulse delivery module;

[0008] The threshold comparison and pulse delivery module is used to compare the membrane level after the leakage operation with the preset pulse delivery threshold, and generate a pulse signal based on the threshold judgment result.

[0009] According to the present invention, a biologically reliable neuronal computing circuit includes a synaptic integration module comprising a neural network synaptic unit.

[0010] The neural network synaptic unit is used to obtain neural network synaptic weight values ​​based on neural network pulse signals, and store the neural network synaptic weight values ​​in the synaptic integration module;

[0011] The synaptic integration module is used to perform weighted summation of the neural network pulse signal based on pre-stored neural network synaptic weight values.

[0012] According to the biologically reliable neuronal computing circuit provided by the present invention, the synaptic integration module further includes a random number generation unit;

[0013] The random number generation unit is used to randomly filter the neural network pulse signals to obtain a subset of the neural network pulse signals;

[0014] The synaptic integration module is used to perform a weighted summation of a subset of the neural network pulse signals based on pre-stored neural network synaptic weight values.

[0015] According to the present invention, a biologically reliable neuronal computing circuit performs a leakage operation on the membrane level at the current moment, including:

[0016] Forward leakage is performed on the membrane level at the current moment;

[0017] or

[0018] Reverse leakage of the membrane level at the current moment;

[0019] or

[0020] Randomly leak the membrane level at the current moment.

[0021] According to a biologically reliable neuronal computing circuit provided by the present invention, the leakage integration module is further configured to receive the membrane level after threshold comparison by the threshold comparison and pulse firing module and perform leakage operation.

[0022] According to the present invention, a biologically reliable neuronal computing circuit includes a pulse firing threshold, comprising comparing a preset pulse firing threshold with the membrane level after a leakage operation, and generating a pulse signal based on the threshold determination result, including:

[0023] When the membrane level after the leakage operation is higher than or equal to the positive threshold, a pulse signal and a level reset signal are generated.

[0024] According to the present invention, a biologically reliable neuronal computing circuit includes a negative threshold for pulse firing, which compares a preset pulse firing threshold with the membrane level after a leakage operation, and generates a pulse signal based on the threshold determination result, comprising:

[0025] If the membrane level after the leakage operation is lower than the negative threshold, only a level reset signal is generated.

[0026] According to the present invention, a biologically reliable neuronal computing circuit is provided, wherein the threshold comparison and pulse firing module includes a membrane level reset unit;

[0027] The membrane level reset unit is used to receive the level reset signal and reset the membrane level at the current moment to a preset level according to the level reset signal.

[0028] The present invention also provides a computational method for a spiking neural network, comprising:

[0029] The membrane level at the previous moment and the neural network pulse signal are processed to obtain the membrane level at the current moment;

[0030] A pulse signal is generated based on the membrane level at the current moment.

[0031] According to a calculation method for a spiking neural network provided by the present invention, the step of generating a pulse signal based on the membrane level at the current moment includes:

[0032] If the membrane level at the current moment is higher than or equal to the positive threshold, a pulse signal is output.

[0033] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the computational method for a spiking neural network as described above.

[0034] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the computational method for a spiking neural network as described above.

[0035] This invention provides a biologically reliable neuronal computing circuit and method. The circuit, through a synaptic integration module, a leakage integration module, a threshold comparison module, and a pulse firing module, calculates the membrane level and neural network pulse signal from the previous moment to obtain the current membrane level and generates a pulse signal based on the current membrane level. Compared to traditional mixed-signal design's overemphasis on precise neuromorphic behavior and traditional digital design's overemphasis on extremely low computational complexity, this invention's biologically reliable neuronal computing circuit achieves a better trade-off between biological reliability and computational complexity. It enables richer neuronal dynamic behaviors with relatively low hardware costs, achieving the largest-scale enhanced LIF neuron integration and synaptic integration, thus enabling the deployment of more complex and diverse neuromorphic brain-like applications. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0037] Figure 1 This is a schematic diagram of the module of the biologically reliable neuronal computing circuit provided by the present invention;

[0038] Figure 2 This is a schematic diagram of the synaptic integration module of the biologically trusted neuronal computing circuit provided by the present invention;

[0039] Figure 3 This is a schematic diagram of the leakage integration module of the biologically trusted neuronal computing circuit provided by the present invention;

[0040] Figure 4 This is a schematic diagram of the leakage inversion mode of the leakage integration module provided by the present invention;

[0041] Figure 5 This is a schematic diagram of the threshold comparison and pulse firing module of the biologically reliable neuronal computing circuit provided by the present invention;

[0042] Figure 6 This is a flowchart of the neuron computing circuit provided by the present invention;

[0043] Figure 7 This is a schematic diagram of the neuromorphic processing kernel provided by the present invention;

[0044] Figure 8 This is a schematic diagram of the basic neuronal behavior provided by the present invention;

[0045] Figure 9 This is a schematic diagram of the phased firing neuron behavior provided by the present invention;

[0046] Figure 10 This is a schematic diagram of neuronal behavior in inhibitory basal firing provided by the present invention;

[0047] Figure 11 This is a schematic diagram of neuronal behavior in the basic cluster firing provided by the present invention;

[0048] Figure 12 This is a schematic diagram of the topology of the logical function AND provided by the present invention;

[0049] Figure 13 This is a schematic diagram of the topology of the logical function OR provided by the present invention;

[0050] Figure 14This is a schematic diagram of the topological structure of the NOT logic function provided by the present invention;

[0051] Figure 15 This is a schematic diagram of the topology of the XOR logic function provided by the present invention;

[0052] Figure 16 This is a schematic diagram of the topological structure of the arithmetic function addition provided by the present invention;

[0053] Figure 17 This is a schematic diagram of the topological structure of the maximum value of the arithmetic function provided by the present invention;

[0054] Figure 18 This is a schematic diagram of the topological structure of the arithmetic function division provided by the present invention;

[0055] Figure 19 This is a schematic diagram of the topological structure of the arithmetic function square provided by the present invention;

[0056] Figure 20 This is a flowchart illustrating the computation method for a spiking neural network provided by the present invention;

[0057] Figure 21 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0059] Originating from neuroscience, spiking neural networks (SNNs) are hailed as the next generation of neural networks. SNNs aim to bridge the gap between current neuroscience and machine learning by using models that best fit the mechanisms of biological neurons for computation. They have garnered widespread attention from researchers due to their rich spatiotemporal neurodynamic properties, diverse encoding mechanisms, and event-driven advantages.

[0060] In a semi-neural network (SNN), a neuron typically consists of input synapses, an activation function, an integrator, and an output synapse. Input synapses receive input signals from other neurons; these signals are transmitted through the synapse and can be chemical or electrochemical. The activation function determines whether the neuron's output is activated or inhibited. In SNNs, the activation function is usually a threshold function or a sigmoid function. The integrator accumulates the input signal and determines whether the neuron fires a pulse. The integrator is typically a capacitor or an integrator. The output synapse transmits the pulse to other neurons. These components together form the neuron in an SNN.

[0061] Existing neuronal circuit designs do not strike a good balance between biological confidence and computational complexity. Analog circuits, in their pursuit of precise neuromorphic behavior, suffer from high energy consumption, making large-scale scalability difficult and thus less acceptable for various applications. Digital circuits, on the other hand, prioritize extremely low computational complexity, employing the overly simplistic LIF neuron model, which severely limits the neuromorphic behaviors and functions that neurons can perform, thereby restricting the widespread application of neuromorphic platforms in various scenarios.

[0062] To address the problems existing in the prior art, reference Figure 1 This invention proposes a biologically reliable neuronal computing circuit, comprising a synaptic integration module 110, a leakage integration module 120, and a threshold comparison and pulse firing module 130 connected in sequence.

[0063] The synaptic integration module 110 is used to calculate the current membrane level based on the membrane level at the previous moment and the input neural network pulse signal, and send the current membrane level to the leakage integration module.

[0064] The leakage integration module 120 is used to perform a leakage operation on the membrane level at the current moment, and send the membrane level after the leakage operation to the threshold comparison and pulse delivery module.

[0065] The threshold comparison and pulse delivery module 130 is used to compare the membrane level after the leakage operation with a preset pulse delivery threshold, and generate a pulse signal based on the threshold judgment result.

[0066] The neuron computing circuit is an important part of the neuron circuit, used to process and calculate pulse signals.

[0067] The synaptic integration module 110 calculates the current membrane level based on the membrane level of the previous moment and the input neural network pulse signal, and sends the current membrane level to the leakage integration module. This module can be implemented by setting an adder and an integrator. The adder is the core part of the synaptic integration module 110, used to add multiple input pulse signals received by the neuron computing circuit to obtain the total input current value of the neuron. Typically, the adder can use a current distributor to weight the input current to adjust the weight of different input signals. The integrator is used to integrate the total input current of the neuron computing circuit to obtain the membrane level value of the neuron. In the neuron circuit, capacitive elements are usually used to simulate the membrane capacitance of the neuron, while the integrator is used to integrate the input current to calculate the change in the neuron membrane level.

[0068] Let V be the membrane level of the neuron at time t. j (t), where V is the membrane level at time t-1. j (t-1) is a weighted sum of the network input pulses. If N represents the total number of synapses to be integrated, x i (t) represents the pulse signal on the i-th axon at time t, w i,j The synaptic connection weight between the i-th axon and the j-th dendrite is represented by . As an enabling signal for random integration mode, Let sgn(·) be a pseudo-random number and sgn(·) be the sign function. Then, the synaptic integration process can be represented as follows:

[0069]

[0070] The leakage integration module 120 can realize random or deterministic forward and reverse leakage, and can realize the film level convergence or divergence towards 0.

[0071] Leakage integration can be performed either before or after the threshold comparison, controlled by a configurable parameter. Let... To prevent leakage of control signals in inversion mode, This is the enable signal for the random leakage mode, with a leakage amplitude of λ. j , Given pseudo-random numbers and F(·) as the comparison function, the leakage integration process can be represented as follows:

[0072]

[0073]

[0074] The threshold comparison and pulse emission module 130 includes a pulse emission unit used to detect whether the neuron membrane level exceeds a threshold and to generate an output pulse when the threshold is exceeded. Typically, the pulse emission unit uses a comparator to compare the neuron membrane level with the threshold to determine whether to output a pulse. Simultaneously, the emission unit can also reset the membrane level using a reset switch or a subtractor to simulate the level change after a neuron pulses.

[0075] set up A positive threshold Negative threshold V is a random threshold. rst,j To reset the level, where It is a pseudo-random number, Mask j For the window of the random number mask, y j (t) represents the pulse generated at time t, δ(·) is the impulse function, and γ j To reset the mode control parameters, κ j By selecting parameters for the negative threshold mode, the threshold comparison and pulse firing reset process of the neuron can be represented as follows:

[0076]

[0077] 1) if

[0078]

[0079] 2) else if

[0080]

[0081] 3) else V j (t)=V j (t),y j (t)=0

[0082] It is understandable that once the pulse emission membrane level is reset, the neuron's activity for one cycle is complete, awaiting the next moment, and the cycle repeats, completing the aforementioned processes of synaptic integration, leakage integration, threshold comparison, and pulse emission reset. From the above expression, compared to the original LIF model, this invention makes improvements in four aspects: First, it incorporates a stochastic process, allowing random accumulation and leakage during the synaptic integration and leakage integration stages, while the threshold can also fluctuate randomly within a certain range. Second, through leakage inversion, it achieves either divergent or convergent leakage modes, and can also implement leakage operations before or after threshold comparison. Third, the membrane level reset after pulse emission has multiple options: it can reset to a fixed value, subtract the threshold, or not reset at all. Fourth, a negative threshold is defined, which can serve as a floor threshold to prevent the membrane level from being too low, and can also adjust the membrane level through a reset mode corresponding to the positive threshold.

[0083] This invention provides a biologically reliable neuronal computing circuit and method. The circuit, through a synaptic integration module, a leakage integration module, a threshold comparison module, and a pulse firing module, calculates the membrane level and neural network pulse signal from the previous moment to obtain the current membrane level and generates a pulse signal based on the current membrane level. Compared to traditional mixed-signal design's overemphasis on precise neuromorphic behavior and traditional digital design's overemphasis on extremely low computational complexity, this invention's biologically reliable neuronal computing circuit achieves a better trade-off between biological reliability and computational complexity. It enables richer neuronal dynamic behaviors with relatively low hardware costs, achieving the largest-scale enhanced LIF neuron integration and synaptic integration, thus enabling the deployment of more complex and diverse neuromorphic brain-like applications.

[0084] As a further optional embodiment, the synaptic integration module includes neural network synaptic units;

[0085] The neural network synaptic unit is used to obtain neural network synaptic weight values ​​based on neural network pulse signals, and store the neural network synaptic weight values ​​in the synaptic integration module;

[0086] The synaptic integration module is used to perform weighted summation of the neural network pulse signal based on pre-stored neural network synaptic weight values.

[0087] Reference Figure 2 The synaptic integration module performs a dot product operation based on the input pulse and the corresponding synaptic weights; the circuit implementation only requires simple AND gates. Each time, 64 1-bit pulse data x passes through the dendritic integration module. i (t) will be divided into 8 groups of 8-bit data, and then compared with the synaptic weights w, which are also divided into 8 groups. i,jPerform eight-way parallel synaptic operations. The eight 1-bit results output by the AND gate are first partially accumulated to obtain the Input. 0～7 It is then processed by neuronal integration.

[0088] As a further optional embodiment, the synaptic integration module also includes a random number generation unit;

[0089] The random number generation unit is used to randomly filter the neural network pulse signals to obtain a subset of the neural network pulse signals;

[0090] The synaptic integration module is used to perform a weighted summation of a subset of the neural network pulse signals based on pre-stored neural network synaptic weight values.

[0091] Reference Figure 2 In this embodiment, random integration is enabled. The system filters out different inputs based on whether the operation is in deterministic or random mode: in deterministic mode, the input will be sent directly. 0～7 Pseudo-random number generator in random mode This will randomly filter out 8 sets of pulse portions, resulting in a random accumulation effect. The filtered input then passes through a three-stage pipeline adder tree to obtain the sum of these 64 pulse inputs, which is then compared with the membrane level V from the previous time step. j (t-1) The iterative accumulation is completed, and the accumulation operation is finished. During this process, if a higher precision 2 / 4 / 8-bit weight is used, the circuit will use shift addition instead of the more expensive multiplier, and complete the synaptic integration operation in 2 / 4 / 8 steps.

[0092] As a further optional embodiment, a leakage operation is performed on the membrane level at the current moment, including:

[0093] Forward leakage is performed on the membrane level at the current moment;

[0094] or

[0095] Reverse leakage of the membrane level at the current moment;

[0096] or

[0097] Randomly leak the membrane level at the current moment.

[0098] Reference Figure 3 In this embodiment, the leakage integration module can perform complex leakage operations on the accumulated membrane level during the leakage integration stage. These operations include using deterministic or random leakage integration modes, leakage reversal modes, and pre-comparison or post-comparison leakage modes. Specifically, random leakage is enabled. The leakage integration mode is controlled to determine whether to perform deterministic or random leakage integration. For deterministic leakage integration, the leakage value λ is directly accumulated. j That's sufficient; for random leaks and integration, a pseudo-random number generator can be used. The probability of leakage is +1, -1, or 0. For leakage inversion mode, when leakage inversion is enabled... like Figure 4 As shown, the leakage integration module can adjust the current membrane level V based on the current membrane level V. j The positive or negative attribute of (t) can be used to adjust the direction of leakage, and the final result is that the membrane level after leakage can either converge toward 0 or diverge away from 0.

[0099] As a further optional embodiment, the leakage integration module is also used to receive the membrane level after threshold comparison by the threshold comparison and pulse emission module and perform leakage operation.

[0100] In this embodiment, the leakage operation can be performed either after or before the threshold comparison. This embodiment expands the functionality of the neuron computing circuit by enriching the calculation methods of the leakage integration module.

[0101] As a further optional embodiment, the pulse firing threshold includes a positive threshold. A pulse signal is generated by comparing a preset pulse firing threshold with the membrane level after the leakage operation, and generating the pulse signal based on the threshold determination result.

[0102] When the membrane level after the leakage operation is higher than or equal to the positive threshold, a pulse signal and a level reset signal are generated.

[0103] As a further optional embodiment, the pulse firing threshold includes a negative threshold. A pulse signal is generated by comparing a preset pulse firing threshold with the membrane level after the leakage operation, and generating a pulse signal based on the threshold determination result.

[0104] If the membrane level after the leakage operation is lower than the negative threshold, only a level reset signal is generated.

[0105] Reference Figure 5 In this embodiment, the pulse emission unit is used to detect whether the neuron membrane level has reached a threshold, and generates an output pulse when the threshold is reached. Specifically, during threshold comparison, a positive threshold is determined. negative threshold And the random swing amplitude part The random swing portion can be achieved using a pseudo-random number generator and a variable-width mask. jThis is implemented by summing a random number with positive and negative thresholds, allowing for a customizable random threshold range. The positive threshold is related to the pulse firing rate; if the membrane level V... j When the threshold (t) exceeds a positive threshold, the neuron fires a pulse and resets the membrane level. Furthermore, when the negative threshold mode selects κ... j When enabled, the negative threshold can also act as a floor threshold, ensuring that the membrane level is not lower than this predefined value.

[0106] Understandably, a random swing portion can be added to the positive and negative thresholds to achieve a random threshold within a custom range.

[0107] As a further optional embodiment, the threshold comparison and pulse delivery module includes a membrane level reset unit;

[0108] The membrane level reset unit is used to receive the level reset signal and reset the membrane level at the current moment to a preset level according to the level reset signal.

[0109] In this embodiment, after the threshold comparison and pulse emission module reaches the positive threshold, a pulse is emitted and the membrane level is reset. The membrane level reset unit can reset the current membrane level to a preset level based on the level reset signal. Specifically, three modes are defined for membrane level reset, and the signal γ is selected according to the reset mode. j The following operations can be performed on the neuron membrane level: 1) reset to a specified value, 2) subtract a threshold, and 3) leave it unchanged.

[0110] Understandably, although the negative threshold does not involve pulse delivery, the membrane level can still be reset according to the three modes mentioned above after it falls below the negative threshold.

[0111] The application scenarios of the neuron computing circuit of the present invention are described below.

[0112] Reference Figure 6 Taking LIF neuron calculation with eight neurons as an example, the neurons first cycle through synaptic integration until all synapses have completed weighted accumulation with the pulses. These eight neurons accumulate membrane levels of 2, 4, 8, 4, 3, 2, -8, and 6, respectively. Then, before comparison, the neurons leak -1, -1, -1, -2, -2, 0, 1, and 0, respectively, resulting in membrane levels of 1, 3, 7, 2, 1, 2, -7, and 6. Since the threshold is set to 3, three neurons have membrane levels greater than or equal to 3, will emit pulses, and reset their membrane levels to 0. The other five neurons do not emit pulses, and their membrane levels remain unchanged. Therefore, the final membrane levels of the eight neurons are 1, 0, 0, 2, 1, 2, -7, and 0, where neurons j = 1, 2, and 7 will emit pulses.

[0113] The neuron computing circuit in this invention can serve as the core computing module in a neuromorphic processing kernel. (Reference) Figure 7 Each processing core mainly consists of an input pulse scheduler module, a synaptic cross array module, a neuron module, an interface routing module, and a system control module.

[0114] The input scheduling module serves as a buffer for pulse inputs, storing them based on time and spatial information tagged in the input data packets. Pulse inputs are then fed into the synaptic array at designated times. This array is a virtual connection implemented using reconfigurable logic, connecting the data input to specific neurons. After passing through the lateral axons in the synaptic array and undergoing bitwise AND operations at the synaptic points, the pulse input is sent to the longitudinal output, called the dendrite, which feeds into the enhanced LIF neuron module for computation. Following the aforementioned neuronal circuit computation steps, the emitted pulses are sent to the interface routing module. Using address event representation, the pulses or data generated by the neurons are packaged into standard format data packets, enabling data interaction with external systems. The packaged data packets sent locally are then sent to the input scheduling module for parsing. This data flow forms a complete closed loop, allowing the neuronal circuit to continuously integrate input pulses and generate output pulses, thus realizing its rich neurodynamic behavior.

[0115] Based on the enhanced LIF neuron dynamics model proposed in this invention, a richer simulation of neuronal behavior can be achieved, such as basal firing, phased firing, basal cluster firing, mixed modes, frequency-modulated firing, type I excitation, type II excitation, delayed firing, subthreshold oscillation, frequency-matched firing, integrated firing, rebound firing, rebound cluster firing, threshold modulation, bistable state, depolarization potential, short response, inhibitory basal firing, and inhibitory basal cluster firing. Izhikevich neuron behavior is generally the different pulse firing manifestations of a single neuron under different external stimuli. Using the enhanced LIF neuron circuit proposed in this invention, 1 to 3 neurons can be connected in a specific topology and reasonable dynamic parameters can be set to achieve these 20 behaviors. This demonstrates that the design proposed in this invention has the ability to simulate basic brain-like behaviors, which is a key difference between it and the basic LIF neuron model.

[0116] Referring to Table 1, which lists the configuration topologies and dynamic parameters for some representative behaviors,...

[0117] refer to Figure 8 In the basic distribution, let the weight w = 1 and the positive threshold be... Reset level V rst =0, then the neuron can reach the positive threshold after receiving three pulse inputs, emit a pulse and reset the membrane level to 0, thus forming a uniform pulse with a period interval of 3.

[0118] refer to Figure 9 In the phased distribution, let the weight w = 1, the leakage λ = 1, and the positive threshold be... Reset level V rst = -10, and enable leakage inversion (leakage is +1 when membrane level is positive, leakage is -1 when membrane level is negative, and no leakage when membrane level is 0) and set the ground membrane level. When the first input arrives, the membrane level reaches 2 through synaptic and leakage integration, a pulse is emitted and reset to -10. After that, since the synaptic integration of +1 and leakage integration of -1 cancel each other out, the membrane level always remains at -10, and no more pulses are emitted.

[0119] refer to Figure 10 In the inhibitory basal release, let the weight w = -10, the leakage λ = -1, and the positive threshold be... negative threshold Reset level V rst = -30, and enable leakage inversion, disable floor threshold mode. When the inhibitory pulse does not arrive, leakage inversion with leakage λ < 0 will cause the membrane level to converge toward 0. Figure 4 Therefore, no impulses are fired. When inhibitory impulses arrive continuously, the neuronal membrane level can accumulate below the negative threshold. At this point, the neuronal membrane level will be reset to -V. rst =30, and after synaptic and leakage integration at the next moment, the membrane level still reaches 19, so it can exceed the positive threshold to deliver a pulse.

[0120] refer to Figure 11 In the basic cluster distribution, two neurons are required. The weight of the 0th neuron is w = 1, -100, the leakage is λ = 1, and the positive threshold is... floor threshold Reset level V rst =18, and enable leak reversal; the weight w of the first neuron is 1, with no leaks, and a positive threshold. floor threshold Reset level V rst=0. When neuron 0 receives 10 pulse inputs and 10 leaks, its membrane level reaches 20, exceeding the positive threshold, and it fires a pulse, resetting the membrane level to 18. Then, at the next moment, after synaptic and leak integration, the membrane level reaches 20 again, exceeding the positive threshold, and fires a pulse, resetting the membrane level to 18. This cycle repeats at the next time step. The pulses fired by neuron 0 are transmitted to neuron 1, increasing its membrane level by 1 each time. Therefore, after neuron 0 fires six pulses, neuron 1's membrane level reaches 6, exceeding the positive threshold, and fires a pulse, resetting the level to 0. This pulse is then transmitted back to neuron 0. As a result, neuron 0's membrane level decreases by 100, falling below the floor threshold, and its membrane level is reset to 0. Neuron 0 then needs to receive another 10 pulse inputs and 10 leaks before it can continue firing in clusters. The effect is that neuron 0 fires 6 pulses consecutively every 10 cycles.

[0121]

[0122] Table 1

[0123] The neural circuit of this invention can also be used to implement logic functions and arithmetic functions with more practical functions. In logic functions, a single neuron can implement OR, AND, NOT, NOR, NAND, and buffering functions, while three neurons can implement XNOR and XOR functions. In arithmetic functions, a single neuron can implement addition, subtraction, multiplication, Nth power, logarithm, and fixed coefficient multiplication and division functions, while two neurons can implement division, squaring, maximum value, and minimum value operations, and three neurons can implement absolute value and square root operations.

[0124] Refer to Table 3, which lists the configuration topology and dynamic parameters of some representative logic functions.

[0125] refer to Figure 12 In the logical AND operation, let the weight w = 1, the leakage λ = -1, and the positive threshold be... floor threshold Reset level V rst =0, then the membrane level can only reach 1 when both X and Y have input pulses at the same time, and a pulse is emitted, and the membrane level is reset to 0; when only one of X and Y has an input pulse, the membrane level is 0, and when there is no input pulse, the membrane level is -1. In both cases, no pulse is emitted, and the membrane level is assigned the floor threshold value of 0 after comparison.

[0126] refer to Figure 13 In the logical OR operation, assume a weight w = 1, no leakage, and a positive threshold. floor threshold Reset level V rst=0, then when at least one of X and Y is input pulse, the membrane level can reach 1, a pulse is emitted, and the membrane level is reset to 0; when there is no pulse input to X and Y, the membrane level is 0 and no pulse is emitted.

[0127] refer to Figure 14 In the logical NOT case, let the weight w = -1, the leakage λ = 1, and the positive threshold be... floor threshold Reset level V rst =0, then when there is an input pulse, the weight and leakage integration cancel each other out, the membrane level remains at 0, and no pulse is emitted; when there is no input pulse, the membrane level reaches 1 after leakage integration, a pulse is emitted, and the membrane level is reset to 0.

[0128] refer to Figure 15 In the logical "XOR" operation, three neurons are required. The weight of the 0th neuron is w = -1, 1, with no leakage and a positive threshold. floor threshold Reset level V rst =0; the first neuron has the opposite weight, w=1,-1, with the other parameters the same; the second neuron has a weight w=1, with the other parameters the same. When both X and Y have input pulses, the cumulative membrane level of the 0th and 1st neurons is 0, and they do not fire pulses. The 2nd neuron also does not fire pulses because it has no pulse input. When X has an input pulse but Y does not, the membrane level of the 0th neuron is -1, and it does not fire pulses. The membrane level is assigned to the floor threshold of 0. The membrane level of the 1st neuron is 1, and it fires pulses. The membrane level is reset to 0. At this time, the 2nd neuron receives the input from the 1st neuron, and the membrane level reaches the positive threshold of 1, and it fires pulses. Similarly, when X has no input pulses but Y has some, the 0th neuron fires pulses, the 1st neuron does not fire, and the 2nd neuron still fires pulses. When neither X nor Y has pulse inputs, the membrane level of the 0th and 1st neurons is 0, and they do not fire pulses. The 2nd neuron also does not fire pulses.

[0129]

[0130]

[0131] Table 2

[0132] Refer to Table 3, which lists the configuration topology and dynamic parameters of some representative arithmetic functions.

[0133] refer to Figure 16 In the function "addition", let the weight w = 1, no leakage, and a positive threshold. floor threshold The reset mode involves subtracting a threshold from the membrane level for each output pulse emitted. Therefore, the membrane level accumulates according to the total number of input pulses received by neurons X and Y, ultimately resulting in the emission of the same number of output pulses – this is called addition.

[0134] refer to Figure 17 In the function "maximum value", two neurons are required. The weight of the 0th neuron is w = 1, -1, with no leakage and a positive threshold. floor threshold The reset mode involves subtracting the threshold from the membrane level for each output pulse emitted. The first neuron has a weight w=1, no leakage, and a positive threshold. floor threshold The reset mode involves subtracting a threshold from the membrane level for each output pulse emitted. When the number of input pulses X is greater than Y, the membrane level of neuron 0 is positive, reaching the threshold and emitting (XY) number of output pulses. The (XY) number of pulses and the Y number of pulses are accumulated in neuron 1, ultimately causing neuron 1 to produce X number of output pulses. When the number of input pulses X is less than Y, the membrane level of neuron 0 is negative and no pulses are generated. Neuron 1 then accumulates Y number of input pulses, ultimately producing Y number of output pulses.

[0135] refer to Figure 18 In the function "division", two neurons are required. The weight of the 0th neuron is w=1, the leakage is λ=-1, and the positive threshold is used. floor threshold Reset level V rst =0. The weights of the first neuron are w = 1, -1, no leakage, positive threshold. floor threshold No level reset is performed. This structure contains a feedback structure from neuron 1 to neuron 0. Let the output pulse of neuron 1 be Spike, then the output pulse of neuron 0 is Y*Spike (the aforementioned AND gate function). The membrane level of neuron 1 is XY*Spike. As long as X>Y*Spike, neuron 1 will continuously emit pulses; only when X=Y*Spike, the membrane level of neuron 1 drops to 0, will it stop emitting pulses. At this time, Spike=X / Y, that is, the number of output pulses is the division of the number of input pulses.

[0136] refer to Figure 19 In the function "square", two neurons are required. The weight of the 0th neuron is w=1, there is no leakage, and it has a positive threshold. There is a threshold with 10 bits of random accumulation, and a floor threshold. No level reset is performed. The weight w = 1 for the first neuron, the leakage λ = -1, and the positive threshold. floor threshold Reset level V rst =0. The 0th neuron contains a random number window Mask = 1023, with a random threshold between 1 and 1024. Since no level reset is performed, each input pulse increases its level by 1. Assuming X pulses are input, the expected number of pulses emitted by neuron 0 is... The relationship is approximately the square of X. Neuron 1 acts as a modulator, preventing neuron 0 from firing pulses even when there are no input pulses.

[0137]

[0138] Table 3

[0139] The calculation method for spiking neural networks provided by this invention is described below, with reference to... Figure 20 The computational method for spiking neural networks described below is based on the biologically reliable neuronal computational circuit described above.

[0140] Step 2010: Calculate the membrane level at the previous moment and the input neural network pulse signal to obtain the membrane level at the current moment;

[0141] Step 2020: Generate a pulse signal based on the membrane level at the current moment.

[0142] Figure 21 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 21 As shown, the electronic device may include: a processor 2110, a communications interface 2120, a memory 2130, and a communication bus 2140, wherein the processor 2110, the communications interface 2120, and the memory 2130 communicate with each other via the communication bus 2140. The processor 2110 can call logical instructions in the memory 2130 to execute a computational method for a spiking neural network, the method including:

[0143] The membrane level at the previous moment and the input neural network pulse signal are processed to obtain the membrane level at the current moment;

[0144] A pulse signal is generated based on the membrane level at the current moment.

[0145] Furthermore, the logical instructions in the aforementioned memory 2130 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0146] On the other hand, the present invention also provides a computer program product, the computer program product comprising a computer program that can be stored on a non-transitory computer-readable storage medium, wherein when the computer program is executed by a processor, the computer is able to execute the computational method for a spiking neural network provided by the above methods, the method comprising:

[0147] The membrane level at the previous moment and the input neural network pulse signal are processed to obtain the membrane level at the current moment;

[0148] A pulse signal is generated based on the membrane level at the current moment.

[0149] In another aspect, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to perform the computational methods for spiking neural networks provided by the methods described above, the methods comprising:

[0150] The membrane level at the previous moment and the input neural network pulse signal are processed to obtain the membrane level at the current moment;

[0151] A pulse signal is generated based on the membrane level at the current moment.

[0152] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0153] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0154] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A biologically reliable neuronal computing circuit, characterized in that, It includes a synaptic integration module, a leakage integration module, and a threshold comparison and pulse delivery module connected in sequence; The synaptic integration module is used to calculate the current membrane level based on the membrane level at the previous moment and the input neural network pulse signal, and send the current membrane level to the leakage integration module; The leakage integration module is used to perform a leakage operation on the membrane level at the current moment, and send the membrane level after the leakage operation to the threshold comparison and pulse delivery module; The threshold comparison and pulse delivery module is used to compare the membrane level after the leakage operation with the preset pulse delivery threshold, and generate a pulse signal based on the threshold judgment result; The synaptic integration module includes neural network synaptic units; The neural network synaptic unit is used to obtain neural network synaptic weight values ​​based on neural network pulse signals, and store the neural network synaptic weight values ​​in the synaptic integration module; The synaptic integration module is used to perform a weighted summation of the neural network pulse signal according to the pre-stored neural network synaptic weight values, and then accumulate it with the membrane level at the previous moment to obtain the membrane level at the current moment. The synaptic integration module also includes a random number generation unit; The random number generation unit is used to randomly filter the neural network pulse signals to obtain a subset of the neural network pulse signals; The synaptic integration module is used to perform a weighted summation of a subset of the neural network pulse signals based on pre-stored neural network synaptic weight values, and then accumulate it with the membrane level at the previous moment to obtain the membrane level at the current moment. Perform a leakage operation on the current membrane level, including: Forward leakage is performed on the membrane level at the current moment; or Reverse leakage of the membrane level at the current moment; or Randomly leak the membrane level at the current moment; The pulse firing threshold includes a positive threshold. A pulse signal is generated based on a comparison between a pre-set pulse firing threshold and the membrane level after the leakage operation, and the threshold determination result includes: When the membrane level after the leakage operation is higher than or equal to the positive threshold, a pulse signal and a level reset signal are generated; The pulse firing threshold includes a negative threshold. A pulse signal is generated based on a comparison between a pre-set pulse firing threshold and the membrane level after the leakage operation, and the threshold determination result. This includes: If the membrane level after the leakage operation is lower than the negative threshold, only a level reset signal is generated.

2. The biologically reliable neuronal computing circuit according to claim 1, characterized in that, The leakage integration module is also used to receive the membrane level after threshold comparison by the threshold comparison and pulse emission module and perform leakage operation.

3. The biologically reliable neuronal computing circuit according to claim 1, characterized in that, The threshold comparison and pulse delivery module includes a membrane level reset unit; The membrane level reset unit is used to receive the level reset signal and reset the membrane level at the current moment to a preset level according to the level reset signal.

4. A computational method for a spiking neural network, characterized in that, The biologically trusted neuronal computing circuit as described in claim 1 includes: The membrane level at the previous moment and the input neural network pulse signal are processed to obtain the membrane level at the current moment; A pulse signal is generated based on the membrane level at the current moment.

5. The calculation method for a spiking neural network according to claim 4, characterized in that, The step of generating a pulse signal based on the current membrane level includes: If the membrane level at the current moment is higher than or equal to the positive threshold, a pulse signal is output.

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