A dynamic element matching device and method

Abstract

A dynamic element matching device and method provided by the present invention add the output signal of the current cycle of the NS SAR ADC to the shift pointer of the current cycle, perform trigger delay, shift the output signal of the next week of the decoded NS SAR ADC, and then perform logical selection on the DAC capacitor array, so that in each cycle, the shift pointer contains the information of the output signal of the previous cycle of the NS SAR ADC. The shift pointer is used to shift the digital decoding signal of the current cycle, and then select the capacitors of each weight bit in the DAC capacitor array of the current cycle. After multiple cycles of modification, the mismatch error of the DAC capacitor array is effectively shaped, greatly improving the performance of capacitor dynamic matching; in terms of logical selection of the DAC capacitor array, a simple output decoding unit replaces a complex binary-to-thermometer decoder to realize weight bit rotation, without setting 1 buffer module for each capacitor, avoiding the exponential growth of the hardware structure complexity, and greatly reducing the hardware cost.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and particularly to a dynamic element matching device and method. Background Art

[0002] The noise shaping successive approximation analog-to-digital converter (NS SAR ADC) has been widely used due to its advantages of high resolution and low power consumption. The NS SAR ADC mainly includes a sampling switch, a digital-to-analog converter (DAC), a noise shaping filter, a comparator, and a SAR logic module. The analog signal is input to the sampling switch for sampling to obtain an input voltage. The DAC stores the charge of the sampled input voltage and outputs a successive comparison voltage to the comparator. The noise shaping filter integrates the residual voltage on the capacitor array in the DAC to obtain an integrated voltage. The comparator adds the input voltage and the integrated voltage and provides gain for the integrated voltage. The SAR logic module adjusts the voltage of the capacitor array in the DAC according to the output signal of the comparator to achieve successive approximation.

[0003] The accuracy of the NS SAR ADC is mainly determined by the dynamic performance of the DAC, and the dynamic performance of the DAC depends on the matching performance of the capacitor array. The capacitor array uses capacitors with different ratios and different numbers for charging and discharging to achieve the conversion from digital quantity to analog quantity. Affected by process parameters, device area, layout design and other factors, the matching degree of the DAC capacitor array often cannot reach the preset target.

[0004] In view of the capacitor mismatch problem of the DAC capacitor array, the prior art uses a binary-to-thermometer code circuit for capacitor selection. Its disadvantage is that the circuit structure of the binary-to-thermometer code circuit itself is complex, and the quantity increases exponentially with the number of bits of the DAC capacitor array, resulting in too high hardware cost.

[0005] The "data weighted average algorithm module and analog-to-digital conversion circuit" with the application number 202010717304.5 controls the multi-bit high-order capacitor array by setting multiple parallel structures. The parallel structure is a loop body composed of a state machine unit, a logic comparator, a pointer generator, and a trigger, so that when the data weighted average algorithm module controls the external multi-bit high-order capacitor array, the selection probability of each capacitor in the external multi-bit high-order capacitor array is the same, minimizing the mismatch error of the capacitor by the module, and thus improving the accuracy of the analog-to-digital converter. This solution has the following disadvantages: the number of groups of the parallel structure needs to be set according to the number of capacitors of the DAC. For example, if 3-bit digital-to-analog conversion is to be performed, seven groups of parallel structures need to be set, resulting in an exponential increase in hardware cost as the number of bits of the DAC capacitor array increases; only probabilistic selection is made for each capacitor of the multi-bit high-order capacitor array, and no judgment and processing are performed on the middle and low bits, resulting in the matching performance of the DAC capacitor array being insufficient to meet the actual requirements.

[0006] Therefore, there is a need to propose a dynamic matching device and method with high matching performance achieved at low hardware cost to solve the capacitance mismatch problem of the DAC capacitor array. Summary of the Invention

[0007] The present invention provides a dynamic element matching device and method to solve the problems of high hardware cost and poor capacitance matching performance existing in the prior art.

[0008] A dynamic element matching method includes the following steps:

[0009] (1) Add the output signal of the external NS SAR ADC in the current cycle and the shift pointer in the current cycle, and after trigger delay, obtain the shift pointer in the next cycle.

[0010] (2) When the above addition and trigger delay are completed, the output signal of the external NS SAR ADC in the next cycle has been decoded to obtain a digital decoded signal.

[0011] (3) Shift the digital decoded signal according to the shift pointer in the next cycle to obtain a digital selection signal.

[0012] (4) The digital selection signal performs logical selection on the DAC capacitor array of the external NS SAR ADC.

[0013] Furthermore, the number of bits of the output signal in the current cycle, the shift pointer in the current cycle, the shift pointer in the next cycle, the digital decoded signal, and the digital selection signal is the same as the number of bits of the DAC capacitor array of the external NS SAR ADC.

[0014] Furthermore, in the step (4), the DAC capacitor array of the external NS SAR ADC contains at least one capacitor sub-array, and the digital selection signal is respectively input to each capacitor sub-array to perform logical selection on the capacitors in each capacitor sub-array.

[0015] A dynamic element matching device applying the above method includes an output decoding unit, a shift pointer unit, and a shift register unit; the shift pointer unit includes an adder and a trigger; the adder adds the output signal of the current cycle of the external NS SAR ADC and the shift pointer of the current cycle; under the control of the external NS SAR ADC, the trigger triggers and delays the added data to obtain the shift pointer of the next cycle; when the shift pointer of the next cycle is obtained, the output decoding unit has received the output signal of the next cycle of the external NS SAR ADC and completed the decoding of the output signal of the next cycle to obtain a digital decoding signal; the shift register unit shifts the digital decoding signal according to the shift pointer of the next cycle to obtain a digital selection signal, and the digital selection signal is input to the DAC capacitor array.

[0016] Further, the number of bits of the output decoding unit is the same as the number of bits of the DAC capacitor array.

[0017] Further, the output decoding unit includes at least 1 buffer module; the number of buffer modules is the same as the number of bits of the DAC capacitor array.

[0018] Further, in each buffer module, 2 inverters connected in series are provided.

[0019] Further, the number of bits of the adder and the trigger is the same.

[0020] The advantages and effects of the present invention are:

[0021] (1) In each cycle, the shift pointer contains the information of the output signal of the previous cycle of the NS SAR ADC. Using this shift pointer to shift the digital decoding signal of this cycle, and then selecting the capacitors of each weight bit in the DAC capacitor array of this cycle. After being modified and changed through multiple cycles, the mismatch error of the DAC capacitor array is effectively shaped, greatly improving the performance of capacitor dynamic matching;

[0022] In terms of logically selecting the DAC capacitor array, the output decoding unit with a simple structure replaces the complex binary-to-thermometer decoder to achieve weight bit rotation. There is no need to set 1 buffer module for each capacitor, avoiding the exponential growth of the hardware structure complexity and greatly reducing the hardware cost;

[0023] (2) When the number of bits of the DAC capacitor array is large and the number of capacitors is relatively large, the DAC capacitor array can be divided into multiple capacitor sub-arrays, and then the technical solution of the present invention can be used for the high-bit and middle-bit capacitors of each capacitor sub-array, which can further avoid the exponential growth of the hardware circuit complexity while ensuring the matching performance, and further reduce the hardware cost. Description of the Drawings

[0024] Figure 1 This is the structural principle block diagram of the present invention.

[0025] Figure 2 This is the circuit schematic diagram of the output decoding unit.

[0026] Figure 3 This is the circuit schematic diagram of the shift pointer unit.

[0027] Figure 4 This is the circuit schematic diagram of the shift register unit.

[0028] Figure 5 This is the circuit schematic diagram of the present invention applied to a 9-bit NS SAR ADC.

[0029] Figure 6 This is the matching process of the present invention applied to the 3-bit DAC capacitor array.

[0030] Figure 7 This is the output spectrum of the NS SAR ADC without enabling the technical solution of the present invention.

[0031] Figure 8 This is the output spectrum of the NS SAR ADC with the technical solution of the present invention enabled. Detailed implementation manners

[0032] The present invention will be further described below in conjunction with embodiments, but the present invention is not limited to these embodiments.

[0033] A dynamic element matching method includes the following steps:

[0034] (1) Add the output signal of the external NS SAR ADC in the current cycle and the shift pointer in the current cycle, and after trigger delay, obtain the shift pointer in the next cycle;

[0035] (2) When the above addition and trigger delay are completed, the output signal of the external NS SAR ADC in the next cycle has been decoded to obtain a digital decoding signal;

[0036] (3) Shift the digital decoding signal according to the shift pointer in the next cycle to obtain a digital selection signal;

[0037] (4) The digital selection signal makes a logical selection of the DAC capacitor array of the external NS SAR ADC.

[0038] Furthermore, the number of bits of the output signal in the current cycle, the shift pointer in the current cycle, the shift pointer in the next cycle, the digital decoding signal, and the digital selection signal is the same as the number of bits of the DAC capacitor array of the external NS SAR ADC.

[0039] Further, in the step (4), the DAC capacitor array of the external NS SAR ADC includes at least one capacitor sub-array, and the digital selection signals are respectively input to each capacitor sub-array to perform logical selection on the capacitors in each capacitor sub-array.

[0040] A dynamic element matching device applying the above method includes an output decoding unit, a shift pointer unit, and a shift register unit; the shift pointer unit includes an adder and a trigger; the adder adds the output signal of the current cycle of the external NS SAR ADC and the shift pointer of the current cycle; under the control of the external NS SAR ADC, the trigger triggers and delays the added data to obtain the shift pointer of the next cycle; when the shift pointer of the next cycle is obtained, the output decoding unit has received the output signal of the next cycle of the external NS SAR ADC and completed the decoding of the output signal of the next cycle to obtain a digital decoding signal; the shift register unit shifts the digital decoding signal according to the shift pointer of the next cycle to obtain a digital selection signal, and the digital selection signal is input to the DAC capacitor array.

[0041] The structural principle block diagram of the present invention is as Figure 1 shown. The input end of the output decoding unit is connected to the output end of the external NS SAR ADC, and the output end of the output decoding unit is connected to the input end of the shift register unit; the shift pointer unit includes an adder and a trigger, one input end of the adder is connected to the output end of the external NS SAR ADC, the other input end of the adder is connected to the output end of the trigger, and the output end of the adder is connected to the input end of the trigger; the control end of the trigger is connected to the sampling clock signal of the external NS SAR ADC, the output end of the trigger is connected to the control end of the shift register unit, and the output end of the trigger is also connected to the other input end of the adder; the output end of the shift register unit is connected to the DAC capacitor array of the external NS SAR ADC.

[0042] The number of bits of the output decoding unit is the same as that of the DAC capacitor array. The output decoding unit includes at least one buffer module; the number of buffer modules is the same as that of the DAC capacitor array. When the DAC bit number is n, the number of bits of the output decoding unit is also n, the number of buffer modules is also n, and the output bit number of the output decoding unit is 2 n -1. The circuit schematic diagram of the output decoding unit is as Figure 2 shown, where A1, A2, A3... An are the input terminals of the output decoding unit, and Y1, Y2, Y3... Y2 n-1 is the output terminal of the output decoding unit. The number of input terminals is the same as the number of bits of the DAC capacitor array, and the total number of output terminals has an exponential relationship with the number of bits of the DAC capacitor array.

[0043] In each buffer module, there are 2 inverters connected in series, and the output terminal of each buffer module is 2 n -2 n-1 For example, the input of the first buffer module is A1 and the output is Y1. The input of the second buffer module is A2 and the output is Y2, Y3. The input of the third buffer module is A3 and the output is Y4, Y5, Y6, Y7. The input of the nth buffer module is An and the output is Y2 n-1 to Y2 n -1. When the number of bits of the output decoding unit is n, there are n buffer modules, and the output decoding unit converts the n-bit digital input code into 2 n -1-bit digital output code. Taking n = 3 as an example, when the output decoding unit is 3, there are 3 buffer modules. The output decoding unit converts the bit digital input code into a 7-bit digital output code. At this time, the input of the output decoding unit is A3A2A1, and the output is Y7Y6Y5Y4Y3Y2Y1.

[0044] The shift pointer unit includes an adder and a flip-flop, and the number of bits of the adder and the flip-flop is the same. The circuit schematic diagram of the shift pointer unit is as Figure 3 shown. Through Figure 3 it can be seen that the input terminals of the adder are A1, A2, A3, Q1, Q2, Q3. Among them, A1, A2, A3 are also the input signals of the output decoding unit at the same time, that is, the input signals of the adder and the output decoding unit are the same, both are the output signals of the NS SAR ADC, and Q1, Q2, Q3 are the output signals of the flip-flop, and the current shift pointer is fed back to the adder in each cycle to participate in the acquisition process of the shift pointer in the next cycle. In Figure 3 Fs is the sampling signal, provided by the NSSAR ADC, and is used to control the sampling process.

[0045] The shift register unit is a barrel shift register. The barrel shift register is composed of multiple two-input data selectors, receives the shift pointer from the flip-flop as the control signal, receives the digital decoding signal to be shifted from the output decoding unit as the input signal, and cyclically shifts the digital decoding signal to be shifted according to the value of the shift pointer to obtain the digital selection signal.

[0046] Taking the number of bits n = 3 of the DAC capacitor array as an example, the circuit schematic diagram of the shift register unit is as Figure 4 shown, through Figure 4It can be seen that the shift register unit is composed of 7 rows and 3 columns of two-input selectors, namely M1 - M21, where the control terminals are correspondingly connected to Q1, Q2, and Q3 of the flip-flop, and the input terminals are correspondingly connected to the output terminals Y1, Y2, Y3, Y4, Y5, Y6, and Y7 of the output decoding unit. After shifting and registering, digital signals D1 - D7 are obtained, that is, digital selection signals. These digital selection signals are input to the DAC capacitor array for capacitor selection.

[0047] The circuit schematic diagram of applying the present invention to a 9-bit NS SAR ADC is as Figure 5 shown. In Figure 5 , the 9-bit DAC capacitor array is divided into 2 capacitor sub-arrays, namely C DAC and C DAC' . The analog signal V i1 is input to C s1 through the sampling switch φ DAC , and the analog signal V i2 is input to C s2 through the sampling switch φ DAC' . C DAC is divided into the high 4-bit C DAC1 , the middle 4-bit C DAC2 , and the low 1-bit C DAC3 . C DAC' is divided into the high 4-bit C DAC1' , the middle 4-bit C DAC2' , and the low 1-bit C DAC3' . The starting positions of the high, middle, and low capacitors are variable and are determined by the output signal of the NSSAR ADC and the shift pointer. Since the mismatch error generated by the low capacitors is small, in this application, only the high and middle capacitors in each capacitor sub-array are subjected to capacitor matching, and the low capacitors can also be matched as needed. Compared with the method of only performing mismatch processing on the high capacitors, the accuracy is higher and the matching performance is more excellent. The functions of the sampling switch, DAC, noise shaping filter, comparator, and SAR logic module have been described in the background art and will not be elaborated here.

[0048] The method for dividing the high, middle, and low capacitors is as follows: Since the n-bit DAC capacitor array contains 2 n - 1 capacitors, then the first bit has 2 n-1 capacitors, the second bit has 2 n-2 capacitors, the third bit has 2 n-3 capacitors... the nth bit has 2 n-n capacitors. Taking n = 3 as an example for illustration, the 3-bit DAC capacitor array contains 7 capacitors, which are divided into high, middle, and low. Then the high part contains 4 capacitors, the middle part contains 2 capacitors, and the low part contains 1 capacitor.

[0049] Taking the 3-bit DAC capacitor array as an example to illustrate the matching process of the present invention, as Figure 6 shown. Under the initial condition, the shift pointer P for N cycles is 000. Assuming that the output signal of the N cycles of the NS SAR ADC is 001, at this time the pointer P points to the high-order C u1 , then C u1 -C u4 is the high-order, C u5 , C u6 are the middle-order, C u7 is the low-order. Then in the N+1 cycle, the shift pointer P is the sum of the shift pointer of the N cycles and the output signal of the N cycles of the NS SAR ADC, obtaining 001. Assuming that the output signal of the N+1 cycle of the NS SAR ADC is 010, then shift the output signal 010 of the N+1 cycle of the NS SAR ADC with the shift pointer 001 of the N+1 cycle. At this time, the pointer points to C u2 , then select C u2 -C u5 as the high-order, select C u6 , C u7 as the middle-order, select C u1 as the low-order. And so on. In the N+2 cycle, the shift pointer P is 011. Assuming that the output signal of the N+2 cycle of the NS SAR ADC is 011, the pointer points to C u4 , select C u4 -C u7 as the high-order, select C u1 , C u2 as the middle-order, select C u3 as the low-order. In the N+3 cycle, the shift pointer P is 110. Assuming that the output signal of the N+3 cycle of the NS SAR ADC is 100, the pointer points to C u7 , select C u7 , C u1 , C u2 , C u3 as the high-order, select C u4 , C u5 as the middle-order, select C u6 as the low-order.

[0050] When adding 0.5% capacitor mismatch to the DAC capacitor array in the NS SAR ADC, without enabling the device and method provided by the present invention, there are many harmonics in the output spectrum of the NS SAR ADC. The effective number of bits (ENOB) of the NS SAR ADC is 13 bits, and the spurious-free dynamic range (SFDR) is 80 dB. The output spectrum is as Figure 7As shown. Under the same conditions, when the device and method provided by the present invention are enabled, the harmonics in the output spectrum of the NS SAR ADC are effectively suppressed. The effective number of bits (ENOB) of the NS SAR ADC is 14.8 bits, and the spurious-free dynamic range (SFDR) is increased to 97.1 dB. The output spectrum is as Figure 8 shown. It can be seen that by using the technical solution provided by the present invention, the capacitance matching performance can be greatly improved.

Claims

1. A dynamic element matching method, characterized in that, It includes the following steps: (1) Add the output signal of the current cycle of the external NS SAR ADC and the shift pointer of the current cycle, and after trigger delay, obtain the shift pointer of the next cycle; (2) When the above addition and trigger delay are completed, the output signal of the next cycle of the external NS SAR ADC has been decoded to obtain a digital decoded signal; (3) Shift the digital decoded signal according to the shift pointer of the next cycle to obtain a digital selection signal; (4) Use the digital selection signal to perform logical selection on the DAC capacitor array of the external NS SAR ADC.

2. The dynamic element matching method according to claim 1, characterized in that: The number of bits of the output signal of the current cycle, the shift pointer of the current cycle, the shift pointer of the next cycle, the digital decoded signal, and the digital selection signal is the same as the number of bits of the DAC capacitor array of the external NS SAR ADC.

3. The dynamic element matching method according to claim 1, characterized in that: In step (4), the DAC capacitor array of the external NS SAR ADC contains at least one capacitor sub-array, and the digital selection signal is respectively input to each capacitor sub-array to perform logical selection on the capacitors in each capacitor sub-array.

4. A dynamic element matching device applying the method according to any one of claims 1-3, characterized in that: It includes an output decoding unit, a shift pointer unit, and a shift register unit; The shift pointer unit includes an adder and a trigger; the adder adds the output signal of the current cycle of the external NS SAR ADC and the shift pointer of the current cycle; under the control of the external NS SAR ADC, the trigger performs trigger delay on the added data to obtain the shift pointer of the next cycle; When the shift pointer of the next cycle is obtained, the output decoding unit has received the output signal of the next cycle of the external NS SAR ADC and completed the decoding of the output signal of the next cycle to obtain a digital decoded signal; The shift register unit shifts the digital decoded signal according to the shift pointer of the next cycle to obtain a digital selection signal, and the digital selection signal is input to the DAC capacitor array.

5. The dynamic element matching device according to claim 4, characterized in that: The number of bits of the output decoding unit is the same as the number of bits of the DAC capacitor array.

6. The dynamic element matching device according to claim 5, characterized in that: The output decoding unit includes at least one buffer module; the number of buffer modules is the same as the number of bits of the DAC capacitor array.

7. The dynamic element matching device according to claim 6, characterized in that: In each buffer module, two inverters connected in series are provided.

8. The dynamic element matching device according to claim 4, characterized in that: The adder and the trigger have the same number of bits.

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