Voltage regulator circuit for RFID circuit

Abstract

A voltage regulator circuit for RFID circuits utilizes a highly efficient circuit topology to minimize power consumption, providing only the current required to regulate the output voltage. This voltage regulator circuit consumes no quiescent current, minimizing power consumption. It does not include an inductor, transformer, operational amplifier, reference voltage source, or reference current source, reducing complexity and chip area. The voltage regulator circuit includes a driver element, a control circuit, and a sensing circuit. The driver element drives a controlled current to the output to increase the voltage. The sensing circuit measures the voltage at the output and, if it reaches a target value set by the component's internal parameters, sends a signal to the control circuit. When the output voltage reaches a threshold, the control circuit stops driving the element, minimizing the current required to regulate the voltage.

Description

Technical Field

[0001] The present invention relates to a voltage stabilizing circuit for a radio frequency identification (RFID) circuit, and more particularly to an energy-saving voltage stabilizing circuit. Background Art

[0002] Radio frequency identification (RFID) systems utilize "tags" attached to objects to be tracked and have been used in automated payment systems and to track animals or goods in inventory or in transit.

[0003] For passive RFID tags, front-end circuitry, such as rectifiers and regulators, is used to extract energy from the incoming radio frequency (RF) signal and power the processor circuitry within the RFID chip. Because the energy available from the RF signal is inversely proportional to the read distance, the maximum read distance of an RFID tag is limited by the power consumption of the RFID circuitry.

[0004] In order to reduce the power consumption of the circuit without affecting the processor of the RFID tag, the power consumption of the front-end circuit (such as the voltage stabilization circuit) can be reduced.

[0005] U.S. Patent No. 7,538,673B2 describes a voltage regulator circuit based on a low-dropout oscillator (LDO). The LDO approach has the advantage of not requiring an inductor or transformer, which would be impossible in an RFID tag. However, it has several components that consume quiescent current, resulting in high power consumption. Furthermore, the circuit has multiple active circuits, such as operational amplifiers and reference current sources, which increases complexity and chip area.

[0006] U.S. Patent No. 10,043,124B2 describes a switching regulator-based voltage regulation circuit that eliminates the need for an inductor or transformer. The invention incorporates a static comparator that consumes quiescent current. While the circuit can be designed to consume very low current using very large resistors, its size is impractical for a regulator within an RFID chip. Furthermore, the output voltage level is set by the input voltage level, which is achieved by using a shunt limiter to divert excess power to ground. Therefore, lowering the target output voltage results in greater power waste.

[0007] In view of the above situation, there is a need to provide an improved regulator for RFID tags, which does not consume static current to reduce power consumption and does not include an operational amplifier, a reference voltage source or a reference current source to reduce complexity and chip area. Summary of the Invention

[0008] The present invention relates to a voltage stabilizing circuit for an RFID circuit, comprising:

[0009] a first input node and a second input node, each connected to an output of a rectifier circuit that generates a half-wave rectified voltage signal from an electromagnetic wave signal received through the RFID circuit;

[0010] an output node connected to the RFID circuit;

[0011] a control circuit connected to the first input node and the second input node, the control node, and the sensing node, wherein the control circuit can control the control node when triggered by the sensing node, the control circuit comprising:

[0012] a first transistor and a second transistor of a cross-coupled pair forming a cross-coupled pair configuration, a pulse current source connected to the first transistor and the second transistor of the cross-coupled pair,

[0013] a first switch connected to the first transistor and the second transistor of the cross-coupled pair,

[0014] a second switch connected to the first and second transistors of the cross-coupled pair, and

[0015] a third switch connected to the first and second transistors of the cross-coupled pair;

[0016] a driving element coupled between the first input node and the output node and driven by the control node, wherein the driving element comprises:

[0017] a drive transistor connected to the first input node and the control node so as to drive current from the first input node to the output node when driven by the control node, and

[0018] a blocking diode coupled between the driving transistor and the output node to block current from flowing back to the first input node; and

[0019] A sensing circuit is connected to the output node, wherein the sensing circuit can sense the output voltage and send a signal to other circuits when the sensed voltage reaches a target value, the sensing circuit comprising:

[0020] Output voltage adjustment components,

[0021] a fourth switch connecting the sensing node and the output voltage adjustment component, and

[0022] A fifth switch connects the sensing node to the ground terminal.

[0023] According to the present invention, the voltage stabilizing circuit for an RFID circuit further includes an output capacitor connecting the output node to the ground terminal.

[0024] According to the present invention, the first switch and the third switch are connected to the first transistor and the second transistor of the cross-coupled pair via a latch node.

[0025] According to the invention, the second switch is connected to the first transistor and the second transistor of the cross-coupled pair via a control node.

[0026] According to the present invention, a pulsed current source is connected between the first input node and the first transistor of the cross-coupled pair.

[0027] According to the present invention, the first switch is configured to be connected between the latch node and the ground terminal.

[0028] According to the present invention, the second switch is configured to be connected between the control node and the ground terminal.

[0029] According to the present invention, the third switch is configured to be connected between the latch node and the first input node, or between the latch node and the ground terminal.

[0030] According to the present invention, the first switch is a transistor driven by the sensing node.

[0031] According to the present invention, the second switch and the third switch are transistors driven by a second holding node controlled by a switch controller.

[0032] According to the present invention, a switch controller includes a first transistor, a second transistor, a third transistor, and a fourth transistor of the switch controller, wherein the first transistor and the second transistor of the switch controller are connected in a diode-connected configuration.

[0033] According to the present invention, the first transistor of the switch controller is configured to connect the first input node to the first holding node.

[0034] According to the present invention, the second transistor of the switch controller is configured to connect the second input node to the second holding node.

[0035] According to the present invention, the third transistor of the switch controller is driven to connect the first holding node to the ground terminal through the second input node.

[0036] According to the present invention, the fourth transistor of the switch controller is configured to connect the second holding node to the ground terminal via the first holding node drive.

[0037] According to the present invention, the first and second transistors of the switch controller connect the respective input nodes to the third switch and the second switch.

[0038] According to the present invention, the first and second transistors of the switch controller can be replaced by diodes.

[0039] According to the present invention, a pulse current source in a control circuit includes a current mirror having a first mirror transistor and a second mirror transistor, wherein source terminals of the first mirror transistor and the second mirror transistor are commonly connected to a first input node, gate terminals of the first mirror transistor and the second mirror transistor are commonly connected to a mirror node, and a current source reset transistor couples the mirror node to a ground terminal.

[0040] According to the present invention, the mirror node is coupled to the ground terminal via a current source reset transistor.

[0041] According to the present invention, the current source reset transistor is driven by the second input node.

[0042] According to the invention, the drain of the first mirror transistor is connected to the mirror node.

[0043] According to the present invention, the voltage stabilizing circuit for an RFID circuit further includes a capacitor connecting the mirror node to the ground terminal.

[0044] According to the present invention, the blocking diode can be replaced by a diode-connected transistor.

[0045] According to the present invention, the output voltage adjustment component is a diode, a diode-connected transistor, a transistor stack, a diode-connected transistor, a resistor, or any combination thereof.

[0046] According to the present invention, the target value can be adjusted internally.

[0047] According to the present invention, the fourth switch is a transistor driven by one of the input nodes.

[0048] According to the present invention, the fifth switch is a transistor driven by the other one of the input nodes.

[0049] The general purpose of the present invention is to provide an energy-saving voltage stabilization circuit for RFID tags, which minimizes the power consumption of the voltage stabilization circuit and maximizes the reading range of the RFID tag. The voltage stabilization circuit has most (if not all) of the advantages of the voltage regulators of the prior art, while not having their significant disadvantages. To achieve this purpose, the developed voltage stabilization circuit implements voltage regulation by using a driving element having a control circuit and a sensing circuit. The driving element drives a controlled current to the output terminal to increase the voltage. The sensing circuit measures the voltage at the output terminal and sends a signal to the control circuit if the voltage reaches a target value, which is set by the internal parameters of the component. When the output voltage reaches the target value, the control circuit stops the driving element, minimizing the current required to regulate the voltage. In addition, the voltage stabilization circuit does not contain any static current branches, which further improves the efficiency of the voltage stabilization circuit.

[0050] Another object of the present invention is to provide a voltage stabilization circuit of the type described which does not require a coupling transformer or an inductor and which can be easily constructed utilizing a relatively small area on an RFID tag.

[0051] Another object of the present invention is to provide a voltage stabilization circuit of the type described which does not require any additional reference voltage source or reference current source and which can be easily constructed using a relatively small area on an RFID tag.

[0052] These objects are achieved according to the circuit features that have been briefly summarized above and will be described in further detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 This is the functional block diagram of an RFID tag.

[0054] Figure 2 is a schematic framework diagram of a voltage stabilizing circuit according to the present invention.

[0055] Figure 3 The invention relates to a control circuit of a voltage stabilizing circuit.

[0056] Figure 4 is an exemplary circuit implementation of a switch and a switch controller in a control circuit of a voltage stabilization circuit according to the present invention.

[0057] Figure 5 is an exemplary circuit implementation of a pulse current source in a control circuit of a voltage stabilization circuit according to the present invention.

[0058] Figure 6 is an exemplary circuit implementation of a driving element of a voltage stabilization circuit according to the present invention.

[0059] Figure 7 The present invention relates to an induction circuit of a voltage stabilizing circuit.

[0060] Figure 8 It is an exemplary embodiment of the voltage stabilizing circuit of the present invention.

[0061] Figure 9 Shown in Figure 8 The voltage and current waveforms appearing at various circuit points referenced in . DETAILED DESCRIPTION

[0062] Figure 1 1 shows a functional block diagram of the RFID tag 100. Figure 1In the example, an RF signal is received via antenna 101. Rectifier circuit 102 then rectifies the signal into two half-wave rectified signals with a phase difference of approximately 180 degrees at first input node 103 and second input node 104. These signals are then fed into voltage regulator circuit 105, which powers output capacitor 106 and provides a regulated voltage at output node 107. The regulated voltage at output node 107, maintained near a predetermined value (referred to as the "target value") with a fluctuation of less than 10%, is used to power RFID circuit 108.

[0063] Figure 2 1 shows a schematic block diagram of a voltage stabilization circuit 105 according to the present invention. The voltage stabilization circuit 105 has two input terminals connected to a first input node 103 and a second input node 104, respectively, and has one output terminal connected to an output node 107. The voltage stabilization circuit 105 includes a control circuit 201, a driver element 202, and a sensing circuit 203. The control circuit 201 is connected to the sensing circuit 203 via a sensing node 204, and is connected to the driver element 202 via a control node 205. The driver element 202 is also connected to the sensing circuit 203 via the output node 107.

[0064] Voltage regulator circuit 105 operates in a cycle that can be divided into two phases: a driving phase and a reset phase. During the driving phase, the voltage at first input node 103 is greater than 0 volts, while the voltage at second input node 104 is approximately 0 volts. During the reset phase, the voltage at second input node 104 is greater than 0 volts, while the voltage at first input node 103 is approximately 0 volts. During the driving phase, control circuit 201 controls driver element 202 via control node 205 to drive current from first input node 103 to output node 107 through control element 202, thereby increasing the voltage at output node 107. When the voltage at output node 107 reaches a "target value," sensing circuit 203 sends a signal to control circuit 201 via sensing node 204. Control circuit 201 then stops driver element 202 from driving current to output node 107, preventing the voltage at output node 107 from rising above the "target value" (typically, no more than 5% of the target value). In the reset phase, the voltage stabilizing circuit 105 is reset to its initial state before the start of the driving phase and is ready for the next driving phase. Therefore, the voltage at the output node 107 will be regulated and maintained near the "target value".

[0065] The size of the output capacitor 106 can be adjusted to control the magnitude of the fluctuation in the output voltage at the output node 107 .

[0066] Figure 3A control circuit 201 for a voltage regulator circuit according to the present invention is shown. Control circuit 201 includes: a first transistor 319 of a cross-coupled pair and a second transistor 320 of a cross-coupled pair, which form a cross-coupled pair configuration; a pulsed current source 310; a first switch 321; a second switch 322; and a third switch 316. The first transistor 319 of the cross-coupled pair and the second transistor 320 of the cross-coupled pair are connected to the first switch 321 and the third switch 316 via a latch node 303, and to the second switch 322 via a control node 205. The pulsed current source 310 is connected between the first input node 103 and the first transistor 319 of the cross-coupled pair. The first switch 321 is connected between the node 303 and ground. The second switch 322 is connected between the control node 205 and ground. The third switch 316 is connected between the latch node 303 and the first input node 103.

[0067] Operation of the control circuit 201 initially begins with a drive phase. All switches 321, 322, and 316 are open, and the pulsed current source 310 briefly supplies current from the first input node 103 through the first transistor 319 of the cross-coupled pair and into the latch node 303, causing the voltage at the latch node 303 to be higher than the voltage at the control node 205. The duration of this current supply must be minimized to reduce power consumption. After the first input node 103 rises sufficiently high, the first transistor 319 of the cross-coupled pair will turn on before the second transistor 320 of the cross-coupled pair turns on, causing the first and second transistors 319 and 320 of the cross-coupled pair to latch, latching the latch node 303 high and the control node 205 to ground. If the first switch 321 were turned on during the drive phase, the voltage at the latch node 303 would be pulled to ground, triggering the first and second transistors 319 and 320 of the cross-coupled pair and pulling the voltage at the control node 205 up to the voltage at the first input node 103.

[0068] As known to those skilled in the art, a switch can be implemented by a transistor or a combination of transistors. For example, the first switch 321 can be implemented by a transistor driven by the sensing node 204 to trigger the operation of the control circuit 201.

[0069] The voltage at control node 205 may be used to control drive element 202 ; for example, directly by connecting control node 205 to drive element 202 , or indirectly by placing a buffer or inverter between control node 205 and drive element 202 .

[0070] For the reset phase, the first switch 321 must be turned off, and the second switch 322 and the third switch 316 must be turned on to reset the latch node 303 and the control node 205 , keeping the voltage of both nodes at ground.

[0071] In another embodiment, the third switch 316 may be connected between the latch node 303 and the ground terminal instead of being connected between the first input node 103 and the latch node 303 .

[0072] Figure 4 is an exemplary circuit implementation of the switches (i.e., the third switch 316 and the second switch 322) and the switch controller in the control circuit 201 of the voltage stabilization circuit according to the present invention. For example, the second switch 322 and the third switch 316 can be implemented using transistors that are commonly driven by the second holding node 302. The second holding node 302 is controlled by the switch controller so that the third switch 316 and the second switch 322 are kept off during the driving phase and kept on during the reset phase.

[0073] The switch controller includes a first transistor 311, a second transistor 312, a third transistor 313, and a fourth transistor 314 of the switch controller, wherein the first transistor 311 and the second transistor 312 of the switch controller are connected in a diode-connected configuration. The first transistor 311 of the switch controller connects the first input node 103 to the first holding node 301. The second transistor 312 of the switch controller connects the second input node 104 to the second holding node 302. The third transistor 313 of the switch controller is driven by the second input node 104 to connect the first holding node 301 to the ground terminal. The fourth transistor 314 of the switch controller is driven by the first holding node 301 to connect the second holding node 302 to the ground terminal.

[0074] During the driving phase, the voltage at the first input node 103 turns on the first transistor 311 of the switch controller, while the second input node 104 keeps the second transistor 312 and the third transistor 313 of the switch controller off. This makes the voltage at the first holding node 301 equal to the voltage at the first input node 103 minus the internal threshold voltage of the first transistor 311 of the switch controller. This in turn turns on the fourth transistor 314 of the switch controller and keeps the voltage at the second holding node 302 at approximately 0 volts, keeping the third switch 316 and the second switch 322 off. When the first input node 103 drops, the voltage at the first holding node 301 will remain at a maximum value, causing the first transistor 311 of the switch controller to block reverse current, ensuring that the third switch 316 and the second switch 322 are always off during the driving phase.

[0075] During the reset phase, the voltage at first input node 103 is approximately 0 volts, keeping first transistor 311 of the switch controller off. The voltage at second input node 104 turns on second and third transistors 312 and 313 of the switch controller, pulling the voltage at first holding node 301 down to 0 volts, which in turn turns off fourth transistor 314 of the switch controller. This causes the voltage at second holding node 302 to equal the voltage at second input node 104 minus an internal threshold, ultimately turning on third switch 316 and second switch 322. As second input node 104 decreases, the voltage at second holding node 302 remains at its maximum value, ensuring that third switch 316 and second switch 322 remain on during the reset phase.

[0076] In another embodiment, the first transistor 311 and the second transistor 312 of the switch controller are connected in a diode-connected configuration and may be replaced by diodes.

[0077] Figure 5 FIG2 is an exemplary circuit implementation of a pulsed current source 310 in the control circuit 201 of the voltage regulator circuit according to the present invention. The pulsed current source 310 includes a current source reset transistor 315 driven by the second input node 104, and a current mirror having a first mirror transistor 317 and a second mirror transistor 318. The first mirror transistor 317 and the second mirror transistor 318 each have a source terminal connected to the first input node 103 and a gate connected to the mirror node 304. The drain of the first mirror transistor 317 is connected to the mirror node 304. The mirror node 304 is coupled to ground via the current source reset transistor 315. The main current path of the pulsed current source 310 is from the first input node 103 through the second mirror transistor 318 to a node at the other terminal, which is connected to another node in the circuit.

[0078] The operation of pulsed current source 310 is divided into two phases: a driving phase and a reset phase. During the driving phase, when the voltage of first input node 103 rises, first mirror transistor 317 is turned on, and current begins to flow from first input node 103 into mirror node 304. Due to parasitic capacitance at mirror node 304, the voltage at mirror node 304 will rise later than that of first input node 103, resulting in a larger voltage difference between mirror node 304 and first input node 103. However, the voltage at first input node 103 will rise more slowly, allowing the voltage at mirror node 304 to catch up and subsequently resulting in a smaller voltage difference between mirror node 304 and first input node 103. During this period, depending on the magnitude of the voltage difference, second mirror transistor 318 is also turned on and off, providing current for a short period of time. The amount of time that second mirror transistor 318 provides current when it is on can be adjusted by increasing the threshold voltage of second mirror transistor 318 or lowering the threshold voltage of first mirror transistor 317. The amount of current provided can also be adjusted by adding a capacitor coupling the mirror node 304 to ground or adjusting the parasitic capacitance at the mirror node 304. In another aspect of the present invention, the mirror node 304 is also connected to ground via a current source reset transistor 315. The current source reset transistor 315 is driven by the second input node 104 to reset the circuit during a reset phase in which the voltage at the second input node 104 rises.

[0079] Figure 6 2 is an exemplary circuit implementation of the driving element 202 of the voltage stabilization circuit according to the present invention. The driving element 202 includes a driving transistor 323 connected in series with a blocking diode 324. The driving transistor 323 is used to drive current from one terminal to the other terminal, and the blocking diode 324 is used to block reverse current.

[0080] In another embodiment, the blocking diode 324 may be replaced by a diode-connected transistor.

[0081] Figure 7 Schematic diagram of sensing circuit 203 of the voltage stabilization circuit according to the present invention. Sensing circuit 203 includes two switches, a fourth switch 326 and a fifth switch 327, and an output voltage adjustment component 325. Fourth switch 326 connects sensing node 204 to output voltage adjustment component 325. Fifth switch 327 connects sensing node 204 to ground. The operation of sensing circuit 203 is divided into two phases: a driving phase and a reset phase.

[0082] During the driving phase, the fourth switch 326 must be turned on and the fifth switch 327 must be turned off in order to connect the sensing node 204 to the output node 107 via the output voltage regulating component 325. This results in the voltage at the sensing node 204 becoming equal to the voltage at the output node 107 minus the voltage across the output voltage regulating component 325 if the voltage at the output node 107 is greater than the voltage across the output voltage regulating component 325. Otherwise, the voltage at the sensing node 204 will remain approximately equal to 0 volts. When the voltage at the sensing node 204 reaches a certain voltage, it will serve as a signal to trigger the control circuit 201 to stop driving the element 202.

[0083] Therefore, the target value is equal to the sum of the voltage across the output voltage adjustment component 325 and the trigger voltage of the control circuit 201 .

[0084] The voltage across the output voltage adjustment component 325 may be used to set a target value for the regulation voltage at the output node 107 .

[0085] The output voltage adjustment component 325 can be implemented using any component that can generate a voltage across the component, such as a diode, a diode-connected transistor, a transistor, a resistor, a diode stack, or any combination thereof. Using the component's internal parameters to set the target value eliminates the need for an external reference circuit and reduces complexity, chip area, and power consumption.

[0086] During the reset phase, the fourth switch 326 must be turned off to cut off the current path from the output node 107 to the sensing node 204 , and the fifth switch 327 must be turned on to reset the sensing node 204 to the ground.

[0087] Figure 8 An exemplary embodiment of the voltage stabilizing circuit of the present invention is shown, wherein each stage is connected to Figure 2 The first switch 321 is implemented, for example, using a transistor driven by the sensing node 204. The second switch 322 and the third switch 316 are implemented, for example, using Figure 4 The driving element 202 uses Figure 6 , wherein the driving transistor 323 is connected to the first input node 103 and is directly driven by the control node 205, and the blocking diode 324 is connected to the output node 107. In the sensing circuit 203, the fourth switch 326 is implemented, for example, using a transistor driven by the first input node 103, the fifth switch 327 is implemented, for example, using a transistor driven by the second input node 104, and the output voltage adjustment component 325 is implemented using a diode, so that the target value is equal to the sum of the internal threshold voltages of the output voltage adjustment component 325 and the first switch 321.

[0088] Figure 9 Shown in Figure 8 Voltage and current waveforms appearing at various circuit points referenced in .

[0089] During the driving phase, the voltage stabilizing circuit 105 operates as follows.

[0090] First, the voltage at the first input node 103 continues to rise, causing the first transistor 311 of the switch controller to turn on, while the second input node 104 remains at approximately 0 volts, keeping the second transistor 312 and the third transistor 313 of the switch controller and the current source reset transistor 315 off. This makes the voltage at the first holding node 301 equal to the voltage at the first input node 103 minus the internal threshold voltage of the first transistor 311 of the switch controller, which in turn turns on the fourth transistor 314 of the switch controller and pulls the voltage at the second holding node 302 to ground, keeping the third switch 316 and the second switch 322 off. When the first input node 103 falls, the voltage at the first holding node 301 will remain at a maximum value, causing the first transistor 311 of the switch controller to block reverse current, thereby ensuring that the third switch 316 and the second switch 322 are always off throughout the entire driving phase.

[0091] When the voltage at the output node 107 does not reach the target value, as shown in FIG. Figure 9 As shown in the first two cycles of the waveform in FIG, the voltage at the sensing node 204 remains approximately 0 volts, which causes the first switch 321 to remain open.

[0092] Input node 103 also turns on first mirror transistor 317, while second input node 104 holds current source reset transistor 315 off, which in turn turns on second mirror transistor 318 and subsequently provides a current to latch node 303 through first transistor 319 of the cross-coupled pair. Since first transistor 319 and second transistor 320 of the cross-coupled pair form a cross-coupled pair, the current provided by first transistor 319 of the cross-coupled pair will latch the cross-coupled pair, keeping the voltage at latch node 303 equal to first input node 103 while the voltage at control node 205 remains approximately 0 volts. This ultimately turns on driver transistor 323, causing current to flow from first input node 103 through driver transistor 323 to output node 107, causing the voltage at output node 107 to rise.

[0093] In the driving phase, when the voltage at the output node 107 rises above the target value, as in Figure 9As described in the third, fourth, and fifth cycles of the waveform in FIG, the voltage at the sense node 204 will also rise and turn on the first switch 321, which in turn pulls the voltage at the latch node 303 down to ground, triggering the first transistor 319 and the second transistor 320 of the cross-coupled pair to pull the control node 205 high, disconnecting and stopping the current flow through the drive transistor 323, and stopping the rise of the voltage at the output node 107. Therefore, the voltage at the output node 107 will be regulated and maintained near the "target value".

[0094] It should be noted that in Figure 9 The waveform shown in FIG is an example; meaning, the operation of the voltage regulator circuit 105 may use more or less than three cycles so that the voltage at the output node 107 reaches the target value. This depends on a number of factors, such as the level of the target value, the capacitance value of the output capacitor 106, the current consumption of the RFID circuit 108, the amplitude of the half-wave rectified signal at the first input node 103, etc.

[0095] During the reset phase, the voltage stabilization circuit 105 operates as follows.

[0096] The voltage at the first input node 103 remains approximately 0 volts, keeping the first transistor 311 of the switch controller off. The voltage at the second input node 104 begins to rise, turning on the second transistor 312 and the third transistor 313 of the switch controller, pulling the voltage at the first holding node 301 down to 0 volts. This, in turn, turns off the fourth transistor 314 of the switch controller and causes the voltage at the second holding node 302 to equal the voltage at the second input node 104 minus the internal threshold voltage of the second transistor 312 of the switch controller, thereby turning on the third switch 316 and the second switch 322. As the second input node 104 falls, the voltage at the second holding node 302 is maintained at its maximum value, keeping the third switch 316 and the second switch 322 turned on throughout the reset phase.

[0097] Third switch 316 maintains the voltage at first input node 103 equal to latch node 303, thereby turning off second transistor 320 of the cross-coupled pair and causing second switch 322 to reset the voltage at control node 205 to ground, which in turn resets injection node 305 to ground. Second input node 104 also turns on current source reset transistor 315, resetting the voltage at mirror node 304 to ground. Blocking diode 324 blocks current from flowing back from output node 107 to first input node 103. First input node 103 turns off fourth switch 326, blocking current from output node 107 to sense node 204. Second input node 104 also turns on fifth switch 327, resetting the voltage at sense node 204 to ground. The circuit is then fully reset and ready to operate again in the drive phase.

[0098] The operation of the voltage stabilizing circuit according to the present invention does not require any branch with static current, but only requires a small amount of current for operation; for example, only a small voltage is required at the sensing node 204 to turn on the first switch 321, thereby minimizing power consumption.

Claims

1. A voltage stabilizing circuit for an RFID circuit, comprising: a first input node and a second input node, both connected to an output of the rectifier circuit; an output node connected to the RFID circuit; a control circuit connected to the first and second input nodes, a control node, and a sensing node, wherein the control circuit is configured to control the control node when triggered by the sensing node, the control circuit comprising: a first transistor and a second transistor arranged in a cross-coupled pair configuration between the control node and the latch node, a pulse current source coupling the first input node to the source of the first transistor, a first switch coupling the latch node to ground, wherein the first switch is a third transistor driven by a sense node, a second switch coupling the control node to ground, wherein the second switch is a fourth transistor driven by a second holding node controlled by a switch controller, and a third switch coupling the first input node to the latch node, wherein the third switch is a fifth transistor driven by the second holding node, the second holding node being controlled by a switch controller; a driving element coupled between the first input node and the output node and driven by the control node, wherein the driving element comprises: a drive transistor connected to the first input node and the control node so as to drive current from the first input node to the output node when driven by the control node, and a blocking diode coupled between the driving transistor and the output node to block current from flowing back to the first input node; and a sensing circuit connected to the output node, wherein the sensing circuit is configured to sense a voltage of the output node, the sensing circuit comprising: Voltage regulator components, a fourth switch connecting the sensing node and the voltage adjustment component, wherein the fourth switch is a sixth transistor driven by one of the input nodes, and a fifth switch connecting the sensing node to a ground terminal, wherein the fifth switch is a seventh transistor driven by another one of the input nodes. 2 . The voltage stabilizing circuit for an RFID circuit according to claim 1 , further comprising an output capacitor connecting the output node to a ground terminal.

3. The voltage stabilizing circuit for an RFID circuit according to claim 1, wherein: The third switch is configured to be connected between the latch node and the first input node, or between the latch node and a ground terminal.

4. The voltage stabilizing circuit for an RFID circuit according to claim 1, wherein: The switch controller includes: a first transistor of a switch controller arranged to be connected in a diode-connected configuration, wherein the first transistor of the switch controller is configured to connect the first input node to a first holding node; a second transistor of a switch controller arranged to be connected in a diode-connected configuration, wherein the second transistor of the switch controller is configured to connect the second input node to a second holding node; a third transistor of the switch controller, driven by the second input node to connect the first holding node to ground; and A fourth transistor of the switch controller is driven to connect the second holding node to the ground terminal through the first holding node.

5. The voltage stabilizing circuit for an RFID circuit according to claim 4, wherein: a first transistor of the switch controller coupling the first input node to the third switch, and A second transistor of the switch controller couples the second input node to the second switch.

6. The voltage stabilizing circuit for an RFID circuit according to claim 4, wherein: The first transistor and the second transistor of the switch controller are replaced by diodes.

7. The voltage stabilizing circuit for an RFID circuit according to claim 1, wherein: The pulse current source comprises: a current mirror having a first mirror transistor and a second mirror transistor, wherein the first mirror transistor is arranged in a diode-connected configuration, wherein source terminals of the first mirror transistor and the second mirror transistor are commonly connected to the first input node, and gate terminals of the first mirror transistor and the second mirror transistor are commonly connected to a mirror node; and A current source reset transistor is driven by the second input node to couple the mirror node to ground.

8. The voltage stabilizing circuit for an RFID circuit according to claim 7, further comprising a capacitor connecting the mirror node to a ground terminal.

9. The voltage stabilizing circuit for an RFID circuit according to claim 1, wherein: The blocking diode is replaced by a diode-connected transistor.

10. The voltage stabilizing circuit for an RFID circuit according to claim 1, wherein: The voltage adjustment component is a diode, a diode-connected transistor, a transistor stack, a resistor or any combination thereof.

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