Display panel and display device

Abstract

The application provides a display panel and a display device, which comprise a substrate substrate, at least two gate lines and at least two data lines are arranged on the substrate substrate, the gate lines and the data lines are insulated and overlapped on the substrate substrate to form a pixel area; a pixel electrode is arranged on one side of the substrate substrate close to the pixel area, and the pixel electrode is connected with the gate lines and the data lines respectively; a common electrode is arranged on one side of the gate lines and the data lines away from the substrate substrate, and the orthogonal projection of the common electrode on the substrate substrate covers the orthogonal projection of the gate lines and / or the data lines on the substrate substrate; the common electrode in the application covers the gate lines and / or the data lines, can shield the chaotic electric field generated by the gate lines and / or the data lines, avoids the light leakage phenomenon generated on both sides of the gate lines and the data lines, and thus improves the aperture ratio and light efficiency of the pixel area.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] LCD (Liquid Crystal Display Panel) has advantages such as low power consumption, thinness, light weight, and low driving voltage, and is widely used in modern information devices such as televisions, computers, and mobile phones. An LCD contains multiple gate lines and data lines, which serve as the driving circuit for the display panel. Typically, the gate lines and data lines are made of metal. When the display panel is in use, a relatively chaotic electric field is generated around the gate lines or data lines. This chaotic electric field interferes with the surrounding liquid crystal molecules, resulting in light leakage on both sides of the gate lines and data lines. Therefore, a relatively wide black matrix layer (BM) is usually covered on the gate lines and data lines. However, a wider black matrix layer reduces the aperture ratio of the pixel area, reducing the light efficiency of the pixel area and thus affecting the display effect of the display panel. Summary of the Invention

[0003] In view of the above, this application aims to provide a display panel and display device to solve the aforementioned technical problems.

[0004] For the purposes described above, this application provides a display panel, including:

[0005] A substrate having at least two gate lines and at least two data lines disposed thereon, wherein the gate lines and the data lines are insulated and overlapped on the substrate to form a pixel region.

[0006] A pixel electrode is disposed on the side of the substrate near the pixel region, and the pixel electrode is connected to the gate line and the data line respectively.

[0007] A common electrode is disposed on the side of the gate line and the data line away from the substrate, and the orthogonal projection of the common electrode on the substrate covers the orthogonal projection of the gate line and / or the data line on the substrate.

[0008] Optionally, the common electrode includes:

[0009] A first electrode layer is disposed on the side of the gate line and the data line away from the substrate, and on the side of the substrate away from the pixel electrode;

[0010] The domain display area includes multiple parallel slits formed on the first electrode layer, and the slits adjacent to the pixel area form a first shielding electrode. The orthographic projection of the first shielding electrode on the substrate covers the orthographic projection of the gate line on the substrate.

[0011] Optionally, the common electrode further includes:

[0012] A second shielding electrode is disposed between adjacent pixel regions, and the orthogonal projection of the second shielding electrode on the substrate covers the orthogonal projection of the data line on the substrate.

[0013] Optionally, the common electrode includes:

[0014] A second electrode layer is disposed on the side of the gate line and the data line away from the substrate, and on the side of the pixel electrode close to the substrate. The orthogonal projection of the second electrode layer on the substrate covers the orthogonal projection of the gate line and / or the data line on the substrate.

[0015] Optionally, the end face of the slit near the data line is configured as a plane or an arc surface.

[0016] Optionally, at least two domain display regions are provided within the pixel region, and the slits in adjacent domain display regions have different directions, so that an intersecting domain region is formed between two adjacent domain display regions.

[0017] Optionally, the display panel further includes:

[0018] A common line is disposed on the side of the substrate near the pixel region and connected to the common electrode. The orthographic projection of the common line on the substrate overlaps with the orthographic projection of the domain crossing region on the substrate.

[0019] Alternatively, the common line can be disposed on the side of the substrate near the pixel region, with the common line extending in the same direction as the data line, and the distance between the common line and the data line set to 4μm-10μm.

[0020] Optionally, the display panel further includes:

[0021] An organic film layer is disposed on the side of the gate line and the data line away from the substrate, and the organic film layer is disposed on the side of the common electrode close to the substrate.

[0022] Optionally, the display panel further includes:

[0023] A carrier portion is provided on the data line. The width of the carrier portion is greater than the width of the data line. A spacer is provided on the side of the carrier portion away from the substrate. The orthographic projection of the spacer on the substrate is located within the orthographic projection of the carrier portion on the substrate.

[0024] Based on the same inventive concept, this application also provides a display device, including the display panel described in any of the above embodiments.

[0025] As can be seen from the above, the display panel and display device provided in this application can shield the messy electric field generated by the gate lines and / or data lines by covering the common electrode on the gate lines and / or data lines, avoid light leakage on both sides of the gate lines and data lines, reduce the coverage area of ​​the black matrix layer by the gate lines and / or data lines, increase the aperture ratio of the pixel area, and thus improve the display effect of the display panel. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1a This is a schematic diagram of the structure of an existing display panel;

[0028] Figure 1b This is a schematic diagram of the structure of the existing pixel region;

[0029] Figure 2 This is a schematic diagram of the planar structure of the display panel in this application;

[0030] Figure 3a for Figure 2 A schematic diagram of the structure of region A-A' in the first state;

[0031] Figure 3b for Figure 2 A schematic diagram of the structure of the B-B' region in the first state;

[0032] Figure 3c for Figure 2 A schematic diagram of the structure of the C-C' region in the first state;

[0033] Figure 4a for Figure 2 Schematic diagram of the structure of region A-A' in the second state;

[0034] Figure 4b for Figure 2A schematic diagram of the structure of the B-B' region in the second state;

[0035] Figure 4c for Figure 2 A schematic diagram of the structure of the C-C' region in the second state;

[0036] Figure 5a for Figure 2 Schematic diagram of the structure of region A-A' in the third state;

[0037] Figure 5b for Figure 2 A schematic diagram of the structure of the B-B' region in the third state;

[0038] Figure 5c for Figure 2 A schematic diagram of the structure of the C-C' region in the third state;

[0039] Figure 6a for Figure 2 A schematic diagram of the structure of region A-A' in the fourth state;

[0040] Figure 6b for Figure 2 A schematic diagram of the structure of the B-B' region in the fourth state;

[0041] Figure 6c for Figure 2 A schematic diagram of the structure of the C-C' region in the fourth state;

[0042] Figure 7a for Figure 2 A schematic diagram of the structure of region A-A' in the fifth state;

[0043] Figure 7b for Figure 2 A schematic diagram of the structure of the B-B' region in the fifth state;

[0044] Figure 7c for Figure 2 A schematic diagram of the structure of the C-C' region in the fifth state;

[0045] Figure 8a for Figure 2 A schematic diagram of the structure of region A-A' in the sixth state;

[0046] Figure 8b for Figure 2 A schematic diagram of the structure of the B-B' region in the sixth state;

[0047] Figure 8c for Figure 2 A schematic diagram of the structure of the C-C' region in the sixth state;

[0048] Figure 9 This is a schematic diagram of the structure of the domain intersection region in an embodiment of this application;

[0049] Figure 10a This is a schematic diagram of the slit structure in the first embodiment of this application;

[0050] Figure 10b This is a schematic diagram of the slit structure in the second form of the embodiments of this application;

[0051] Figure 11a This is a schematic diagram of the structure of the common line in the domain intersection region in the embodiments of this application;

[0052] Figure 11b This is a schematic diagram of the common line in the domain intersection region in the embodiments of this application;

[0053] Figure 11c This is a schematic diagram of the structure of the common line in the embodiments of this application.

[0054] Explanation of reference numerals in the attached drawings: 1. Substrate; 110. Thin-film transistor; 2. Gate line; 3. Data line; 4. Pixel electrode; 5. Common electrode; 510. First electrode layer; 520. Domain display area; 520a. Domain crossing area; 521. Slit; 522. First shielding electrode; 530. Second shielding electrode; 6. Common line; 710. Organic film layer; 720. Passivation layer; 730. Gate insulating layer; 8. Black matrix layer; 9. Supporting portion; 10. Color filter layer. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0056] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0057] Among related technologies, LCDs have advantages such as low power consumption, thinness, light weight, and low driving voltage, and are widely used in modern information devices such as televisions, computers, and mobile phones; for example Figure 1a and Figure 1b As shown, an LCD contains multiple gate lines, multiple data lines, and a common line, which serve as the driving circuit for the display panel. Correspondingly, the display panel also includes a common line to reduce the parallel arrangement between the common line and the gate lines. Normally, the gate lines and data lines are made of metal. When the display panel is in use, a relatively chaotic electric field is generated around the gate lines or data lines. This chaotic electric field interferes with the surrounding liquid crystal molecules, resulting in light leakage on both sides of the gate lines and data lines. Therefore, a relatively wide black matrix layer (BM) is usually covered on the gate lines and data lines. However, a wider black matrix layer reduces the aperture ratio of the pixel area, reduces the light efficiency of the pixel area, and thus affects the display effect of the display panel.

[0058] This application provides a display panel, comprising: a substrate 1, on which at least two gate lines 2 and at least two data lines 3 are disposed, the gate lines 2 and data lines 3 overlapping and insulatingly intersecting on the substrate 1 to form a pixel region; a pixel electrode 4 disposed on the side of the substrate 1 near the pixel region, the pixel electrode 4 being connected to the gate lines 2 and the data lines 3 respectively; and a common electrode 5 disposed on the side of the gate lines 2 and the data lines 3 away from the substrate 1, the orthographic projection of the common electrode 5 on the substrate 1 covering the orthographic projection of the gate lines 2 and / or the data lines 3 on the substrate 1.

[0059] Specifically, please refer to Figures 2-11cThe display panel includes a substrate 1, which supports and protects the components and film structures disposed on its surface. At least two gate lines 2 and at least two data lines 3 are alternately and insulatedly arranged on the substrate 1, forming multiple pixel areas. The display panel also includes pixel electrodes 4 and common electrodes 5. When the display panel is working, a voltage is generated between the pixel electrodes 4 and the common electrode 5, which drives the liquid crystal molecules to deflect, allowing light to pass through the pixel areas, thereby enabling the display panel to perform its display function. The pixel electrodes 4 can be red, green, or blue, to suit different types of pixels. The area; and when the display panel is working, a disordered electric field is generated around the gate line 2 and data line 3, which interferes with the liquid crystal molecules arranged around them, causing light leakage around the gate line 2 and data line 3; by placing the common electrode 5 on the side of the gate line 2 and data line 3 away from the substrate 1, and making the orthogonal projection of the common electrode 5 on the substrate 1 cover the orthogonal projection of the gate line 2 and / or data line 3 on the substrate 1, the common electrode 5 can form a shielding layer to shield the disordered electric field generated by the data line 3 and / or gate line 2, avoiding light leakage on both sides of the gate line 2 and / or data line 3, thereby reducing the area required by the gate line 2 and data line 3 for the black matrix layer 8, thereby improving the aperture ratio of the pixel area.

[0060] For example, please see Figures 3a-3c When the display panel uses forward-facing liquid crystal, the common electrode 5 can be positioned on the side of the gate line 2 away from the substrate 1, so that the orthogonal projection of the common electrode 5 on the substrate 1 covers the orthogonal projection of the gate line 2 on the substrate 1. At this time, the common electrode 5 can shield the random electric field generated by the gate line 2, avoid light leakage on both sides of the gate line 2, and reduce the area of ​​the black matrix layer 8 used to cover the gate line 2, thereby improving the aperture ratio of the pixel area. At the same time, it should be noted that since the electric field generated by the common electrode 5 and the data line 3 will not cause the forward-facing liquid crystal to deflect, the common electrode 5 does not need to shield the data line 3.

[0061] For example, please see Figures 4a-4c When the display panel uses negative liquid crystal, the common electrode 5 can be set on the side of the gate line 2 away from the substrate 1, so that the positive projection of the common electrode 5 on the substrate 1 covers the positive projection of the data line 3 on the substrate 1. At this time, the common electrode 5 can shield the messy electric field generated by the data line 3, avoid light leakage on both sides of the data line 3, reduce the area of ​​the black matrix layer 8 used to cover the data line 3, and improve the aperture ratio of the pixel area. Similarly, since the electric field generated by the common electrode 5 and the gate line 2 will not cause the negative liquid crystal to deflect, the common electrode 5 does not need to shield the gate line 2.

[0062] It should be noted that you should refer to [link / reference]. Figures 3a-8cIn the display panel, the substrate 1 is used to support and protect the components and related film layers arranged on its surface; the substrate 1 may include a base layer, a thin film transistor 110 (TFT) and a gate insulating layer 730 (GI); wherein, the base layer may be formed of one or more materials such as glass, polyimide and polycarbonate, so that the base layer has good impact resistance and water and oxygen barrier capabilities, effectively extending the life of the display panel.

[0063] Thin-film transistor 110 can be disposed on a substrate layer, and can be connected to corresponding data lines 3 and gate lines 2 respectively, for use as a driving circuit for a display panel. Thin-film transistor 110 includes an active layer, a gate electrode, a source electrode, and a drain electrode. The active layer can be disposed on the substrate layer and can be formed using an oxide semiconductor material or an organic semiconductor material. A gate insulating layer 730 can be disposed on the substrate layer, and the active layer is disposed within the gate insulating layer 730. To insulate the active layer and the source or drain electrode, the gate insulating layer 730 needs to be formed of an insulating material, such as an inorganic material, silicon nitride or silicon oxide, and the insulating effect of the gate insulating layer 730 must be guaranteed. The gate insulating layer 730 can be one or more layers. The source electrode and the drain electrode can both be located on the side of the gate insulating layer 730 away from the active layer, and the two are separated from each other. For the source electrode and the drain electrode, they can be formed of one of the materials selected from molybdenum, aluminum, chromium, gold, titanium, nickel, neodymium and copper, or an alloy composed of multiple of them, which will not be elaborated here.

[0064] In addition, the substrate 1 also includes a passivation layer 720 (PVX). The passivation layer 720 can be disposed on the side of the gate insulating layer 730 away from the base layer, and is used to planarize the thin film transistor 110 and the gate insulating layer 730, and also to protect the components disposed on the base layer. The passivation layer 720 can be formed from one or more of polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin and polystyrene resin, which will not be described in detail here.

[0065] It should be noted that the common electrode 5 and the pixel electrode 4 can be made of transparent metal electrodes so that light can pass through the pixel electrode 4 and the common electrode 5 and be projected to the outside of the pixel unit. Transparent electrodes made of materials such as indium tin oxide, indium zinc oxide, zinc oxide, and indium oxide will not be described in detail here.

[0066] In some embodiments, the common electrode 5 includes a first electrode layer 510 disposed on the side of the gate line 2 and data line 3 away from the substrate 1, and disposed on the side of the substrate 1 away from the pixel electrode 4; the domain display area 520 includes a plurality of parallel slits 521 formed on the first electrode layer 510, the slits 521 of adjacent pixel areas form a first shielding electrode 522, and the orthographic projection of the first shielding electrode 522 on the substrate 1 covers the orthographic projection of the gate line 2 on the substrate 1.

[0067] Specifically, please refer to Figures 3a-6c and Figure 9 A voltage is formed between the pixel electrode 4 and the common electrode 5 disposed on the substrate 1 to drive the liquid crystal molecules to deflect, thereby enabling the display panel to perform display functions. The common electrode 5 may include a first electrode layer 510 and a domain display area 520. A corresponding voltage can be formed between the pixel electrode 4 and the first electrode layer 510 to drive the liquid crystal molecules to deflect. The domain display area 520 is provided with multiple parallel slits 521. The multiple slits 521 are arranged on the first electrode layer 510 so that a corresponding electric field is generated at the edge region of the slits 521. The electric field generated between the first electrode layer 510 and the pixel electrode 4 constitutes a multi-dimensional electric field, which can better control the alignment direction and deflection shape of the liquid crystal molecules, thereby improving the display effect of the display panel.

[0068] Furthermore, the slit 521 between adjacent pixel regions forms a first shielding electrode 522, that is, the first shielding electrode 522 is located between the first two adjacent pixel regions, and the first shielding electrode 522 can be arranged parallel to the gate line 2, so that the orthogonal projection of the first shielding electrode 522 on the substrate 1 covers the orthogonal projection of the gate line 2 on the substrate 1; at this time, such as Figures 5a-5c As shown, when a forward-facing liquid crystal is used in the display panel, the orthogonal projection of the first shielding electrode 522 on the substrate 1 covers the orthogonal projection of the gate line 2 on the substrate 1. At this time, the first shielding electrode 522 can shield the random electric field generated by the gate line 2, avoid light leakage on both sides of the gate line 2, reduce the coverage area of ​​the black matrix layer 8 on the gate line 2, and thus improve the aperture ratio of the pixel area.

[0069] In some embodiments, the common electrode 5 further includes a second shielding electrode 530 disposed between adjacent pixel regions, and the orthogonal projection of the second shielding electrode 530 on the substrate 1 covers the orthogonal projection of the data line 3 on the substrate 1.

[0070] Specifically, please refer to Figures 6a-6cSince the common electrode 5 is positioned on the side of the gate line 2 and data line 3 away from the substrate 1, the common electrode 5 can shield the cluttered electric field of the gate line 2 and / or data line 3, preventing light leakage from both sides of the gate line 2 and / or data line 3. The common electrode 5 includes a second shielding electrode 530 for shielding the data line 3. The orthogonal projection of the second shielding electrode 530 on the substrate 1 covers the orthogonal projection of the data line 3 on the substrate 1. When the display panel uses negative liquid crystal, the second shielding electrode 530 is positioned on the side of the data line 3 away from the substrate 1, and its orthogonal projection covers the orthogonal projection of the data line 3 on the substrate 1. In this case, the second shielding electrode 530 can shield the cluttered electric field generated by the data line 3, preventing light leakage from both sides of the data line 3, reducing the coverage area of ​​the black matrix layer 8 on the data line 3, and increasing the aperture ratio of the pixel area.

[0071] In some embodiments, the common electrode 5 includes a second electrode layer disposed on the side of the gate line 2 and data line 3 away from the substrate 1, and disposed on the side of the pixel electrode 4 close to the substrate 1. The orthogonal projection of the second electrode layer on the substrate 1 covers the orthogonal projection of the gate line 2 and / or data line 3 on the substrate 1.

[0072] Specifically, the second electrode layer is disposed on the side of the pixel electrode 4 closest to the substrate 1, and the orthogonal projection of the second electrode layer on the substrate 1 covers the orthogonal projection of the gate line 2 and / or the data line 3 on the substrate 1; for example, please refer to Figures 7a-7c When the display panel uses negative liquid crystal, the second electrode layer is disposed on the side of the data line 3 away from the substrate 1, and the orthogonal projection of the data line 3 on the substrate 1 covers the orthogonal projection of the data line 3 on the substrate 1. At this time, the second electrode layer can shield the messy electric field generated by the data line 3, avoid light leakage on both sides of the data line 3, reduce the coverage area of ​​the black matrix layer 8 on the data line 3, increase the aperture ratio of the pixel area, and improve the display effect of the display panel. Since the electric field generated between the second electrode layer and the gate line 2 will not cause the negative liquid crystal to deflect, the second electrode layer does not need to shield the gate line 2.

[0073] For example, when the display panel uses a front-facing LCD, please refer to... Figures 8a-8c The second electrode layer is disposed on the side of the gate line 2 away from the substrate 1, and its orthogonal projection on the substrate 1 covers the orthogonal projection of the gate line 2 on the substrate 1. At this time, the second electrode layer can shield the random electric field generated by the gate line 2, avoid light leakage on both sides of the gate line 2, reduce the coverage area of ​​the black matrix layer 8 on the gate line 2, and improve the aperture ratio of the pixel area. At the same time, since the electric field generated between the second electrode layer and the data line 3 will not cause the forward liquid crystal to deflect, the second electrode layer does not need to shield the data line 3.

[0074] In some embodiments, the end face of the slit 521 near the data line 3 is configured as a planar or arc-shaped surface.

[0075] Specifically, when a display panel is subjected to external pressure, liquid crystal molecules with a larger tilt angle are squeezed and rearranged, causing a change in the light transmittance within the pixel area. After the external pressure is removed, the rearranged liquid crystal molecules cannot return to their original positions quickly under the influence of an electric field, thus reducing the display effect of the display panel; please refer to Figure 10a and Figure 10b By setting the end of the slit 521 to a flat or arc-shaped surface, the influence of external pressure on the electric field of the edge region of the slit 521 can be reduced, thereby reducing interference with the arrangement of liquid crystal molecules and ensuring the light transmission effect of the pixel region.

[0076] In some embodiments, at least two domain display regions 520 are provided within a pixel region, and the slits 521 in adjacent domain display regions 520 have different directions, so that an intersecting domain region 520a is formed between two adjacent domain display regions 520.

[0077] Specifically, please refer to Figure 9 Each pixel region contains at least two domain display regions 520. Within adjacent domain display regions 520, the extension direction of the corresponding slits 521 differs, resulting in different deflection directions of the liquid crystal molecules within each domain display region 520. This ensures that the light effect of the display panel is consistent when viewed from different angles, thereby improving the brightness and color shift of the display panel. Due to the difference in deflection directions of the liquid crystals within the two domain display regions 520, cross-domain regions 520a with poor light transmittance are formed within adjacent domain display regions 520. Furthermore, within any display region, the domain display regions 520 can be set to two, three, or even more, depending on the area of ​​the pixel region and the light transmittance effect; details will not be elaborated further here.

[0078] In some embodiments, the display panel further includes a common line 6 disposed on the side of the substrate 1 near the pixel area. The common line 6 is connected to the common electrode 5, and the orthographic projection of the common line 6 on the substrate 1 overlaps with the orthographic projection of the cross-domain region 520a on the substrate 1.

[0079] Specifically, please refer to Figure 11a In addition to the common line 6 forming the pixel area, the substrate 1 also includes a common line 6 connected to the common electrode 5. Since the common line 6 is a metal trace, to reduce its impact on the light effect of the pixel area, it needs to be covered by a black matrix layer 8, etc. For any pixel area, each pixel area contains two domain display areas 520, and adjacent domain display areas 520 form an intersection domain area 520a, such as... Figure 1b and Figure 11bAs shown, since the light transmittance between adjacent domain display areas 520 is poor, by setting the common line 6 in the domain intersection region 520a and making the orthographic projection of the common line 6 on the substrate 1 overlap with the orthographic projection of the domain intersection region 520a on the substrate 1, that is, by arranging the common line 6 in the area of ​​poor light transmittance of the pixel area, a black matrix layer 8 can be set in the domain intersection region 520a to shield the common line 6. On the one hand, the influence of the black matrix layer 8 set in this area on the aperture ratio of the pixel area can be reduced; on the other hand, the domain intersection region 520a shields at least part of the common line 6, improving the shielding effect of the common line 6, thereby improving the light efficiency and aperture ratio of the pixel area.

[0080] As an alternative embodiment, the display panel also includes a common line 6, which is disposed on the side of the substrate 1 near the pixel area. The common line 6 is connected to the common electrode 5. The extension direction of the common line 6 is the same as the extension direction of the data line 3. The distance between the common line 6 and the data line 3 is set to 4μm-10μm.

[0081] Specifically, please refer to Figure 11c The substrate 1 has gate lines 2 and data lines 3, which are metal traces. Therefore, a black matrix layer 8 is needed to cover the gate lines 2 and data lines 3 to prevent light leakage in the pixel area and to prevent color mixing between adjacent pixel areas. Since the spacer is placed on the light-shielding layer covering the data lines 3, in the display panel, in order to prevent the spacer from sliding off the light-shielding layer on the data lines 3 and scratching the film layer, the width of the black matrix layer 8 covering the data lines 3 is usually large, which affects the aperture ratio of the pixel area. By arranging the common line 6 next to the data lines 3 and making its extension direction the same as the extension direction of the data lines 3, the black matrix layer 8 covering the data lines 3 can be used to simultaneously shield the common line 6, so that the common line 6 can be covered by the black matrix layer 8 of the data lines 3, eliminating the need for the original black matrix layer 8 covering the common line 6, thereby improving the aperture ratio of the pixel area.

[0082] In addition, to avoid mutual interference between the common line 6 and the data line 3, the distance between the data line 3 and the common line 6 should be greater than 4 μm; and to ensure that the black matrix layer 8 covering the data line 3 can completely cover the common line 6 and ensure the aperture ratio of the pixel area, the distance between the data line 3 and the common line 6 should be set to less than 10 μm.

[0083] In some embodiments, the display panel further includes an organic film layer 710 disposed on the side of the gate line 2 and data line 3 away from the substrate 1, and the organic film layer 710 disposed on the side of the common electrode 5 close to the substrate 1.

[0084] Specifically, please refer to Figures 5a-8cBy placing the organic film layer 710 on the side of the gate line 2 and data line 3 away from the substrate 1, and placing the organic film layer 710 on the side of the common electrode 5 close to the substrate 1, at least one insulating layer is present between the common electrode 5 and the gate line 2. This insulating and blocking layer is used to prevent the formation of parasitic capacitance between the common electrode 5 and the data line 3 and / or the gate line 2, thus ensuring the display effect of the display panel and enabling it to be used in high-resolution display devices.

[0085] In some embodiments, a carrier portion 9 is provided on the data line 3. The width of the carrier portion 9 is greater than the width of the data line 3. A spacer is provided on the side of the carrier portion 9 away from the substrate 1. The orthographic projection of the spacer on the substrate 1 is located within the orthographic projection of the carrier portion 9 on the substrate 1.

[0086] Specifically, please refer to Figure 11a and Figure 11b The carrier portion 9 is disposed on the data line 3, so that the carrier portion 9 is located in the edge area of ​​the pixel unit, thereby reducing the occlusion of the pixel area and improving the aperture ratio. Furthermore, the width of the carrier portion 9 is greater than the width of the data line 3, so that the data line 3 has a larger carrying area, improving the carrying effect on the spacers. The carrier portion 9 is covered with a light-shielding layer, therefore the black matrix layer 8 arranged on the carrier portion 9 is relatively wide, preventing the spacers from slipping out of the black matrix layer 8 and causing scratches on the film layer, ensuring the light transmission effect of the pixel area. It should be noted that the black matrix layer 8 can be manufactured by coating, exposure, development, or baking, etc., which will not be elaborated here.

[0087] In addition, a color film (CF) layer is provided on the side of the black matrix layer 8 away from the substrate 1. This layer can prevent color mixing or cross-coloring between adjacent pixel areas, and can also shield external light to prevent the thin film transistor from generating photocurrent due to light, which would cause the current of the thin film transistor to increase in the off state. This will not be elaborated further here.

[0088] Based on the same inventive concept, this application also provides a display device, including the display panel of any of the above embodiments. The display device includes the display panel described in any of the above embodiments. Therefore, the display device has all the advantages and beneficial effects of the display panel in the above embodiments. For the purposes of this application, the display device provided by this application can be applied to products or components with LCD display panels, such as monitors and televisions. Further details are not provided here.

[0089] It should be noted that the method in this embodiment can be executed by a single device, such as a computer or server. The method can also be applied in a distributed scenario, where multiple devices cooperate to complete the task. In such a distributed scenario, one of these devices may execute only one or more steps of the method in this embodiment, and the multiple devices will interact with each other to complete the method.

[0090] It should be noted that the above description describes some embodiments of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0091] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this application (including the claims) is limited to these examples; within the framework of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of this application as described above, which are not provided in the details for the sake of brevity.

[0092] Furthermore, to simplify the description and discussion, and to avoid obscuring the embodiments of this application, the apparatus may be shown in block diagram form. This is to prevent the embodiments of this application from being difficult to understand, and it also takes into account the fact that the details of the implementation of these block diagram apparatuses are highly dependent on the platform on which the embodiments of this application will be implemented (i.e., these details should be fully within the understanding of those skilled in the art). In setting forth specific details to describe exemplary embodiments of this application, it will be apparent to those skilled in the art that the embodiments of this application may be implemented without these specific details or with variations thereof. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0093] Although this application has been described in conjunction with specific embodiments thereof, many substitutions, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description.

[0094] The embodiments of this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this application should be included within the protection scope of this application.

Claims

1. A display panel, characterized in that, include: The substrate and pixel electrode are provided, wherein at least two gate lines and at least two data lines are disposed on the substrate, and the gate lines and the data lines are insulated and overlapped on the substrate to form a pixel region; the pixel electrode is disposed on the side of the substrate close to the pixel region. A common electrode and a common line are provided. The common electrode is disposed on the side of the gate line and the data line away from the substrate. The orthographic projection of the common electrode on the substrate covers the orthographic projection of the gate line and the data line on the substrate. The common electrode includes a first electrode layer and a domain display region. The first electrode layer is disposed on the side of the gate line and the data line away from the substrate, and is also disposed on the side of the pixel electrode away from the substrate. The domain display region includes a plurality of parallel slits formed in the first electrode layer. A first shielding electrode is formed between the slits of adjacent pixel regions. The orthographic projection of the first shielding electrode on the substrate covers the orthographic projection of the gate line on the substrate. Each of the pixel regions has at least two adjacent domain display regions, the slits in the adjacent domain display regions have different extension directions and are connected accordingly; an inter-domain region is formed between the adjacent domain display regions, the inter-domain region intersects with the extension direction of the gate line; the common line is disposed on the side of the substrate near the pixel region, the common line is a metal trace and is electrically connected to the common electrode, the orthographic projection of the common line on the substrate overlaps with the orthographic projection of the inter-domain region on the substrate, so that the inter-domain region shields at least a portion of the common line; the inter-domain region is provided with a black matrix, the black matrix in the inter-domain region is used to shield the common line.

2. The display panel according to claim 1, characterized in that, The common electrode further includes: A second shielding electrode is disposed between adjacent pixel regions, and the orthogonal projection of the second shielding electrode on the substrate covers the orthogonal projection of the data line on the substrate.

3. The display panel according to claim 1, characterized in that, The end face of the slit near the data line is set as a plane or an arc surface.

4. The display panel according to claim 1, characterized in that, Also includes: An organic film layer is disposed on the side of the gate line and the data line away from the substrate, and the organic film layer is disposed on the side of the common electrode close to the substrate.

5. The display panel according to claim 1, characterized in that, A carrier portion is provided on the data line. The width of the carrier portion is greater than the width of the data line. A spacer is provided on the side of the carrier portion away from the substrate. The orthographic projection of the spacer on the substrate is located within the orthographic projection of the carrier portion on the substrate.

6. A display device, characterized in that, Includes the display panel as described in any one of claims 1-5.

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