A semiconductor structure and a method of fabricating the same
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2023-06-27
- Publication Date
- 2026-06-23
Smart Images
Figure CN116682737B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology
[0002] With the development of semiconductor technology, indium gallium zinc oxide (IGZO) has gradually become an ideal channel material for thin-film transistors. Currently, memory devices with IGZO semiconductor oxide typically use metal materials as the gate layer and ITO conductive films or metals as the source and drain.
[0003] However, current storage devices have at least the following problems:
[0004] 1) The source, drain, and gate layers of memory devices are fabricated separately, which is a complex process;
[0005] 2) The contact between the source, drain and channel regions of the memory device is a Schottky contact, which has a relatively large contact resistance. Summary of the Invention
[0006] In view of the above problems, embodiments of this application provide a semiconductor structure and a method for fabricating the same, which can simplify the fabrication process of memory devices and reduce the contact resistance of memory devices.
[0007] A first aspect of this application provides a method for fabricating a semiconductor structure, comprising the following steps:
[0008] Provide substrate;
[0009] A first oxide semiconductor layer is formed on the substrate;
[0010] A gate stack is formed on the first oxide semiconductor layer, the gate stack including a gate dielectric layer and a second oxide semiconductor layer located on the gate dielectric layer, wherein the first oxide semiconductor layer and the first oxide semiconductor layer are made of the same material;
[0011] Vertical etching is performed on portions of the gate stack located on both sides of the channel region, while retaining portions of the gate stack opposite to the channel region;
[0012] Ion implantation is performed on the second oxide semiconductor layer and the first oxide semiconductor layer located on both sides of the channel region to form a gate layer and a source and drain electrode respectively on both sides of the channel region.
[0013] The semiconductor structure fabrication method provided in this application has at least the following advantages:
[0014] In the semiconductor structure fabrication method provided in this application embodiment, the same ion implantation process is used to implant ions into the first oxide semiconductor layer and the second oxide semiconductor layer on both sides of the channel region to form the source, drain and gate layers; furthermore, part of the first oxide semiconductor layer serves as the channel region, and part of the first oxide semiconductor layer serves as the source and drain.
[0015] Compared with related technologies where the source, drain, and gate layers of memory devices are all fabricated separately using metal materials, the fabrication method provided in this application forms the source, drain, and gate layers simultaneously, which simplifies the fabrication process.
[0016] Furthermore, both the source and drain are made of oxide semiconductor layers, which can reduce the contact resistance between the source, drain and channel regions compared to the Schottky contacts (metal-semiconductor contacts) formed by the source, drain and channel regions in related technologies.
[0017] The semiconductor structure fabrication method described above further includes, before the step of forming a first oxide semiconductor layer on the substrate, forming an insulating layer on the substrate.
[0018] The semiconductor structure fabrication method described above, wherein the gate dielectric layer is a high-k dielectric layer; the step of forming a gate stack on the first oxide semiconductor layer includes: depositing a high-k dielectric material on the first oxide semiconductor layer to form a high-k dielectric layer.
[0019] The method for fabricating the semiconductor structure as described above further includes the step of forming a gate stack on the first oxide semiconductor layer:
[0020] An isolation layer is formed on the high-k dielectric layer;
[0021] The second oxide semiconductor layer is formed on the isolation layer.
[0022] The semiconductor structure fabrication method described above, after the step of ion implantation of the second oxide semiconductor layer and the first oxide semiconductor layer located on both sides of the channel region, further includes: annealing the semiconductor structure after ion implantation.
[0023] In the semiconductor structure fabrication method described above, the materials used to fabricate the first oxide semiconductor layer and the second oxide semiconductor layer are indium gallium zinc oxide.
[0024] A semiconductor structure provided in the second aspect of this application includes: a substrate having a first oxide semiconductor layer thereon, wherein a portion of the first oxide semiconductor layer that is not doped with ions is configured as a channel region; portions of the first oxide semiconductor layer that are doped with ions located on both sides of the channel region respectively forming a source and a drain; and a gate structure disposed above the channel region, the gate structure including a gate dielectric layer and a second oxide semiconductor layer disposed on the gate dielectric layer, wherein the second oxide semiconductor layer is doped with ions and configured as a gate layer.
[0025] The semiconductor structure provided in the second aspect of this application has the same advantages as the semiconductor structure obtained by the preparation method provided in the first aspect, and will not be repeated here.
[0026] The semiconductor structure described above further includes an insulating layer; the insulating layer is disposed between the first oxide semiconductor layer and the substrate, and the insulating layer covers the entire substrate.
[0027] In the semiconductor structure described above, the gate dielectric layer is configured as a high-k dielectric layer.
[0028] In the semiconductor structure described above, an isolation layer is provided between the high-k dielectric layer and the second oxide semiconductor layer. Attached Figure Description
[0029] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0030] Figure 1 A flowchart of the method for fabricating a semiconductor structure provided in Embodiment 1 of this application;
[0031] Figure 2 This is a flowchart illustrating step S300 in Embodiment 1 of this application.
[0032] Figures 3 to 7 A schematic diagram of the structure corresponding to each process step of the method for fabricating the semiconductor structure provided in Embodiment 1 of this application;
[0033] Figure 8 This is a flowchart of a method for fabricating a semiconductor structure provided in Embodiment 2 of this application;
[0034] Figures 9 to 16This is a schematic diagram of the structure corresponding to each process step of the semiconductor structure fabrication method provided in Embodiment 2 of this application.
[0035] Explanation of reference numerals in the attached figures:
[0036] 10-Substrate;
[0037] 20 - First oxide semiconductor layer;
[0038] 30-Gate stack;
[0039] 31-Gate dielectric layer; 31a-High-K dielectric layer; 32-Second oxide semiconductor layer; 33-Isolation layer;
[0040] 40 - Insulation layer;
[0041] 100 - Storage devices;
[0042] 101 - Source; 102 - Drain; 103 - Channel region; 104 - Gate layer. Detailed Implementation
[0043] As described in the background section, current memory device fabrication processes are complex, and the contact resistance between the source, drain, and channel regions is relatively high. The inventors have discovered that this problem arises because existing memory devices typically use a metal material as the gate layer and an ITO conductive film or metal as the source and drain. The source, drain, and gate layers are fabricated separately, and the contact between the channel region and the source / drain regions is a Schottky contact (metal-semiconductor contact), which has a relatively high contact resistance.
[0044] To address the aforementioned technical problems, the semiconductor structure and its fabrication method provided in this application employ the same ion implantation process to implant ions into the first oxide semiconductor layer and the second oxide semiconductor layer on both sides of the channel region to form the source, drain, and gate layers; furthermore, a portion of the first oxide semiconductor layer serves as the channel region, and a portion of the first oxide semiconductor layer serves as the source and drain.
[0045] With this configuration, the source, drain, and gate layers are formed simultaneously in the semiconductor structure fabrication method provided in this application embodiment, which simplifies the fabrication process. Furthermore, since both the source and drain are fabricated using oxide semiconductor layers, the contact resistance between the source / drain and the channel region can be reduced compared to the Schottky contact (metal-semiconductor contact) formed between the source / drain and the channel region in related technologies.
[0046] To make the above-mentioned objectives, features, and advantages of the embodiments of this application more apparent and understandable, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0047] Example 1
[0048] To facilitate the description of the embodiments of this application, the coordinate system in the accompanying drawings will be explained. The X-axis direction can be a first direction, which is the left and right direction in the figure; the Z-axis direction can be a second direction, which is the up and down direction in the figure.
[0049] like Figure 1 and Figure 2 As shown in the embodiments of this application, the method for fabricating a semiconductor structure includes the following steps:
[0050] Step S100: Provide substrate 10.
[0051] Specifically, substrate 10 is typically a semiconductor substrate, including silicon substrates, germanium substrates, etc. For example, in the embodiments of this application, substrate 10 is a silicon substrate, wherein the silicon substrate can be an N-type doped silicon substrate or a P-type doped silicon substrate. Of course, the silicon substrate can also be an undoped silicon substrate, and the embodiments of this application do not limit this.
[0052] Step S200: A first oxide semiconductor layer 20 is formed on the substrate 10. The structure formed in this step is as follows: Figure 3 As shown.
[0053] Specifically, an oxide semiconductor material can be deposited on the substrate 10 to form a first oxide semiconductor layer 20, and the first oxide semiconductor layer 20 covers the entire active region of the substrate 10. For example, the oxide semiconductor material can be indium gallium zinc oxide (IGZO), that is, the first oxide semiconductor layer 20 can be defined as an IGZO semiconductor layer. Of course, the material used to prepare the first oxide semiconductor layer 20 is not limited to IGZO.
[0054] Step S300: A gate stack 30 is formed on the first oxide semiconductor layer 20. The gate stack 30 includes a gate dielectric layer 31 and a second oxide semiconductor layer 32 located on the gate dielectric layer 31. The structure formed in this step is as follows: Figure 4 As shown.
[0055] Specifically, step S300 includes step S310: forming a gate dielectric layer 31 on the first oxide semiconductor layer 20. For example, silicon oxide or aluminum oxide may be deposited on the first oxide semiconductor layer 20 to form the gate dielectric layer 31, and the gate dielectric layer 31 covers the first oxide semiconductor layer 20.
[0056] Step S320: Form a second oxide semiconductor layer 32 on the gate dielectric layer 31. For example, the second oxide semiconductor layer 32 can be made of the same material as the first oxide semiconductor layer 20, i.e., IGZO can be deposited on the gate dielectric layer 31 to form an IGZO semiconductor layer covering it. To distinguish it from the first oxide semiconductor layer 20, this IGZO semiconductor layer is the second oxide semiconductor layer 32, and the second oxide semiconductor layer 32 is subsequently used to form the gate layer 104.
[0057] Step S400: Vertically etch the portion of the gate stack 30 located on both sides of the channel region 103, and retain the portion of the gate stack 30 opposite to the channel region 103; the structure formed in this step is as follows Figure 5 As shown.
[0058] After the gate stack 30 is formed in the first oxide semiconductor layer 20, a portion of the gate stack 30 may be etched. The semiconductor structure includes a channel region, and a portion of the first oxide semiconductor layer 20 is configured as the channel region 103.
[0059] For example, along the first direction, the first oxide semiconductor layer 20 located in the middle is configured as a channel region 103; and along the first direction, a portion of the gate stack 30 located on both sides of the channel region is vertically etched to remove a portion of the gate stack 30, while retaining the gate stack 30 located above the channel region. This configuration exposes a portion of the first oxide semiconductor layer 20 on both sides of the channel region, facilitating the subsequent formation of source and drain electrodes on both sides of the channel region.
[0060] Step S500: Ion implantation is performed on the second oxide semiconductor layer 32 and the first oxide semiconductor layer 20 located on both sides of the channel region 103 to form the gate layer 104 and the source 101 and drain 102 on both sides of the channel region 103, respectively; the structure formed in this step is as follows Figure 6 , 7 As shown.
[0061] Specifically, based on self-aligned ion implantation (IMP) technology, ion implantation is performed on the semiconductor structure formed after step S400, which can simultaneously implant ions into the second oxide semiconductor layer and the first oxide semiconductor layer 20 exposed on both sides of the channel region 103, thereby improving the conductivity of the first oxide semiconductor layer 20 and the second oxide semiconductor layer 32.
[0062] Furthermore, after ion implantation into the second oxide semiconductor layer 32, a gate layer 104 can be formed; the portion of the first oxide semiconductor layer exposed on both sides of the channel region 103, after ion implantation, can serve as the source 101 and drain 102, respectively. For example, in the above ion implantation process, the implanted ions are arsenic ions (A... S The injection concentration is 5*10 15 / cm 2 The injected energy is 100 keV.
[0063] Compared with the related technologies in which the source, drain and gate layers of memory devices are all made of metal materials separately, in the preparation method provided in this application, the source 101, drain 102 and gate layer 104 are formed simultaneously using the same implantation process, which can simplify the preparation process.
[0064] Furthermore, in the preparation method provided in this application, both the source 101 and the drain 102 are made of oxide semiconductor layers. Compared with the Schottky contact (metal-semiconductor contact) formed between the source, drain and channel region in related technologies, the contact resistance between the source 101, drain 102 and channel region can be reduced.
[0065] Example 2
[0066] like Figure 8 As shown in the embodiments of this application, another method for fabricating a semiconductor structure includes:
[0067] Step S100': Provide substrate 10. This step is the same as step S100 and will not be described again here.
[0068] Step S110': An insulating layer 40 is formed on the substrate 10. The structure formed in this step is as follows: Figure 9 As shown.
[0069] Specifically, the substrate 10 can be a silicon substrate 10, and a silicon oxide layer can be buried between the substrate 10 and the first oxide semiconductor layer 20. This oxide layer serves as an insulating layer 40, meaning that the semiconductor structure subsequently formed is disposed on the insulator to achieve isolation between the channel in the semiconductor structure and the substrate 10, thereby preventing leakage between the substrate 10 and the channel.
[0070] For example, an amorphous silicon oxide film can be grown on the surface of the substrate 10 using a thermal growth process. This silicon oxide film can serve as the insulating layer 40 mentioned above to effectively isolate the channel from the substrate 10, thereby preventing leakage between the substrate 10 and the channel. The thermal growth process will not be described in detail here.
[0071] Step S200': A first oxide semiconductor layer 20 is formed on the insulating layer 40. This step is the same as step S200, and the resulting structure is as follows. Figure 10 As shown, it will not be elaborated further here.
[0072] Based on the above embodiments, the gate dielectric layer 31 in this embodiment can be configured as a high-k dielectric layer 31a; therefore, after performing step S200', the fabrication method provided in this embodiment includes step S310': depositing a high-k dielectric material on the first oxide semiconductor layer 20 to form a high-k dielectric layer 31a, the structure formed by this step is as follows. Figure 11 As shown.
[0073] For example, after forming a first oxide semiconductor layer 20 on the insulating layer 40, a high-K dielectric material, which may be hafnium dioxide (HfO2), is deposited on the first oxide semiconductor layer 20, and the formed high-K dielectric layer 31a covers the first oxide semiconductor layer 20.
[0074] Furthermore, it also includes step S320': forming an isolation layer 33 on the high-k dielectric layer 31a, the structure formed by this step is as follows Figure 12 As shown.
[0075] Specifically, after the high-k dielectric layer 31a is formed on the first oxide semiconductor layer 20, an isolation layer 33 is formed on the high-k dielectric layer 31a. For example, silicon nitride is deposited on the high-k dielectric layer 31a to form the isolation layer 33 covering the high-k dielectric layer 31a. Of course, other isolation materials can also be deposited on the high-k dielectric layer 31a to form the isolation layer 33, and the embodiments of this application do not limit this.
[0076] This configuration, forming an isolation layer 33 on the high-k dielectric layer 31a, avoids the following during subsequent ion implantation of the second oxide semiconductor layer 32: A S Ions diffuse into the gate dielectric layer 31 and the channel region.
[0077] After forming the isolation layer 33 on the high-k dielectric layer 31a, the method further includes step S330': forming a second oxide semiconductor layer 32 on the isolation layer 33. This step can be referred to in step S320, and the resulting structure is as follows. Figure 13 As shown, it will not be elaborated further here.
[0078] Furthermore, the method includes step S400': vertically etching a portion of the gate stack 30 located on both sides of the channel region 103, while retaining the portion of the gate stack 30 opposite to the channel region 103. This step is the same as step S400, and the resulting structure is as follows: Figure 14 As shown, it will not be elaborated further here.
[0079] Step S500': Ion implantation is performed on the second oxide semiconductor layer 32 and the first oxide semiconductor layer 20 located on both sides of the channel region 103 to form the gate layer 104 and the source 101 and drain 102 on both sides of the channel region 103, respectively; this step can be referred to step S500, and the formed structure is as follows Figure 15 , 16 As shown, it will not be elaborated further here.
[0080] The semiconductor structure fabrication method provided in this application embodiment further includes step S600' after step S500': annealing after ion implantation of the semiconductor structure.
[0081] Specifically, after ion implantation to form the source 101, drain 102, and gate layer 104, the semiconductor structure can be annealed, also known as post-ion implantation annealing. This involves placing the ion-implanted semiconductor structure in a high-temperature, oxygen-filled environment, such as 525°C, for 30 minutes. This setup repairs the crystal lattice and activates the implanted As ions. Furthermore, annealing in an oxygen environment prevents the formation of oxygen vacancies in the gate layer 104, source 101, and drain 102. After As+3 doping replaces Zn2+, an acceptor is introduced, enhancing conductivity.
[0082] Example 3
[0083] It should be noted that the semiconductor structure provided in this application embodiment is prepared by the method of preparing the semiconductor structure provided in Embodiments 1 and 2, and its structure is as follows;
[0084] like Figure 6 and Figure 7 As shown, the semiconductor structure provided in this application embodiment can be a memory device 100. The memory device 100 includes a substrate 10, a drain 102, a source 101, and a gate structure, wherein the substrate 10 is provided with a first oxide semiconductor layer 20, and the first oxide semiconductor layer 20 can cover the entire active region of the substrate 10.
[0085] Furthermore, the first oxide semiconductor layer 20 may be an IGZO semiconductor layer. Along the first direction, the first oxide semiconductor layer 20 includes a first portion, a second portion, and a third portion disposed sequentially. The second portion is disposed at the middle position of the first oxide semiconductor layer 20. The second portion is not doped with ions and is configured as the channel region 103 of the memory device 100. In other words, a portion of the IGZO semiconductor layer is configured as the channel region 103 of the memory device 100.
[0086] After ion implantation into the first and third portions of the first oxide semiconductor layer 20, its conductivity is enhanced. The second portion of the first oxide semiconductor layer 20 can be configured as the source 101 of the memory device 100, and the third portion of the first oxide semiconductor layer 20 can be configured as the drain 102 of the memory device 100. For example, the first portion is doped with arsenic ions and forms the source 101, and the third portion is doped with arsenic ions and forms the drain 102. The source 101 and drain 102 are located on both sides of the channel region 103, and all three are formed within the first oxide semiconductor layer 20.
[0087] In this embodiment, the gate structure is disposed on the first oxide semiconductor layer 20, and the gate structure is opposite to the channel region 103. The gate structure includes a gate dielectric layer 31 and a second oxide semiconductor layer 32 sequentially stacked along the second direction, that is, the gate dielectric layer 31 is located between the first oxide semiconductor layer 20 and the second oxide semiconductor layer 32, and the gate dielectric layer 31 is attached to the upper surface of the first oxide semiconductor layer 20, and the second oxide semiconductor layer 32 is attached to the upper surface of the gate dielectric layer 31.
[0088] Furthermore, in this embodiment, the gate dielectric layer 31 can be an oxide layer, such as a silicon oxide layer or an aluminum oxide layer; this embodiment is not limited in this respect. The second oxide semiconductor layer 32 is made of the same material as the first oxide semiconductor layer 20, that is, the second oxide semiconductor layer 32 can be an IGZO semiconductor layer. The second oxide semiconductor layer 32 is doped with arsenic ions to improve its conductivity, and the second oxide semiconductor layer 32 can be configured as a gate layer 104.
[0089] Compared with the related technologies in which the source, drain and gate layers of the memory device are all made of metal materials and are separately fabricated, and the source, drain and channel regions form Schottky contacts (metal-semiconductor contacts), the semiconductor structure provided in this application embodiment is made of oxide semiconductor layers for the source 101, drain 102 and channel region 103, which can reduce the contact resistance between the source 101, drain 102 and channel region.
[0090] like Figure 16 As shown, based on the above embodiments, the semiconductor structure provided in this application further includes an insulating layer 40, wherein the insulating layer 40 is disposed between the first oxide semiconductor layer 20 and the substrate 10 along the second direction, and the insulating layer 40 covers the entire substrate 10; it should be noted that the insulating layer 40 can be a silicon oxide film layer formed on the surface of the substrate 10 by a thermal growth process. With this configuration, an isolation layer is formed between the substrate 10 and the channel region 103, which can isolate the channel region from the substrate 10 and prevent leakage between the substrate 10 and the channel.
[0091] In this embodiment, the gate dielectric layer 31 is configured as a high-k dielectric layer 31a, which increases the thickness of the gate dielectric layer 31 and prevents tunneling current. Furthermore, an isolation layer 33 is provided between the high-k dielectric layer 31a and the second oxide semiconductor layer 32. This isolation layer 33 can be a silicon nitride layer, and it covers the entire high-k dielectric layer 31a to effectively isolate the high-k dielectric layer 31a from the second oxide semiconductor layer 32, preventing ions in the second oxide semiconductor layer 32 from entering the high-k dielectric layer 31a and the channel region 103.
[0092] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.
[0093] In the description of this specification, references to "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0094] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A method for fabricating a semiconductor structure, comprising the following steps: Provide substrate; A first oxide semiconductor layer is formed on the substrate; A gate stack is formed on the first oxide semiconductor layer, the gate stack including a gate dielectric layer and a second oxide semiconductor layer located on the gate dielectric layer; wherein the first oxide semiconductor layer is made of the same material as the first oxide semiconductor layer. Vertical etching is performed on portions of the gate stack located on both sides of the channel region, while retaining portions of the gate stack opposite to the channel region; Ion implantation is performed on the second oxide semiconductor layer and the first oxide semiconductor layer located on both sides of the channel region to form a gate layer and a source and drain electrode respectively on both sides of the channel region.
2. The preparation method according to claim 1, characterized in that, The step of forming a first oxide semiconductor layer on the substrate further includes forming an insulating layer on the substrate.
3. The preparation method according to claim 2, characterized in that, The gate dielectric layer is a high-k dielectric layer; The step of forming a gate stack on the first oxide semiconductor layer includes: A high-k dielectric material is deposited on the first oxide semiconductor layer to form a high-k dielectric layer.
4. The preparation method according to claim 3, characterized in that, The step of forming a gate stack on the first oxide semiconductor layer further includes: An isolation layer is formed on the high-k dielectric layer; The second oxide semiconductor layer is formed on the isolation layer.
5. The preparation method according to any one of claims 1 to 4, characterized in that, After performing ion implantation on the second oxide semiconductor layer and the first oxide semiconductor layer located on both sides of the channel region, the method further includes: The semiconductor structure is annealed after ion implantation.
6. The method for preparing a semiconductor structure according to claim 1, characterized in that, The first oxide semiconductor layer and the second oxide semiconductor layer are made of indium gallium zinc oxide.
7. A semiconductor structure, characterized in that, include: A substrate having a first oxide semiconductor layer, wherein a portion of the first oxide semiconductor layer that is not doped with ions is configured as a channel region; The portions of the first oxide semiconductor layer located on both sides of the channel region and doped with ions respectively form the source and drain electrodes; A gate structure is disposed above the channel region. The gate structure includes a gate dielectric layer and a second oxide semiconductor layer disposed on the gate dielectric layer, wherein the second oxide semiconductor layer is doped with ions and configured as a gate layer.
8. The semiconductor structure according to claim 7, characterized in that, The semiconductor structure also includes an insulating layer; The insulating layer is disposed between the first oxide semiconductor layer and the substrate, and the insulating layer covers the entire substrate.
9. The semiconductor structure according to claim 7, characterized in that, The gate dielectric layer is configured as a high-k dielectric layer.
10. The semiconductor structure according to claim 9, characterized in that, An isolation layer is provided between the high-k dielectric layer and the second oxide semiconductor layer.