Semiconductor structure and method of manufacturing the same

Abstract

The embodiment of the present disclosure relates to the field of semiconductor, and provides a semiconductor structure and a manufacturing method thereof, the semiconductor structure comprising: a substrate; a first oxide semiconductor layer perpendicular to a surface of the substrate, comprising a first channel region and first source-drain doped regions located on opposite sides of the first channel region along an extension direction of the first oxide semiconductor layer; first gates located on at least opposite sides of the first oxide semiconductor layer along any direction parallel to the surface of the substrate, the first gates located on opposite sides of the first oxide semiconductor layer being gate regions, and the first gates further comprising a connecting region connecting the gate regions; and first source-drain electrodes comprising first source electrodes and first drain electrodes located on opposite sides of the first oxide semiconductor layer, the first source-drain electrodes being in contact with the first source-drain doped regions; wherein the first oxide semiconductor layer, the first gates and the first source-drain electrodes constitute a first transistor. At least the performance of the semiconductor structure can be improved while reducing the size of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and a method for manufacturing the same. Background Technology

[0002] As semiconductor process technology advances, semiconductor process nodes are shrinking in accordance with Moore's Law. To accommodate this shrinking process node, the channel length of MOSFETs is also continuously shortening. However, as the channel length decreases, the distance between the source and drain also decreases, resulting in poorer gate control over the channel and increasing the difficulty of pinching off the channel with the gate voltage. This makes subthreshold leakage, also known as short-channel effects (SCE), more likely to occur.

[0003] The short-channel effect can affect the performance of semiconductor structures, making it difficult to improve semiconductor structure performance while reducing the size of the semiconductor structure. Summary of the Invention

[0004] This disclosure provides a semiconductor structure and a method for manufacturing the same, which can at least improve the performance of the semiconductor structure while reducing its size.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a semiconductor structure, including: a substrate; a first oxide semiconductor layer, the first oxide semiconductor layer being located above the substrate and extending perpendicularly to the surface of the substrate, the first oxide semiconductor layer including a first channel region and first source / drain doped regions located on opposite sides of the first channel region along the extending direction of the first oxide semiconductor layer; a first gate, the first gate being located at least on opposite sides of the first oxide semiconductor layer in any direction parallel to the surface of the substrate, and the first gate located on opposite sides of the first oxide semiconductor layer being a gate region, the gate region being at least directly opposite the first channel region, the first gate further including a connection region, the connection region connecting the gate region; and a first source / drain, the first source / drain including a first source and a first drain located on opposite sides of the first oxide semiconductor layer along the extending direction of the first oxide semiconductor layer, and the first source / drain contacting the first source / drain doped region; wherein the first oxide semiconductor layer, the first gate, and the first source / drain constitute a first transistor.

[0006] In some embodiments, the length of the region of the first oxide semiconductor layer opposite to the first gate accounts for 60% to 90% of the total length of the first oxide semiconductor layer.

[0007] In some embodiments, the first gate surrounds the first oxide semiconductor layer on three sides in a direction parallel to the surface of the substrate, or the first gate surrounds the first oxide semiconductor layer.

[0008] In some embodiments, the first gate is located only on opposite sides of the first oxide semiconductor layer in any direction parallel to the substrate surface.

[0009] In some embodiments, the connection region is located on the side of the first oxide semiconductor layer closer to the substrate, and the first drain is located on the side of the first oxide semiconductor layer away from the substrate.

[0010] In some embodiments, the connection region is located on the side of the first oxide semiconductor layer away from the substrate, and the first drain is located on the side of the first oxide semiconductor layer close to the substrate.

[0011] In some embodiments, the first transistor is a write transistor, and the semiconductor structure further includes: a second gate, the second gate being located on the surface of the first drain away from the first oxide semiconductor layer, and the second gate being electrically connected to the first drain; a second oxide semiconductor layer, at least located on the side of the second gate away from the first transistor, and the extension direction of the second oxide semiconductor layer being parallel to the surface of the substrate, the second oxide semiconductor layer including a second channel region and second source / drain doped regions located on opposite sides of the second channel region along the extension direction of the second oxide semiconductor layer, the second channel region being directly opposite the second gate; and second source / drain electrodes located on both sides of the second oxide semiconductor layer along the extension direction of the second oxide semiconductor layer, and the second source / drain electrodes being in contact with the second source / drain doped regions; wherein the second gate, the second oxide semiconductor layer, and the second source / drain electrodes constitute a second transistor, and the second transistor is a read transistor.

[0012] In some embodiments, the second oxide semiconductor layer surrounds the second gate on three sides, and the second oxide semiconductor layer also covers at least a portion of the sides of the second gate.

[0013] According to some embodiments of this disclosure, another aspect of this disclosure provides a method for manufacturing a semiconductor structure, comprising: providing a substrate; forming a first gate, a first oxide semiconductor layer, and a first source / drain electrode, wherein the first oxide semiconductor layer is located above the substrate and the extension direction of the first oxide semiconductor layer is perpendicular to the surface of the substrate, the first oxide semiconductor layer includes a first channel region and first source / drain doped regions located on opposite sides of the first channel region along the extension direction of the first oxide semiconductor layer, wherein in any direction parallel to the surface of the substrate, the first gate is located on at least opposite sides of the first oxide semiconductor layer, and the first gate located on opposite sides of the first oxide semiconductor layer is a gate region, the gate region being at least directly opposite the first channel region, the first gate further includes a connection region connecting the gate region, and in the extension direction of the first oxide semiconductor layer, the first source / drain electrode includes a first source electrode and a first drain electrode located on opposite sides of the first oxide semiconductor layer, and the first source / drain electrode is in contact with the first source / drain doped region; wherein the first gate, the first oxide semiconductor layer, and the first source / drain electrode constitute a first transistor.

[0014] In some embodiments, the first transistor is a write transistor; after forming the first gate, the first oxide semiconductor layer, and the first source / drain, or before forming the first gate, the first oxide semiconductor layer, and the first source / drain, the method further includes: forming a second gate, a second oxide semiconductor layer, and a second source / drain, wherein the second gate is located on the surface of the first drain away from the first oxide semiconductor layer, and the second gate is electrically connected to the first drain, the second oxide semiconductor layer is located at least on the side of the second gate away from the first transistor, and the extension direction of the second oxide semiconductor layer is parallel to the surface of the substrate, the second oxide semiconductor layer includes a second channel region and second source / drain doped regions located on opposite sides of the second channel region along the extension direction of the second oxide semiconductor layer, the second channel region is directly opposite the second gate, the second source / drain is located on both sides of the second oxide semiconductor layer along the extension direction of the second oxide semiconductor layer, and the second source / drain is in contact with the second source / drain doped regions; wherein the second gate, the second oxide semiconductor layer, and the second source / drain constitute a second transistor, and the second transistor is a read transistor.

[0015] The technical solutions provided in this disclosure have at least the following advantages:

[0016] The semiconductor structure provided in this disclosure includes: a substrate; a first oxide semiconductor layer perpendicular to the surface of the substrate, the first oxide semiconductor layer including a first channel region and first source / drain doped regions located on opposite sides of the first channel region; a first gate, located at least on opposite sides of the first oxide semiconductor layer in any direction parallel to the surface of the substrate, and the first gates located on opposite sides of the first oxide semiconductor layer are gate regions, at least directly opposite the first channel region, and the first gate also includes a connection region for connecting the gate regions; and first source / drain electrodes located on opposite sides of the first oxide semiconductor layer, the first source / drain electrodes being in contact with the first source / drain doped regions; wherein the first oxide semiconductor layer, the first gate, and the first source / drain electrodes constitute a first transistor. In this disclosure, the extension direction of the first oxide semiconductor layer is perpendicular to the surface of the substrate, that is, the extension direction of the channel of the first transistor is perpendicular to the surface of the substrate, which can greatly reduce the size occupied by the first transistor in the direction parallel to the surface of the substrate, which is beneficial to improving the integration density of the semiconductor structure and reducing the size of the semiconductor structure. Furthermore, in related technologies, the channel extension direction of the first transistor is parallel to the substrate surface. To reduce the size of the semiconductor structure and improve its integration density, the size of the first transistor channel needs to be reduced. This leads to a short-channel effect, reducing the carrier mobility of the first transistor and affecting its performance. However, in this disclosure, the extension direction of the first transistor channel region is perpendicular to the substrate surface. This allows for a reduction in the size of the semiconductor structure without compressing the channel length, avoiding the short-channel effect and enabling the first transistor to have a higher carrier mobility, thus enhancing the performance of the semiconductor structure. Additionally, in this disclosure, the first gate of the first transistor is located at least on opposite sides of the channel region, and the gate regions on both sides are connected by a connection region. This increases the area of ​​the region directly opposite the first gate and the channel region, improving the control capability of the first gate over the first transistor, thereby improving the performance of the first transistor and enhancing the performance of the semiconductor structure. Attached Figure Description

[0017] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a top view of a semiconductor structure provided in an embodiment of the present disclosure;

[0019] Figure 2 This is a cross-sectional view of a semiconductor structure provided in an embodiment of the present disclosure;

[0020] Figure 3 This is another cross-sectional view of a semiconductor structure provided in an embodiment of the present disclosure;

[0021] Figure 4 This is a top view of a semiconductor structure provided in another embodiment of the present disclosure;

[0022] Figure 5 This is a top view of a semiconductor structure provided in another embodiment of the present disclosure;

[0023] Figure 6 This is a top view of a semiconductor structure provided in another embodiment of the present disclosure;

[0024] Figure 7 This is a cross-sectional view of a semiconductor structure provided in another embodiment of the present disclosure;

[0025] Figure 8 This is another cross-sectional view of a semiconductor structure provided in another embodiment of the present disclosure;

[0026] Figure 9 This is a cross-sectional view of a semiconductor structure provided in another embodiment of the present disclosure;

[0027] Figure 10 A simplified circuit diagram corresponding to a semiconductor structure provided in one embodiment of this disclosure;

[0028] Figure 11 A cross-sectional structural schematic diagram of a semiconductor structure provided in another embodiment of this disclosure;

[0029] Figure 12 A cross-sectional structural schematic diagram of a semiconductor structure provided in another embodiment of this disclosure;

[0030] Figure 13 This is a cross-sectional view of a semiconductor structure provided in another embodiment of the present disclosure;

[0031] Figure 14 This is a cross-sectional view of a semiconductor structure provided in another embodiment of the present disclosure;

[0032] Figures 15 to 29 This is a cross-sectional structural diagram corresponding to each step in the manufacturing method of the semiconductor structure provided in the embodiments of this disclosure. Detailed Implementation

[0033] As can be seen from the background technology, current semiconductor structures have the problem of not being able to simultaneously reduce the size of semiconductor structures and improve their performance.

[0034] This disclosure provides a semiconductor structure in which the extension direction of the first oxide semiconductor layer of the first transistor is perpendicular to the surface of the substrate. The first oxide semiconductor layer includes a first channel region and first source / drain doped regions located on opposite sides of the first channel region. That is, the extension direction of the channel is perpendicular to the surface of the substrate. When miniaturizing the substrate, it is not necessary to reduce the length of the channel, thus avoiding short-channel effects and not affecting the performance of the semiconductor structure, allowing the transistor to have higher carrier mobility. Furthermore, the first gate is located at least on opposite sides of the channel region, and the gate regions on both sides are connected by a connection region. This increases the area of ​​the region directly opposite the first gate and the channel region, improving the control capability of the first gate over the first transistor, thereby improving the performance of the first transistor and enhancing the performance of the semiconductor structure.

[0035] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the various embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0036] Figure 1 This is a top view schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure. Figure 2 for Figure 1 A schematic diagram of the cross-sectional structure of the semiconductor structure along the AA1 direction. Figure 3 for Figure 1 A schematic diagram of the cross-sectional structure of the semiconductor structure along the BB1 ​​direction.

[0037] refer to Figures 1 to 3The semiconductor structure includes: a substrate 100; a first oxide semiconductor layer 210, the first oxide semiconductor layer 210 being located above the substrate 100 and extending perpendicularly to the surface of the substrate 100, the first oxide semiconductor layer 210 including a first channel region 211 and first source / drain doped regions 212 located on opposite sides of the first channel region 211 along the extending direction of the first oxide semiconductor layer 210; and a first gate 220, the first gate 220 being located at least on opposite sides of the first oxide semiconductor layer 210 in any direction parallel to the surface of the substrate 100, and located within the first oxide semiconductor layer. The first gate 220 on both sides of the first oxide semiconductor layer 210 is a gate region 221, which is at least directly opposite the first channel region 211. The first gate 220 also includes a connection region 222, which is connected to the gate region 221. The first source and drain 230, along the extension direction of the first oxide semiconductor layer 210, includes a first source 231 and a first drain 232 located on both sides of the first oxide semiconductor layer 210, and the first source and drain 230 is in contact with the first source and drain doped region 212. The first oxide semiconductor layer 210, the first gate 220 and the first source and drain 230 constitute the first transistor 200.

[0038] In some embodiments, the substrate 100 may be an active region. The material of the substrate 100 may include single-crystal silicon (Si), single-crystal germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it may also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it may be a glass substrate or other materials, such as gallium arsenide or other III-V compounds. The material of the substrate 100 may be single-crystal silicon (Si) or a glass substrate.

[0039] In some embodiments, the material of the first oxide semiconductor layer 210 may include IGZO (indium gallium zinc oxide). IGZO contains indium, gallium, and zinc, and is a novel semiconductor material. Using IGZO material in the first oxide semiconductor layer 210 of a semiconductor structure as the channel of the first transistor can improve the performance of the semiconductor structure. Compared to amorphous silicon channels, the carrier mobility of a channel using IGZO material is 20-30 times that of amorphous silicon, and IGZO can also improve the charge and discharge rate of the semiconductor structure, thereby improving the energy efficiency of the semiconductor structure.

[0040] Along the extension direction of the first oxide semiconductor layer 210, the first source / drain doped regions 212 are located on opposite sides of the first channel region 211. The first source / drain doped regions 212 require doping treatment. If N-type doping is required, N-type ions, such as nitrogen ions or phosphorus ions, can be implanted. If P-type doping is required, P-type ions, such as boron ions or aluminum ions, can be implanted.

[0041] When the extension direction of the first oxide semiconductor layer 210 is perpendicular to the surface of the substrate 100, if the size of the substrate 100 is compressed, the length of the first oxide semiconductor layer 210 is not required, that is, the length of the channel does not need to be compressed, and therefore the short-channel effect will not occur. It is possible to improve the performance of the semiconductor structure and increase the carrier mobility of the first transistor while compressing the size of the semiconductor structure.

[0042] In some embodiments, the material of the first gate 220 may include one or more of polysilicon or tungsten. The first gate 220, as a control structure in the first transistor, must at least be directly opposite the first channel region 211 in the first transistor to control the conduction of the first transistor.

[0043] In any direction parallel to the surface of the substrate 100, the first gate 220 is located at least on opposite sides of the first oxide semiconductor layer 210, that is, the first gate 220 is directly opposite at least two sides of the first oxide semiconductor layer 210. This increases the area of ​​the region directly opposite the first gate 220 and the first channel region 211, thereby improving the control capability of the first gate 220 over the first transistor. Furthermore, to enable the first gates 220 located on opposite sides of the first oxide semiconductor layer 210 to be electrically connected, a connection region 222 is also required, which connects the gate regions located on opposite sides of the first oxide semiconductor layer 210 within the first gate 220.

[0044] In some embodiments, the length of the region directly opposite the first oxide semiconductor layer 210 and the first gate 220 can be 60% to 90% of the total length of the first oxide semiconductor layer 210. For example, the length of the region directly opposite the first oxide semiconductor layer 210 and the first gate 220 can be 65%, 70%, 80%, 85%, etc. If the length of the region directly opposite the first oxide semiconductor layer 210 and the first gate 220 is too small, the length of the region directly opposite the first oxide semiconductor layer 210 and the first gate 220 will be too short, the length of the first channel region 211 may be too short, and the first gate 220 will have a weaker control effect on the conduction of the first transistor. This will affect the performance of the first transistor to some extent, thereby affecting the performance of the semiconductor structure. Therefore, when the area of ​​the first oxide semiconductor layer 210 and the first gate 220 facing each other accounts for 60% to 90% of the total length of the first oxide semiconductor layer 210, the area of ​​the area of ​​the first gate 220 and the first oxide semiconductor layer 210 facing each other is larger, and the length of the first channel region 211 in the first oxide semiconductor layer 210 is longer, which can enhance the control effect of the first gate 220 on the first transistor, thereby improving the performance of the first transistor.

[0045] Figure 4 This is a top view schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure. Figure 5 This is a top view of another embodiment of the present disclosure.

[0046] refer to Figures 4 to 5 In some embodiments, the first gate 220 may surround the first oxide semiconductor layer 210 on three sides in a direction parallel to the surface of the substrate 100, or the first gate 220 may surround the first oxide semiconductor layer 210. Figure 4 The first gate 220 surrounds the first oxide semiconductor layer 210 on three sides in a direction parallel to the surface of the substrate 100. Figure 5The first gate 220 surrounds the first oxide semiconductor layer 210 on all four sides in a direction parallel to the surface of the substrate 100. Thus, the first gate 220 located on opposite sides of the first oxide semiconductor layer 210 can be electrically connected via first gate 220 located on the other side or two other sides of the first oxide semiconductor layer 210, eliminating the need for connection regions 222 in other areas. The first gate 220 located on the other side or two other sides of the first oxide semiconductor layer 210 serves as the connection region 222 within the first gate 220. This structure of the first gate 220 further increases the area of ​​the region directly opposite the first oxide semiconductor layer 210, further improving the control capability of the first gate 220 over the first transistor, further improving the carrier mobility of the first transistor, and enhancing the performance of the semiconductor structure.

[0047] In some embodiments, when the first gate 220 surrounds the first oxide semiconductor layer 210 on three sides or on all four sides in a direction parallel to the surface of the substrate 100, the first gate 220 can be an annular ring with an opening, a square annular ring with an opening, an annular ring without an opening, or a square annular ring without an opening. Figure 4 as well as Figure 5 Only square annular rings with openings and square annular rings without openings are shown. Furthermore, it is understood that the first gate 220, located on one or both sides of the first oxide semiconductor layer 210 as a connection region 222, may only be directly opposite a portion of the first oxide semiconductor layer 210. Also, in the direction perpendicular to the surface of the substrate 100, the thickness of the connection region 222 may be less than the thickness of the gate region 221, and the connection region 222 may be located at any height of the gate region 221.

[0048] Figure 6 This is a top view schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure. Figure 7 for Figure 6 A schematic diagram of the cross-sectional structure of the semiconductor structure along the AA1 direction. Figure 8 for Figure 6 A schematic diagram of the cross-sectional structure of the semiconductor structure along the BB1 ​​direction.

[0049] refer to Figures 1 to 3 as well as Figures 6 to 8In some embodiments, the first gate 220 may be located only on opposite sides of the first oxide semiconductor layer 210 in any direction parallel to the surface of the substrate 100. The fact that the first gate 220 is located only on opposite sides of the first oxide semiconductor layer 210 means that the connection region 222 is not located on the side of the first oxide semiconductor layer 210 in the direction parallel to the surface of the substrate 100. The connection region 222 may be located on the side of the first oxide semiconductor layer 210 closer to the substrate 100, or the connection region 222 may be located on the side of the first oxide semiconductor layer 210 away from the substrate 100.

[0050] refer to Figures 1 to 3 In some embodiments, the connection region 222 may be located on the side of the first oxide semiconductor layer 210 near the substrate 100, the first drain 232 may be located on the side of the first oxide semiconductor layer 210 away from the substrate 100, and the first source 231 may be located on the side of the first oxide semiconductor layer 210 near the substrate 100. If the first transistor is used as the write transistor in the semiconductor structure, the first drain 232 of the first transistor needs to be electrically connected to the gate of the read transistor. Therefore, when the connection region 222 is located on the side of the first oxide semiconductor layer 210 near the substrate 100, the read transistor can be disposed on the side of the first transistor away from the substrate 100, and the first drain 232 on the side of the first oxide semiconductor layer 210 away from the substrate 100 can be electrically connected to the gate of the read transistor. In addition, the connection region 222 located on the side of the first oxide semiconductor layer 210 near the substrate 100 extends along the AA1 direction, and the width of the connection region 222 along the BB1 ​​direction is adjustable, as is the position of the connection region 222 in the BB1 ​​direction.

[0051] refer to Figures 6 to 8 In some embodiments, the connection region 222 may be located on the side of the first oxide semiconductor layer 210 away from the substrate 100, the first drain 232 may be located on the side of the first oxide semiconductor layer 210 close to the substrate 100, and the first source 231 may be located on the side of the first oxide semiconductor layer 210 away from the substrate 100. If a first transistor is used as a write transistor in a semiconductor structure, the first drain 232 of the first transistor needs to be electrically connected to the gate of the read transistor. Therefore, when the connection region 222 is located on the side of the first oxide semiconductor layer 210 away from the substrate, the read transistor may be located on the side of the first transistor close to the substrate 100, and the first drain 232 on the side of the first transistor close to the substrate 100 may be electrically connected to the gate of the read transistor. In addition, the connection region 222 located on the side of the first oxide semiconductor layer 210 away from the substrate 100 extends along the AA1 direction, and the width of the connection region 222 in the BB1 ​​direction is adjustable, as is the position of the connection region 222 in the BB1 ​​direction.

[0052] In some embodiments, the height difference between the gate regions located on opposite sides of the first oxide semiconductor layer in the direction perpendicular to the substrate can be less than or equal to 10 nm. For example, it can be 0 nm, 2 nm, 4 nm, 6 nm, 8 nm, etc. If the length difference between the gate regions on opposite sides of the first oxide semiconductor layer is too small, the control effect of the two gate regions on the first oxide semiconductor layer will be uneven, which may affect the performance of the first transistor. Therefore, when the length difference between the gate regions on opposite sides of the first oxide semiconductor layer is less than or equal to 10 nm in any direction parallel to the substrate surface, the control effect of the two opposite parts of the first gate in the first oxide semiconductor layer can be more balanced, improving the performance of the first transistor.

[0053] The first source / drain 230 is a conductive structure electrically connected to the first source / drain doped region 212. Specifically, the first source 231 electrically connects the source region in the first source / drain doped region 212 to other components in the semiconductor structure, and the first drain 232 electrically connects the drain region in the first source / drain doped region 212 to other components in the semiconductor structure. In some embodiments, the material of the first source / drain 230 may include one or more of polysilicon and tungsten. The material of the first source / drain 230 may be the same as the material of the first gate 220.

[0054] refer to Figure 9 In some embodiments, the semiconductor structure may further include a first gate dielectric layer 240, which is located between the first oxide semiconductor layer 210 and the gate region 221, and covers at least two sides of the first oxide semiconductor layer 210. The first gate dielectric layer 240 improves the electronic conductivity of the first transistor, making electron conduction in the semiconductor structure smoother. Furthermore, the first gate dielectric layer 240 can control the current, preventing excessive current from causing overheating or short circuits. It can form a charge channel to control the flow of electrons in the device, improve device stability and efficiency, and protect the device from environmental factors to some extent. Additionally, the first gate dielectric layer 240 has a certain surface activity and can serve as a surface-active layer in the semiconductor structure, used to receive or place other substances.

[0055] In some embodiments, the material of the first gate dielectric layer 240 can be an insulating material. For example, the material of the first gate dielectric layer 240 may include one or more of silicon nitride or silicon oxide. This allows the first gate dielectric layer 240 to better improve the device's conductivity and stability.

[0056] In some embodiments, the semiconductor structure may further include a filling layer 110, which is located on the same side of the substrate 100 as the first transistor, and fills the area around each component in the semiconductor structure. If the connection region 222 is located on the side of the first oxide semiconductor layer 210 closer to the substrate 100, the filling layer 110 is also located between the connection region 222 and the first source 231; if the connection region 222 is located on the side of the first oxide semiconductor layer 210 away from the substrate 100, the filling layer 110 is also located between the connection region 222 and the first source 231.

[0057] Since the fill layer 110 is also located between the first gate 220 and the first oxide semiconductor layer 210, the fill layer 110 can also serve as a gate dielectric layer. In some embodiments, the material of the fill layer 110 may include silicon oxide.

[0058] Figure 10 This is a simplified circuit diagram corresponding to a semiconductor structure provided in one embodiment of the present disclosure. The semiconductor structure can be a 2TOC structure. (See reference...) Figure 10 In some embodiments, the first transistor can be a write transistor. The semiconductor structure may also include a second transistor, which can serve as a read transistor. The first and second transistors can constitute a memory cell. When the semiconductor structure is operating, charge is stored in the gate capacitance of the second transistor, and the location where the charge is stored is typically referred to as the memory node (SN). The write operation of the 2TOC memory cell is controlled by the first transistor, and the read operation is controlled by the second transistor. Charge is stored using the gate capacitance of the transistors. Studies have shown that transistors fabricated using metal-oxide-semiconductor (MOS) transistors have a smaller cutoff current, allowing the charge stored in the gate capacitance to be retained for a longer period.

[0059] Specifically, the first gate 220 of the first transistor, which serves as the write transistor, is electrically connected to the write word line WWL; the first source 231 of the first transistor is electrically connected to the write bit line WBL; the first drain 232 of the first transistor is electrically connected to the gate of the second transistor, which serves as the read transistor; and the source and drain of the second transistor are electrically connected to the read word line RWL and the read bit line RBL, respectively. For clarity, the read word line, read bit line, write word line, and write bit line are not shown in the structural diagram.

[0060] The memory cell structure is of the 2T0C type, without capacitors, which helps to reduce the size of the memory cell structure. Moreover, the first transistor and the second transistor are stacked vertically along the direction perpendicular to the surface of the substrate 100, which helps to reduce the size of the substrate 100, thereby helping to reduce the size of the semiconductor structure.

[0061] Figure 11 This is a schematic cross-sectional view of a semiconductor structure provided in an embodiment of the present disclosure. Figure 12 This is a cross-sectional view of a semiconductor structure corresponding to another embodiment of the present disclosure.

[0062] refer to Figures 11 to 12 In some embodiments, the second transistor may include: a second gate 310, located on the surface of the first drain 232 away from the first oxide semiconductor layer 210, and electrically connected to the first drain 232; a second oxide semiconductor layer 320, located at least on the side of the second gate 310 away from the first transistor, and extending parallel to the surface of the substrate 100, the second oxide semiconductor layer 320 including a second channel region 321 and second source / drain doped regions 322 located on opposite sides of the second channel region 321 along the extending direction of the second oxide semiconductor layer 320, the second channel region 321 being directly opposite the second gate 310; and second source / drain electrodes 330 located on both sides of the second oxide semiconductor layer 320 along the extending direction of the second oxide semiconductor layer 320, and in contact with the second source / drain doped regions 322; wherein the second gate 310, the second oxide semiconductor layer 320, and the second source / drain electrodes 330 constitute the second transistor, which is a read transistor.

[0063] refer to Figure 11 In the first transistor, the connection region 222 is located on the side of the first oxide semiconductor layer 210 closer to the substrate 100, and the first drain 232 is located on the side of the first oxide semiconductor layer 210 away from the substrate 100. Therefore, the second transistor can be disposed on the side of the first transistor away from the substrate 100. The second gate 310 of the second transistor is electrically connected to the first drain 232 of the first transistor, forming a storage node.

[0064] refer to Figure 12 In the first transistor, the connection region 222 is located on the side of the first oxide semiconductor layer 210 away from the substrate 100, and the first drain 232 is located on the side of the first oxide semiconductor layer 210 closer to the substrate 100. The second transistor can then be disposed on the side of the first transistor closer to the substrate 100, and the second transistor can be located between the first transistor and the substrate 100. The second gate 310 of the second transistor is electrically connected to the first drain 232 of the first transistor to form a memory node.

[0065] In some embodiments, the material of the second gate 310 may include one or more of polysilicon or tungsten. The second gate 310, as a control structure in the second transistor, must at least be directly opposite the second channel region 321 in the second transistor to control the conduction of the second transistor.

[0066] In some embodiments, the material of the second oxide semiconductor layer 320 may include IGZO (indium gallium zinc oxide). IGZO contains indium, gallium, and zinc, and is a novel semiconductor material. Using IGZO material in the second oxide semiconductor layer 320 of a semiconductor structure as a channel for a second transistor can improve the performance of the semiconductor structure. Compared to a channel made of amorphous silicon material, the carrier mobility of a channel made of IGZO is 20-30 times that of amorphous silicon, and IGZO can also improve the charge and discharge rate of the semiconductor structure, thereby improving the energy efficiency of the semiconductor structure.

[0067] Along the extension direction of the second oxide semiconductor layer 320, the second source / drain doped regions 322 are located on opposite sides of the second channel region 321. The second source / drain doped regions 322 require doping treatment. If N-type doping is required, N-type ions, such as nitrogen ions or phosphorus ions, can be implanted. If P-type doping is required, P-type ions, such as boron ions or aluminum ions, can be implanted.

[0068] Figure 13 This is a schematic cross-sectional view of a semiconductor structure provided in an embodiment of the present disclosure. Figure 14 This is a cross-sectional view of a semiconductor structure corresponding to another embodiment of the present disclosure.

[0069] refer to Figures 13 to 14 In some embodiments, the second oxide semiconductor layer 320 may surround the second gate 310 on three sides, and the second oxide semiconductor layer 320 may also cover at least a portion of the sides of the second gate 310. The second oxide semiconductor layer 320 surrounding the second gate 310 on three sides enables the second transistor to form a vertical-ring channel transistor (CAA). In a vertical-ring channel transistor, the channel may surround the periphery of the gate. This increases the area of ​​the region directly opposite the second gate 310 and the second channel region 321, improving the control capability of the second gate 310 over the conduction of the second transistor, thereby improving the performance of the semiconductor structure.

[0070] The second source / drain 330 is a conductive structure electrically connected to the second source / drain doped region 322. In some embodiments, the material of the second source / drain 330 may include one or more of polysilicon and tungsten. The material of the second source / drain 330 may be the same as the material of the second gate 310.

[0071] refer to Figures 12 to 14In some embodiments, the semiconductor structure may further include a second gate dielectric layer 340, which is located at least between the second oxide semiconductor layer and the second gate. The second gate dielectric layer 340 improves the electronic conductivity of the first transistor, making electron conduction in the semiconductor structure smoother. Furthermore, the second gate dielectric layer 340 can control the current, preventing excessive current from causing overheating or short circuits. It can form a charge channel to control the flow of electrons in the device, improve device stability and efficiency, and protect the device from environmental factors to some extent. Additionally, the second gate dielectric layer 340 has a certain degree of surface activity and can serve as a surface-active layer in the semiconductor structure, used to receive or place other substances.

[0072] In some embodiments, the material of the second gate dielectric layer 340 can be an insulating material. For example, the material of the second gate dielectric layer 340 may include one or more of silicon nitride or silicon oxide. This allows the second gate dielectric layer 340 to better improve the device's conductivity and stability.

[0073] The semiconductor structure provided in this disclosure includes: a substrate; a first oxide semiconductor layer perpendicular to the substrate, the first oxide semiconductor layer including a first channel region and first source / drain doped regions located on opposite sides of the first channel region; a first gate located at least on opposite sides of the first oxide semiconductor layer along any direction parallel to the substrate surface, the first gate located on opposite sides of the first oxide semiconductor layer being a gate region, the gate region being at least directly opposite the first channel region, the first gate further including a connection region connecting the gate region; and first source / drain electrodes located on opposite sides of the first oxide semiconductor layer and in contact with the first source / drain doped regions. Thus, without inducing short-channel effects, the size of the semiconductor structure can be reduced, the integration density of the semiconductor structure can be increased, the carrier mobility of the first transistor can be improved, and the performance of the semiconductor structure can be enhanced. Furthermore, having the first gate located at least on opposite sides of the channel region and the gate regions on both sides connected by the connection region can improve the control capability of the first gate over the first transistor, thereby improving the performance of the semiconductor structure.

[0074] Accordingly, another embodiment of this disclosure also provides a method for manufacturing a semiconductor structure, which can be used to form the above-mentioned semiconductor structure. The method for manufacturing a semiconductor structure provided by another embodiment of this disclosure will be described in detail below with reference to the accompanying drawings. For parts that are the same as or corresponding to the previous embodiment, please refer to the corresponding descriptions of the foregoing embodiments; detailed descriptions will not be repeated below.

[0075] refer to Figure 15 Provides a base of 100.

[0076] In some embodiments, the substrate 100 may be an active region. The material of the substrate 100 may include single-crystal silicon (Si), single-crystal germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it may also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it may be a glass substrate or other materials, such as gallium arsenide or other III-V compounds. The material of the substrate 100 may be single-crystal silicon (Si) or a glass substrate.

[0077] refer to Figures 16 to 17 A first gate 220, a first oxide semiconductor layer 210, and a first source / drain 230 are formed. The first oxide semiconductor layer 210 is located above the substrate 100, and its extension direction is perpendicular to the surface of the substrate 100. The first oxide semiconductor layer 210 includes a first channel region 211 and first source / drain doped regions 212 located on opposite sides of the first channel region 211 along the extension direction of the first oxide semiconductor layer 210. In any direction parallel to the surface of the substrate 100, the first gate 220 is located at least on opposite sides of the first oxide semiconductor layer 210 and is located on the first oxide semiconductor layer 230. The first gate 220 on opposite sides of the first oxide semiconductor layer 210 is a gate region 221, which is at least directly opposite to the first channel region 211. The first gate 220 also includes a connection region 222, which connects to the gate region 221. Along the extension direction of the first oxide semiconductor layer 210, the first source and drain 230 includes a first source 231 and a first drain 232 located on opposite sides of the first oxide semiconductor layer 210, and the first source and drain 230 are in contact with the first source and drain doped region 212. The first gate 220, the first oxide semiconductor layer 210 and the first source and drain 230 constitute the first transistor.

[0078] In some embodiments, the first transistor can be a write transistor. A second transistor can be formed after the first transistor, serving as a read transistor. The first and second transistors can constitute a memory cell. During semiconductor structure operation, charge is stored in the gate capacitance of the second transistor; the location where the charge is stored is typically referred to as the storage node (SN). The 2TOC memory cell has its write operation controlled by the first transistor and its read operation controlled by the second transistor. Charge is stored using the gate capacitance of the transistors. Studies have shown that transistors fabricated using metal-oxide-semiconductor (MOS) transistors have a smaller cutoff current, allowing the charge stored in the gate capacitance to be retained for a longer period.

[0079] Continue to refer to Figures 16 to 17In some embodiments, the step of forming the second transistor includes: forming a second gate 310, a second oxide semiconductor layer 320, and a second source / drain 330. The second gate 310 is located on the surface of the first drain 232 away from the first oxide semiconductor layer 210, and the second gate 310 is electrically connected to the first drain 232. The second oxide semiconductor layer 320 is located at least on the side of the second gate 310 away from the first transistor, and the extension direction of the second oxide semiconductor layer 320 is parallel to the surface of the substrate 100. The second oxide semiconductor layer 320 includes a second channel region 3. 21 and second source / drain doped regions 322 located on opposite sides of the second channel region 321 along the extension direction of the second oxide semiconductor layer 320, the second channel region 321 being directly opposite the second gate 310, the second source / drain 330 being located on both sides of the second oxide semiconductor layer 320 along the extension direction of the second oxide semiconductor layer 320, and the second source / drain 330 being in contact with the second source / drain doped regions 322; wherein, the second gate 310, the second oxide semiconductor layer 320 and the second source / drain 330 constitute a second transistor, and the second transistor is a read transistor.

[0080] in, Figure 16 This is a cross-sectional view of the semiconductor structure in an embodiment where the connection region 222 of the first gate 220 is located on the side of the first oxide semiconductor layer 210 near the substrate 100. Figure 17 This is a cross-sectional view of a semiconductor structure in an embodiment where the connection region 222 of the first gate 220 is located on the side of the first oxide semiconductor layer 210 away from the substrate 100.

[0081] The following describes the specific steps of semiconductor structure formation using an embodiment where the connection region 222 of the first gate 220 is located on the side of the first oxide semiconductor layer 210 near the substrate 100 as an example.

[0082] refer to Figure 18 A substrate 100 is provided and a filling layer 110 is formed on the substrate 100.

[0083] refer to Figure 19 The fill layer 110 is patterned to form a trench located on the fill layer 110 and above the substrate 100.

[0084] refer to Figure 20 A first gate 220 is formed within a trench. The first gate 220 includes a gate region 221 opposite to each other in any direction parallel to the surface of the substrate 100 and a connection region 222 connecting the gate region 221. In some embodiments, the material of the connection region 222 of the first gate 220 may be the same as the material of the gate region 221. The gate region 221 and the connection region 222 thus formed can be formed in the same step, which helps to simplify the process steps and improve production efficiency.

[0085] refer to Figure 21 The filling layer 110 is filled such that it covers the surface of the first gate 220 away from the substrate 100, and the filling layer 110 has a trench.

[0086] refer to Figure 22 The first source 231 of the first transistor is formed in the trench of the filling layer 110.

[0087] refer to Figure 23 A first gate dielectric layer 240 is formed in the trench of the filling layer 110. The first gate dielectric layer 240 is located on the surface of the first source 231 away from the substrate 100 and covers both sides of the trench. The first gate dielectric layer 240 has a trench.

[0088] refer to Figure 24 A first oxide semiconductor layer 210 is formed in a trench in the first gate dielectric layer 240, and the portions of the first oxide semiconductor layer 210 located on opposite sides in a direction perpendicular to the surface of the substrate 100 are doped with source and drain to form a first source and drain doped region 212, and the remaining portion of the first oxide semiconductor layer 210 serves as a first channel region 211.

[0089] refer to Figure 25 A partial filling layer 110 is formed, and the filling layer 110 has a trench that exposes the top surface of the first oxide semiconductor layer 210 and the top surface of the first gate dielectric layer 240, and the width of the trench is greater than the width of the first source 231.

[0090] refer to Figure 26 A first drain 232 and a second gate 310 are formed. The first drain 232 is located on the top surface of the first oxide semiconductor layer 210 and the top surface of the first gate dielectric layer 240, and the second gate 310 is located on the top surface of the first drain 232. In some embodiments, the material of the first drain 232 and the material of the second gate 310 can be the same. Therefore, the first drain 232 and the second gate 310 can be formed in the same step, which can simplify the process steps.

[0091] refer to Figure 27 A second gate dielectric layer 340 and a second oxide semiconductor layer 320 are formed. A portion of the second oxide semiconductor layer 320 is doped to form a second source / drain doped region 322. The remaining second oxide semiconductor layer 320 serves as a second channel region 321. The second channel region 321 is directly opposite the second gate 310, and the second source / drain doped region 322 is located on both sides of the second channel region 321.

[0092] refer to Figure 28An initial second source and drain are formed, which fills the trench and covers the top surface of the second oxide semiconductor layer 320.

[0093] refer to Figure 29 The initial second source and drain are graphically patterned to form the second source and drain 330, and the remaining portion of the second gate dielectric layer 340 is formed to fill the trench.

[0094] The semiconductor structure manufacturing method provided in this disclosure includes: providing a substrate; forming a first gate, a first oxide semiconductor layer, and a first source / drain electrode. The first oxide semiconductor layer is located above the substrate, and its extension direction is perpendicular to the surface of the substrate. The first oxide semiconductor layer includes a first channel region and first source / drain doped regions located on opposite sides of the first channel region. In any direction parallel to the substrate surface, the first gate is located at least on opposite sides of the first oxide semiconductor layer. The first gates on opposite sides of the first oxide semiconductor layer are gate regions, which are at least directly opposite the first channel region. The first gate also includes a connection region for connecting the gate regions. The first source / drain electrode is located on opposite sides of the first oxide semiconductor layer and is electrically connected to the first source / drain doped regions. The first gate, the first oxide semiconductor layer, and the first source / drain electrode constitute a transistor. This allows for a reduction in the size of the semiconductor structure without shortening the channel length, improving semiconductor structure performance while reducing its size. Furthermore, having the first gate located at least on opposite sides of the channel region and the gate regions on both sides connected by connection regions allows the first gate to be formed in the same manufacturing step, simplifying the manufacturing process and improving the control capability of the first gate over the first transistor, thereby improving the performance of the first transistor and enhancing the performance of the semiconductor structure.

[0095] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Base; A first oxide semiconductor layer is located above the substrate, and the extension direction of the first oxide semiconductor layer is perpendicular to the surface of the substrate. The first oxide semiconductor layer includes a first channel region and first source / drain doped regions located on opposite sides of the first channel region along the extension direction of the first oxide semiconductor layer. The material of the first oxide semiconductor layer is IGZO indium gallium zinc oxide. The first gate, in any direction parallel to the surface of the substrate, is located at least on opposite sides of the first oxide semiconductor layer, and the first gate located on opposite sides of the first oxide semiconductor layer is a gate region, the gate region being at least directly opposite the first channel region. The first gate also includes a connection region, the connection region connecting the gate regions on both sides in a direction perpendicular to the surface of the substrate. The first source and drain, along the extension direction of the first oxide semiconductor layer, includes a first source and a first drain located on opposite sides of the first oxide semiconductor layer, and the first source and drain are in direct contact with the first source and drain doped region. The first oxide semiconductor layer, the first gate, and the first source / drain constitute the first transistor.

2. The semiconductor structure according to claim 1, characterized in that, The length of the region of the first oxide semiconductor layer that is directly opposite the first gate accounts for 60-90% of the total length of the first oxide semiconductor layer.

3. The semiconductor structure according to claim 1, characterized in that, In a direction parallel to the surface of the substrate, the first gate surrounds the first oxide semiconductor layer on three sides, or the first gate surrounds the first oxide semiconductor layer.

4. The semiconductor structure according to claim 1, characterized in that, In any direction parallel to the surface of the substrate, the first gate is located only on opposite sides of the first oxide semiconductor layer.

5. The semiconductor structure according to claim 4, characterized in that, The connection region is located on the side of the first oxide semiconductor layer closer to the substrate, and the first drain is located on the side of the first oxide semiconductor layer away from the substrate.

6. The semiconductor structure according to claim 4, characterized in that, The connection region is located on the side of the first oxide semiconductor layer away from the substrate, and the first drain is located on the side of the first oxide semiconductor layer closer to the substrate.

7. The semiconductor structure according to claim 1, characterized in that, The first transistor is a write transistor, and the semiconductor structure further includes: The second gate is located on the side surface of the first drain away from the first oxide semiconductor layer, and the second gate is electrically connected to the first drain. The second oxide semiconductor layer is located at least on the side of the second gate away from the first transistor, and the extension direction of the second oxide semiconductor layer is parallel to the surface of the substrate. The second oxide semiconductor layer includes a second channel region and second source / drain doped regions located on opposite sides of the second channel region along the extension direction of the second oxide semiconductor layer. The second channel region is directly opposite the second gate. The second source and drain are located on both sides of the second oxide semiconductor layer along the extension direction of the second oxide semiconductor layer, and the second source and drain are in contact with the second source and drain doped region. The second gate, the second oxide semiconductor layer, and the second source / drain constitute the second transistor, which is a read transistor.

8. The semiconductor structure according to claim 7, characterized in that, The second oxide semiconductor layer surrounds the second gate on three sides, and the second oxide semiconductor layer also covers at least a portion of the sides of the second gate.

9. A method for manufacturing a semiconductor structure, characterized in that, include: Provide a base; A first gate, a first oxide semiconductor layer, and first source / drain electrodes are formed. The first oxide semiconductor layer is located above the substrate, and its extension direction is perpendicular to the surface of the substrate. The first oxide semiconductor layer includes a first channel region and first source / drain doped regions located on opposite sides of the first channel region along the extension direction of the first oxide semiconductor layer. The material of the first oxide semiconductor layer is IGZO (indium gallium zinc oxide). In any direction parallel to the surface of the substrate, the first gate is located only on opposite sides of the first oxide semiconductor layer, and the first gates located on opposite sides of the first oxide semiconductor layer are discrete gate regions. The gate regions are at least directly opposite the first channel region. The first gate also includes a connection region that connects the gate regions on both sides in a direction perpendicular to the surface of the substrate. In the extension direction of the first oxide semiconductor layer, the first source / drain electrodes include first source electrodes and first drain electrodes located on opposite sides of the first oxide semiconductor layer, and the first source / drain electrodes are in direct contact with the first source / drain doped regions. The first gate, the first oxide semiconductor layer, and the first source and drain electrodes constitute the first transistor.

10. The manufacturing method according to claim 9, characterized in that, The first transistor is a write transistor; after forming the first gate, the first oxide semiconductor layer, and the first source / drain, or before forming the first gate, the first oxide semiconductor layer, and the first source / drain, the method further includes: A second gate, a second oxide semiconductor layer, and a second source / drain are formed. The second gate is located on the surface of the first drain away from the first oxide semiconductor layer and is electrically connected to the first drain. The second oxide semiconductor layer is located at least on the side of the second gate away from the first transistor, and the extension direction of the second oxide semiconductor layer is parallel to the surface of the substrate. The second oxide semiconductor layer includes a second channel region and second source / drain doped regions located on opposite sides of the second channel region along the extension direction of the second oxide semiconductor layer. The second channel region is directly opposite the second gate. The second source / drain is located on both sides of the second oxide semiconductor layer along the extension direction of the second oxide semiconductor layer and is in contact with the second source / drain doped regions. The second gate, the second oxide semiconductor layer, and the second source / drain constitute the second transistor, which is a read transistor.

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