High-speed delay phase-locked loop with wide frequency locking range and its locking method

Abstract

This invention discloses a high-speed delay-locked loop (DLL) with a wide frequency locking range and its locking method, belonging to the field of integrated circuit design. The high-speed DLL includes: an input buffer stage for inputting a reference clock; a voltage-controlled delay chain (VDC) for generating nine eight-phase differential clock signals; a logic level converter for generating nine eight-phase single-ended clock signals; a lockout detection module for generating a voltage adjustment signal based on a comparison between the total delay of the VDC and the period of the reference clock; and a phase detection module for adjusting the total delay of the VDC based on the voltage adjustment signal. After the phase detection module enters normal operating mode, it adjusts the control voltage value based on the comparison result of the phase difference between the reference clock and the feedback clock to adjust the total delay of the VDC until the reference clock and the feedback clock have the same frequency and phase synchronization, thus locking the DLL. The built-in lockout detection module avoids erroneous locking of the DLL at integer frequency multiples or divisions.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a high-speed delay phase-locked loop with a wide frequency locking range and its locking method. Background Technology

[0002] With the rapid development of CMOS integrated circuit chips, clock circuits have become a crucial component in both digital and analog integrated circuit design. This is especially true in the system-on-a-chip (SoC) design of transceivers in optical communication, where the performance of the clock circuit often determines the overall signal transmission quality. Transceiver chips based on PLLs (Phase Lock Loops) are typically designed using fully analog circuitry, which is complex, consumes a lot of power, and has poor reusability, requiring a separate clock circuit for each data channel. Transceiver chips based on DLLs (Delay Lock Loops), on the other hand, can be designed using digital circuitry, allowing multiple data paths to share a single clock circuit, significantly reducing power consumption.

[0003] Meanwhile, with the continuous improvement of communication standards, increasingly stringent requirements are being placed on clock frequencies. For example, in the latest optical communication standards, clock rates have reached 28G to 56G. To adapt to the rate requirements of different standards, the operating frequency range of DLLs also needs to be maximized. Furthermore, in some circuits, clock phase is also crucial. For instance, DLL-based PI (Phase Interpolator) clock data recovery circuits require strictly orthogonal clocks. DLLs can generate multi-phase clocks, thus having a wide range of applications. Summary of the Invention

[0004] This invention provides a high-speed delay-locked loop (DLL) with a wide locking frequency range. By incorporating a built-in error detection module, the working state of the phase detection module is controlled by comparing the total delay of the delay chain with the reference clock period, thus avoiding erroneous locking of the DLL at integer multiples or divisions and improving the locking range of the DLL.

[0005] A first aspect of the present invention provides a high-speed delay phase-locked loop with a wide frequency locking range, comprising: an input buffer stage, wherein the input port of the input buffer stage is connected to a reference clock;

[0006] A voltage-controlled delay chain, wherein the first input port of the voltage-controlled delay chain is connected to the output port of the input buffer stage, and is used to generate nine eight-phase differential clock signals;

[0007] A logic level converter, wherein the input port of the logic level converter is connected to the output port of the voltage-controlled delay chain, is used to generate nine eight-phase single-ended clock signals based on the nine eight-phase differential clock signals;

[0008] An error lock detection module, wherein the input port of the error lock detection module is connected to the output port of the logic level converter, is used to compare the total delay of the voltage-controlled delay chain with the reference clock period, and generate a voltage adjustment signal based on the comparison result;

[0009] A phase detection module is included, with its control input port connected to the output port of the fault lock detection module and its output port connected to the second input port of the voltage-controlled delay chain. This module adjusts the control voltage value output to the voltage-controlled delay chain based on the voltage adjustment signal, thereby adjusting the total delay of the voltage-controlled delay chain and enabling the phase detection module to enter normal operating mode. The clock input port of the phase detection module is connected to two in-phase clock signals output by the logic level converter, serving as a reference clock and a feedback clock. After the phase detection module enters normal operating mode, it compares the phase difference between the reference clock and the feedback clock, and adjusts the control voltage value based on the comparison result to adjust the total delay of the voltage-controlled delay chain until the reference clock and the feedback clock have the same frequency and synchronized phase, thus locking the delay-locked loop.

[0010] Optionally, in one embodiment of the present invention, the voltage-controlled delay chain includes multiple identical delay units connected in series.

[0011] Optionally, in one embodiment of the present invention, the fault detection module is further configured to output a first voltage adjustment signal when the total delay of the voltage-controlled delay chain is less than or equal to 2 / 3 times the reference clock period, output a second voltage adjustment signal when the total delay of the voltage-controlled delay chain is greater than or equal to 4 / 3 times the reference clock period, and output a third voltage adjustment signal when the total delay of the voltage-controlled delay chain is greater than 2 / 3 times the reference clock period and less than 4 / 3 times the reference clock period.

[0012] Optionally, in one embodiment of the present invention, the fault lock detection module includes a set of triggers and corresponding digital logic, and obtains multiple level output results through digital logic combination to correspond to the first voltage adjustment signal, the second voltage adjustment signal and the third voltage adjustment signal.

[0013] Optionally, in one embodiment of the present invention, a set of triggers in the fault detection module samples the 0° phase clock signal Q0 through a 90° phase clock signal Q2, a 180° phase clock signal Q4, and a 270° phase clock signal Q6 to obtain signals Q0_2, Q0_4, and Q0_6, respectively. The first voltage adjustment signal is obtained by ANDing Q0_2, Q0_4, and Q0_6. The second voltage adjustment signal is obtained by ANDing Q0_2 and Q0_4, then performing a NAND gate with the inverted signal of Q0_4, and finally performing a NAND gate with Q0_2. The third voltage adjustment signal is obtained by ANDing Q0_2 with the inverted signals of Q0_6.

[0014] Optionally, in one embodiment of the present invention, when the fault detection module outputs the first voltage adjustment signal, the phase detection module is further configured to reduce the control voltage value according to the first voltage adjustment signal, so as to increase the total delay of the delay signal chain;

[0015] When the fault detection module outputs the second voltage adjustment signal, the phase detection module is further configured to raise the control voltage value according to the second voltage adjustment signal, so as to reduce the total delay of the delay signal chain;

[0016] When the fault detection module outputs the third voltage adjustment signal, the phase detection module enters normal operation.

[0017] Optionally, in one embodiment of the present invention, the phase detection module is a half-rate structure, and before phase detection, the phase detection module performs frequency reduction by dividing the reference clock and the feedback clock by two respectively.

[0018] Optionally, in one embodiment of the present invention, the phase detection module includes a half-rate phase-frequency detector, a high-speed charge pump, and a control voltage conversion circuit, wherein the control input port of the half-rate phase-frequency detector is connected to the output port of the fault-locking detection module, the clock input port of the half-rate phase-frequency detector is connected to the output port of the logic level converter, the input port of the high-speed charge pump is connected to the output port of the half-rate phase-frequency detector, the input port of the control voltage conversion circuit is connected to the output port of the high-speed charge pump, and the output port of the control voltage conversion circuit is connected to the second input port of the voltage-controlled delay chain.

[0019] A second aspect of the present invention provides a locking method for a high-speed delay-locked loop (DLL) with a wide frequency locking range, used in the high-speed DLL with a wide frequency locking range described in the above embodiments. The method includes the following steps: comparing the total delay of a voltage-controlled delay chain (VCD) with a reference clock period, and generating a voltage adjustment signal based on the comparison result; adjusting the control voltage value output to the VCD according to the voltage adjustment signal to adjust the total delay of the VCD, so that the phase detection module enters a normal operating state; comparing the phase difference between the reference clock and the feedback clock in the phase detection module, and adjusting the control voltage value based on the comparison result to adjust the total delay of the VCD, until the reference clock and the feedback clock have the same frequency and are phase-synchronized, thereby locking the DLL.

[0020] Optionally, in one embodiment of the present invention, comparing the total delay of the voltage-controlled delay chain with the reference clock period and generating the voltage adjustment signal based on the comparison result includes: generating a first voltage adjustment signal when the total delay of the voltage-controlled delay chain is less than or equal to 2 / 3 times the reference clock period; generating a second voltage adjustment signal when the total delay of the voltage-controlled delay chain is greater than or equal to 4 / 3 times the reference clock period; and generating a third voltage adjustment signal when the total delay of the voltage-controlled delay chain is greater than 2 / 3 times the reference clock period and less than 4 / 3 times the reference clock period.

[0021] This invention discloses a high-speed delay-locked loop (DLL) with a wide frequency locking range and its locking method. The DLL incorporates a built-in error-locking detection module. Based on a comparison between the total delay of the voltage-controlled delay chain (VDC) and the reference clock period, a voltage adjustment signal is generated. A phase detection module adjusts the control voltage value output to the VDC based on this voltage adjustment signal, thereby adjusting the total delay of the VDC and enabling the phase detection module to enter normal operating mode. The phase detection module sets a reference clock and a feedback clock. After entering normal operating mode, it compares the phase difference between the reference clock and the feedback clock, adjusting the control voltage value based on the comparison result to adjust the total delay of the VDC until the reference clock and the feedback clock have the same frequency and are phase-synchronized, thus locking the DLL. Therefore, by comparing the total delay of the delay chain with the reference clock period through the built-in error-locking detection module, the operating state of the phase detection module is controlled, avoiding potential error-locking of the DLL at integer multiples or divisions of the frequency, and significantly expanding the frequency locking range of the DLL.

[0022] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0023] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0024] Figure 1 A schematic diagram of a high-speed delay phase-locked loop structure with a wide frequency locking range provided according to an embodiment of the present invention;

[0025] Figure 2 This is a schematic diagram of a high-speed delay phase-locked loop structure with a wide frequency locking range according to an embodiment of the present invention;

[0026] Figure 3 This is a schematic diagram of the structure of a mislock detection module according to an embodiment of the present invention;

[0027] Figure 4 This is a schematic diagram of a half-rate frequency and phase detection module according to an embodiment of the present invention;

[0028] Figure 5 This is a flowchart illustrating a locking method for a high-speed delay phase-locked loop with a wide frequency locking range, according to an embodiment of the present invention. Detailed Implementation

[0029] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0030] The following description, with reference to the accompanying drawings, describes a high-speed delay-locked loop (DLL) with a wide locking frequency range and its locking method according to embodiments of the present invention. Addressing the issues mentioned in the background section regarding the difficulty in designing clock circuits for all-analog circuits, their high power consumption, poor reusability, and the need for a separate clock circuit for each data channel, while digital circuit designs can share a single clock circuit for multiple data paths with significantly reduced power consumption, the present invention provides a high-speed DLL with a wide locking frequency range. By comparing the total delay of the delay chain with the reference clock period through a built-in error detection module, the operating state of the phase detection module is controlled, avoiding potential erroneous locking of the DLL at integer multiples or divisions of the frequency, and significantly expanding the locking frequency range of the DLL.

[0031] Specifically, Figure 1 This is a schematic diagram of a high-speed delay phase-locked loop structure with a wide frequency locking range according to an embodiment of the present invention.

[0032] like Figure 1As shown, the high-speed delay phase-locked loop with a wide frequency locking range includes: an input buffer stage 100, a voltage-controlled delay chain 200, a logic level converter 300, an error locking detection module 400, and a phase detection module 500.

[0033] Input buffer stage 100, the input port of the input buffer stage is connected to the reference clock.

[0034] The voltage-controlled delay chain 200 has its first input port connected to the output port of the input buffer stage, used to generate nine eight-phase differential clock signals N<8:0> and P<8:0>, such as... Figure 2 As shown, the extra path is a 2π delay for a certain phase.

[0035] The logic level converter 300 connects its input port to the output port of the voltage-controlled delay chain to generate nine eight-phase single-ended clock signals Q<8:0> based on nine eight-phase differential clock signals.

[0036] The error lock detection module 400 has its input port connected to the output port Q<8:0> of the logic level converter. It is used to compare the total delay of the voltage-controlled delay chain with the reference clock period and generate a voltage adjustment signal based on the comparison result.

[0037] The phase detection module 500 has its control input port connected to the output port of the fault lock detection module, and its output port connected to the second input port of the voltage-controlled delay chain. It is used to adjust the control voltage value output to the voltage-controlled delay chain according to the voltage adjustment signal, thereby adjusting the total delay of the voltage-controlled delay chain and enabling the phase detection module to enter normal operating condition. The clock input port of the phase detection module is connected to two in-phase clock signals Q output from the logic level converter. <0> With Q <8> As the reference clock and feedback clock, the phase of the feedback clock lags behind the internal reference clock by 2π. After the phase detection module enters normal working state, the phase difference between the reference clock and the feedback clock is compared. Based on the comparison result, the control voltage value is adjusted to adjust the total delay of the voltage-controlled delay chain until the frequency of the reference clock and the phase of the feedback clock are the same and the phase is synchronized, and the delay phase-locked loop is locked.

[0038] The phase detection module compares the phases of the reference clock and the feedback clock. When the feedback clock phase leads the reference clock phase, the total delay of the voltage-controlled delay chain will increase, and when the feedback clock phase lags the reference clock phase, the total delay of the voltage-controlled delay chain will decrease.

[0039] After the delay signal chain is properly locked, a total of 9 eight-phase clock signals with a phase interval of 45° will be generated.

[0040] In one embodiment of the present invention, the voltage-controlled delay chain 200 is composed of identical delay units connected in series, and its delay time can be controlled by the control voltage value output by the phase detection module 500.

[0041] Combination Figure 2 As shown, the output port of the lock detection module 400 can output three lock detection states, which correspond to the total delay of the pressure-controlled delay chain being much lower, much higher, and near the reference clock period, respectively.

[0042] Furthermore, the fault detection module 400 is further configured to output a first voltage adjustment signal when the total delay of the voltage-controlled delay chain is less than or equal to 2 / 3 times the reference clock period, output a second voltage adjustment signal when the total delay of the voltage-controlled delay chain is greater than or equal to 4 / 3 times the reference clock period, and output a third voltage adjustment signal when the total delay of the voltage-controlled delay chain is greater than 2 / 3 times the reference clock period and less than 4 / 3 times the reference clock period.

[0043] In order to achieve different lock detection state signal outputs and obtain different voltage adjustment signals, the lock failure detection module 400 includes a set of triggers and corresponding digital logic. Through the combination of digital logic, multiple level output results are obtained to correspond to the first voltage adjustment signal, the second voltage adjustment signal and the third voltage adjustment signal.

[0044] like Figure 2 and Figure 3 As shown, the fault lock detection module 400 consists of a set of flip-flops and corresponding digital logic. Its input port is connected to the 8-phase clock signal output by the logic level converter, and its output port outputs three fault lock detection results, corresponding to fault lock state I (LOWER, the total delay of the voltage-controlled delay chain is less than 2 / 3 times the reference clock period), fault lock state II (UPPER, the total delay of the voltage-controlled delay chain is more than 4 / 3 times the reference clock period), and correct lock state (LOCK_PRE, the total delay of the voltage-controlled delay chain is close to the reference clock period, allowing the loop to complete the lock).

[0045] like Figure 3 As shown, in the fault lock detection module 400, a set of triggers samples the 0° phase clock signal Q0 through the 90° phase clock signal Q2, the 180° phase clock signal Q4, and the 270° phase clock signal Q6 to obtain signals Q0_2, Q0_4, and Q0_6 respectively. The LOWER signal is obtained by ANDing Q0_2, Q0_4, and Q0_6. The UPPER signal is obtained by ANDing Q0_2 and Q0_4, then performing a NAND gate with the inverted signal of Q0_4, and finally performing a NAND gate with Q0_2. The LOCK_PRE signal is obtained by ANDing Q0_2 with the inverted signal of Q0_6.

[0046] like Figure 2 As shown, the phase detection module of this embodiment includes a half-rate phase-frequency detector (PFD), a high-speed charge pump (CP), and a control voltage conversion circuit. The control input port of the half-rate phase-frequency detector is connected to the output port of the fault-locking detection module, the clock input port of the half-rate phase-frequency detector is connected to the output port of the logic level converter, the input port of the high-speed charge pump is connected to the output port of the half-rate phase-frequency detector, the input port of the control voltage conversion circuit is connected to the output port of the high-speed charge pump, and the output port of the control voltage conversion circuit is connected to the second input port of the voltage-controlled delay chain.

[0047] The input port of the control voltage conversion circuit is connected to the output voltage port V of the high-speed charge pump. c Further synchronously generate a pair of differential control voltages to control V cp With V cn V cp With V cn Directly connected to the voltage-controlled delay chain. Specifically, when V c When increased, the voltage control signal V cp Synchronous increase, V cn Synchronous reduction increases the delay of the voltage-controlled delay chain when V c When the voltage decreases, the voltage control signal V cp Synchronous decrease, V cn As the voltage increases synchronously, the delay of the pressure-controlled delay chain decreases.

[0048] like Figure 4 As shown, the half-rate phase-frequency detector in the phase detection module 500 consists of frequency division logic and a PFD with control bits. In the frequency division logic, the two clock input ports (reference clock Q0 and feedback clock Q8) of the half-rate phase-frequency detector and one of the control input ports LOCK_PRE undergo the logic operation shown in the diagram to obtain three signals after retiming: half-rate reference clock QL0, half-rate feedback clock QL8, and control signal LOCK. The two clock input ports of the PFD with control bits are respectively connected to the two clock output ports of the frequency division logic; one of the three control input ports is connected to the LOCK signal of the frequency division logic, and the other two control input ports UPPER and LOWER are directly connected to the corresponding output ports of the fault-lock detection module. The two output ports UP and DN of the phase detection module are used to connect to the CP module. The CP is further charged according to the UP signal, causing V c Increase; based on the DN signal, make V c reduce.

[0049] In an embodiment of the present invention, when the lockout detection module outputs a first voltage adjustment signal, the phase detection module is further configured to reduce the control voltage value according to the first voltage adjustment signal, so as to increase the total delay of the delay signal chain; specifically, DN is forcibly set high, UP is set low, and CP is then reduced by discharging to decrease the control voltage value. When the lockout detection module outputs a second voltage adjustment signal, the phase detection module is further configured to raise the control voltage value according to the second voltage adjustment signal, so as to decrease the total delay of the delay signal chain; specifically, DN is forcibly set low, UP is set high, and CP is then raised by charging to increase the control voltage value. When the lockout detection module outputs a third voltage adjustment signal, the phase detection module enters a normal operating state; specifically, according to the third voltage adjustment signal, the PFD is allowed to enter a normal frequency and phase discrimination operating state, and the UP and DN signals will be determined according to the phase relationship between QL0 and QL8.

[0050] Combination Figure 2 As shown, when the total delay of the voltage-controlled delay chain is less than 2 / 3 of the reference clock period, the output signal LOWER of the fault lock detection module is in a high-level active state, and the phase detection module forcibly reduces the control voltage V. c By controlling the voltage conversion circuit, V cn Decrease, V cp As the delay increases, the total delay of the delay signal chain will increase rapidly. When the total delay of the voltage-controlled delay chain exceeds 4 / 3 times the reference clock cycle, the output signal UPPER of the fault lock detection module is active high, and the phase detection module forcibly raises the control voltage V. c By controlling the voltage conversion circuit, V cn Increase, V cp As the delay is reduced, the total delay of the delay signal chain will decrease rapidly. When the total delay of the voltage-controlled delay chain is higher than 2 / 3 times the reference clock period but lower than 4 / 3 times the reference clock period, the output signal LOCK_PRE of the fault lock detection module will be active high, and the phase detection module will enter the normal frequency and phase discrimination operation state.

[0051] In one embodiment of the present invention, the phase detection module is a half-rate structure, and before phase detection, the phase detection module performs frequency reduction by dividing the reference clock and the feedback clock by two respectively.

[0052] It is understood that the phase detection module in the embodiments of the present invention can adopt a half-rate structure, which divides the reference clock and the feedback clock by two to reduce their speed before performing phase detection, thereby doubling the upper limit of the DLL's operating frequency, improving the operating speed of the delay phase-locked loop, and widening the locking range of the delay phase-locked loop.

[0053] The high-speed delay-locked loop (DLL) with a wide frequency locking range proposed in this embodiment incorporates a lockout detection module. This module generates a voltage adjustment signal based on a comparison between the total delay of the voltage-controlled delay chain (VDC-LDL) and the reference clock period. A phase detection module adjusts the control voltage value output to the VDC-LDL according to this voltage adjustment signal, thereby adjusting the total delay of the VDC-LDL and enabling the phase detection module to enter normal operating mode. The phase detection module sets a reference clock and a feedback clock. After entering normal operating mode, it compares the phase difference between the reference clock and the feedback clock, adjusting the control voltage value based on the comparison result to adjust the total delay of the VDC-LDL until the reference clock and the feedback clock have the same frequency and synchronized phase, locking the DLL. Therefore, by comparing the total delay of the delay chain with the reference clock period through the built-in lockout detection module, the operating state of the phase detection module is controlled, avoiding potential lockout errors that may occur in the DLL at integer multiples or divisions of the frequency, and significantly expanding the frequency locking range of the DLL.

[0054] Next, referring to the accompanying drawings, a locking method for a high-speed delay phase-locked loop with a wide frequency locking range according to an embodiment of the present invention is described.

[0055] Figure 5 This is a flowchart illustrating a locking method for a high-speed delay phase-locked loop with a wide frequency locking range, according to an embodiment of the present invention.

[0056] like Figure 5 As shown, the locking method for a high-speed delay phase-locked loop with a wide frequency locking range is used in the high-speed delay phase-locked loop with a wide frequency locking range described in the above embodiment. The method includes the following steps:

[0057] In step S101, the total delay of the voltage-controlled delay chain and the reference clock period are compared, and a voltage regulation signal is generated based on the comparison result.

[0058] Optionally, in one embodiment of the present invention, comparing the total delay of the voltage-controlled delay chain with the reference clock period and generating a voltage adjustment signal based on the comparison result includes: generating a first voltage adjustment signal when the total delay of the voltage-controlled delay chain is less than or equal to 2 / 3 times the reference clock period; generating a second voltage adjustment signal when the total delay of the voltage-controlled delay chain is greater than or equal to 4 / 3 times the reference clock period; and generating a third voltage adjustment signal when the total delay of the voltage-controlled delay chain is greater than 2 / 3 times the reference clock period and less than 4 / 3 times the reference clock period.

[0059] In step S102, the control voltage value output to the voltage-controlled delay chain is adjusted according to the voltage adjustment signal to adjust the total delay of the voltage-controlled delay chain, so that the phase detection module enters the normal working state.

[0060] Optionally, in one embodiment of the present invention, adjusting the control voltage value output to the voltage-controlled delay chain according to the voltage adjustment signal includes: decreasing the control voltage value according to the first voltage adjustment signal to increase the total delay of the delay signal chain; increasing the control voltage value according to the second voltage adjustment signal to decrease the total delay of the delay signal chain; and controlling the phase detection module to enter a normal working state according to the third voltage adjustment signal.

[0061] In step S103, the phase difference between the reference clock and the feedback clock in the phase detection module is compared, and the control voltage value is adjusted according to the comparison result to adjust the total delay of the voltage-controlled delay chain until the reference clock and the feedback clock have the same frequency and phase synchronization, and the delay phase-locked loop is locked.

[0062] It should be noted that the foregoing explanation of the high-speed delay phase-locked loop embodiment with a wide frequency locking range also applies to the locking method of the high-speed delay phase-locked loop with a wide frequency locking range in this embodiment, and will not be repeated here.

[0063] The locking method for a high-speed delay-locked loop (DLL) with a wide locking frequency range proposed in this invention involves generating a voltage adjustment signal based on a comparison between the total delay of the voltage-controlled delay chain (VDCLD) and the reference clock period. The control voltage value output to the VDCLD is adjusted according to the voltage adjustment signal to adjust the total delay of the VDCLD, allowing the phase detection module to enter normal operation. The phase difference between the reference clock and the feedback clock within the phase detection module is compared, and the control voltage value is adjusted according to the comparison result to further adjust the total delay of the VDCLD until the reference clock and the feedback clock have the same frequency and are phase-synchronized, thus locking the DLL. This method avoids potential erroneous locking of the DLL at integer multiples or divisions of the frequency, significantly expands the locking frequency range of the DLL, improves the operating speed of the DLL, and broadens the locking range of the DLL.

[0064] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0065] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "N" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0066] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more N executable instructions for implementing custom logic functions or processes, and the scope of preferred embodiments of the invention includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as should be understood by those skilled in the art to which embodiments of the invention pertain.

Claims

1. A high-speed delay phase-locked loop with a wide frequency locking range, characterized in that, include: An input buffer stage, wherein the input port of the input buffer stage is connected to a reference clock; A voltage-controlled delay chain, wherein the first input port of the voltage-controlled delay chain is connected to the output port of the input buffer stage, and is used to generate nine eight-phase differential clock signals; A logic level converter, wherein the input port of the logic level converter is connected to the output port of the voltage-controlled delay chain, is used to generate nine eight-phase single-ended clock signals based on the nine eight-phase differential clock signals; An error lock detection module, wherein the input port of the error lock detection module is connected to the output port of the logic level converter, is used to compare the total delay of the voltage-controlled delay chain with the reference clock period, and generate a voltage adjustment signal based on the comparison result; A phase detection module is included, with its control input port connected to the output port of the fault lock detection module and its output port connected to the second input port of the voltage-controlled delay chain. This module adjusts the control voltage value output to the voltage-controlled delay chain based on the voltage adjustment signal, thereby adjusting the total delay of the voltage-controlled delay chain and enabling the phase detection module to enter normal operating mode. The clock input port of the phase detection module is connected to two in-phase clock signals output by the logic level converter, serving as a reference clock and a feedback clock. After the phase detection module enters normal operating mode, it compares the phase difference between the reference clock and the feedback clock, and adjusts the control voltage value based on the comparison result to adjust the total delay of the voltage-controlled delay chain until the reference clock and the feedback clock have the same frequency and synchronized phase, thus locking the delay-locked loop.

2. The high-speed delay phase-locked loop according to claim 1, characterized in that, The pressure-controlled delay chain includes multiple identical delay units, which are connected in series.

3. The high-speed delay phase-locked loop according to claim 1, characterized in that, The fault detection module is further configured to output a first voltage adjustment signal when the total delay of the voltage-controlled delay chain is less than or equal to 2 / 3 times the reference clock period, output a second voltage adjustment signal when the total delay of the voltage-controlled delay chain is greater than or equal to 4 / 3 times the reference clock period, and output a third voltage adjustment signal when the total delay of the voltage-controlled delay chain is greater than 2 / 3 times the reference clock period and less than 4 / 3 times the reference clock period.

4. The high-speed delay phase-locked loop according to claim 3, characterized in that, The fault lock detection module includes a set of triggers and corresponding digital logic. Multiple level output results are obtained through digital logic combination to correspond to the first voltage adjustment signal, the second voltage adjustment signal and the third voltage adjustment signal.

5. The high-speed delay phase-locked loop according to claim 4, characterized in that, The fault detection module contains a set of triggers that sample the 0° phase clock signal Q0 using a 90° phase clock signal Q2, a 180° phase clock signal Q4, and a 270° phase clock signal Q6 to obtain signals Q0_2, Q0_4, and Q0_6, respectively. The first voltage adjustment signal is obtained by ANDing Q0_2, Q0_4, and Q0_6. The second voltage adjustment signal is obtained by ANDing Q0_2 and Q0_4, then performing a NAND gate with the inverted signal of Q0_4, and finally performing a NAND gate with Q0_2. The third voltage adjustment signal is obtained by ANDing Q0_2 with the inverted signals of Q0_6.

6. The high-speed delay phase-locked loop according to claim 3, characterized in that, When the fault detection module outputs the first voltage adjustment signal, the phase detection module is further used to reduce the control voltage value according to the first voltage adjustment signal, so as to increase the total delay of the voltage-controlled delay chain; When the fault detection module outputs the second voltage adjustment signal, the phase detection module is further configured to raise the control voltage value according to the second voltage adjustment signal, so as to reduce the total delay of the voltage-controlled delay chain; When the fault detection module outputs the third voltage adjustment signal, the phase detection module enters normal operation.

7. The high-speed delay phase-locked loop according to claim 1, characterized in that, The phase detection module is a half-rate structure. Before phase detection, the phase detection module divides the reference clock and the feedback clock by two to reduce their speed.

8. The high-speed delay phase-locked loop according to claim 1 or 7, characterized in that, The phase detection module includes a half-rate phase-frequency detector, a high-speed charge pump, and a control voltage conversion circuit. The control input port of the half-rate phase-frequency detector is connected to the output port of the fault-locking detection module. The clock input port of the half-rate phase-frequency detector is connected to the output port of the logic level converter. The input port of the high-speed charge pump is connected to the output port of the half-rate phase-frequency detector. The input port of the control voltage conversion circuit is connected to the output port of the high-speed charge pump. The output port of the control voltage conversion circuit is connected to the second input port of the voltage-controlled delay chain.

9. A locking method for a high-speed delay phase-locked loop with a wide frequency locking range, used in the high-speed delay phase-locked loop with a wide frequency locking range as described in any one of claims 1-8, characterized in that, Includes the following steps: The total delay of the voltage-controlled delay chain is compared with the reference clock period, and a voltage regulation signal is generated based on the comparison result. The control voltage value output to the voltage-controlled delay chain is adjusted according to the voltage adjustment signal to adjust the total delay of the voltage-controlled delay chain, so that the phase detection module enters the normal working state; The phase difference between the reference clock and the feedback clock in the phase detection module is compared, and the control voltage value is adjusted according to the comparison result to adjust the total delay of the voltage-controlled delay chain until the frequency of the reference clock and the feedback clock are the same and the phase is synchronized, and the delay phase-locked loop is locked.

10. The method according to claim 9, characterized in that, The total delay of the voltage-controlled delay chain is compared with the reference clock period, and the voltage regulation signal is generated based on the comparison result, including: When the total delay of the voltage-controlled delay chain is less than or equal to 2 / 3 of the reference clock period, a first voltage regulation signal is generated; When the total delay of the voltage-controlled delay chain is greater than or equal to 4 / 3 times the reference clock period, a second voltage regulation signal is generated; A third voltage regulation signal is generated when the total delay of the voltage-controlled delay chain is greater than 2 / 3 times the reference clock period and less than 4 / 3 times the reference clock period.

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