True random number generator circuit structure of single ring oscillator

Abstract

The application discloses a kind of single ring oscillator true random number generator circuit structure, the circuit structure includes ring oscillator, fast oscillation circuit, counter, eigen transistor, exclusive or gate, reset signal generating circuit and post-processing circuit.The circuit structure of above-mentioned, the two different inverter stages of ring oscillator are XOR and the width of rectangular pulse generated by output is determined by the change caused by time-invariant inherent propagation delay and time-varying jitter noise, the width of the continuous pulse generated is quantified by fast oscillation circuit and counter, that is, the delay change caused by jitter noise can be represented from the minimum significant bit of the above-mentioned counter;By changing the gate voltage of eigen transistor, the supply voltage of ring oscillator is adjusted, so that the amplitude of the jitter noise of ring oscillator is maximized by reducing its charging / discharging current, so that the true random number generator circuit structure has the application effect of high energy efficiency and high throughput.

Description

Technical Field

[0001] This invention relates to the technical field of circuits, and more particularly to a true random number generator circuit structure with a single-ring oscillator. Background Technology

[0002] Random number generators have become a fundamental component of secure communication and information systems, playing a crucial role in a wide range of cryptographic applications, including authentication protocols, data encryption, and random padding. Furthermore, numerical simulations and randomized experiments in software also require large quantities of high-quality random numbers. However, pseudo-random number generators (PRNGs) rely on deterministic mathematical models and initial states (also known as seeds), making them vulnerable to attack. In contrast, true random number generators (TRNGs) extract randomness from non-deterministic physical processes, such as the electrical noise prevalent in solid-state circuits, which is theoretically unpredictable. Highly random raw bitstreams can be generated by collecting entropy sources based on electronic noise using dedicated chip circuitry. These bitstreams are typically fed into subsequent post-processing modules to further optimize their randomness.

[0003] Various types of true random number generators have been disclosed in existing technologies. One such generator directly amplifies device voltage fluctuations caused by thermal noise and compares them with a given threshold voltage to obtain random output bits. While thermal noise is an ideal entropy source with a uniform power spectrum, the necessary amplifiers and comparators with ultra-wide bandwidths make it difficult to utilize in low-power and small-area solutions. Chaotic mapping-based TRNGs can generate highly stable random bits, but analog-to-digital converters complicate the entire structure, and the output throughput is limited to 0.27 Mbps. Another disclosed true random number generator is based on metastable TRNG designs, such as those using SRAM cells and cross-coupled circuits, which can achieve ultra-high throughput of up to 3 Gbps. However, to minimize the impact of process, voltage, and temperature (PVT) variations, metastable TRNG designs often require a complex calibration circuit, leading to a significant increase in area and power. Therefore, existing true random number generators suffer from the problem of not being able to balance throughput and circuit power consumption. Summary of the Invention

[0004] This invention provides a true random number generator circuit structure with a single-ring oscillator, aiming to solve the problem that existing true random number generators cannot simultaneously achieve high throughput and low power consumption.

[0005] This invention discloses a true random number generator circuit structure using a single-ring oscillator. The circuit structure includes a ring oscillator, a fast oscillation circuit, a counter, an intrinsic transistor, an XOR gate, a reset signal generation circuit, and a post-processing circuit. The ring oscillator includes cascaded NAND gates and multiple inverters. A level signal is input to the first input terminal of each NAND gate, and the second input terminal of each NAND gate is connected to the output terminal of an inverter at the end of the ring oscillator. The input terminal of the first inverter of the ring oscillator is connected to the output terminal of the NAND gate, and the output terminal of the preceding inverter is connected to the input terminal of the following inverter. The control output terminal of the intrinsic transistor is connected to the control terminals of each inverter and the control terminals of the NAND gates. The source of the intrinsic transistor serves as the control output terminal, the gate is connected to the bias voltage terminal, and the drain is connected to the power supply voltage terminal. The output terminals of one inverter in the middle section and the output terminal of the last inverter in the ring oscillator are respectively connected to one input terminal of the XOR gate. The output terminal of the XOR gate is connected to the input terminal of the fast oscillation circuit, the input terminal of the reset signal generation circuit, and the first processing input terminal of the post-processing circuit. The output terminal of the fast oscillation circuit is connected to the first counting input terminal of the counter, the reset signal output terminal of the reset signal generation circuit is connected to the second counting input terminal of the counter, the output terminal of the counter is connected to the second processing input terminal of the post-processing circuit, and the output terminal of the post-processing circuit is used to output a true random number sequence.

[0006] The true random number generator circuit structure of the single ring oscillator, wherein the ring oscillator contains 2N+1 inverters, where N is a positive integer greater than 2.

[0007] The true random number generator circuit structure of the single ring oscillator, wherein the inverter connected to the input terminal of the XOR gate is the Nth inverter and the 2N+1th inverter in the ring oscillator.

[0008] The true random number generator circuit structure of the single ring oscillator, wherein the inverter in the ring oscillator includes a first MOS transistor and a second MOS transistor;

[0009] The gate of the first MOS transistor is connected to the gate of the second MOS transistor, and the connection point serves as the input terminal of the inverter; the source of the first MOS transistor serves as the control terminal of the inverter and is connected to the control output terminal of the intrinsic transistor; the drain of the first MOS transistor is connected to the drain of the second MOS transistor, and the connection point serves as the output terminal of the inverter; the source of the second MOS transistor is grounded.

[0010] The true random number generator circuit structure of the single-ring oscillator, wherein the intrinsic transistor is an NMOS transistor.

[0011] The true random number generator circuit structure of the single ring oscillator, wherein the fast oscillation circuit includes an oscillation NAND gate, a first oscillation inverter and a second oscillation inverter cascaded in sequence;

[0012] One input terminal of the oscillation NAND gate is connected to the output terminal of the XOR gate as the input terminal of the fast oscillation circuit, and the other input terminal is connected to the output terminal of the second oscillation inverter and is also connected to the first counting input terminal of the counter as the output terminal of the fast oscillation circuit; the input terminal of the first oscillation inverter is connected to the output terminal of the oscillation NAND gate, and the input terminal of the second oscillation inverter is connected to the output terminal of the first oscillation inverter.

[0013] The true random number generator circuit structure of the single-ring oscillator includes a counter comprising three cascaded counting circuits; each counting circuit includes a counting output terminal.

[0014] The true random number generator circuit structure of the single ring oscillator, wherein each of the counting circuits includes a first counting MOS transistor, a second counting MOS transistor, a third counting MOS transistor, a fourth counting MOS transistor, a fifth counting MOS transistor, a sixth counting MOS transistor, a seventh counting MOS transistor, an eighth counting MOS transistor, a ninth counting MOS transistor, a tenth counting MOS transistor, and an eleventh counting MOS transistor;

[0015] The sources of the first, second, fourth, seventh, eighth, and tenth counting MOSFETs are all connected to a regulated power supply; the sources of the third, fifth, sixth, ninth, and eleventh counting MOSFETs are all grounded; the gates of the third, fifth, and seventh counting MOSFETs are connected and serve as clock signal input terminals to receive clock signals; the gates of the second, sixth, and eighth counting MOSFETs are connected and serve as reset signal input terminals to obtain reset signals from the reset signal generation circuit.

[0016] The gate of the first counting MOS transistor is connected to the second ring terminal as the first ring terminal, and the drain of the first counting MOS transistor is connected to the drain of the second counting MOS transistor, the drain of the third counting MOS transistor, and the gate of the fourth counting MOS transistor; the drain of the fourth counting MOS transistor is connected to the drain of the fifth counting MOS transistor, the drain of the sixth counting MOS transistor, and the gate of the ninth counting MOS transistor.

[0017] The drain of the seventh counting MOS transistor is connected to the drain of the ninth counting MOS transistor, the drain of the eighth counting MOS transistor, the gate of the tenth counting MOS transistor, and the gate of the eleventh counting MOS transistor, and the connection point serves as the second loop terminal; the drain of the tenth counting MOS transistor is connected to the drain of the eleventh counting MOS transistor, and the connection point serves as the counting output terminal.

[0018] The true random number generator circuit structure of the single ring oscillator, wherein the reset signal generation circuit includes a first delay unit, a second delay unit and a reset NAND gate, and the first delay unit is in-phase output and the second delay unit is out-of-phase output;

[0019] The input terminals of the first delay unit and the second delay unit are both connected to the output terminal of the XOR gate; the output terminals of the first delay unit and the second delay unit are respectively connected to one input terminal of the reset NAND gate, and the output terminal of the reset NAND gate serves as the reset signal output terminal of the reset signal generation circuit.

[0020] The true random number generator circuit structure of the single ring oscillator, wherein the post-processing circuit is a 5-stage XOR chain circuit, and each stage of the post-processing circuit consists of two post-processing D flip-flops and one post-processing XOR gate.

[0021] This application discloses a true random number generator circuit structure with a single-ring oscillator. The circuit structure includes a ring oscillator, a fast oscillation circuit, a counter, an intrinsic transistor, an XOR gate, a reset signal generation circuit, and a post-processing circuit. In the above circuit structure, the two different inverter stages of the ring oscillator are XORed to generate rectangular pulses. The width of these pulses is determined by the time-invariant inherent propagation delay and the variation caused by time-varying jitter noise. By quantizing the width of the generated continuous pulses through the fast oscillation circuit and the counter, the delay variation caused by jitter noise can be characterized from the least significant bit of the counter. By changing the gate voltage of the intrinsic transistor, the supply voltage of the ring oscillator is adjusted, so that the amplitude of the ring oscillator's jitter noise is maximized by reducing its charging / discharging current. This gives the true random number generator circuit structure high energy efficiency and high throughput. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 A circuit diagram of a true random number generator circuit structure for a single-ring oscillator provided in an embodiment of the present invention;

[0024] Figure 2 A partial circuit diagram of the true random number generator circuit structure of a single-ring oscillator provided in an embodiment of the present invention;

[0025] Figure 3 Another partial circuit diagram of the true random number generator circuit structure of the single ring oscillator provided in the embodiment of the present invention;

[0026] Figure 4 Another partial circuit diagram of the true random number generator circuit structure of the single-ring oscillator provided in the embodiment of the present invention;

[0027] Figure 5 Another partial circuit diagram of the true random number generator circuit structure of the single-ring oscillator provided in the embodiment of the present invention;

[0028] Figure 6 The following is a partial circuit diagram of the true random number generator circuit structure of the single-ring oscillator provided in the embodiment of the present invention.

[0029] Figure 7 A waveform diagram of the true random number generator circuit structure of a single-ring oscillator provided in an embodiment of the present invention;

[0030] Figure 8 A schematic diagram illustrating the effect of the true random number generator circuit structure of the single-ring oscillator provided in the embodiment of the present invention;

[0031] Figure 9 Another schematic diagram illustrating the effect of the true random number generator circuit structure of the single-ring oscillator provided in the embodiment of the present invention;

[0032] Figure 10 Another schematic diagram illustrating the effect of the true random number generator circuit structure of the single-ring oscillator provided in the embodiment of the present invention;

[0033] Figure 11 This is another schematic diagram illustrating the effect of the true random number generator circuit structure of the single-ring oscillator provided in the embodiment of the present invention.

[0034] Reference numerals: RO, Ring Oscillator; FO, Fast Oscillator Circuit; 3-Bit CNT, Counter; M0, Intrinsic Transistor; G, XOR Gate; RPG, Reset Signal Generator Circuit; PPU, Post-Processing Circuit; H, NAND Gate; S1, Inverter; M1, First MOSFET; M2, Second MOSFET; HZ, Oscillator NAND Gate; S2, First Oscillator Inverter; S3, Second Oscillator Inverter; P, Counting Circuit; M3, First Counting MOSFET; M4, Second Counting MOSFET; M5, Third Counting MOSFET; M6, Fourth Counting MOSFET; M7, Fifth Counting MOSFET; M8, Sixth Counting MOSFET; M9, Seventh Counting MOSFET; M10, Eighth Counting MOSFET; M11, Ninth Counting MOSFET; M12, Tenth Counting MOSFET; M13, Eleventh Counting MOSFET; DU1, First Delay Unit; DU2, Second Delay Unit; HF, Reset NAND Gate. Detailed Implementation

[0035] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0036] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0037] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0038] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0039] This invention discloses a true random number generator circuit structure using a single-ring oscillator, such as... Figure 1As shown, the circuit structure includes a ring oscillator RO, a fast oscillation circuit FO, a 3-bit counter CNT, an intrinsic transistor M0, an XOR gate G, a reset signal generation circuit RPG, and a post-processing circuit PPU. The ring oscillator RO includes a NAND gate H and multiple inverters S1 cascaded in sequence. The first input terminal of the NAND gate H receives a level signal, and the second input terminal of the NAND gate H is connected to the output terminal of one of the inverters S1 at the end of the ring oscillator RO. The input terminal of the first inverter S1 of the ring oscillator RO is connected to the output terminal of the NAND gate H, and the output terminal of the preceding inverter S1 is connected to the input terminal of the following inverter S1. The control output terminal of the intrinsic transistor M0 is connected to the control terminal of each inverter S1 and the control terminal of the NAND gate H. The source of the intrinsic transistor M0 serves as the control output terminal, the gate is connected to the bias voltage terminal, and the drain is connected to the power supply voltage terminal. The bias voltage terminal corresponds to the bias voltage V. bias The power supply voltage terminal corresponds to the power supply voltage V. DD The outputs of one inverter S1 in the middle section and the output of one inverter S1 at the end of the ring oscillator RO are respectively connected to one input of the XOR gate G; the output of the XOR gate G is connected to the input of the fast oscillation circuit FO, the input of the reset signal generation circuit RPG, and the first processing input of the post-processing circuit PPU; the output of the fast oscillation circuit FO is connected to the first counting input of the counter 3-BitCNT, the reset signal output of the reset signal generation circuit RPG is connected to the second counting input of the counter 3-BitCNT, the output of the counter 3-BitCNT is connected to the second processing input of the post-processing circuit PPU, and the output of the post-processing circuit PPU is used to output a true random number sequence. The intrinsic transistor M0 is an NMOS transistor.

[0040] In a specific embodiment, such as Figure 1 As shown, the ring oscillator RO contains 2N+1 inverters S1, where N is a positive integer greater than 2. The inverters S1 connected to the input of the XOR gate G are the Nth inverter S1 and the (2N+1)th inverter S1 in the ring oscillator RO. Therefore, the difference between the number of inverters through which the oscillation signal output from the Nth inverter S1 passes and the number of inverters through which the oscillation signal output from the (2N+1)th inverter S1 passes is minimized.

[0041] In one specific embodiment, this scheme designs a ring oscillator RO consisting of one NAND gate H and 16 inverters S1 cascaded together. Jitter noise is obtained from two different inverter S1 stages within the single ring oscillator RO. An intrinsic transistor M0 regulates the ring oscillator RO to minimize the impact of power supply voltage variations. When the input EN1 of the NAND gate H in the ring oscillator RO is set to a high level, the entire ring oscillator RO is equivalent to a 17-stage inverter S1 chain and begins to oscillate. Figure 7 As shown, the output signals Out8 and Out8 of the 8th and 17th stages of the ring oscillator RO are inverters. 17 The phase difference is mainly determined by two factors: the time-invariant inherent propagation delay of the eight inverters between them, and the time-varying difference caused by jitter noise. This is achieved by using an XOR gate greater than the difference between Out8 and Out8. 17 The pulse width of the output EN2 signal, after XOR operation, is attributed to the aforementioned phase difference plus the fixed delay caused by the XOR gate, resulting in a pulse width T. pulse It can be expressed using formula (1).

[0042] T pulse =8×t inv +t xor +t jitter (1);

[0043] Where t inv The inherent propagation delay time t of an inverter xor t is the inherent propagation delay time of an XOR gate. jitter The random jitter noise accumulated from the 8th stage inverter to the 17th stage inverter. Only t in equation (1) jitter It is a variable that changes over time, while T pulse The entropy contained therein is entirely determined by t jitter The variance determines, i.e. Based on the relevant derivation process, when the ring oscillator is operated in the strong inversion region... It can be calculated using formula (2):

[0044]

[0045] Where k is the Boltzmann constant, T is the Kelvin temperature, and γ N and γ P These are the noise figures of NMOS and PMOS, respectively. From equation (2), we can see... This can be achieved by reducing the power supply voltage V DD Or increase the delay t of the inverter d To increase, both can be increased, and both can be decreased. Figure 1 The bias voltage V of the intrinsic transistor biasTo achieve this.

[0046] In a specific embodiment, such as Figure 2 As shown, the inverter S1 in the ring oscillator RO includes a first MOS transistor M1 and a second MOS transistor M2; the gate of the first MOS transistor M1 is connected to the gate of the second MOS transistor M2, and the connection point serves as the input terminal of the inverter S1; the source of the first MOS transistor M1 serves as the control terminal of the inverter S1 and is connected to the control output terminal of the intrinsic transistor M0; the drain of the first MOS transistor M1 is connected to the drain of the second MOS transistor M2, and the connection point serves as the output terminal of the inverter S1; the source of the second MOS transistor M2 is grounded.

[0047] In a specific embodiment, such as Figure 3 As shown, the fast oscillation circuit FO includes a cascaded NAND gate HZ, a first oscillation inverter S2, and a second oscillation inverter S3. One input terminal of the NAND gate HZ serves as the input terminal of the fast oscillation circuit FO and is connected to the output terminal of the XOR gate G. The other input terminal is connected to the output terminal of the second oscillation inverter S3 and serves as the output terminal of the fast oscillation circuit FO, which is then connected to the first counting input terminal of the 3-Bit CNT counter. The input terminal of the first oscillation inverter S2 is connected to the output terminal of the NAND gate HZ, and the input terminal of the second oscillation inverter S3 is connected to the output terminal of the first oscillation inverter S2.

[0048] In a specific embodiment, such as Figure 4As shown, the 3-BitCNT counter includes three cascaded counting circuits P; each counting circuit P includes a counting output terminal. Specifically, each counting circuit P includes a first counting MOSFET M3, a second counting MOSFET M4, a third counting MOSFET M5, a fourth counting MOSFET M6, a fifth counting MOSFET M7, a sixth counting MOSFET M8, a seventh counting MOSFET M9, an eighth counting MOSFET M10, a ninth counting MOSFET M11, a tenth counting MOSFET M12, and an eleventh counting MOSFET M13; the source of the first counting MOSFET M3, the source of the second counting MOSFET M4, the source of the fourth counting MOSFET M6, and the source of the seventh counting MOSFET M13 are all connected in series. The sources of transistor M9, the eighth counting MOSFET M10, and the tenth counting MOSFET M12 are all connected to a regulated power supply; the sources of the third counting MOSFET M5, the fifth counting MOSFET M7, the sixth counting MOSFET M8, the ninth counting MOSFET M11, and the eleventh counting MOSFET M13 are all grounded; the gates of the third counting MOSFET M5, the fifth counting MOSFET M7, and the seventh counting MOSFET M9 are connected and serve as clock signal input terminals to receive clock signals. The gates of the second counting MOS transistor M4, the sixth counting MOS transistor M8, and the eighth counting MOS transistor M10 are connected and serve as reset signal input terminals to acquire the reset signal from the reset signal generation circuit RPG; the gate of the first counting MOS transistor M3 serves as a first loop terminal connected to the second loop terminal, and the drain of the first counting MOS transistor M3 is connected to the drain of the second counting MOS transistor M4, the drain of the third counting MOS transistor M5, and the gate of the fourth counting MOS transistor M6; the drain of the fourth counting MOS transistor M6 is connected to the gate of the second counting MOS transistor M4, the drain of the third counting MOS transistor M5, and the gate of the fourth counting MOS transistor M6. The drain of the fifth counting MOSFET M7, the drain of the sixth counting MOSFET M8, and the gate of the ninth counting MOSFET M11 are connected together; the drain of the seventh counting MOSFET M9 is connected to the drain of the ninth counting MOSFET M11, the drain of the eighth counting MOSFET M10, the gate of the tenth counting MOSFET M12, and the gate of the eleventh counting MOSFET M13, and the connection point serves as the second loop terminal; the drain of the tenth counting MOSFET M12 is connected to the drain of the eleventh counting MOSFET M13, and the connection point serves as the counting output terminal.

[0049] To extract the entropy source generated by the aforementioned ring oscillator, a high-precision time-digital converter (TDC) is needed to continuously quantize the pulse width T. pulseThe LSBs (least significant bits) of TDC are determined by the delay variations caused by the highly random jitter-noise. Figure 3 As shown, a fast oscillator circuit based on a 3-stage inverter is used as a high-frequency clock to measure T. pulse Connect the enable signal of the 3-stage fast oscillator circuit to EN2. This fast oscillator circuit only operates when EN2 is high (T). pulse The device oscillates at a high frequency. When triggered to oscillate, the output CLK of the 3-stage fast oscillation circuit... f It was used as a clock signal to drive a 3-bit counter based on E-TSPC logic. For example... Figure 4 As shown, the outputs Q0, Q1, and Q2 of the 3-bit counter represent the three LSBs of the TDC used, corresponding to the three counting output terminals respectively. Simultaneously, the falling edge of EN2 triggers the post-processing module to sample these three raw output bits. To maximize the accuracy of the TDC, the transistors of the 3-stage fast oscillation circuit have been optimized to achieve an oscillation frequency up to 10 GHz, even at the worst process corner (i.e., the SS process corner).

[0050] In a specific embodiment, such as Figure 5 As shown, the reset signal generation circuit RPG includes a first delay unit DU1, a second delay unit DU2, and a reset NAND gate HF. The first delay unit DU1 has a same-phase output, and the second delay unit DU2 has an out-of-phase output. The delay times of the two delay units are different. The input terminals of the first delay unit DU1 and the second delay unit DU2 are both connected to the output terminal of the XOR gate G. The output terminals of the first delay unit DU1 and the second delay unit DU2 are respectively connected to one input terminal of the reset NAND gate HF. The output terminal of the reset NAND gate HF serves as the reset signal output terminal of the reset signal generation circuit RPG. In a specific embodiment, as shown... Figure 6 As shown, the post-processing circuit PPU is a 5-stage XOR chain circuit. Each stage of the XOR processing circuit in the post-processing circuit PPU consists of two post-processing D flip-flops and one post-processing XOR gate.

[0051] In addition, for T pulse Each quantization leaves a residue in the 3-bit counter, which can cause correlation between consecutive pulse quantization bits. Therefore, a reset signal RST is needed to clear the residual digits. During the TDC quantization process, the falling edge of EN2 simultaneously inputs two delay units with different delay times. The two outputs are finally processed by a reset NAND gate HF to generate a reset signal pulse, as shown in the specific structure. Figure 5 As shown. Where the in-phase delay time t d1 Compared to the anti-phase delay time td2 The delay time is longer, and both delay times are designed to be much less than half the EN2 period, which ensures that no reset operation occurs during quantization. Finally, the original bits generated by TRNG are preserved, and a 5-level XOR chain is used as a post-processing module to eliminate statistical bias and correlation of consecutive bits. Figure 6 As shown, all adjacent pairs of binary bits are XORed in the post-processing XOR gate of each stage to form a new sequence, and Q<0:2> is post-processed into R<0:2> respectively.

[0052] In this application, a True Random Number Generator (TRNG) corresponding to the above circuit structure was fabricated using a 40nm standard CMOS process. The fabricated TRNG was then tested at a power supply voltage V. DD Experiments were conducted under a voltage of 1.1V to verify the results. To achieve a good balance between randomness and throughput, the bias voltage V at the bias terminal of the intrinsic transistor was set. bias It was set to 900mV. Figure 8 The screenshot shows the high-speed oscilloscope used (Keysight DSOS104A, 20GSa / s). The waveform of the first channel (number 1 from the top) is EN2, and the waveforms of the other three channels are shown from top to bottom as Q0, Q1, and Q2. With the three random bit channels output in parallel, the maximum throughput is 53Mbps, corresponding to a power consumption of 133μW and a high energy efficiency of 2.5pJ / bit. The relationship between power consumption and energy efficiency during the test is as follows: Figure 9 As shown in Figure (a).

[0053] To quantitatively evaluate the randomness of the chip circuitry, we used two widely accepted NIST test tools: Pub SP 800-22 and Pub SP 800-90B. For each bit channel, under normal conditions (27°C, V... DD=1.1V), 10M random bits were collected from 10 test chips and input into the NIST testing tool. Table 1 shows the test results of NIST SP 800-22. It was observed that the confidence (P) of all sub-test items was greater than 0.01, which well demonstrates the high randomness of the proposed TRNG. In the NIST SP 800-90B test results shown in Table 2, all four independent and identically distributed (IID) test items passed, and the lowest minimum entropy in the non-IID test items was 0.928535. As another mainstream randomness assessment tool, the autocorrelation function (ACF) was also adopted. The specific test settings were 10M random sequences and lag from 1 to 5000. The test results are as follows. Figure 9 As shown in Figure (b), the 95% confidence interval is ±0.0019.

[0054] Table 1

[0055]

[0056]

[0057] *For test items with two or more subtests, the confidence level (P) and pass rate in the table are the minimum of the two subtests or the median of the multiple tests.

[0058] Table 2

[0059]

[0060] also, Figure 9 Figures (c) and (d) in the figure show the speckle pattern of 1M random bits and the fast Fourier transform (FFT) results of the Hanning window, respectively. Figure 9 In figure (c), black and white dots are evenly distributed. Figure 9 The flat spectral amplitude in Figure (d) further validates the uncertainty and aperiodic characteristics of the TRNG. To measure the TRNG's tolerance to PVT variations, a 0 / 1 bias test was first performed on 10 chips manufactured at different process angles. The bias value was defined as:

[0061] Bias=|p0-p1|-2 (3);

[0062] Where p0 represents the probability of "0" in the sequence, and p1 represents the probability of "1". Figure 10The bias test results for three output channels R<0:2> of 10 chips are shown, with 1M bits sampled for each channel. Clearly, the probability of the three-bit output sequence being "0" and "1" is close to 50% for all chips, and the bias values ​​for all output channels of the 10 tested chips are all below 0.1%. Figure 10 As shown, the worst-case deviation is 0.08% of the third bit output of chips 2 and 8.

[0063] This paper also calculates the Shannon entropy H of the random sequence. H can be calculated by formula (4):

[0064] H=-[p1log2(p1)+(1-p1)log2(1-p1)] (4);

[0065] Under different VT conditions of 0.8V to 1.1V and -40℃ to 120℃, the Shannon entropy H of 1M bits generated by each chip was calculated, and the results are as follows. Figure 11 As shown in the figure. The results indicate that the minimum Shannon entropy is greater than 0.999995 within the above temperature range, which strongly confirms that the TRNG has good VT tolerance.

[0066] Table 2 summarizes the performance of the proposed TRNG design and compares it with other state-of-the-art TRNG designs. The proposed TRNG exhibits excellent resistance to PVT variations and outperforms all existing designs based on oscillator jitter in terms of throughput. Simultaneously, its high energy efficiency of 2.5 pJ / bit is 2–18 times higher than existing technologies.

[0067] Table 3

[0068]

[0069] The true random number generator circuit structure of the single-ring oscillator disclosed in this application obtains the jitter noise of a single ring oscillator through two different inverter stages with fixed propagation delays. Therefore, the variance of the generated pulse width is entirely determined by the jitter noise, which is independent of the differences in device parameters between ring oscillators during the manufacturing process. Furthermore, the amplitude of the jitter noise is maximized by modulating the charging / discharging current of the ring oscillator using intrinsic transistors. Using a fast oscillator and an E-TSPC-based 3-bit counter to quantize the width of the entropy source pulses, a highly random sequence can be generated with a throughput of 53 Mbps, corresponding to a high energy efficiency of 2.5 pJ / bit. Verification using mainstream evaluation tools based on NIST and ACF shows that the produced chip exhibits excellent randomness. Even within a temperature range of 0.8V to 1.1V and -40℃ to 120℃, a high Shannon entropy exceeding 0.999995 can still be achieved. These results demonstrate that the TRNG disclosed in this application can be widely applied to IoT applications related to hardware security and meets the stringent energy consumption requirements of corresponding application scenarios.

[0070] This invention discloses a true random number generator circuit structure using a single-ring oscillator. The circuit structure includes a ring oscillator, a fast oscillation circuit, a counter, an intrinsic transistor, an XOR gate, a reset signal generation circuit, and a post-processing circuit. In this circuit structure, the two different inverter stages of the ring oscillator are XORed to generate rectangular pulses. The width of these pulses is determined by the time-invariant inherent propagation delay and the variation caused by time-varying jitter noise. By quantizing the width of the generated continuous pulses using the fast oscillation circuit and the counter, the delay variation caused by jitter noise can be characterized from the least significant bit of the counter. By changing the gate voltage of the intrinsic transistor, the supply voltage of the ring oscillator is adjusted, maximizing the amplitude of the ring oscillator's jitter noise by reducing its charging / discharging current. This results in a true random number generator circuit structure with high energy efficiency and high throughput.

[0071] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A true random number generator circuit structure using a single-ring oscillator, characterized in that, The circuit structure includes a ring oscillator, a fast oscillation circuit, a counter, an intrinsic transistor, an XOR gate, a reset signal generation circuit, and a post-processing circuit. The ring oscillator includes a NAND gate and multiple inverters cascaded in sequence; the first input terminal of the NAND gate receives a level signal, and the second input terminal of the NAND gate is connected to the output terminal of an inverter at the end of the ring oscillator; the input terminal of the first inverter of the ring oscillator is connected to the output terminal of the NAND gate, and the output terminal of the preceding inverter is connected to the input terminal of the following inverter; the control output terminal of the intrinsic transistor is connected to the control terminals of each inverter and the control terminal of the NAND gate; wherein, the source of the intrinsic transistor serves as the control output terminal, the gate is connected to the bias voltage terminal, and the drain is connected to the power supply voltage terminal; The output of one inverter in the middle section and the output of one inverter at the end of the ring oscillator are respectively connected to one input of the XOR gate; the output of the XOR gate is connected to the input of the fast oscillation circuit, the input of the reset signal generation circuit, and the first processing input of the post-processing circuit. The output terminal of the fast oscillation circuit is connected to the first counting input terminal of the counter, the reset signal output terminal of the reset signal generation circuit is connected to the second counting input terminal of the counter, the output terminal of the counter is connected to the second processing input terminal of the post-processing circuit, and the output terminal of the post-processing circuit is used to output a true random number sequence. The inverter in the ring oscillator includes a first MOS transistor and a second MOS transistor; The gate of the first MOS transistor is connected to the gate of the second MOS transistor, and the connection point serves as the input terminal of the inverter; the source of the first MOS transistor serves as the control terminal of the inverter and is connected to the control output terminal of the intrinsic transistor; the drain of the first MOS transistor is connected to the drain of the second MOS transistor, and the connection point serves as the output terminal of the inverter; the source of the second MOS transistor is grounded. The fast oscillation circuit includes an oscillation NAND gate, a first oscillation inverter, and a second oscillation inverter cascaded in sequence; One input terminal of the oscillation NAND gate is connected to the output terminal of the XOR gate as the input terminal of the fast oscillation circuit, and the other input terminal is connected to the output terminal of the second oscillation inverter and is also connected to the first counting input terminal of the counter as the output terminal of the fast oscillation circuit; the input terminal of the first oscillation inverter is connected to the output terminal of the oscillation NAND gate, and the input terminal of the second oscillation inverter is connected to the output terminal of the first oscillation inverter.

2. The true random number generator circuit structure of the single-ring oscillator according to claim 1, characterized in that, The ring oscillator contains 2N+1 inverters, where N is a positive integer greater than 2.

3. The true random number generator circuit structure of the single-ring oscillator according to claim 2, characterized in that, The inverters connected to the input of the XOR gate are the Nth inverter and the (2N+1)th inverter in the ring oscillator.

4. The true random number generator circuit structure of the single-ring oscillator according to claim 2 or 3, characterized in that, The intrinsic transistor is an NMOS transistor.

5. The true random number generator circuit structure of the single-ring oscillator according to claim 1, characterized in that, The counter comprises three cascaded counting circuits; each of the counting circuits includes a counting output terminal.

6. The true random number generator circuit structure of the single-ring oscillator according to claim 5, characterized in that, Each of the aforementioned counting circuits includes a first counting MOS transistor, a second counting MOS transistor, a third counting MOS transistor, a fourth counting MOS transistor, a fifth counting MOS transistor, a sixth counting MOS transistor, a seventh counting MOS transistor, an eighth counting MOS transistor, a ninth counting MOS transistor, a tenth counting MOS transistor, and an eleventh counting MOS transistor; The sources of the first, second, fourth, seventh, eighth, and tenth counting MOSFETs are all connected to a regulated power supply; the sources of the third, fifth, sixth, ninth, and eleventh counting MOSFETs are all grounded; the gates of the third, fifth, and seventh counting MOSFETs are connected and serve as clock signal input terminals to receive clock signals; the gates of the second, sixth, and eighth counting MOSFETs are connected and serve as reset signal input terminals to obtain reset signals from the reset signal generation circuit. The gate of the first counting MOS transistor is connected to the second ring terminal as the first ring terminal, and the drain of the first counting MOS transistor is connected to the drain of the second counting MOS transistor, the drain of the third counting MOS transistor, and the gate of the fourth counting MOS transistor; the drain of the fourth counting MOS transistor is connected to the drain of the fifth counting MOS transistor, the drain of the sixth counting MOS transistor, and the gate of the ninth counting MOS transistor. The drain of the seventh counting MOS transistor is connected to the drain of the ninth counting MOS transistor, the drain of the eighth counting MOS transistor, the gate of the tenth counting MOS transistor, and the gate of the eleventh counting MOS transistor, and the connection point serves as the second loop terminal; the drain of the tenth counting MOS transistor is connected to the drain of the eleventh counting MOS transistor, and the connection point serves as the counting output terminal.

7. The true random number generator circuit structure of the single-ring oscillator according to claim 1, characterized in that, The reset signal generation circuit includes a first delay unit, a second delay unit, and a reset NAND gate, wherein the first delay unit is a same-phase output and the second delay unit is an inverse-phase output; The input terminals of the first delay unit and the second delay unit are both connected to the output terminal of the XOR gate; the output terminals of the first delay unit and the second delay unit are respectively connected to one input terminal of the reset NAND gate, and the output terminal of the reset NAND gate serves as the reset signal output terminal of the reset signal generation circuit.

8. The true random number generator circuit structure of the single-ring oscillator according to claim 1, characterized in that, The post-processing circuit is a 5-stage XOR chain circuit. Each stage of the XOR processing circuit consists of two post-processing D flip-flops and one post-processing XOR gate.

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