Data processing apparatus, method for managing registers, and machine-readable storage medium

Abstract

The present invention provides a data processing device, a management method for its registers, and a machine-readable storage medium to reduce the number of entries in a register index table. The data processing device includes a thread group scheduler and a register manager. The thread group scheduler analyzes the number of register requirements of a thread group. The register manager determines the register management granularity corresponding to the thread group based on the number of register requirements of the thread group, where the register management granularity is the number of physical registers corresponding to the physical base index of each entry in the register index table of the thread group. The register manager allocates a plurality of selected physical registers that meet the register management granularity to the thread group, and the register manager fills the base index of the plurality of selected physical registers into the physical base index field of an entry in the register index table.

Description

Technical Field

[0001] The present invention relates to an electronic device, and particularly to a data processing device, a management method for its register, and a machine-readable storage medium. Background Art

[0002] Data processing devices such as a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose computing on GPU (GPGPU), etc. can execute programs to complete various functions such as convolutional neural network (CNN) operations and artificial intelligence operations. Generally, a program includes multiple workgroups, each workgroup includes multiple thread groups (thread group or warp), and each thread group includes multiple operation instructions. The thread group scheduler can schedule the thread groups to the hardware (processing device) for execution. In a vector or single instruction multiple data (SIMD) parallel processor, a large register file is generally configured to support the execution of multiple thread groups. These thread groups need to share the register file resources. If these thread groups are from the same program kernel, then the number of registers required to be allocated for each thread group is the same. To support the simultaneous parallel execution of thread groups of different programs in a vector processor or a single instruction multiple thread (SIMT) processor, fine-grained management and allocation of the registers in the register file are required. How to manage the registers in the register file is one of the many topics in this technical field. Summary of the Invention

[0003] The present invention provides a data processing device, a management method for its register, and a machine-readable storage medium to reduce the number of entries in the register index table.

[0004] In an embodiment according to the present invention, the data processing device includes a thread group scheduler and a register manager. The thread group scheduler analyzes the number of register requirements of a thread group (thread group or warp). The register manager is coupled to the thread group scheduler. The register manager is used to allocate registers based on the requirements of the thread group scheduler. The register manager determines the register management granularity corresponding to the thread group based on the number of register requirements of the thread group, where the register management granularity is the number of physical registers corresponding to the physical base index of each entry in the register index table of the thread group. The register manager allocates a plurality of selected physical registers that meet the register management granularity to the thread group, and the register manager fills the base index of the plurality of selected physical registers into the physical base index field of an entry in the register index table.

[0005] In an embodiment according to the present invention, the management method includes: analyzing the number of register requirements of a thread group; determining the register management granularity corresponding to the thread group based on the number of register requirements of the thread group, where the register management granularity is the number of physical registers corresponding to the physical base index of each entry in the register index table of the thread group; and allocating a plurality of selected physical registers that meet the register management granularity to the thread group, and filling the base index of the plurality of selected physical registers into the physical base index field of an entry in the register index table.

[0006] In an embodiment according to the present invention, the machine-readable storage medium is used to store non-transitory machine-readable instructions. When the non-transitory machine-readable instructions are executed by a computer, the register management method can be implemented.

[0007] Based on the above, the number of physical registers corresponding to each entry in the register index table (register management granularity) is dynamically determined according to the number of register requirements of the thread group. Thread groups with a large number of register requirements use a large register management granularity to reduce the number of entries in the register index table. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic diagram of a circuit block of a data processing device according to an embodiment of the present invention.

[0009] Figure 2 is a schematic diagram of a thread group and a register index table shown according to an embodiment.

[0010] Figure 3 is a schematic flowchart of a register management method according to an embodiment of the present invention.

[0011] Description of Reference Numerals

[0012] 100: Data processing device

[0013] 110: Thread Group Scheduler

[0014] 120: Register Manager

[0015] 130: Execution unit

[0016] 140: Register index table

[0017] IDP_1, IDP_2, IDP_3, IDP_N: physical base index

[0018] S310, S320, S330: Steps

[0019] T_1, T_2, T_3, T_N: Register index table

[0020] W_1, W_2, W_3, W_N: thread groups DETAILED DESCRIPTION

[0021] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0022] The term "coupled (or connected)" used in the entire specification of this case (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be indirectly connected to the second device through other devices or some connection means. The terms "first", "second", etc. mentioned in the entire specification of this case (including the claims) are used to name the components (element), and are not used to limit the upper or lower limit of the number of components, nor are they used to limit the order of components. In addition, wherever possible, components / components / steps with the same number in the drawings and embodiments represent the same or similar parts. Components / components / steps using the same number or the same terminology in different embodiments can refer to the relevant descriptions of each other.

[0023] Figure 1 is a circuit block diagram of a data processing device 100 according to an embodiment of the present invention. Figure 1The data processing device 100 shown includes a thread group (thread group or warp) dispatcher 110, a register manager 120, and an execution unit (EU) 130. The thread group dispatcher 110 is coupled to the register manager 120 and the execution unit 130. The thread group dispatcher 110 can determine to launch a certain thread group into the execution unit 130 according to the register resource situation of the data processing device 100, and at the same time initiate a register application to the register manager 120 for the thread group launched into the execution unit 130. The register manager 120 allocates registers to the thread group and sends the physical indexes of the allocated registers to the register index table 140. When the register manager 120 completes the allocation of all registers of the thread group, the register manager 120 notifies the execution unit 130 that the "register allocation of the thread group" has been completed. During the execution of the thread group, the execution unit 130 will look up the register index table 140 based on the logical register index and warp index of the operation instruction to obtain the physical index of the logical register index. The execution unit 130 can use the physical index to read and write operands to the target physical register.

[0024] According to different design requirements, in some embodiments, the thread group dispatcher 110, the register manager 120, and / or the execution unit 130 may be implemented as hardware circuits. In other embodiments, the thread group dispatcher 110, the register manager 120, and / or the execution unit 130 may be implemented as firmware or software (i.e., programs). In still other embodiments, the thread group dispatcher 110, the register manager 120, and / or the execution unit 130 may be implemented in a combined form of multiple of hardware, firmware, and software.

[0025] In terms of hardware, the above-mentioned thread group scheduler 110, register manager 120, and / or execution unit 130 can be implemented as logic circuits on an integrated circuit. For example, the related functions of the thread group scheduler 110, register manager 120, and / or execution unit 130 can be implemented in various logic blocks, modules, and circuits of one or more controllers, microcontrollers, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), central processing units (CPUs), and / or other processing units. The related functions of the thread group scheduler 110, register manager 120, and / or execution unit 130 can be implemented as hardware circuits, such as various logic blocks, modules, and circuits in an integrated circuit, using hardware description languages (such as Verilog HDL or VHDL) or other suitable programming languages.

[0026] In terms of software form and / or firmware form, the related functions of the above-mentioned thread group scheduler 110, register manager 120, and (or) execution unit 130 can be implemented as programming codes. For example, the thread group scheduler 110, register manager 120, and (or) execution unit 130 are implemented using general programming languages (such as C, C++, or assembly language) or other suitable programming languages. The programming codes can be recorded / stored in a non-transitory machine-readable storage medium. In some embodiments, the machine-readable storage medium includes, for example, semiconductor memory and (or) storage devices. An electronic device (such as a CPU, controller, microcontroller, or microprocessor) can read and execute the programming codes from the machine-readable storage medium to implement the related functions of the thread group scheduler 110, register manager 120, and (or) execution unit 130. Alternatively, the programming codes can be provided to the electronic device via any transmission medium (such as a communication network or broadcast radio waves, etc.). The communication network is, for example, the Internet, a wired communication network, a wireless communication network, or other communication media.

[0027] Figure 2 is shown according to an embodiment, a schematic diagram of a thread group and a register index table. Assume that the execution unit 130 can accommodate at most N thread groups, for example Figure 2 shown thread groups W_1, W_2, W_3,..., W_N. The register index table 140 needs to establish a corresponding index table for each thread group W_1 to W_N, for example Figure 2 shown N register index tables T_1, T_2, T_3,..., T_N, where each register index table T_1 to T_N has the same number of entries. For example, the register index table T_1 has M entries. The other register index tables T_2 to T_N and the other thread groups W_2 to W_N can refer to the related descriptions of the register index table T_1 and the thread group W_1. The physical base index field of each entry can store the physical base index used to point to the corresponding register, for example Figure 2The physical base indexes shown, IDP_1, IDP_2, IDP_3, …, IDP_N. When the operation instructions of thread group W_1 access a register, execution unit 130 uses the index of thread group W_1 and the logical register index to look up the physical base index corresponding to the logical register index in register index table T_1, and then uses this physical base index to perform read and write accesses to the register.

[0028] Different thread groups may have different numbers of register requirements. To support the execution of different thread groups, the number of entries M in each register index table T_1~T_N must be large enough. For example, assume that the register file (not shown) of data processing device 100 has 512 registers, and assume that different thread groups of different programs have the same register management granularity (e.g., the granularity is “1 register”), then the number of entries M is 512. Wherein, the register management granularity refers to the number of physical registers corresponding to the physical base index of each entry in the register index table of the thread group. A large number of entries M in the register index table will result in a large area consumption. A large number of entries M in the register index table will also result in a large access latency of the register index table, which limits the chip clock frequency and performance. A large number of entries M in the register index table will also result in a large power consumption overhead for accessing the register index table. In an actual operating scenario, the number of register requirements of a thread group is often much less than 512. How to reduce the number of entries M in the register index table will be described below.

[0029] Figure 3 is a schematic flowchart of a method for managing registers according to an embodiment of the present invention. In some embodiments, Figure 3 the method for managing the registers shown can be implemented in firmware or software (i.e., a program). For example, Figure 3 the related operations of the method for managing the registers shown can be implemented as non-transitory machine-readable instructions (programming codes or programs), and the non-transitory machine-readable instructions can be stored in a machine-readable storage medium. When the non-transitory machine-readable instructions are executed by a computer, the method for managing the registers shown can be implemented Figure 3 In other embodiments, Figure 3 the method for managing the registers shown can be implemented in hardware, for example, implemented in Figure 1 the data processing device 100 shown.

[0030] Step S310 analyzes the number of register requirements of a thread group, and step S320 determines the register management granularity corresponding to the thread group based on the number of register requirements of the thread group. Wherein, the register management granularity is the number of physical registers corresponding to the physical base index of each entry in the register index table of the thread group. Based on the actual design, in some embodiments, the compiler may execute step S310 and / or S320, and embed relevant information about the number of register requirements and / or the register management granularity in the thread group. For example, the thread group scheduler 110 initiates a register application to the register manager 120 and provides relevant information about the number of register requirements to the register manager 120.

[0031] In some other embodiments, Figure 1 the shown thread group scheduler 110 may execute step S310, and the register manager 120 may execute step S320. For example, the thread group scheduler 110 may analyze the number of register requirements of the thread group (or extract the "number of register requirements" from the relevant information embedded in the thread group). The register manager 120 may allocate registers to the thread group based on the requirements of the thread group scheduler 110. The register manager 120 may determine the register management granularity corresponding to this thread group based on the number of register requirements of the thread group.

[0032] The data processing device 100 may adopt different allocation management granularities (register management granularities) according to the total number of registers required by the program kernel. When the number of registers used by the thread group is small, a fine-grained register allocation (a smaller register management granularity) is adopted. When the number of registers used by the thread group gradually increases, the register management granularity will also be correspondingly increased. There is a certain correspondence between the size of the register requirements of the thread group and the register management granularity to ensure that the number of entries in the register index table used by each thread group maintains a fixed size, thereby reducing the size of the register index table, access latency, and power consumption.

[0033] For example, when the number of register requirements of a thread group belongs to the first quantity range, the data processing device 100 may determine that the register management granularity of this thread group is the first granularity. When the number of register requirements belongs to the second quantity range (different from the first quantity range), the data processing device 100 may determine that the register management granularity of this thread group is the second granularity (different from the first granularity). Table 1 below shows one of the many examples of "dynamically determining the register management granularity". Assuming that the register file has 512 registers, the numerical range of the number of register requirements can be divided into multiple intervals, such as the 5 quantity ranges shown in Table 1: "1 - 32", "33 - 64", "65 - 128", "129 - 256", and "257 - 512". When the number of register requirements of a thread group belongs to the quantity range "1 - 32", the register management granularity of this thread group is "4 registers", that is, the physical base index of each entry in the register index table of this thread group corresponds to 4 physical registers (the unit quantity of registers allocated by the register manager 120 to this thread group is "4 registers"). Because the register management granularity is "4 registers", the physical base index that the register manager 120 allocates registers to this thread group may be one (or more) of 0, 4, 8, 12,..., 508. When the number of register requirements of a thread group belongs to the quantity range "33 - 64", the register management granularity of this thread group is "8 registers", that is, the physical base index of each entry in the register index table of this thread group corresponds to 8 physical registers. Because the register management granularity is "8 registers", the physical base index that the register manager 120 allocates registers to this thread group may be one (or more) of 0, 8, 16, 24,..., 504. The remaining quantity ranges "65 - 128", "129 - 256", and "257 - 512" can be referred to the relevant descriptions of the quantity ranges "1 - 32" and "33 - 64" and analogized, so they will not be elaborated here.

[0034] Table 1: Example Rules for Dynamically Determining Register Management Granularity

[0035]

[0036] Please refer to Figure 1 and Figure 3。In step S330, the register manager 120 allocates multiple selected physical registers that conform to the dynamically determined register management granularity to the thread group, and the register manager 120 fills the base index of the multiple selected physical registers into the physical base index field of an entry in the register index table. Every time the register manager 120 allocates a granularity of registers, it sends information to the register index table 140. When the register manager 120 completes the allocation of all the registers of the thread group, the register manager 120 notifies the execution unit 130 that the register application has been completed. For example, assume that the dynamically determined register management granularity is "4 registers", then the register manager 120 selects "4 consecutive registers" from the free register pool, such as the registers with register indexes 0, 1, 2, and 3, as the multiple selected physical registers. After the register manager 120 decides to allocate the registers "0", "1", "2", and "3" to the thread group, the register manager 120 fills the base index "0" of these registers "0" to "3" into the physical base index field of an entry in the register index table.

[0037] In summary, the number of physical registers (register management granularity) corresponding to each entry in the register index table is dynamically determined according to the register requirement quantity of the corresponding thread group. Thread groups with a large register requirement quantity use a large register management granularity to reduce the number of entries in the register index table. Therefore, the number of entries M in the register index table can be less than the total number of registers in the data processing device 100. The number of entries M in the register index table used by each thread group can be guaranteed to maintain a fixed size, thereby reducing the register index table size, access latency, and power consumption. Taking Table 1 as an illustrative example, the number of entries M in the register index table can be guaranteed to be fixed at 8. Please refer to Figure 2 , assume that the register requirement quantity of thread group W_1 belongs to the quantity range "1 to 32", then the register management granularity of thread group W_1 is "4 registers", and the maximum number of entries M in the register index table T_1 of thread group W_1 is 8 (because the maximum register requirement quantity is 32, and each entry in the register index table corresponds to 4 physical registers). Assume again that the register requirement quantity of thread group W_2 belongs to the quantity range "257 to 512", then the register management granularity of thread group W_2 is "64 registers", and the maximum number of entries M in the register index table T_2 of thread group W_2 is also 8 (because the maximum register requirement quantity is 512, and each entry in the register index table corresponds to 64 physical registers).

[0038] Please refer to Figure 1. The execution unit 130 executes the thread group dispatched by the thread group scheduler 110 based on the register index table 140. For example, the execution unit 130 looks up the register index table T_1 from multiple index tables of the register index table 140 based on the index value of the thread group W_1. The execution unit 130 looks up the register index table T_1 of the thread group W_1 based on the logical register index of the operation instruction of the thread group W_1, and obtains the physical base index corresponding to the logical register index. The execution unit 130 converts the physical base index into the physical indexes of multiple selected physical registers corresponding to the operation instruction based on the register management granularity corresponding to the thread group W_1. For example, assume that the register management granularity of the thread group W_1 is determined dynamically to be "4 registers", and the physical base index obtained from the register index table T_1 is "4". Then the execution unit 130 converts the physical base index "4" into the consecutive physical indexes "4", "5", "6", and "7" of the selected physical registers based on the register management granularity of "4 registers". The execution unit 130 executes the operation instruction based on the physical indexes of the multiple selected physical registers to perform read and write accesses to the operands.

[0039] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data processing device, characterized in that, The data processing device includes: a thread group scheduler that analyzes the number of register requirements of a thread group; and a register manager coupled to the thread group scheduler for allocating registers based on the requirements of the thread group scheduler, wherein the register manager determines the register management granularity corresponding to the thread group based on the number of register requirements of the thread group, determines that the register management granularity increases when the number of register requirements increases, and determines that the register management granularity decreases when the number of register requirements decreases. The register management granularity is the number of physical registers corresponding to the physical base index of each entry in the register index table of the thread group. The register manager allocates a plurality of selected physical registers that meet the register management granularity to the thread group, and the register manager fills the base index of the plurality of selected physical registers into the physical base index field of an entry in the register index table.

2. The data processing device according to claim 1, wherein: when the number of register requirements belongs to a first quantity range, determining that the register management granularity is a first granularity; and when the number of register requirements belongs to a second quantity range different from the first quantity range, determining that the register management granularity is a second granularity different from the first granularity.

3. The data processing device according to claim 1, wherein The data processing device further includes: an execution unit coupled to the thread group scheduler, wherein the execution unit executes the thread group dispatched by the thread group scheduler based on the register index table.

4. The data processing device according to claim 3, characterized in that The execution unit looks up the register index table of the thread group based on the logical register index of the operation instruction of the thread group to obtain the physical base index corresponding to the logical register index, converts the physical base index into the physical index of the plurality of selected physical registers corresponding to the operation instruction based on the register management granularity corresponding to the thread group, and the execution unit executes the operation instruction based on the physical index of the plurality of selected physical registers.

5. The data processing device according to claim 1, characterized in that, The number of entries in the register index table is less than the total number of registers of the data processing device.

6. A method for managing registers, characterized in that, The management method includes: analyzing the number of register requirements of a thread group; determining the register management granularity corresponding to the thread group based on the number of register requirements of the thread group, determining that the register management granularity increases when the number of register requirements increases, and determining that the register management granularity decreases when the number of register requirements decreases, wherein the register management granularity is the number of physical registers corresponding to the physical base index of each entry in the register index table of the thread group; and allocating a plurality of selected physical registers that meet the register management granularity to the thread group, and filling the base index of the plurality of selected physical registers into the physical base index field of an entry in the register index table.

7. The management method according to claim 6, wherein The operation of determining the register management granularity corresponding to the thread group includes: When the number of register requirements belongs to a first quantity range, determining that the register management granularity is a first granularity; and When the number of register requirements belongs to a second quantity range different from the first quantity range, determining that the register management granularity is a second granularity different from the first granularity.

8. The management method according to claim 6, characterized in that, The management method further includes: Executing the thread group based on the register index table.

9. The management method according to claim 8, wherein The management method further includes: Based on the logical register index of the operation instruction of the thread group, looking up the register index table of the thread group to obtain the physical base index corresponding to the logical register index; Based on the register management granularity corresponding to the thread group, converting the physical base index into the physical indexes of the multiple selected physical registers corresponding to the operation instruction; and Based on the physical indexes of the multiple selected physical registers, executing the operation instruction.

10. The management method according to claim 6, characterized in that, The number of entries in the register index table is less than the total number of registers of the data processing device.

11. A machine-readable storage medium for storing non-transitory machine-readable instructions that, when executed by a computer, can implement the register management method according to any one of claims 6-10.

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