Drive circuit

Abstract

A driving circuit is disclosed. The driving circuit includes a driving transistor, a storage capacitor, a first transistor, a second transistor, a third transistor and a fourth transistor. A first end of the driving transistor is electrically connected to a system high voltage terminal. The driving transistor is used to control a driving current provided to a light emitting element. A first end of the storage capacitor is electrically connected to a gate terminal of the driving transistor. A first end of the first transistor is electrically connected to a second end of the storage capacitor, and a second end of the first transistor is used to receive a data signal. When the first transistor is turned on according to a first control signal, the storage capacitor resets a voltage of the gate terminal of the driving transistor according to a voltage variation of the data signal through a capacitive coupling effect.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a driving circuit, and more particularly, to a driving circuit with a reset operation. BACKGROUND

[0002] Nowadays, displays are widely used. In some current pixel driving circuit architectures, the reset operation of the pixel driving circuit turns on a leakage path between a system high voltage terminal and a reference voltage terminal. In such a case, even if the display is at the lowest brightness, a large power consumption is still caused. In addition, if the reset of the pixel driving circuit is not complete, the quality of the display image of the display is affected. Therefore, how to provide a driving circuit to solve the above problems is an important issue in the art. SUMMARY

[0003] The present disclosure provides a driving circuit. The driving circuit includes a driving transistor, a storage capacitor, a first transistor, a second transistor, a third transistor, and a fourth transistor. A first terminal of the driving transistor is electrically coupled to a system high voltage terminal. The driving transistor is configured to control a driving current provided to a light emitting element. A first terminal of the storage capacitor is electrically coupled to a gate terminal of the driving transistor. A first terminal of the first transistor is electrically coupled to a second terminal of the storage capacitor, and a second terminal of the first transistor is configured to receive a data signal. The second transistor is electrically coupled between a second terminal and the gate terminal of the driving transistor. A first terminal of the third transistor is configured to receive a reference voltage, and a second terminal of the third transistor is electrically coupled to the second terminal of the storage capacitor. The fourth transistor is electrically coupled between the second terminal of the driving transistor and a system low voltage terminal. When the first transistor is turned on according to a first control signal, the storage capacitor resets a voltage of the gate terminal of the driving transistor according to a voltage change of the data signal through a capacitive coupling effect.

[0004] The present disclosure provides another driving circuit. The driving circuit includes a driving transistor, a storage capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor. A first terminal of the driving transistor is electrically coupled to a system high voltage terminal. The driving transistor is configured to control a driving current provided to a light emitting element. A first terminal of the storage capacitor is electrically coupled to a gate terminal of the driving transistor. A first terminal of the first transistor is electrically coupled to a second terminal of the storage capacitor, and a second terminal of the first transistor is configured to receive a data signal. The second transistor is electrically coupled between a second terminal and the gate terminal of the driving transistor. A first terminal of the third transistor is configured to receive a first reference voltage, and a second terminal of the third transistor is electrically coupled to the second terminal of the storage capacitor. The fourth transistor is electrically coupled between the second terminal of the driving transistor and a system low voltage terminal. A first terminal of the fifth transistor is electrically coupled to the second terminal of the storage capacitor, and a second terminal of the fifth transistor is configured to receive a second reference voltage.

[0005] The present disclosure provides another driving circuit. The driving circuit includes a driving transistor, a storage capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a reset capacitor. A first end of the driving transistor is electrically coupled to a system high voltage terminal. The driving transistor is used to control a driving current provided to a light emitting element. A first end of the storage capacitor is electrically coupled to a gate terminal of the driving transistor. A first end of the first transistor is electrically coupled to a second end of the storage capacitor, and a second end of the first transistor is used to receive a data signal. The second transistor is electrically coupled between a second end and the gate terminal of the driving transistor. A first end of the third transistor is used to receive a first reference voltage, and a second end of the third transistor is electrically coupled to the second end of the storage capacitor. The fourth transistor is electrically coupled between the second end of the driving transistor and a system low voltage terminal. A first end of the fifth transistor is used to receive a second reference voltage. A first end of the reset capacitor is electrically coupled to a second end of the fifth transistor, and a second end of the reset capacitor is electrically coupled to the gate terminal of the driving transistor.

[0006] In summary, the driving circuit of the present disclosure provides a reset operation, and a path from the system high voltage terminal to the reference voltage terminal is electrically isolated during the reset operation, thereby avoiding the generation of a leakage current in the reset operation of the driving transistor, and reducing power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0007] In order to make the above and other purposes, features, advantages and embodiments of the present disclosure more obvious and easy to understand, the following describes the attached drawings, symbols and the like:

[0008] Figure 1 A schematic diagram of a driving circuit according to some embodiments of the present disclosure.

[0009] Figure 2A A schematic diagram of a driving circuit according to some embodiments of the present disclosure.

[0010] Figure 2B A timing diagram of waveforms of signals and voltages of nodes according to some embodiments of the present disclosure.

[0011] Figure 3A A schematic diagram of a driving circuit according to some embodiments of the present disclosure.

[0012] Figure 3B A timing diagram of waveforms of signals according to some embodiments of the present disclosure.

[0013] Figure 4A A schematic diagram of a driving circuit according to some embodiments of the present disclosure.

[0014] Figure 4B A schematic diagram of a driving circuit according to some embodiments of the present disclosure.

[0015] In the drawings, the following symbols are used:

[0016] 100[n], 200[n], 300[n], 400[n]: drive circuit

[0017] 110, 210, 310: reset and data set circuit

[0018] 410: data set circuit

[0019] 420: reset circuit

[0020] Td: drive transistor

[0021] T1: first transistor

[0022] T2: second transistor

[0023] T3: third transistor

[0024] T4: fourth transistor

[0025] T53, T54: fifth transistor

[0026] L1: light emitting element

[0027] Cst: storage capacitor

[0028] DATA: data signal

[0029] S[n], S[n-1]: control signal EM[n]: light emission control signal

[0030] OVDD: system high voltage terminal

[0031] OVSS: system low voltage terminal Vp, Vn: reference voltage

[0032] P RD : reset and data set period

[0033] P PRE : precharge period

[0034] P R ,P RES : reset period

[0035] P D : data set period

[0036] P COM : compensation period

[0037] P C : threshold voltage compensation period

[0038] P EM : light emission period

[0039] Vprc : pre-charge voltage

[0040] V res : reset voltage

[0041] Vdata[n]~Vdata[n+3]: data voltage DETAILED DESCRIPTION

[0042] The following detailed description is provided to enable any person skilled in the art to make and use the disclosure. Various modifications to the embodiments described in this disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other embodiments without the use of the innovation. Thus, the present disclosure is not intended to be limited to the embodiments described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein. The structure and operation of the various embodiments are described in detail below, but the description provided is not intended to be limiting. Any structure that results from recombination of elements, which produces an apparatus having equivalent functionality, is within the scope of the disclosure. In addition, the drawings are not drawn to scale. For ease of understanding, the same reference numbers will be used across various drawings to refer to the same or like parts.

[0043] As used throughout this description, the following words or phrases have the meanings indicated: "includes," "comprising," "having," "containing," "involving," and "decomprising," "including," "containing," "embodying," "comprise,” “comprising,” “having,” “including,” “contain” and variants thereof as used herein, are meant to be open ended terms that specifically permit the inclusion of one or more elements. It will be understood by those within the art that any method, system and composition described herein can include additional or fewer steps, procedures, acts, elements, components, and / or in a different order, and / or using one or more variations of those described herein. Making additional changes can be undertaken in accordance with this disclosure. The elements in which described implemented with the structure, operation, sequence of acts or the like is not meant to be a limitation on the disclosure. Various modifications can be made to the embodiments described in this disclosure without departing from the spirit and scope of the disclosure, which is defined by the appended claims.

[0044] Referring to Figure 1 , Figure 1 is a schematic diagram of a driving circuit 100[n] according to some embodiments of the disclosure. As shown in Figure 1 , the driving circuit 100[n] includes a driving transistor Td, a second transistor T2, a third transistor T3, a fourth transistor T4, a storage capacitor Cst, a reset and data setting circuit 110, and a light emitting element L1. In some embodiments, the driving circuit 100[n] can be a sub-pixel driving circuit of a pixel in a pixel array of a display, and where "n" represents the nth column of pixels in the pixel array, the driving circuit 100[n] refers to a sub-pixel circuit in the nth column of pixels. In some embodiments, the light emitting element L1 can be implemented by a micro light emitting diode. In other embodiments, the light emitting element L1 can be implemented by a light emitting diode of other sizes, for example, a sub-millimeter light emitting diode. Thus, the disclosure is not limited thereto.

[0045] In some embodiments, the voltage change transmitted by the reset and data setting circuit 110 will change the potential of the gate terminal of the driving transistor Td to an enabling level through the capacitive coupling effect of the storage capacitor Cst to perform the reset operation.

[0046] In some embodiments, the control signal S[n] is applied to the second transistor T2 to compensate for a threshold voltage of the drive transistor Td.

[0047] In some embodiments, the emission control signal EM[n] is applied to the fourth transistor T4 to turn on a current path between a drain terminal of the drive transistor Td and a system low voltage terminal OVSS. The drive transistor Td is disposed on the current path of a drive current flowing from a system high voltage terminal OVDD to the system low voltage terminal OVSS, such that the drive transistor Td controls a magnitude of the drive current according to a potential of a gate terminal thereof. The light emitting element L1 is disposed on the current path of the drive current. The aforementioned drive current is used to provide light emission of the light emitting element L1.

[0048] The aforementioned transistors each have a first terminal, a second terminal, and a gate terminal (Gate). When the first terminal of one of the transistors is a drain terminal (a source terminal), the second terminal of the transistor is a source terminal (a drain terminal). In addition, the aforementioned capacitors each have a first terminal and a second terminal.

[0049] In terms of architecture, the drive transistor Td, the fourth transistor T4, and the light emitting element L1 are electrically connected in series between the system high voltage terminal OVDD and the system low voltage terminal OVSS. In some embodiments, the drive transistor Td is electrically coupled between the system high voltage terminal OVDD and the system low voltage terminal OVSS. In some embodiments, the first terminal of the drive transistor Td is electrically coupled to the system high voltage terminal OVDD.

[0050] In some embodiments, the fourth transistor T4 is electrically coupled between the drive transistor Td and the light emitting element L1. In some embodiments, the first terminal of the fourth transistor T4 is electrically coupled to the second terminal of the drive transistor Td, and the second terminal of the fourth transistor T4 is electrically coupled to the first terminal of the light emitting element L1. In some embodiments, the gate terminal of the fourth transistor T4 is configured to receive the emission control signal EM[n].

[0051] In some embodiments, the light emitting element L1 is electrically coupled between the fourth transistor T4 and the system low voltage terminal OVSS. In some embodiments, the first terminal of the light emitting element L1 is electrically coupled to the second terminal of the fourth transistor T4, and the second terminal of the light emitting element L1 is electrically coupled to the system low voltage terminal OVSS.

[0052] In some embodiments, the second transistor T2 is electrically coupled between the gate terminal of the drive transistor Td and the second terminal of the drive transistor Td. In some embodiments, the first terminal of the second transistor T2 is electrically coupled to the gate terminal of the drive transistor Td, and the second terminal of the second transistor T2 is electrically coupled to the second terminal of the drive transistor Td. In some embodiments, the gate terminal of the second transistor T2 is configured to receive the control signal S[n].

[0053] In some embodiments, the first terminal of the third transistor T3 is configured to receive a reference voltage Vp, and the second terminal of the third transistor T3 is electrically coupled to the second terminal of the storage capacitor Cst. In some embodiments, the gate terminal of the third transistor T3 is configured to receive an emission control signal EM[n]. In some embodiments, the emission control signal EM[n] is a row-by-row scanning signal. In other embodiments, the emission control signal EM[n] is a global scanning signal, without limitation.

[0054] Please refer to Figure 2A . Figure 2A A schematic diagram of a driving circuit 200[n] according to some embodiments of the present disclosure is shown. In some embodiments, the driving circuit 200[n] corresponds to the driving circuit 100[n] in Figure 1 . As shown in Figure 2A , the driving circuit 200[n] includes a driving transistor Td, a second transistor T2, a third transistor T3, a fourth transistor T4, a storage capacitor Cst, a reset and data setting circuit 110, and a light emitting element L1.

[0055] In some embodiments, the reset and data setting circuit 110 includes a first transistor T1. Specifically, the first terminal of the first transistor T1 is electrically coupled to the second terminal of the storage capacitor Cst, and the second terminal of the first transistor T1 is configured to receive a data signal DATA. In some embodiments, the gate terminal of the first transistor T1 is configured to receive a control signal S[n]. In some embodiments, the node N1 represents a junction of the first terminal of the first transistor T1, the second terminal of the storage capacitor Cst, and the second terminal of the third transistor T3.

[0056] Please refer to Figure 2A and Figure 2B . Figure 2B A timing diagram of waveforms of signals and voltages of nodes according to some embodiments of the present disclosure is shown. As shown in Figure 2B , one display period in the control timing of the driving circuit 200[n] can be divided into two periods, which are a reset and data setting period P RD and a light emitting period P EM . It should be particularly noted that the time lengths of the periods in Figure 2B are merely used for example, and are not used to limit the present disclosure.

[0057] Specifically, the control signal S[n] has a first logic level (e.g., an enabling level / low logic level) during the reset and data setting period P RD , and the control signal S[n] has a second logic level (e.g., a disabling level / high logic level) during the light emitting period P EM . The emission control signal EM[n] has a first logic level (e.g., an enabling level / low logic level) during the reset and data setting period PRD has a second logic level (e.g., disable level / high logic level); the light emission control signal EM[n] has the second logic level during the light emission period P EM has a first logic level (e.g., enable level / low logic level).

[0058] In some embodiments, during the reset and data set periods P RD includes a pre-charge period P PRE , a reset period P R , and a data set period P D .

[0059] In some embodiments, the data signal DATA is provided by a driver (not shown), and the driver includes a source driver and a multiplexing circuit. In some embodiments, the driver provides a pre-charge voltage V PRE as the data signal DATA during the pre-charge period P prc . In some embodiments, at the end of the pre-charge period P PRE and entering the reset period P R , the driver pulls down the pre-charge voltage V prc to a reset voltage V res , and provides the reset voltage V R as the data signal DATA during the reset period P res . In some embodiments, the length of the reset period P R is set to 1 microsecond, which can fully compensate for the threshold voltage of the driving transistor Td, and the compensation current can reach the order of microamperes. In some embodiments, the length of the reset period P R may be set to be greater than or equal to 1 microsecond, without being limited thereto. In some embodiments, the reset voltage V res may be set to 2 volts. In some embodiments, the driver provides a data voltage Vdata[n] during the data set period P D . In some embodiments, the amplitudes of the pre-charge voltage V prc and the reset voltage V res are within the value range of the voltage output of the source driver, and the source driver can output the pre-charge voltage V prc and the reset voltage V res . In some embodiments, the source driver outputs the pre-charge voltage V PRE as the data signal DATA during the pre-charge period P prc . In some embodiments, the source driver can pull down the pre-charge voltage V prc to the reset voltage V res and provide the reset voltage V R during the reset period P resis output as a data signal DATA. In some embodiments, a pre-charge voltage V prc A lower limit of voltage output of the source driver can be set, and a pre-charge voltage V res An upper limit of voltage output of the source driver can be set. In other embodiments, a pre-charge voltage V prc and a reset voltage V res Other values can be set, and the present application is not limited thereto. In some embodiments, each of the data voltages Vdata[n]~Vdata[n+3] of the data signal DATA is preceded by a pre-charge voltage V prc and a reset voltage V res to provide a reset operation to the driving circuit of the corresponding pixel. In some embodiments, a pre-charge voltage V prc , a reset voltage V res and data voltages Vdata[n]~Vdata[n+3] are provided by the source driver, and a connection multiplexing circuit is provided between the source driver and the data line to transmit the pre-charge voltage V prc , the reset voltage V res and the data voltage Vdata[n] to the driving circuit 200[n] through the multiplexing circuit in one or more corresponding time intervals.

[0060] During the reset and data setting periods P RD , the pre-charge period P PRE , the reset period P R and the data setting period P D , the first transistor T1 and the second transistor T2 are turned on according to the control signal S[n], and the third transistor T3 and the fourth transistor T4 are turned off according to the emission control signal EM[n]. In some embodiments, the first transistor T1 is turned on according to the control signal S[n] to transmit the data signal DATA to the second end of the storage capacitor Cst. In some embodiments, the second transistor T2 is turned on according to the control signal S[n] to electrically connect the gate end of the driving transistor Td to the second end of the driving transistor Td.

[0061] During the pre-charge period P PRE , the pre-charge voltage V prc of the data signal DATA is transmitted to the second end ( / node N1) of the storage capacitor Cst through the first transistor T1.

[0062] When the pre-charge period P PRE ends and enters the reset period P R , the pre-charge voltage V prc of the data signal DATA is pulled down to the reset voltage V res. At this time, the voltage variation AV of the data signal DATA, which refers to the difference between the pre-charge voltage V prc and the reset voltage V res , is transmitted to the gate terminal of the drive transistor Td through the capacitive coupling effect of the storage capacitor Cst. Thus, during the reset period P R , when the first transistor Tl is turned on according to the control signal S[n], the storage capacitor Cst changes the potential of the gate terminal of the drive transistor Td according to the voltage variation AV of the data signal DATA through the capacitive coupling effect, and then resets the voltage of the gate terminal of the drive transistor Td.

[0063] During the reset period P R , when the potential of the gate terminal of the drive transistor Td drops to the low logic level based on the voltage variation AV, the drive transistor Td is turned on and conducts the current path from the system high voltage terminal OVDD to the gate terminal of the drive transistor Td via the drive transistor Td, the second transistor T2, until the drive transistor Td is turned off, thereby compensating for the threshold voltage of the drive transistor Td. In some embodiments, the time during which the drive transistor Td performs the threshold voltage compensation operation can be represented by the reset period P R . In some embodiments, the threshold voltage compensation period P c overlaps with the reset period P R , and the threshold voltage compensation period P c extends to the data set period P D , and overlaps with the partial data set period P D .

[0064] During the data set period P D , the data voltage Vdata[n] of the data signal DATA is transmitted to the second terminal ( / node Nl) of the storage capacitor Cst. In some embodiments, when the voltage of the data signal DATA changes from the reset voltage V res to the data voltage Vdata[n], the data voltage Vdata[n] does not affect the potential of the gate terminal of the drive transistor Td because the drive transistor Td is still turned on and performs the threshold voltage compensation operation.

[0065] At the end of the threshold voltage compensation period P c of the drive transistor Td, the potential of the gate terminal of the drive transistor Td is substantially equal to (OVDD-Vth), where Vth represents the threshold voltage of the drive transistor Td, and OVDD represents the potential of the system high voltage terminal OVDD. At this time, the potential of the second terminal of the storage capacitor Cst is substantially equal to the data voltage Vdata[n].

[0066] During the light emission period P EM, the first transistor T1 and the second transistor T2 are turned off according to the control signal S[n], and the third transistor T3 and the fourth transistor T4 are turned on according to the light emission control signal EM[n]. In some embodiments, the third transistor T3 is turned on according to the light emission control signal EM[n] to transmit the reference voltage Vp to the second end ( / node N1) of the storage capacitor Cst. That is, when the third transistor T3 is turned on, the potential of the second end ( / node N1) of the storage capacitor Cst changes from the data voltage Vdata[n] to the reference voltage Vp, and this change is transmitted to the gate end of the driving transistor Td through the storage capacitor Cst, so that the potential of the gate end of the driving transistor Td carries the information of the data voltage Vdata[n]. At this time, the potential of the gate end of the driving transistor Td is substantially equal to [(OVDD-Vth)+(Vp-Vdata[n])]. Thus, during the light emission period P EM , the third transistor T3 is turned on according to the light emission control signal EM to couple the difference between the reference voltage Vp and the data voltage Vdata[n] to the gate end of the driving transistor Td through the storage capacitor Cst by the capacitive coupling effect.

[0067] , during the light emission period P EM , the fourth transistor T4 is turned on according to the light emission control signal EM[n] to drive the current from the system high voltage end OVDD, through the driving transistor Td, the fourth transistor T4, the light emitting element L1, to the system low voltage end OVSS. Thus, during the light emission period P EM , the driving current controlled by the driving transistor Td based on the potential of the gate end thereof can be provided to the light emitting element L1 to emit light, and the amplitude of the driving current provided to the light emitting element L1 to emit light is related to the potential [(OVDD-Vth)+(Vp-Vdata[n])] of the gate end of the driving transistor Td.

[0068] Please refer to Figure 3A . Figure 3A is a schematic diagram of a driving circuit 300[n] according to some embodiments of the present disclosure. In some embodiments, the driving circuit 300[n] corresponds to the driving circuit 100[n] in Figure 1 . As shown in Figure 3A , the driving circuit 300[n] includes a driving transistor Td, a second transistor T2, a third transistor T3, a fourth transistor T4, a storage capacitor Cst, a reset and data setting circuit 310, and a light emitting element L1. The circuit structure between the driving transistor Td, the second transistor T2, the third transistor T3, the fourth transistor T4, the storage capacitor Cst, and the light emitting element L1 of the driving circuit 300[n] is similar to that of the driving circuit 100[n] in Figure 1The circuit architecture among the driving transistor Td, the second transistor T2, the third transistor T3, the fourth transistor T4, the storage capacitor Cst, and the light emitting element L1 in the driving circuit 100[n] is not described in detail herein.

[0069] The reset and data setting circuit 310 includes a first transistor T1 and a fifth transistor T53. Specifically, a first end of the first transistor T1 is electrically coupled to a second end of the storage capacitor Cst, and a second end of the first transistor T1 is configured to receive a data signal DATA. A first end of the fifth transistor T53 is electrically coupled to the second end of the storage capacitor Cst, and a second end of the fifth transistor T53 is configured to receive a reference voltage Vn. In some embodiments, the reference voltage Vn is a negative voltage.

[0070] In some embodiments, a gate end of the first transistor T1 is configured to receive a control signal S[n], and a gate end of the fifth transistor T53 is configured to receive a control signal S[n-1]. In some embodiments, the control signal S[n] is a control signal provided to the current stage driving circuit 300[n], and the control signal S[n-1] is a control signal provided to a previous stage driving circuit or a driving circuit in a previous column of pixels. In other embodiments, the control signals S[n] and S[n-1] are not related to the previous and next stages, and the present disclosure is not limited thereto.

[0071] Please refer to Figure 3A and Figure 3B . Figure 3B is a timing diagram of waveforms of signals according to some embodiments of the present disclosure. As shown in Figure 3B , one display period in the control timing of the driving circuit 300[n] can be divided into three periods, which are a reset period P RES , a compensation period P COM , and a light emitting period P EM . It should be particularly noted that Figure 3B the time lengths of the periods in the present disclosure are only used for example, and are not used for limitation.

[0072] Specifically, the control signal S[n-1] has a first logic level (e.g., an enabling level / low logic level) in the reset period P RES , and has a second logic level (e.g., a disabling level / high logic level) in the compensation period P COM and the light emitting period P EM . The control signal S[n] has the first logic level (e.g., the enabling level / low logic level) in the compensation period P COM , and has the second logic level (e.g., the disabling level / high logic level) in the reset period P RES and the light emitting period P EMhas the second logic level (e.g., the disable level / high logic level). The light emission control signal EM[n] has the first logic level (e.g., the enable level / low logic level) during the light emission period P EM has the first logic level (e.g., the enable level / low logic level); the light emission control signal EM[n] has the second logic level (e.g., the disable level / high logic level) during the reset period P RES and the compensation period P COM has the second logic level (e.g., the disable level / high logic level).

[0073] During the reset period P RES , the fifth transistor T53 is turned on according to the control signal S[n-1], the first transistor T1 and the second transistor T2 are turned off according to the control signal S[n], and the third transistor T3 and the fourth transistor T4 are turned off according to the light emission control signal EM[n]. In some embodiments, the fifth transistor T53 is turned on according to the control signal S[n-1] to transmit the reference voltage Vn to the second terminal of the storage capacitor Cst. In some embodiments, the potential of the reference voltage Vp is higher than that of the reference voltage Vn. After the end of the light emission operation of the previous display period, the potential of the second terminal of the storage capacitor Cst is substantially equal to that of the reference voltage Vp. In some embodiments, in the current display period, when the fifth transistor T53 is turned on, the potential of the second terminal of the storage capacitor Cst changes from the reference voltage Vp to the reference voltage Vn, and this change is transmitted to the gate terminal of the driving transistor Td through the storage capacitor Cst to perform the reset operation. At this time, the gate terminal of the driving transistor Td is at the enable level, so that the driving transistor Td is turned on.

[0074] Thus, during the reset period P RES , the fifth transistor T53 is turned on according to the first control signal S[n-1] to transmit the difference between the reference voltage Vn and the reference voltage Vp to the gate terminal of the driving transistor Td through the storage capacitor Cst by the capacitive coupling effect.

[0075] During the compensation period P COM , the first transistor T1 and the second transistor T2 are turned on according to the control signal S[n], the fifth transistor T53 is turned off according to the control signal S[n-1], and the third transistor T3 and the fourth transistor T4 are turned off according to the light emission control signal EM[n]. In some embodiments, the first transistor T1 is turned on according to the control signal S[n] to transmit the data voltage of the data signal DATA to the second terminal of the storage capacitor Cst. In some embodiments, the second transistor T2 is turned on according to the control signal S[n] to transmit the potential of the system high voltage terminal OVDD to the gate terminal of the driving transistor Td through the driving transistor Td and the second transistor T2 until the driving transistor Td is turned off, thereby performing the compensation operation. At this time, the potential of the gate terminal of the driving transistor Td is substantially equal to (OVDD-Vth).

[0076] During the compensation period P COM , the third transistor T3 and the fourth transistor T4 are turned on according to the emission control signal EM[n], the first transistor T1 and the second transistor T2 are turned off according to the control signal S[n], and the fifth transistor T53 is turned off according to the control signal S[n-1]. In some embodiments, the third transistor T3 is turned on according to the emission control signal EM[n] to change the potential of the second terminal of the storage capacitor Cst from the data voltage to the reference voltage Vp, and this change is transmitted to the gate terminal of the driving transistor Td through the storage capacitor Cst, so that the potential of the gate terminal of the driving transistor Td is substantially equal to [(OVDD-Vth)+(Vp-Vdata)], where Vdata represents the data voltage. Thus, during the emission period P EM , the third transistor T3 is turned on according to the emission control signal EM[n] to couple the difference between the reference voltage Vp and the data voltage to the gate terminal of the driving transistor Td through the storage capacitor Cst by the capacitive coupling effect.

[0077] Also, during the emission period P EM , the fourth transistor T4 is turned on according to the emission control signal EM[n] to drive the current from the system high voltage terminal OVDD, through the driving transistor Td, the fourth transistor T4, the light emitting element L1, to the system low voltage terminal OVSS. Thus, during the emission period P EM , the driving current controlled by the driving transistor Td based on the potential of the gate terminal thereof can be provided to the light emitting element L1 to emit light, and the amplitude of the driving current provided to the light emitting element L1 to emit light is related to the potential of the gate terminal of the driving transistor Td [(OVDD-Vth)+(Vp-Vdata[n])].

[0078] Please refer to Figure 4A . Figure 4A for a driving circuit 400[n] according to some embodiments of the present disclosure. As shown in Figure 4A , the driving circuit 400[n] includes the driving transistor Td, the second transistor T2, the third transistor T3, the fourth transistor T4, the storage capacitor Cst, the data setting circuit 410, the reset circuit 420, and the light emitting element L1. The circuit architecture of the driving transistor Td, the second transistor T2, the third transistor T3, the fourth transistor T4, the storage capacitor Cst, and the light emitting element L1 in the driving circuit 400[n] is similar to the circuit architecture of the driving transistor Td, the second transistor T2, the third transistor T3, the fourth transistor T4, the storage capacitor Cst, and the light emitting element L1 in the driving circuit 300[n] of Figure 3A , which will not be described again here.

[0079] In some embodiments, the data setting circuit 410 includes a first transistor Tl. A first terminal of the first transistor Tl is electrically coupled to a second terminal of the storage capacitor Cst, and a second terminal of the first transistor Tl is configured to receive the data signal DATA. In some embodiments, a gate terminal of the first transistor Tl is configured to receive the control signal S[n].

[0080] Referring to Figure 4A and Figure 4B . Figure 4B is a schematic diagram of a driving circuit 400[n] according to some embodiments of the present disclosure. As shown in Figure 4B , the reset circuit 420 includes a fifth transistor T54 and a reset capacitor Cr. A first terminal of the fifth transistor T54 is configured to receive the reference voltage Vn. In some embodiments, a first terminal of the reset capacitor Cr is electrically coupled to a second terminal of the fifth transistor T54, and a second terminal of the reset capacitor Cr is electrically coupled to a gate terminal of the driving transistor Td.

[0081] Figure 4B The driving circuit 400[n] in Figure 3B is suitable for the operation timing of the control signal in Figure 3B , Figure 4A and Figure 4B . One display period in the control timing of the driving circuit 400[n] can be divided into three periods, which are a reset period P RES , a compensation period P COM and a light emitting period P EM .

[0082] In the reset period P RES , the fifth transistor T54 is turned on according to the control signal S[n-1], the first transistor Tl and the second transistor T2 are turned off according to the control signal S[n], and the third transistor T3 and the fourth transistor T4 are turned off according to the light emitting control signal EM[n]. In some embodiments, the fifth transistor T54 is turned on according to the control signal S[n-1] to transmit the reference voltage Vn to the second terminal of the storage capacitor Cst. In some embodiments, the reference voltage Vn is a negative voltage. After the light emitting operation of the previous display period ends, the potential of the gate terminal of the driving transistor Td is substantially equal to [(VDD-Vth)+(Vp-Data)], which is a positive value, greater than the reference voltage Vn. Therefore, when the fifth transistor T54 is turned on, the reference voltage Vn can be coupled downward through the reset capacitor Cr to achieve the reset operation.

[0083] Thus, in the reset period P RESThe fifth transistor T54 is turned on according to the first control signal S[n-1], so that the storage capacitor Cst changes the voltage at the second terminal thereof according to the voltage at the first terminal thereof, and resets the voltage at the gate terminal of the driving transistor Td through the capacitive coupling effect.

[0084] During the compensation period P COM The first transistor T1 and the second transistor T2 are turned on according to the control signal S[n], the fifth transistor T54 is turned off according to the control signal S[n-1], and the third transistor T3 and the fourth transistor T4 are turned off according to the light emission control signal EM[n]. In some embodiments, the first transistor T1 is turned on according to the control signal S[n] to transmit the data voltage of the data signal DATA to the second terminal of the storage capacitor Cst. In some embodiments, the second transistor T2 is turned on according to the control signal S[n] to transmit the potential of the system high voltage terminal OVDD to the gate terminal of the driving transistor Td through the driving transistor Td and the second transistor T2 until the driving transistor Td is turned off, thereby performing the compensation operation. At this time, the potential of the gate terminal of the driving transistor Td is substantially equal to (OVDD-Vth).

[0085] During the light emission period P EM The third transistor T3 and the fourth transistor T4 are turned on according to the light emission control signal EM[n], the first transistor T1 and the second transistor T2 are turned off according to the control signal S[n], and the fifth transistor T54 is turned off according to the control signal S[n-1]. In some embodiments, the third transistor T3 is turned on according to the light emission control signal EM[n] to change the potential of the second terminal of the storage capacitor Cst from the data voltage to the reference voltage Vp, and this change is transmitted to the gate terminal of the driving transistor Td through the storage capacitor Cst, so that the potential of the gate terminal of the driving transistor Td is substantially equal to [(OVDD-Vth)+(Vp-Vdata)], where Vdata represents the data voltage. Thus, during the light emission period P EM The third transistor T3 is turned on according to the light emission control signal EM to couple the difference between the reference voltage Vp and the data voltage to the gate terminal of the driving transistor Td through the capacitive coupling effect of the storage capacitor Cst.

[0086] Furthermore, during the light emission period P EM The fourth transistor T4 is turned on according to the light emission control signal EM[n] to drive the current from the system high voltage terminal OVDD to the system low voltage terminal OVSS through the current path of the driving transistor Td, the fourth transistor T4, and the light emitting element L1. Thus, during the light emission period P EMThe drive current controlled by the drive transistor Td based on the potential of the gate terminal thereof can be supplied to the light emitting element L1 to emit light, and the amplitude of the drive current supplied to the light emitting element L1 to emit light is related to the potential [(OVDD-Vth)+(Vp-Vdata[n])] of the gate terminal of the drive transistor Td.

[0087] In summary, the drive circuit 100[n], 200[n] and 300[n] of the present disclosure provides a reset operation. The drive circuit 100[n] omits the path of the system high voltage terminal OVDD to the reference voltage Vn, and the paths of the system high voltage terminal OVDD to the reference voltage Vn of the drive circuit 200[n] and 300[n] are shorted during the reset period P RES Electrically isolated. In this way, the drive circuit 100[n], 200[n] and 300[n] can avoid generating a leakage current in the reset operation, thereby reducing power consumption.

[0088] Although the present disclosure has been disclosed with the implementation as above, it is not intended to limit the present disclosure, and any person with ordinary skill in the art can make various modifications and decorations without departing from the spirit and scope of the present disclosure, and therefore the protection scope of the present disclosure shall be subject to the appended claims.

Claims

1. A drive circuit characterized by comprising: Comprising: a driving transistor having a first end electrically coupled to a system high voltage terminal, wherein the driving transistor is used to control a driving current provided to a light emitting element; a storage capacitor having a first end electrically coupled to a gate terminal of the driving transistor; a first transistor having a first end electrically coupled to a second end of the storage capacitor and a second end used to receive a data signal; a second transistor electrically coupled between a second end and the gate terminal of the driving transistor; a third transistor having a first end used to receive a reference voltage and a second end electrically coupled to the second end of the storage capacitor; and a fourth transistor electrically coupled between the second end of the driving transistor and a system low voltage terminal, wherein, when the first transistor is turned on according to a first control signal, the storage capacitor resets a voltage of the gate terminal of the driving transistor according to a voltage variation of the data signal through a capacitive coupling effect; the voltage variation of the data signal is a variation between a pre-charge voltage and a reset voltage. During a compensation period, the second transistor is turned on according to the first control signal to electrically connect the second end of the driving transistor to the gate terminal of the driving transistor, so that a voltage of the system high voltage terminal is transmitted to the gate terminal of the driving transistor through the driving transistor and the second transistor until the driving transistor is turned off.

2. The drive circuit of claim 1, wherein During a data setting period, the first transistor is turned on according to a first control signal and a data voltage of the data signal is transmitted to the second end of the storage capacitor.

3. The drive circuit of claim 1, wherein During a light emitting period, the third transistor is turned on according to a light emitting control signal to couple a difference between the reference voltage and the data voltage to the gate terminal of the driving transistor through the storage capacitor by a capacitive coupling effect.

4. The drive circuit of claim 3, wherein During a light emitting period, the fourth transistor is turned on according to a light emitting control signal and the second end of the driving transistor is electrically connected to the system low voltage terminal, so that the driving current flows from the system high voltage terminal to the system low voltage terminal through the driving transistor and the fourth transistor.

5. The drive circuit of claim 1, wherein, Comprising:

6. A drive circuit, characterized by a driving transistor having a first end electrically coupled to a system high voltage terminal, wherein the driving transistor is used to control a driving current provided to a light emitting element; a storage capacitor having a first end electrically coupled to a gate terminal of the driving transistor; a first transistor having a first end electrically coupled to a second end of the storage capacitor and a second end used to receive a data signal; a second transistor electrically coupled between a second end and the gate terminal of the driving transistor; a third transistor having a first end used to receive a first reference voltage and a second end electrically coupled to the second end of the storage capacitor; a fourth transistor electrically coupled between the second end of the driving transistor and a system low voltage terminal; and a fifth transistor having a first end electrically coupled to the second end of the storage capacitor and a second end used to receive a second reference voltage; During a reset period, the fifth transistor is turned on according to a first control signal to couple a difference between the second reference voltage and the first reference voltage to the gate terminal of the driving transistor through the storage capacitor by a capacitive coupling effect. Comprising:

7. A drive circuit, characterized by ​ a driving transistor, a first end of which is electrically coupled to a system high voltage terminal, wherein the driving transistor is used to control a driving current provided to a light emitting element; a storage capacitor, a first end of which is electrically coupled to a gate terminal of the driving transistor; a first transistor, a first end of which is electrically coupled to a second end of the storage capacitor, and a second end of which is used to receive a data signal; a second transistor, which is electrically coupled between a second end and the gate terminal of the driving transistor; a third transistor, a first end of which is used to receive a first reference voltage, and a second end of which is electrically coupled to the second end of the storage capacitor; a fourth transistor, which is electrically coupled between the second end of the driving transistor and a system low voltage terminal; a fifth transistor, a first end of which is used to receive a second reference voltage; and a reset capacitor, a first end of which is electrically coupled to a second end of the fifth transistor, and a second end of which is electrically coupled to the gate terminal of the driving transistor; during a reset period, the fifth transistor is turned on according to a first control signal, so that the storage capacitor changes a voltage at the first end thereof, and the gate terminal of the driving transistor is reset by a capacitive coupling effect. ​

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