A method for forwarding a protocol packet of a multi-core switch stack and a stack system

Abstract

The application discloses a multi-core switch stack protocol message forwarding method and a stack system. The stack system comprises: a first multi-core switch having a first stack protocol CPU core and a first stack protocol memory; a first stack protocol message transceiving special channel is arranged in a CPU transceiving message channel of the first multi-core switch; the first stack protocol CPU core is used for processing stack protocol tasks independently, and the first stack protocol memory is used for storing stack protocol messages independently; the priority of the first stack protocol message transceiving special channel is higher than that of other channels; a second multi-core switch having a second stack protocol CPU core and a second stack protocol memory; a second stack protocol message transceiving special channel is arranged in a CPU transceiving message channel of the second multi-core switch; the second stack protocol CPU core is used for processing stack protocol tasks independently, and the second stack protocol memory is used for storing stack protocol messages independently; and the priority of the second stack protocol message transceiving special channel is higher than that of other channels.

Description

Technical Field

[0001] This invention belongs to the field of stacking protocol message forwarding technology, and specifically relates to a method and system for forwarding stacking protocol messages in multi-core switches. Background Technology

[0002] Stacking technology virtualizes a group of devices into a single device for management and maintenance, thereby simplifying the topology and facilitating maintenance. A stacking system consists of one master device, one backup device, and multiple slave devices. The backup device, slave devices, and master device interact through stacking protocol messages, which communicate via the stacking port.

[0003] There are two ways to implement stacking ports on a switch. The first is to reserve a dedicated stacking port on the device and use a dedicated stacking cable for connection. The link only forwards stacking protocol packets, such as... Figure 1 As shown.

[0004] The second approach involves directly converting the panel service ports into stacking ports on existing switch equipment, using universal cables for connection. There are no hardware changes; this is achieved through software. Figure 2 As shown.

[0005] Stacking protocol messages, network protocol messages, and data messages are all forwarded on the primary channel. When the primary channel fails, communication can switch to the backup channel, thus improving the stability of the stacking system. Since the first method requires hardware upgrades, which is too costly, most equipment manufacturers currently use the second method. For example, Cisco's VSS function and H3C's IRF function both use the second method for connection.

[0006] The joining, leaving, splitting, and merging of devices in a stacking system are achieved through stacking protocol messages. Especially when the master device fails, the backup device needs to be able to quickly detect the failure via stacking protocol messages, switch over to become the master device, and take over the entire stacking system, enabling customers to quickly resume normal operations. To achieve this, the stacking protocol messages must have the shortest possible latency to avoid packet loss. Otherwise, if there is latency or packet loss in the stacking protocol messages, the stacking system may fail to establish itself successfully, or false alarms of stack splitting may occur, leading to instability in the stacking system.

[0007] From the current implementation of stacking systems, delays or packet loss in stacking protocol messages are still unavoidable. Specific reasons include:

[0008] (1) Since stacking protocol messages, network protocol messages, and data service traffic are all forwarded on the same physical link channel, when the network protocol messages or data service traffic is too large, it will cause stacking protocol messages to be lost or delayed.

[0009] (2) Since the stacking port and service port of the switch share a CPU resource, once the task processing on the service port occupies too much CPU resource, the task processing the stacking protocol message will not be able to obtain CPU resource, resulting in delay or packet loss.

[0010] (3) Since the service processing on the stacking port and service port of the switch shares a memory resource, the exhaustion of memory will cause the stacking protocol message to be unable to obtain the memory resource, which will result in the untimely sending and receiving of the stacking protocol message, causing delay or packet loss.

[0011] Existing solutions cannot solve this problem. For example, the patent application number "201710597638.1" entitled "A Stacking System Keep-alive Method and Stacking System" uses two stacking ports. One stacking port is dedicated to forwarding data packets and service protocol packets, and the other stacking port is dedicated to forwarding stacking keep-alive protocol packets. This method can solve the problem (1) and ensure that the stacking keep-alive packets are not limited by the bandwidth of the service data traffic, but it cannot solve the problems (2) and (3). At the same time, it will cause packet loss or delay of other stacking protocol packets besides the stacking keep-alive packets. Moreover, there are often backup links in the stacking system, so two more stacking ports need to be created, which multiplies the complexity of software processing. The patent application number "201310498992.0" entitled "A Stacking Separation Detection Scheme and Device" uses ping packets to detect stacking, but this method The method still cannot avoid the problem of packet loss or delay in ping packets; the patent application number "201210445352.9" "A method and device for rapid detection of stack split" uses BFD to detect splits. This method can solve problem 1 in detecting stack splits, but it does not solve problems (2) and (3). In addition, the stacking protocol messages of the stacking system are not only used to determine stack splits, but also require low latency and no packet loss in stacking protocol messages to quickly and correctly determine the addition and departure of stack members. The patent application number "201611094388.1" "Switch stacking system, slave device, switching chip and method for processing protocol messages" forwards protocol messages through chip hardware, which can speed up the processing efficiency of protocol messages, but it still cannot completely avoid the delay or packet loss caused by the above problems (1), (2), and (3). Summary of the Invention

[0012] The purpose of this invention is to overcome the shortcomings of the prior art and establish a "virtual private channel for stacking protocol messages" that can achieve millisecond-level forwarding of stacking protocol messages. Even when the stacking port is congested and customer services consume a large amount of CPU and memory, the stability of the stacking system can be guaranteed.

[0013] The technical solution provided by this invention is as follows:

[0014] A stacking system, comprising:

[0015] The first multi-core switch is equipped with a first stacking protocol CPU core and a first stacking protocol memory; the CPU transmit and receive message channel of the first multi-core switch is equipped with a dedicated channel for transmitting and receiving messages of the first stacking protocol.

[0016] The first stacking protocol CPU core is used to process stacking protocol tasks separately, and the first stacking protocol memory is used to store stacking protocol messages separately. The priority of the first dedicated channel for sending and receiving stacking protocol messages is higher than the priority of other channels in the CPU message sending and receiving channels of the first multi-core switch.

[0017] The second multi-core switch is equipped with a second stacking protocol CPU core and a second stacking protocol memory; the CPU transmit and receive message channel of the second multi-core switch is equipped with a dedicated channel for transmitting and receiving messages of the second stacking protocol.

[0018] The second stacking protocol CPU core is used to process stacking protocol tasks separately, and the second stacking protocol memory is used to store stacking protocol messages separately. The priority of the dedicated channel for sending and receiving messages of the second stacking protocol is higher than the priority of other channels in the CPU sending and receiving message channels of the second multi-core switch.

[0019] Preferably, the CPU data forwarding channel of the first multi-core switch is provided with a dedicated channel for forwarding first stacking protocol messages;

[0020] Among them, the priority of the first stacking protocol message forwarding dedicated channel is higher than the priority of other channels in the CPU data forwarding channel of the first multi-core switch;

[0021] The second multi-core switch has a dedicated channel for forwarding second stacking protocol packets in its CPU data forwarding channel;

[0022] Among them, the priority of the second stacking protocol message forwarding dedicated channel is higher than the priority of other channels in the CPU data forwarding channel of the second multi-core switch.

[0023] Preferably, the keep-alive time of the stacking system is set to 500ms.

[0024] A method for forwarding stacking protocol messages in a multi-core switch, wherein the CPU message receiving and processing process includes:

[0025] Set the stacking protocol message to the highest priority queue of the chip, and set the queue scheduling mode of the chip's CPU port to strict priority mode, so that the stacking protocol message will enter the DMA with priority over other messages, triggering the DMA interrupt;

[0026] In the DMA interrupt handler, the stack protocol message is placed into the stack message data queue, and the stack receiving task is notified to process it.

[0027] Set the CPU task scheduling mode to priority preemption mode so that the stack packet receiving task can preempt low-priority tasks in real time to occupy CPU resources, and retrieve stack protocol packets from the stack data queue for priority processing.

[0028] Memory is reserved for stacked packet receiving tasks, stacked packet data queues, and stacked protocol packets; and

[0029] Reserve CPU cores for stacked packet receiving tasks.

[0030] Preferably, the CPU message processing procedure includes:

[0031] Stacked protocol messages are placed in a stacked data queue and processed by a high-priority stacked packet sending task, which is locked onto a dedicated CPU core.

[0032] Set the CPU's task scheduling mode to priority preemption to ensure that stacking protocol messages are executed by the CPU first for chip packet sending.

[0033] Preferably, the chip sends packets in an asynchronous mode during the CPU's message processing.

[0034] The beneficial effects described in this invention are:

[0035] This invention constructs a virtual dedicated channel for stacking protocol messages, effectively solving the problems of latency and packet loss in stacking protocol messages. Even if other tasks exhaust their CPU and memory resources or the stacking port becomes congested, the establishment, splitting, addition, and removal of devices can still proceed normally. When the master device of the stacking system fails, the backup device can detect the master device's abnormality within 1 second through stacking protocol messages and perform master-slave failover to restore services. In this way, the requirements for millisecond-level fault recovery can be met without changing the existing topology and hardware facilities. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of the first type of switch stacking port implementation in the background technology.

[0037] Figure 2 This is a schematic diagram of the second type of switch stacking port implementation in the background technology.

[0038] Figure 3 This is a schematic diagram of the stacking system described in this invention.

[0039] Figure 4 This is a schematic diagram of the CPU message receiving and processing flow according to the present invention.

[0040] Figure 5 This is a schematic diagram of the CPU message sending process described in this invention. Detailed Implementation

[0041] The present invention will now be described in further detail with reference to the accompanying drawings, so that those skilled in the art can implement it based on the description.

[0042] This invention provides a method for forwarding stacking protocol packets in a multi-core switch, such as... Figure 3 As shown, multi-core switch A and multi-core switch B form a stacked system, and the stacked ports are interconnected to form a data forwarding channel.

[0043] On multi-core switch A and multi-core switch B, CPU cores are separately allocated for processing stacking protocol tasks, and separate memory resources are reserved for storing and forwarding stacking protocol packets. The remaining CPU cores and memory are used for other services. In this way, even if other services cause CPU cores to be busy or memory resources to be insufficient, there are still CPU and memory resources to prioritize the processing of stacking protocol packets.

[0044] In this embodiment, the CPU affinity provided by the Linux kernel is utilized to bind the processes and threads used for stacking protocol task processing to a specific CPU core, preventing other processes and threads from using this CPU core. During device startup, the software system dynamically allocates a memory pool for storing and forwarding stacking protocol packets; this memory is never released, thus preventing other applications from using it.

[0045] A dedicated channel is reserved on the CPU's message transmission and reception channels for processing stacking protocol messages, with a higher priority than other channels. This ensures that stacking protocol messages are sent and received before other messages. At the software level, multiple message queues are used, with the highest priority message queue reserved for stacking protocol messages. At the hardware chip level, the CPU has multiple channels for packet reception, and the software allocates the highest priority channel to stacking messages. Stacking messages have a unique identifier that distinguishes them from other messages.

[0046] In the data forwarding channel, a dedicated forwarding channel is reserved for stacking protocol messages, and the channel has a higher priority than the forwarding channels of other data messages. This ensures that even if the stacking port link is congested, the stacking protocol messages will be forwarded first, without delay or packet loss.

[0047] Stacked packets have special identifiers, such as ethertype and mac, which are privately defined. At the hardware chip level, there are multiple forwarding channels for a port, which have the function of setting priorities. In software, a stacked packet can be bound to a certain channel according to its identifier and the channel can be set as the highest priority. In this way, other protocol packets or service packets cannot use this channel.

[0048] In this embodiment, the keep-alive time of the stacking system is set to 500ms.

[0049] Through the above process, stacking protocol messages are always prioritized over other messages, thus creating a virtual dedicated channel for stacking protocol messages.

[0050] like Figure 4 As shown, the CPU message receiving and processing flow is as follows:

[0051] By leveraging the characteristics of the switching chip, stacking protocol messages are placed in the chip's highest priority queue, and the chip's CPU port queue scheduling mode is set to strict priority mode. This way, stacking protocol messages will enter the DMA before other messages, triggering a DMA interrupt.

[0052] In the DMA interrupt handler, the stack protocol message is placed into the stack message data queue, and the stack receiving task is notified to process it.

[0053] Set the CPU task scheduling mode to priority preemption mode. This way, the stacking packet receiving task will preempt low-priority tasks in real time to occupy CPU resources, retrieve stacking protocol packets from the stacking data queue, and process them first.

[0054] Memory is reserved for stacking packet receiving tasks, stacking message data queues, and stacking protocol messages. This ensures that even when memory resources are insufficient, there is still memory available to receive and process stacking protocol messages in a timely manner via DMA.

[0055] By reserving CPU cores for the stacking packet receiving task, even if other service message processing tasks occupy the remaining 100% of the CPU cores, it will not affect the stacking packet receiving task's processing of stacking protocol messages.

[0056] There should be no waiting in the stacked packet receiving task. The use of delay or lock is prohibited, otherwise it will cause the task to be delayed.

[0057] like Figure 5As shown, the CPU message processing flow is as follows:

[0058] Stacking protocol messages are placed in the stacking data queue and processed by high-priority stacking packet sending tasks. The stacking packet sending tasks are locked on a single CPU core, and the CPU's task scheduling mode is set to priority preemption. This ensures that stacking protocol messages will be executed by the CPU first for chip packet sending.

[0059] The chip sends packets in an asynchronous mode. It does not block and wait for the packet to be sent successfully. Instead, it returns immediately after sending. After the chip sends the packet, it generates an interrupt to notify the upper layer to release the memory space occupied by the packet.

[0060] Operations that are blocking or time-consuming, such as reading hardware or using locks, are prohibited in stacked packet sending tasks.

[0061] This invention leverages CPU affinity to dedicate the sending and receiving of stacking protocol messages to a single CPU core, while reserving memory resources for stacking protocol messages, stacking send / receive tasks, and stacking send / receive queues. CPU packet sending employs an asynchronous mode, with carefully planned channels to avoid service protocol messages and stacking protocol messages sharing the same channel. Furthermore, software read / write operations replace hardware chip read / write operations in the packet sending process, significantly improving overall packet sending performance. Stacking protocol messages are placed on the highest CPU queue of the switching chip, ensuring the switching chip prioritizes CPU scheduling for stacking protocol messages. Simultaneously, the software queues for stacking messages and service protocol messages are separated, and the stacking receive task is given the highest priority, ensuring the CPU prioritizes scheduling the stacking receive task. Additionally, the lock acquisition step for receive packets is removed to avoid prolonged lock waiting affecting receive performance. Stacking protocol messages are placed on the highest forwarding queue of each port, above the forwarding queues of other messages, ensuring that stacking protocol messages are prioritized for forwarding at the port forwarding layer.

[0062] The above technical solution can construct a virtual dedicated channel for stacking protocol messages. Testing revealed that the latency and packet loss issues of stacking protocol messages are effectively resolved. With the keep-alive time of the stacking system set to 500ms, even if other tasks exhaust their CPU and memory resources or the stacking port becomes congested, the establishment, splitting, addition, and removal of devices from the stack can proceed normally. When the primary device of the stacking system fails, the backup device can detect the primary device's anomaly within 1 second via stacking protocol messages and perform primary / backup failover to restore services. This allows for millisecond-level fault recovery without altering the existing topology and hardware.

[0063] Currently, the hardware performance of switching equipment is getting higher and higher, especially in data centers where most equipment uses multi-core CPUs, large memory, high-end switching chips and high-speed service ports. This invention fully utilizes the hardware performance of the equipment to achieve millisecond-level forwarding of stacking protocol messages. Even when the stacking port is congested and customer services consume a lot of CPU and memory, the stability of the stacking system can be guaranteed. The service recovery time after the main equipment fails is in the millisecond range.

[0064] This invention establishes a "stacked protocol message virtual private channel" from multiple aspects such as CPU resources, memory resources, chip forwarding and scheduling, and CPU message sending and receiving. Physically, no upgrades or additions to hardware facilities are required, thus avoiding any increase in cost.

[0065] Although embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the specification and embodiments. They can be applied to various fields suitable for the present invention. For those skilled in the art, other modifications can be easily made. Therefore, without departing from the general concept defined by the claims and their equivalents, the present invention is not limited to the specific details and illustrations shown and described herein.

Claims

1. A stacking system, characterized in that, include: The first multi-core switch is equipped with a first stacking protocol CPU core and a first stacking protocol memory; The first multi-core switch has a dedicated channel for transmitting and receiving first stacking protocol messages in its CPU message transmission and reception channel; The first stacking protocol CPU core is used to process stacking protocol tasks separately, and the first stacking protocol memory is used to store stacking protocol messages separately. The priority of the first dedicated channel for sending and receiving stacking protocol messages is higher than the priority of other channels in the CPU message sending and receiving channels of the first multi-core switch. The second multi-core switch is equipped with a second stacking protocol CPU core and a second stacking protocol memory; the CPU transmit and receive message channel of the second multi-core switch is equipped with a dedicated channel for transmitting and receiving messages of the second stacking protocol. The second stacking protocol CPU core is used to process stacking protocol tasks separately, and the second stacking protocol memory is used to store stacking protocol messages separately; the priority of the second stacking protocol message transmission and reception dedicated channel is higher than the priority of other channels in the CPU transmission and reception channels of the second multi-core switch. The first multi-core switch has a dedicated channel for forwarding first stacking protocol packets in its CPU data forwarding channel; Among them, the priority of the first stacking protocol message forwarding dedicated channel is higher than the priority of other channels in the CPU data forwarding channel of the first multi-core switch; The second multi-core switch has a dedicated channel for forwarding second stacking protocol packets in its CPU data forwarding channel; Among them, the priority of the second stacking protocol message forwarding dedicated channel is higher than the priority of other channels in the CPU data forwarding channel of the second multi-core switch.

2. The stacking system according to claim 1, characterized in that, The keep-alive time of the stacking system is set to 500ms.

3. A method for forwarding stacking protocol packets in a multi-core switch, using the stacking system as described in any one of claims 1-2, characterized in that, The CPU message receiving and processing process includes: Set the stacking protocol message to the highest priority queue of the chip, and set the queue scheduling mode of the chip's CPU port to strict priority mode, so that the stacking protocol message will enter the DMA with priority over other messages, triggering the DMA interrupt; In the DMA interrupt handler, the stack protocol message is placed into the stack message data queue, and the stack receiving task is notified to process it. Set the CPU task scheduling mode to priority preemption mode so that the stack packet receiving task can preempt low-priority tasks in real time to occupy CPU resources, and retrieve stack protocol packets from the stack data queue for priority processing. Memory is reserved for stacked packet receiving tasks, stacked packet data queues, and stacked protocol packets; and Reserve CPU cores for stacked packet receiving tasks.

4. The method for forwarding multi-core switch stacking protocol packets according to claim 3, characterized in that, The CPU message processing procedure includes: Stacked protocol messages are placed in a stacked data queue and processed by a high-priority stacked packet sending task, which is locked onto a dedicated CPU core. Set the CPU's task scheduling mode to priority preemption to ensure that stacking protocol messages are executed by the CPU first for chip packet sending.

5. The method for forwarding multi-core switch stacking protocol packets according to claim 4, characterized in that, During the CPU's message sending and processing, the chip sends packets in an asynchronous mode.

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