Message forwarding system and method

Abstract

The present application discloses a message forwarding system and method, including a CPU module and a TSN module, the CPU module is connected to the TSN module, a DMA module, a message scheduling module, a clock synchronization module and a transmission module are set in the TSN module, the message scheduling module is connected to the DMA module and the transmission module respectively, and the message scheduling module is connected to the clock synchronization module, the transmission module receives an initial message or sends a message to be sent, and divides the initial message into a first message and a second message, divides the first message into a third message and a fourth message and then sends them to the message scheduling module, and sends the second message to the clock synchronization module to obtain a global clock; the system obtains the global clock and schedules the time of receiving or sending the fourth message according to the upload time schedule table, which can reduce the jitter of receiving time-sensitive flows, effectively avoid queue competition between different messages, cause congestion, and thus effectively improve the certainty of the message; the method has the same beneficial effect.

Description

Technical Field

[0001] The present invention relates to the technical field of data communications, and in particular to a message forwarding system and method. Background Art

[0002] In application scenarios such as industrial control, autonomous driving, and 5G communications, there exists a type of periodic real-time traffic with strict requirements on latency and jitter. This is known as time-sensitive traffic, and packets belonging to this type of traffic are also known as time-sensitive packets. In some applications, time-sensitive traffic also places strict demands on end-to-end determinism. For example, remote robotic surgery requires guaranteed latency of 1 to 10 ms, autonomous driving requires high data rates and low latency of less than 10 ms to ensure rapid response to changing road conditions, and augmented reality (AR) and virtual reality (VR) for gaming and entertainment require high-speed video transmission and extremely low latency to avoid jitter in video and audio.

[0003] Time Sensitive Networking (TSN) builds on standard Ethernet by introducing features such as time synchronization, deterministic packet forwarding, frame replication and redundancy elimination technology, and resource reservation, upgrading the "event-triggered" standard Ethernet to a "time-triggered" Ethernet. In a TSN network, the time of each network node, such as the switching system and end system, is aligned with the global time, and the global time is divided into time slots of equal length. Each time-sensitive flow in a TSN network can be described by a five-tuple consisting of source, destination, period, message length, and deadline. Since time-sensitive flows are periodic and static, a scheduling cycle is pre-planned for each flow. Within a scheduling cycle, the time slot, network node, priority, etc. of each time-sensitive flow are guaranteed, ensuring the determinism of transmission within the network.

[0004] On the current TSN end system, deterministic messages need to go through the following steps to reach the memory: network card reception, deterministic message demapping, and DMA engine. The network card receives the message from the physical link, performs deterministic message demapping, and then becomes an ordinary data message. The DMA engine then writes the message to the main memory. Similarly, the TSN end system sends a message from the memory to the deterministic network through the following steps: DMA engine, deterministic message mapping, and network card sending. The DMA engine reads the message from the memory, maps the deterministic message, and then sends it from the network card according to the scheduling cycle.

[0005] The existing DMA engine is a data transmission method that allows I / O devices to directly exchange data with memory without CPU intervention. Data transmission does not require CPU participation, thus significantly reducing the CPU workload. However, the working process of the general DMA engine is "event-triggered" and cannot meet the "time-triggered" requirements. After the current deterministic messages are converted into ordinary messages, they will compete with other non-deterministic messages in the queue, even causing congestion, resulting in reduced message determinism and failure to meet latency requirements.

[0006] In view of this, it is an urgent problem to be solved by those skilled in the art to provide a message forwarding system and method that can avoid queue competition between different messages, resulting in congestion and reduced message certainty. Summary of the Invention

[0007] The object of the present invention is to provide a message forwarding system and method, which can effectively avoid queue competition between different messages and cause congestion, thereby effectively improving the certainty of the message.

[0008] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0009] A message forwarding system, comprising: a CPU module and a TSN module;

[0010] The CPU module is connected to the TSN module;

[0011] The TSN module includes: a DMA module, a message scheduling module, a clock synchronization module and a transmission module;

[0012] The message scheduling module is connected to the DMA module and the transmission module respectively;

[0013] The message scheduling module is connected to the clock synchronization module;

[0014] The CPU module is used to configure an upload time schedule for the message scheduling module;

[0015] The transmission module is used to receive an initial message or send a processed message;

[0016] The transmission module is further configured to divide the initial message into a first message and a second message, and send the first message to the message scheduling module, and send the second message to the clock synchronization module;

[0017] The transmission module is further configured to divide the first message into a third message and a fourth message;

[0018] The clock synchronization module is configured to obtain a global clock according to the second message and send the global clock to the message scheduling module;

[0019] The message scheduling module is used to receive the third message and the fourth message, and send the third message to the DMA module according to a first preset rule;

[0020] The message scheduling module is further configured to send the fourth message to the DMA module at a regular time according to the global clock and the time scheduling table;

[0021] The DMA module is configured to obtain a DMA address and send the third message and the fourth message to the CPU module according to a second preset rule based on the DMA address.

[0022] Preferably, the message scheduling module includes: a first message sending scheduler and a second message sending scheduler;

[0023] The second message sending scheduler is connected to the clock synchronization module;

[0024] The first message sending scheduler is used to send the third message to the DMA module according to a first-in-first-out rule;

[0025] The second message sending scheduler is used to send the fourth message to the DMA module at a regular time according to the global clock sent by the clock synchronization module and the configured upload time schedule.

[0026] Preferably, the DMA module includes: a DMA sending module and a DMA address module;

[0027] The DMA sending module is connected to the DMA address module;

[0028] The DMA address module is used to store and update the DMA address;

[0029] The DMA sending module is configured to obtain a DMA address from the DMA address module, and send the fourth message to the CPU module according to the DMA address, and then send the third message to the CPU module.

[0030] Preferably, it further comprises: an interface module;

[0031] The interface module is used to enable the TSN module to complete data interaction with the CPU module;

[0032] The interface module includes: a first interface and a second interface connected to each other;

[0033] The first interface is provided in the TSN module, and the first interface is connected to the DMA sending module;

[0034] The second interface is provided in the CPU module;

[0035] The first interface is configured to send the third message and the fourth message sent by the DMA sending module to the second interface;

[0036] The second interface is used to receive the third message and the fourth message.

[0037] Preferably, the CPU module further comprises: a CPU memory and a CPU core;

[0038] The CPU memory is connected to the CPU core;

[0039] The CPU memory and the CPU core are both connected to the second interface;

[0040] The second interface is further configured to send a message status register change request or an interrupt signal to the CPU core after sending the third message and the fourth message to the CPU memory;

[0041] The CPU memory is used to store the third message and the fourth message;

[0042] The CPU core is used to configure the upload time schedule and the send time schedule for the message scheduling module;

[0043] The CPU core is further configured to read the third message and the fourth message in the CPU memory after determining through polling that the message status register has been changed or responding to an interrupt signal, and release a DMA address to the DMA address module.

[0044] Preferably, the message scheduling module further includes: a first message receiving scheduler and a second message receiving scheduler;

[0045] The CPU core is further configured to obtain the updated DMA address from the DMA address module, and generate a DMA descriptor according to the updated DMA address and a preset message length;

[0046] The CPU core is further configured to send the DMA descriptor to the first message receiving scheduler and the second message receiving scheduler;

[0047] The CPU core is further configured to store the message to be sent in the CPU memory, and determine whether the message to be sent includes the fourth message, and if the message to be sent includes the fourth message, configure a time schedule for sending to the second message receiving scheduler;

[0048] The second message receiving scheduler is connected to the clock synchronization module;

[0049] The second message receiving scheduler is used to regularly send DMA descriptors to the DMA module according to the global clock sent by the clock synchronization module and the configured sending time schedule;

[0050] The first message receiving scheduler is used to send DMA descriptors to the DMA module in a first-in-first-out order.

[0051] Preferably, the DMA module further includes: a DMA receiving module;

[0052] The DMA receiving module is connected to the DMA sending module and the DMA address module respectively;

[0053] The DMA receiving module is further connected to the first message receiving scheduler and the second message receiving scheduler respectively;

[0054] The DMA receiving module is used to obtain the DMA address through the DMA address module;

[0055] The DMA receiving module is further configured to send the DMA descriptor and the DMA address sent by the first message receiving scheduler and the second message receiving scheduler to the DMA sending module;

[0056] The DMA sending module is further configured to send the DMA descriptor and the DMA address to the second interface.

[0057] Preferably, the CPU memory is further used to divide the message to be sent into a third message and a fourth message, and send the third message and the fourth message to the DMA receiving module according to the DMA descriptor and the DMA address;

[0058] The DMA receiving module is further configured to receive the third message and the fourth message, and first send the fourth message to the second message receiving scheduler and then send the third message to the first message receiving scheduler;

[0059] The first message receiving scheduler and the second message receiving scheduler are further configured to send the third message and the fourth message to the transmission module.

[0060] Preferably, the transmission module includes: a matching engine and a priority scheduler;

[0061] The matching engine is connected to the first message sending scheduler, the second message sending scheduler and the clock synchronization module respectively;

[0062] The matching engine is configured to receive an initial message sent by an external communication device and divide the initial message into the first message and the second message;

[0063] The matching engine is further configured to send the first message to the first message sending scheduler and the second message sending scheduler, and send the second message to the clock synchronization module;

[0064] The priority scheduler is connected to the first message receiving scheduler and the second message receiving scheduler respectively;

[0065] The priority scheduler is configured to send the fourth message sent by the second message receiving scheduler to the external communication device and then send the third message sent by the first message receiving scheduler to the external communication device.

[0066] A message forwarding method, based on the message forwarding system, comprises the following steps:

[0067] The transmission module receives the initial message and divides the initial message into a first message and a second message, and sends the first message to the message scheduling module and sends the second message to the clock synchronization module;

[0068] The clock synchronization module obtains a global clock according to the second message, and sends the global clock to the message scheduling module;

[0069] The message scheduling module receives the third message and the fourth message, and sends the fourth message to the DMA module according to the global clock and the upload time scheduling table, and then sends the third message to the DMA module according to the first preset rule;

[0070] The DMA module obtains a DMA address and sends the third message and the fourth message to the CPU module according to a second preset rule based on the DMA address;

[0071] The first message includes: the third message and the fourth message.

[0072] Preferably, after the DMA module obtains the DMA address and sends the third message and the fourth message to the CPU module according to the DMA address and a second preset rule, the method further includes the following steps:

[0073] The CPU module obtains the updated DMA address from the DMA address module, and generates a DMA descriptor according to the updated DMA address and a preset message length;

[0074] The CPU module sends the DMA descriptor to the message scheduling module according to the message to be sent;

[0075] The message scheduling module sends the DMA descriptor to the DMA module in a first-in-first-out order according to the global clock sent by the clock synchronization module and the configured sending time schedule;

[0076] The DMA module sends the DMA descriptor and the DMA address to the CPU module;

[0077] The CPU module sends the message to be sent to the DMA module according to the DMA descriptor and the DMA address;

[0078] The DMA module sends the message to be sent to the external communication device through the message scheduling module.

[0079] The present invention provides a message forwarding system, comprising a CPU module and a TSN module, wherein the CPU module is connected to the TSN module, a DMA module, a message scheduling module, a clock synchronization module and a transmission module are arranged in the TSN module, the message scheduling module is connected to the DMA module and the transmission module respectively, the message scheduling module is connected to the clock synchronization module, an initial message is received or a message to be sent is sent through the transmission module, and the initial message is divided into a first message and a second message, and the first message is sent to the message scheduling module, and the second message is sent to the clock synchronization module, wherein the transmission module divides the first message into a third message and a fourth message; a global clock is obtained according to the second message through the clock synchronization module, and the global clock is sent to the message scheduling module. block; the message scheduling module receives the third message and the fourth message, and sends the third message to the DMA module according to the first preset rule, and then sends the fourth message to the DMA module according to the global clock and upload time scheduling table; the DMA module obtains the DMA address and sends the third message and the fourth message to the CPU module according to the second preset rule based on the DMA address; the system calculates the global clock according to the second message through the clock synchronization module, and schedules the time to send the fourth message according to the upload time scheduling table configured by the CPU module, and gives priority to sending the fourth message before sending the third message in the subsequent sending process, which can effectively avoid queue competition between different messages and congestion, thereby effectively improving the certainty of the message.

[0080] The present invention also provides a message forwarding method. Since this method solves the same technical problem as the message forwarding system, belongs to the same technical concept, and should have the same beneficial effects, it will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0081] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in this application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0082] Figure 1 Schematic diagram of the structure of a message forwarding system according to an embodiment of the present invention;

[0083] Figure 2 Flowchart of a message forwarding method according to an embodiment of the present invention;

[0084] Figure 3 This is a flow chart after step S4 in an embodiment of the present invention. DETAILED DESCRIPTION

[0085] In order to help those skilled in the art better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of this application.

[0086] like Figure 1 As shown, an embodiment of the present invention provides a message forwarding system, including: a CPU module and a TSN module;

[0087] The CPU module is connected to the TSN module;

[0088] The TSN module includes: DMA module, message scheduling module, clock synchronization module and transmission module;

[0089] The message scheduling module is connected to the DMA module and the transmission module respectively;

[0090] The message scheduling module is connected to the clock synchronization module;

[0091] CPU module, used to configure the upload time schedule for the message scheduling module;

[0092] A transmission module, used to receive initial messages or send processed messages;

[0093] The transmission module is further used to divide the initial message into a first message and a second message, and send the first message to the message scheduling module and send the second message to the clock synchronization module;

[0094] The transmission module is further configured to divide the first message into a third message and a fourth message;

[0095] A clock synchronization module, configured to obtain a global clock according to the second message and send the global clock to the message scheduling module;

[0096] a message scheduling module, configured to receive the third message and the fourth message, and send the third message to the DMA module according to a first preset rule;

[0097] The message scheduling module is further used to send the fourth message to the DMA module at a regular time according to the global clock and the upload time scheduling table;

[0098] The DMA module is used to obtain a DMA address and send the third message and the fourth message to the CPU module according to the DMA address and a second preset rule.

[0099] In actual application, after the transmission module receives the initial message from the TSN module, it looks up the wildcard matching table sent by the CPU module, divides the initial message into the first message and the second message, and sends them to the clock synchronization module and the message scheduling module respectively, wherein the first message is also divided into the third message and the fourth message, and then the fourth message needs to obtain the determined message flow FID through the wildcard matching table sent by the CPU module; the first message sending scheduler in the message scheduling module sends the third message to the DMA sending module in the DMA module in the order of first-in-first-out, and the second message sending scheduler sends the fourth message to the DMA sending module according to the global clock sent by the clock synchronization module and the upload time scheduling table configured by the CPU module; the DMA sending module obtains the DMA address of the CPU module memory from the DMA address module, constructs a TLP write operation and sends it to the first interface in the TSN module, and then gives priority to the first interface. The fourth message in the second message sending scheduler is sent to the first interface set in the TSN module, and then the third message in the first message sending scheduler is sent to the first interface set in the TSN module; the first interface writes the message into the CPU memory of the corresponding CPU module according to the TLP write operation constructed by the DMA sending module, and the CPU core modifies the message status register or sends an interrupt signal; after the CPU memory polls the message status register or receives the interrupt signal, it reads the message in the memory and releases the DMA address to the DMA address module through the first interface; in this embodiment, after the global clock calculated by the set clock synchronization module is matched with the upload time schedule table, the fourth message will be sent regularly, and then the third message will be sent in a first-in-first-out order, which can reduce the jitter of receiving time-sensitive streams, effectively avoid queue competition between different messages, cause congestion, and effectively improve the certainty of the message;

[0100] It should be noted that the third message is a common message; the fourth message is a deterministic message; the first message sending scheduler is a common message sending scheduler; and the second message sending scheduler is a deterministic message sending scheduler.

[0101] Preferably, the message scheduling module includes: a first message sending scheduler and a second message sending scheduler;

[0102] The second message sending scheduler is connected to the clock synchronization module;

[0103] A first message sending scheduler is used to send the third message to the DMA module according to a first-in first-out rule;

[0104] The second message sending scheduler is used to send the fourth message to the DMA module at a regular time according to the global clock sent by the clock synchronization module and the configured upload time schedule.

[0105] In actual use, the second message sending scheduler is connected to the clock synchronization module, and the global clock sent by the clock synchronization module is matched with the upload time schedule configured by the CPU module to obtain a time for sending the fourth message. Then, the second message sending scheduler sends the fourth message to the DMA module at a fixed time.

[0106] It should be noted that each time the second message sending scheduler receives a fourth message, it determines the message flow FID based on the wildcard match table sent by the CPU module and changes the status information of the upload time schedule from no to yes. The second message sending scheduler obtains the global clock from the clock synchronization module, and submits the fourth message based on the global clock, message flow FID and message status information. Only at the specified submission time and when the message status is ready (yes), can the fourth message be sent to the DMA sending module.

[0107] Preferably, the DMA module includes: a DMA sending module and a DMA address module;

[0108] The DMA sending module is connected to the DMA address module;

[0109] DMA address module, used to store and update DMA address;

[0110] The DMA sending module is used to obtain a DMA address from the DMA address module, and send the fourth message to the CPU module according to the DMA address, and then send the third message to the CPU module.

[0111] In actual application, by setting up the DMA sending module to connect with the DMA address module, calling the DMA address from the DMA address module through the DMA sending module, and constructing the TLP write operation according to the DMA address, the fourth message is sent to the CPU module first, and then the third message is sent to the CPU module, and the TLP write operation is also sent to the CPU module.

[0112] Preferably, it further comprises: an interface module;

[0113] Interface module, used to enable data exchange between the TSN module and the CPU module;

[0114] The interface module includes: a first interface and a second interface connected to each other;

[0115] The first interface is provided in the TSN module, and the first interface is connected to the DMA sending module;

[0116] The second interface is provided in the CPU module;

[0117] The first interface is used to send the third message and the fourth message sent by the DMA sending module to the second interface;

[0118] The second interface is used to receive the third message and the fourth message.

[0119] In actual use, the TSN module and the CPU module are connected through an interface module, wherein the interface module includes a first interface provided in the TSN module and a second interface provided in the CPU module. The first interface is connected to the second interface, so that the TSN module and the CPU module can complete data interaction. The first interface sends the third message and the fourth message sent by the DMA sending module to the second interface, and sends the TLP write operation constructed according to the DMA address to the second interface. The second interface receives the third message, the fourth message and the TLP write operation, and writes the third message and the fourth message into the corresponding CPU memory in the CPU module according to the TLP write operation.

[0120] It should be noted that, in this embodiment, the first interface and the second interface in the interface module are both PCIE interfaces.

[0121] Preferably, the CPU module further comprises: a CPU memory and a CPU core;

[0122] CPU memory and CPU core connection;

[0123] The CPU memory and the CPU core are both connected to the second interface;

[0124] The second interface is further used to send a request to change the message status register or send an interrupt signal to the CPU core after sending the third message and the fourth message to the CPU memory;

[0125] CPU memory, used to store the third message and the fourth message;

[0126] CPU core, used to configure the upload time schedule and the download time schedule for the message scheduling module;

[0127] The CPU core is further configured to determine, through polling, that the message status register has been changed or respond to an interrupt signal, read the third message and the fourth message in the CPU memory, and release the DMA address to the DMA address module.

[0128] During actual application, a connection is set between the CPU memory and the CPU core, and both the CPU memory and the CPU core are connected to the second interface. The second interface first sends the third message and the fourth message to the CPU memory for storage, and then sends a request to change the message status register or an interrupt signal to the CPU core. After the CPU core determines through polling that the message status register has been changed or responds to the interrupt signal, it reads the third message and the fourth message in the CPU memory and releases the DMA address to the DMA address module.

[0129] Preferably, the message scheduling module further includes: a first message receiving scheduler and a second message receiving scheduler;

[0130] The CPU core is further configured to obtain an updated DMA address from the DMA address module and generate a DMA descriptor according to the updated DMA address and a preset message length;

[0131] The CPU core is further configured to send a DMA descriptor to the first message receiving scheduler and the second message receiving scheduler;

[0132] The CPU core is further configured to store the message to be sent in the CPU memory, and determine whether the message to be sent includes the fourth message, and if the message to be sent includes the fourth message, configure the second message receiving scheduler to send a time schedule;

[0133] The second message receiving scheduler is connected to the clock synchronization module;

[0134] A second message receiving scheduler is used to send DMA descriptors to the DMA module at regular intervals according to the global clock sent by the clock synchronization module and the configured sending time schedule;

[0135] The first message receiving scheduler is used to send the DMA descriptor to the DMA module in a first-in-first-out order.

[0136] During actual application, the second message receiving scheduler is first connected to the clock synchronization module to facilitate the reception of the global clock sent by the clock synchronization module, and then the message to be sent is stored in the CPU memory, and it is determined whether the message to be sent contains the fourth message. If the message to be sent contains the fourth message, the time schedule is configured to be sent to the second message receiving scheduler. Finally, the CPU core obtains the updated DMA address from the DMA address module, and generates a DMA descriptor based on the updated DMA address and the preset message length, and sends the DMA descriptor to the first message receiving scheduler and the second message receiving scheduler. The second message receiving scheduler sends the DMA descriptor to the DMA module regularly according to the global clock sent by the clock synchronization module and the configured time schedule, and the first message receiving scheduler sends the DMA descriptor to the DMA module in a first-in-first-out order.

[0137] Preferably, the DMA module further includes: a DMA receiving module;

[0138] The DMA receiving module is connected to the DMA sending module and the DMA address module respectively;

[0139] The DMA receiving module is also connected to the first message receiving scheduler and the second message receiving scheduler respectively;

[0140] DMA receiving module, used to obtain DMA address through DMA address module;

[0141] The DMA receiving module is further configured to send the DMA descriptors and DMA addresses sent by the first message receiving scheduler and the second message receiving scheduler to the DMA sending module;

[0142] The DMA sending module is also used to send the DMA descriptor and DMA address to the CPU module.

[0143] During actual application, a DMA receiving module is set to be connected to the DMA sending module and the DMA address module respectively, and also to the first message receiving scheduler and the second message receiving scheduler respectively. The DMA receiving module first receives the DMA descriptor sent by the first message receiving scheduler and the second message receiving scheduler, constructs a TLP read operation according to the DMA address and the preset message length in the DMA descriptor, then obtains the updated DMA address from the DMA address module, and finally sends the TLP read operation and the DMA address to the DMA sending module. The DMA sending module then sends the TLP read operation and the DMA address to the second interface in the CPU module.

[0144] Preferably, the CPU memory is further used to divide the message to be sent into a third message and a fourth message, and send the third message and the fourth message to the DMA receiving module according to the DMA descriptor and the DMA address;

[0145] The DMA receiving module is further configured to receive a third message and a fourth message, and first send the fourth message to the second message receiving scheduler and then send the third message to the first message receiving scheduler;

[0146] The first message receiving scheduler and the second message receiving scheduler are further configured to send the third message and the fourth message to the transmission module.

[0147] During actual application, in the CPU memory, the messages to be sent are divided into the third message and the fourth message, the third message is a normal message, and the fourth message is a deterministic message. The second interface receives the TLP read operation sent by the DMA sending module, and after reading the response TLP operation, the second interface sends the third message and the fourth message in the CPU memory to the DMA receiving module according to the DMA address. After the DMA receiving module receives the third message and the fourth message, it allocates the third message and the fourth message, and first sends the fourth message to the second message receiving scheduler, and then sends the third message to the first message receiving scheduler. Then the first receiving scheduler and the second receiving scheduler send the corresponding received third message and fourth message to the transmission module.

[0148] Preferably, the transmission module includes: a matching engine and a priority scheduler;

[0149] The matching engine is connected to the first message sending scheduler, the second message sending scheduler and the clock synchronization module respectively;

[0150] a matching engine, configured to receive an initial message sent by an external communication device and divide the initial message into a first message and a second message;

[0151] The matching engine is further configured to send the first message to the first message sending scheduler and the second message sending scheduler, and send the second message to the clock synchronization module;

[0152] The priority scheduler is connected to the first message receiving scheduler and the second message receiving scheduler respectively;

[0153] The priority scheduler is configured to send the fourth message sent by the second message receiving scheduler to the external communication device and then send the third message sent by the first message receiving scheduler to the external communication device.

[0154] During actual application, the matching engine in the transmission module is connected to the first message sending scheduler, the second message sending scheduler and the clock synchronization module respectively. First, the matching engine is responsible for receiving the initial message from the external communication device, and then dividing the initial message into the first message and the second message, and finally sending the first message to the first message sending scheduler and the second message sending scheduler, and sending the second message to the clock synchronization module. The priority scheduler in the transmission module is connected to the first message receiving scheduler and the second message receiving scheduler respectively. The priority scheduler is responsible for giving priority to sending the fourth message sent by the second message receiving scheduler to the external communication device, and then sending the third message sent by the first message receiving scheduler to the external communication device, thereby completing the message forwarding process.

[0155] like Figure 2 As shown, the present invention also provides a message forwarding method, based on the message forwarding system, comprising the following steps:

[0156] S1 transmission module receives the initial message and the initial message is divided into a first message and a second message, and sends the first message to the message scheduling module, the second message is sent to the clock synchronization module;

[0157] S2 clock synchronization module obtains the global clock according to the second message, and sends the global clock to the message scheduling module;

[0158] S3. The message scheduling module receives the third and fourth messages, and sends the fourth message to the DMA module according to the global clock and upload time schedule, and then sends the third message to the DMA module according to the first preset rule;

[0159] S4. The DMA module obtains the DMA address and sends the third message and the fourth message to the CPU module according to the second preset rule based on the DMA address;

[0160] The first message includes: a third message and a fourth message.

[0161] In step S1, the transmission module receives an initial message sent by an external communication device, divides the initial message into a first message and a second message, and sends the first message to the message scheduling module for distribution, and sends the second message to the clock synchronization module for processing. In this embodiment, the first message includes a normal message and a deterministic message, and the second message is a clock synchronization message;

[0162] In step S2, the clock synchronization module calculates a global clock based on the second message sent by the transmission module, and sends the global clock to the second message sending scheduler in the message scheduling module for use by the second message sending scheduler. In this embodiment, by calculating a global clock, the global time of message sending can be obtained, and then the message is sent regularly according to the global time, or a rule for interval sending can be set according to actual needs.

[0163] In step S3, the transmission module divides the first message into a third message and a fourth message, the third message is a normal message, and the fourth message is a deterministic message. After receiving the fourth message, the second message sending scheduler in the message scheduling module matches the global clock and the upload clock scheduling table, and sends the fourth message to the DMA sending module in the DMA module at regular intervals. Then, after receiving the third message, the first message sending scheduler in the message scheduling module sends the third message to the DMA sending module in the DMA module in a first-in-first-out order, wherein the first message sending scheduler is a normal message sending scheduler, and the second message sending scheduler is a deterministic message sending scheduler. In this embodiment, an accurate sending time can be obtained by matching the global clock and the upload clock scheduling table, that is, a rule for scheduled sending is set, and this rule for scheduled sending is obtained through the global clock and the upload clock scheduling table, which further avoids queue competition between different messages.

[0164] In step S4, after the message scheduling module sends the third message and the fourth message to the DMA sending module in the DMA module, the DMA sending module calls the DMA address and preferentially sends the fourth message to the CPU module according to the DMA address, and then sends the third message to the CPU module; this embodiment modifies the rules for sending ordinary messages and deterministic messages, and preferentially sends the deterministic message, i.e., the fourth message, to the CPU module for storage, and then sends the ordinary message, i.e., the third message, to the CPU module for storage, thereby avoiding queue competition between different messages and causing congestion problems as a whole, and effectively improving the determinism of the messages.

[0165] like Figure 3 As shown, preferably, after step S4, the following steps are also included:

[0166] S5. The CPU module obtains the updated DMA address from the DMA address module and generates a DMA descriptor based on the updated DMA address and the preset message length;

[0167] S6. The CPU module sends a DMA descriptor to the message scheduling module according to the message to be sent;

[0168] S7. The message scheduling module sends a DMA descriptor to the DMA module according to the global clock and the configured time schedule sent by the clock synchronization module. The DMA descriptor is sent to the DMA module in a first-in-first-out order.

[0169] S8.DMA module sends DMA descriptor to CPU module;

[0170] S9. The CPU module sends the message to be sent to the DMA module according to the DMA descriptor;

[0171] S10. The DMA module sends the message to be sent to the external communication device through the message scheduling module.

[0172] In step S5, after the CPU module stores the third and fourth messages, it releases the DMA address, the DMA address module updates the DMA address, and the CPU module calls the updated DMA address and generates a DMA descriptor using the updated DMA address and the preset message length.

[0173] In step S6, the CPU module first stores the message to be sent into the CPU memory, and then judges the message to be sent. If the message to be sent is a deterministic message, that is, the fourth message, the CPU core in the CPU module will configure a dispatch schedule for the second message receiving scheduler in the message scheduling module. If the message to be sent is an ordinary message, that is, the third message, the DMA descriptor will be directly sent to the first message receiving scheduler in the message scheduling module. In this embodiment, the first message receiving scheduler is a common message receiving scheduler, and the second message receiving scheduler is a deterministic message receiving scheduler.

[0174] In step S7, the second message receiving scheduler in the message scheduling module sends the DMA descriptor to the DMA receiving module in the DMA module at a regular time according to the global clock sent by the clock synchronization module and the configured sending time schedule, and then sends the DMA descriptor to the DMA receiving module in the DMA module in a first-in-first-out order;

[0175] In steps S8 to S9, after the DMA receiving module receives the DMA descriptor from the first message receiving scheduler and the second message receiving scheduler, it constructs a TLP read operation according to the DMA address and the preset message length in the DMA descriptor, and sends the TLP read operation to the DMA sending module. After receiving the TLP read operation from the DMA receiving module, the DMA sending module sends it to the PCIE interface set in the CPU module. After the PCIE interface calls the DMA address updated in the DMA address module, it reads the response TLP operation and sends the third message and the fourth message to be sent in the CPU memory of the CPU module to the DMA receiving module.

[0176] In step S10, the DMA receiving module converts the received read response TLP operation into an internal data communication format and sends the third message and the fourth message to be sent to the first message receiving scheduler and the second message receiving scheduler. The first message receiving scheduler and the second message receiving scheduler send the received third message and the fourth message to be sent to the priority scheduler. The priority scheduler will give priority to ensuring that the fourth message is sent to the communication peripheral device, and then send the third message to the communication peripheral device.

[0177] In the embodiments provided in this application, it should be understood that the disclosed methods and systems can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of modules is only a logical function division. In actual implementation, there may be other division methods, such as: multiple modules or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0178] In addition, all functional modules in the embodiments of the present invention may be integrated into one processor, or each module may be a separate device, or two or more modules may be integrated into one device; the functional modules in the embodiments of the present invention may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0179] Those skilled in the art will understand that all or part of the steps of the above-mentioned method embodiment can be completed by program instructions and related hardware. The aforementioned program instructions can be stored in a computer-readable storage medium. When the program instructions are executed, the steps of the above-mentioned method embodiment are executed; and the aforementioned storage medium includes: mobile storage devices, read-only memories (ROM), magnetic disks or optical disks, and other media that can store program codes.

[0180] It should be understood that the use of "system," "device," "unit," and / or "module" in this application is merely a method for distinguishing different components, elements, parts, portions, or assemblies at different levels. However, if other terms can achieve the same purpose, the terms may be replaced by other expressions.

[0181] As used in this application and the claims, unless the context clearly indicates an exception, the terms "a," "an," "an," and / or "the" are not intended to refer to the singular and may include the plural, unless the context clearly indicates otherwise. Generally speaking, the terms "comprises" and "include" only indicate the inclusion of the steps and elements specifically identified, and these steps and elements do not constitute an exclusive list. A method or apparatus may also include other steps or elements. The phrase "comprises a..." does not preclude the presence of additional identical elements in the process, method, product, or apparatus that includes the elements.

[0182] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the quantity of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features.

[0183] If a flow chart is used in this application, the flow chart is used to illustrate the operations performed by the system according to the embodiments of the application. It should be understood that the previous or subsequent operations are not necessarily performed in exact order. Instead, the steps can be processed in reverse order or simultaneously. At the same time, other operations can be added to these processes, or one or more operations can be removed from these processes.

[0184] The above describes in detail the message forwarding system and method provided by the present invention. The above description of the disclosed embodiments will enable those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein, but is intended to be embodied in the widest possible manner consistent with the principles and novel features disclosed herein.

Claims

1. A message forwarding system, characterized in that: include: CPU module and TSN module; The CPU module is connected to the TSN module; The TSN module includes: a DMA module, a message scheduling module, a clock synchronization module and a transmission module; The message scheduling module is connected to the DMA module and the transmission module respectively; The message scheduling module is connected to the clock synchronization module; The CPU module is used to configure an upload time schedule for the message scheduling module; The transmission module is used to receive an initial message or send a message to be sent; The transmission module is further configured to divide the initial message into a first message and a second message, and send the first message to the message scheduling module, and send the second message to the clock synchronization module; The transmission module is further configured to divide the first message into a third message and a fourth message; The clock synchronization module is configured to obtain a global clock according to the second message and send the global clock to the message scheduling module; The message scheduling module is used to receive the third message and the fourth message, and send the third message to the DMA module according to a first preset rule; The message scheduling module is further configured to send the fourth message to the DMA module at a regular time according to the global clock and the upload time scheduling table; The DMA module is configured to obtain a DMA address and send the third message and the fourth message to the CPU module according to a second preset rule based on the DMA address.

2. The message forwarding system according to claim 1, characterized in that: The message scheduling module includes: a first message sending scheduler and a second message sending scheduler; The second message sending scheduler is connected to the clock synchronization module; The first message sending scheduler is used to send the third message to the DMA module according to a first-in-first-out rule; The second message sending scheduler is used to send the fourth message to the DMA module at a regular time according to the global clock sent by the clock synchronization module and the configured upload time schedule.

3. The message forwarding system according to claim 2, characterized in that: The DMA module includes: a DMA sending module and a DMA address module; The DMA sending module is connected to the DMA address module; The DMA address module is used to store and update the DMA address; The DMA sending module is configured to obtain a DMA address from the DMA address module, and send the fourth message to the CPU module according to the DMA address, and then send the third message to the CPU module.

4. The message forwarding system according to claim 3, characterized in that: Also includes: Interface module; The interface module is used to enable the TSN module to complete data interaction with the CPU module; The interface module includes: a first interface and a second interface connected to each other; The first interface is provided in the TSN module, and the first interface is connected to the DMA sending module; The second interface is provided in the CPU module; The first interface is configured to send the third message and the fourth message sent by the DMA sending module to the second interface; The second interface is used to receive the third message and the fourth message.

5. The message forwarding system according to claim 4, characterized in that: The CPU module also includes: CPU memory and CPU core; The CPU memory is connected to the CPU core; The CPU memory and the CPU core are both connected to the second interface; The second interface is further configured to send a message status register change request or an interrupt signal to the CPU core after sending the third message and the fourth message to the CPU memory; The CPU memory is used to store the third message and the fourth message; The CPU core is used to configure the upload time schedule and the send time schedule for the message scheduling module; The CPU core is further configured to read the third message and the fourth message in the CPU memory after determining through polling that the message status register has been changed or responding to an interrupt signal, and release a DMA address to the DMA address module.

6. The message forwarding system according to claim 5, characterized in that: The message scheduling module further includes: a first message receiving scheduler and a second message receiving scheduler; The CPU core is further configured to obtain the updated DMA address from the DMA address module, and generate a DMA descriptor according to the updated DMA address and a preset message length; The CPU core is further configured to send the DMA descriptor to the first message receiving scheduler and the second message receiving scheduler; The CPU core is further configured to store the message to be sent in the CPU memory, and determine whether the message to be sent includes the fourth message, and if the message to be sent includes the fourth message, configure a time schedule for sending to the second message receiving scheduler; The second message receiving scheduler is connected to the clock synchronization module; The second message receiving scheduler is used to regularly send DMA descriptors to the DMA module according to the global clock sent by the clock synchronization module and the configured sending time schedule; The first message receiving scheduler is used to send DMA descriptors to the DMA module in a first-in-first-out order.

7. The message forwarding system according to claim 6, characterized in that: The DMA module also includes: a DMA receiving module; The DMA receiving module is connected to the DMA sending module and the DMA address module respectively; The DMA receiving module is further connected to the first message receiving scheduler and the second message receiving scheduler respectively; The DMA receiving module is used to obtain the DMA address through the DMA address module; The DMA receiving module is further configured to send the DMA descriptor and the DMA address sent by the first message receiving scheduler and the second message receiving scheduler to the DMA sending module; The DMA sending module is further configured to send the DMA descriptor and the DMA address to the second interface.

8. The message forwarding system according to claim 7, characterized in that: The CPU memory is further configured to divide the message to be sent into a third message and a fourth message, and send the third message and the fourth message to the DMA receiving module according to the DMA descriptor and the DMA address; The DMA receiving module is further configured to receive the third message and the fourth message, and first send the fourth message to the second message receiving scheduler and then send the third message to the first message receiving scheduler; The first message receiving scheduler and the second message receiving scheduler are further configured to send the third message and the fourth message to the transmission module.

9. The message forwarding system according to claim 8, characterized in that: The transmission module includes: a matching engine and a priority scheduler; The matching engine is connected to the first message sending scheduler, the second message sending scheduler and the clock synchronization module respectively; The matching engine is configured to receive an initial message sent by an external communication device and divide the initial message into the first message and the second message; The matching engine is further configured to send the first message to the first message sending scheduler and the second message sending scheduler, and send the second message to the clock synchronization module; The priority scheduler is connected to the first message receiving scheduler and the second message receiving scheduler respectively; The priority scheduler is configured to send the fourth message sent by the second message receiving scheduler to the external communication device and then send the third message sent by the first message receiving scheduler to the external communication device.

10. A message forwarding method, based on the message forwarding system according to any one of claims 1 to 9, characterized in that: The steps include: The transmission module receives the initial message and divides the initial message into a first message and a second message, and sends the first message to the message scheduling module and sends the second message to the clock synchronization module; The clock synchronization module obtains a global clock according to the second message, and sends the global clock to the message scheduling module; The message scheduling module receives the third message and the fourth message, and sends the fourth message to the DMA module according to the global clock and the upload time scheduling table, and then sends the third message to the DMA module according to the first preset rule; The DMA module obtains a DMA address and sends the third message and the fourth message to the CPU module according to a second preset rule based on the DMA address; The first message includes: the third message and the fourth message.

11. The message forwarding method according to claim 10, wherein: After the DMA module obtains the DMA address and sends the third message and the fourth message to the CPU module according to the DMA address and the second preset rule, the following steps are further included: The CPU module obtains the updated DMA address from the DMA address module, and generates a DMA descriptor according to the updated DMA address and a preset message length; The CPU module sends the DMA descriptor to the message scheduling module according to the message to be sent; The message scheduling module sends the DMA descriptor to the DMA module in a first-in-first-out order according to the global clock sent by the clock synchronization module and the configured sending time schedule; The DMA module sends the DMA descriptor and the DMA address to the CPU module; The CPU module sends the message to be sent to the DMA module according to the DMA descriptor and the DMA address; The DMA module sends the message to be sent to the external communication device through the message scheduling module.

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