Adaptive optimization circuit of video stream processing clock and device

Abstract

The present application relates to a kind of adaptive optimization circuit and equipment when video stream processing clock.The circuit includes: video image receiver, line timing adjustment controller, line horizontal blanking area statistics module, RC ring oscillator controller, RC ring oscillator, fixed frequency clock, line total time monitoring module and clock multiplexing switching circuit.First, the frequency of video stream processing clock signal is reduced to one fourth of pixel clock frequency by two line SRAM buffers, then RC ring oscillator controller reduces the oscillation frequency of RC ring oscillator according to the statistical result of line horizontal blanking area statistics module, until output line horizontal blanking time is maintained to the minimum value required by system.When frame refresh rate increases, clock multiplexing switching circuit immediately switches to higher frequency signal, so as to achieve the balance of system performance and power consumption.

Description

Technical Field

[0001] This invention relates to the field of image display and signal processing, and in particular to an adaptive optimization circuit and device for video stream processing clock. Background Technology

[0002] A video stream is the object that an image receiving and processing system needs to process. It consists of a sequence of images and requires certain processing resources. Changes in the video stream will cause changes in the system's processing load. The processing clock refers to the clock set in the image processing system. The signal frequency of the processing clock controls the timing and speed of the system's processing.

[0003] Inside the chip, the image display and signal processing system needs to set a matching video stream processing clock based on the image resolution and frame refresh rate to synchronize and drive the system to acquire, process, and output video stream data according to the set parameters. During image display and signal processing, a high-frequency processing clock can increase processing speed but also increases power consumption, while a low-frequency processing clock can reduce power consumption but slows down processing speed. The aforementioned traditional video stream processing clocks present a technical challenge in balancing performance and power consumption. Summary of the Invention

[0004] Therefore, it is necessary to provide an adaptive optimization circuit for video stream processing clock and a video stream processing device.

[0005] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions:

[0006] On the one hand, an adaptive optimization circuit for video stream processing clock is provided, including a video image receiver, a line timing adjustment controller, an inline horizontal blanking area statistics module, an RC ring oscillator controller, an RC ring oscillator, a fixed frequency clock, an inline total time monitoring module, and a clock multiplexing switching circuit.

[0007] The output of the video image receiver is connected to the input of the horizontal timing adjustment controller and the inline total time monitoring module, respectively. The first output of the horizontal timing adjustment controller is used to output the video stream. The second output of the horizontal timing adjustment controller is connected to the input of the inline horizontal blanking area statistics module. The output of the inline horizontal blanking area statistics module is connected to the input of the RC ring oscillator circuit controller. The output of the RC ring oscillator circuit controller is connected to the input of the RC ring oscillator and the fixed frequency clock, respectively. The outputs of the RC ring oscillator, the fixed frequency clock, and the inline total time monitoring module are connected to the input of the clock multiplexing switching circuit, respectively. The output of the clock multiplexing switching circuit is connected to the input of the horizontal timing adjustment controller and the inline horizontal blanking area statistics module, respectively.

[0008] The video image receiver receives and parses the raw video stream signal, and outputs timing control signals and data channel signals. The horizontal timing adjustment controller, based on the timing control signal and the video stream processing clock signal generated by the clock multiplexing switching circuit, alternately reads and writes the data channel signal through two SRAM buffers, and outputs the video stream and the first valid data identifier. The in-line horizontal blanking area statistics module counts the first valid data identifier based on the video stream processing clock signal and outputs the in-line horizontal blanking area count. The RC ring oscillator circuit controller adjusts the oscillation frequency of the RC ring oscillator based on the in-line horizontal blanking area count. A ring oscillator is used to output a first clock signal according to the oscillation frequency, a fixed frequency clock is used to output a second clock signal, an inline total time monitoring module is used to count the effective pixel area identifiers according to the recovery data clock and output an inline total time reduction identifier, a clock multiplexing switching circuit is used to output a video stream processing clock signal according to the inline total time reduction identifier; the inline total time reduction identifier is used to indicate whether the frame refresh rate remains stable or increases, the video stream processing clock signal includes a first clock signal corresponding to a stable frame refresh rate and a second clock signal corresponding to an increase in the frame refresh rate, and the timing control signal includes the recovery data clock and the effective pixel area identifier.

[0009] In one embodiment, the inline horizontal blanking area statistics module integrates a first register, which stores a configurable interval time parameter. The interval time parameter is used to determine the time range within which the inline horizontal blanking area statistics module performs statistics on the first data valid identifier.

[0010] In one embodiment, the RC ring oscillator circuit controller integrates a second register, which stores a configurable first comparison threshold and a minimum frequency threshold. The first comparison threshold is used to trigger the adjustment of the oscillation frequency, and the minimum frequency threshold is the minimum protection value of the oscillation frequency.

[0011] In one embodiment, the in-line total time monitoring module integrates a third register for storing a configurable second comparison threshold, which triggers the setting of the in-line total time reduction flag to a high level.

[0012] In one embodiment, the fixed-frequency clock is a clock phase-locked loop.

[0013] In one embodiment, the video image receiver uses an eDP or MIPI interface to receive and process the raw video stream signal.

[0014] On the other hand, a video stream processing device is also provided, including the aforementioned adaptive optimization circuit for the video stream processing clock.

[0015] One or more technical solutions provided in the embodiments of this application have at least the following technical effects or advantages:

[0016] The aforementioned adaptive optimization circuit and device for video stream processing clock counts the first valid data identifiers through the inline horizontal blanking area statistics module and outputs the number of inline horizontal blanking areas. The RC ring oscillator circuit controller can reduce the oscillation frequency of the RC ring oscillator according to the statistical results, thereby adaptively reducing the frequency of the video stream processing clock signal until the output inline horizontal blanking time is maintained at the minimum value required by the system. Therefore, power consumption is reduced to the maximum extent while ensuring system performance.

[0017] Because the in-line total time monitoring module outputs an in-line total time reduction flag by statistically identifying the effective pixel area, the clock multiplexing switching circuit outputs a clock signal based on this flag. When this flag indicates that the frame refresh rate remains stable, the clock multiplexing switching circuit outputs a lower-frequency first clock signal; when the flag indicates that the frame refresh rate increases, the clock multiplexing switching circuit immediately switches to a higher-frequency second clock signal. This frequency is sufficient to meet the system's requirements for processing the highest bandwidth video stream, thus enabling timely and efficient processing of the video data stream, achieving a balance between system performance and power consumption. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a first schematic diagram of the structure of an adaptive optimization circuit for video stream processing clock in one embodiment;

[0020] Figure 2 This is a second schematic diagram of the structure of an adaptive optimization circuit for video stream processing clock in one embodiment. Detailed Implementation

[0021] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0023] It is understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first clock signal may be referred to as a second clock signal, and similarly, a second clock signal may be referred to as a first clock signal. Both the first clock signal and the second clock signal are clock signals, but they are not the same clock signal.

[0024] It is understood that the term "connection" in the following embodiments should be interpreted as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., transmit electrical signals or data to each other. Furthermore, terms such as "input terminal" and "output terminal" do not limit the corresponding component to having only one input terminal or output terminal; they can also have multiple similar input terminals or output terminals. Multiple sub-input / output ports can also be integrated into a single input / output port, depending on the port settings of the actual component being used.

[0025] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising,” “including,” or “having,” etc., specify the presence of the stated feature, whole, step, operation, component, part, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0026] In the process of researching and implementing this application, the inventors discovered that in the actual chip circuit design process, for image systems that need to support multiple resolutions and frame rates, multiple phase-locked loop clocks can be used to generate clock signals of different precisions to meet the requirements. However, this method not only increases the complexity and cost of chip design, but also increases the power consumption of the chip.

[0027] Based on this, the present invention provides an adaptive optimization circuit for video stream processing clock, including a video image receiver, a horizontal timing adjustment controller, an inline horizontal blanking area statistics module, an RC ring oscillator controller, an RC ring oscillator, a fixed frequency clock, an inline total time monitoring module, and a clock multiplexing switching circuit. First, the video stream processing clock signal frequency is reduced to one-quarter of the pixel clock frequency by passing through two row SRAM buffers. Then, the inline horizontal blanking area statistics module counts the first valid data identifiers and outputs the number of inline horizontal blanking areas. The RC ring oscillator controller can reduce the oscillation frequency of the RC ring oscillator according to the statistical results, thereby adaptively reducing the frequency of the video stream processing clock signal until the output inline horizontal blanking time is maintained at the minimum value required by the system, thus minimizing power consumption while ensuring system performance. Since the inline total time monitoring module outputs an inline total time reduction identifier by counting valid pixel area identifiers, the clock multiplexing switching circuit outputs a clock signal based on this identifier. When the refresh rate of the indicated frame remains stable, the clock multiplexing switching circuit outputs a first clock signal with a lower frequency; when the refresh rate of the indicated frame increases, the clock multiplexing switching circuit immediately switches to a second clock signal with a higher frequency, which is sufficient to meet the system's requirements for processing the highest bandwidth video stream, thereby processing the video data stream in a timely and efficient manner, thus achieving a balance between system performance and power consumption.

[0028] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0029] In one embodiment, such as Figure 1 As shown, this application embodiment provides an adaptive optimization circuit 100 for video stream processing clock, including a video image receiver 11, a line timing adjustment controller 12, an inline horizontal blanking area statistics module 13, an RC ring oscillator circuit controller 14, an RC ring oscillator 15, a fixed frequency clock 16, an inline total time monitoring module 17, and a clock multiplexing switching circuit 18.

[0030] The output of the video image receiver 11 is connected to the input of the horizontal timing adjustment controller 12 and the inline total time monitoring module 17, respectively. The first output of the horizontal timing adjustment controller 12 is used to output the video stream. The second output of the horizontal timing adjustment controller 12 is connected to the input of the inline horizontal blanking area statistics module 13. The output of the inline horizontal blanking area statistics module 13 is connected to the input of the RC ring oscillator circuit controller 14. The output of the RC ring oscillator circuit controller 14 is connected to the input of the RC ring oscillator 15 and the fixed frequency clock 16, respectively. The outputs of the RC ring oscillator 15, the fixed frequency clock 16 and the inline total time monitoring module 17 are connected to the input of the clock multiplexing switching circuit 18, respectively. The output of the clock multiplexing switching circuit 18 is connected to the input of the horizontal timing adjustment controller 12 and the inline horizontal blanking area statistics module 13, respectively.

[0031] The video image receiver 11 is used to receive and parse the raw video stream signal, and output timing control signals and data channel signals. The horizontal timing adjustment controller 12 is used to alternately read and write the data channel signal through two SRAM buffers according to the timing control signal and the video stream processing clock signal generated by the clock multiplexing switching circuit 18, and output the video stream and the first data valid identifier. The horizontal blanking area statistics module 13 is used to count the first data valid identifier according to the video stream processing clock signal and output the value of the horizontal blanking area in the horizontal line. The RC ring oscillator circuit controller 14 is used to adjust the oscillation frequency of the RC ring oscillator 15 according to the value of the horizontal blanking area in the horizontal line. The RC ring oscillator 15 is used to output a first clock signal according to the oscillation frequency, the fixed frequency clock 16 is used to output a second clock signal, the inline total time monitoring module 17 is used to count the effective pixel area identifier according to the recovery data clock and output an inline total time reduction identifier, and the clock multiplexing switching circuit 18 is used to output a video stream processing clock signal according to the inline total time reduction identifier; the inline total time reduction identifier is used to indicate whether the frame refresh rate remains stable or increases, the video stream processing clock signal includes a first clock signal corresponding to a stable frame refresh rate and a second clock signal corresponding to an increase in the frame refresh rate, and the timing control signal includes the recovery data clock and the effective pixel area identifier.

[0032] It is understandable that the video image receiver 11 can use one or more of the following interface standards to receive and process video data streams: DP (DisplayPort), eDP (Embedded DisplayPort), HDMI (High-Definition Multimedia Interface), MIPI (Mobile Industry Processor Interface), or LVDS (Low-Voltage Differential Signaling). As long as it can receive and parse the raw video stream signal and output timing control signals and data channel signals, it is acceptable. The horizontal timing adjustment controller 12 contains two SRAM buffers. It uses a ping-pong principle (a control mode that achieves continuous and high-speed data processing through two alternately operating components) to achieve alternating read and write operations. The horizontal timing adjustment controller 12 controls these two SRAM buffers, causing one SRAM buffer to write incoming video stream data while the other reads the previous data line and outputs it. When one SRAM buffer completes writing the current line of data, the two SRAMs switch functions to achieve continuous data stream processing. Registers can be integrated into the horizontal blanking area statistics module 13, the RC ring oscillator circuit controller 14, and the horizontal total time monitoring module 17, respectively, so that the modules can directly access their own internal registers; alternatively, the registers can be used as independent storage modules, allowing multiple modules to share access to them, and connected to the horizontal blanking area statistics module 13, the RC ring oscillator circuit controller 14, and the horizontal total time monitoring module 17 via standard interfaces. The fixed frequency clock 16 can reuse the clock generated by the system clock phase-locked loop, or it can be constructed using an RC oscillator and a crystal oscillator, or it can be constructed using a timer and software algorithms, as long as the clock frequency meets the maximum bandwidth of the video stream for system image signal processing. The RC ring oscillator 15 and the clock multiplexing switching circuit 18 can be constructed using similar components in the art.

[0033] Specifically, after receiving and parsing the raw video signal, the video image receiver 11 outputs a timing control signal (which includes a recovery data clock and a valid pixel area identifier) ​​and a data channel signal (which includes a second valid data identifier and image reception data; the second valid data identifier indicates whether the input data is valid). The horizontal timing adjustment controller 12 uses the video stream processing clock signal from the clock multiplexing switching circuit 18 as a time base, reads the video stream data according to the timing control signal, and performs alternating read and write operations through two SRAM buffers using the ping-pong principle. Simultaneously, it generates the video stream and outputs a first valid data identifier (which indicates whether the output data is valid). The inline horizontal blanking area statistics module 13 uses the video stream processing clock signal as a time base, performs statistics on the first valid data identifier signal, and outputs the number of inline horizontal blanking areas to the RC ring oscillator circuit controller 14. If the number of horizontal blanking regions in a row does not reach the set threshold, it means that there are fewer horizontal blanking regions in the row, which means there is more effective output data. Therefore, the output frequency of the RC ring oscillator 15 is kept constant to ensure normal system operation. If the number of horizontal blanking regions in a row reaches the set threshold, it means that there are more horizontal blanking regions in the row, which means there is less effective output data. The RC ring oscillator circuit controller 14 starts to reduce the oscillation frequency of the RC ring oscillator 15 until the horizontal blanking time in the output row is maintained at the minimum value required by the system, thereby reducing system power consumption.

[0034] A fixed-frequency clock 16 is used to output a second clock signal, and the clock frequency meets the maximum bandwidth of the video stream for system image signal processing. The recovery data clock signal remains unchanged after initialization. The in-line total time monitoring module 17 uses the recovery data clock signal as the time base to count the total time of the last line of video image in the vertical blanking area of ​​the effective pixel area identifier. It starts working on a frame-by-frame basis, and counts once per frame. It calculates the difference between the total time of the last line of video image in the current frame and the total time of the last line of video image in the previous frame, and outputs an in-line total time reduction indicator based on the difference. When the difference does not exceed the set threshold, it indicates that the frame refresh rate remains stable, and a low-level inline total time reduction indicator is output as an indication (the inline total time reduction indicator is used to indicate whether the frame refresh rate remains stable or increases; in this embodiment and in the following text, a low level is used to represent a stable frame refresh rate, and vice versa). The clock multiplexing switching circuit 18 selects the output first clock signal as the video stream processing clock signal. When the difference exceeds the set threshold, it indicates that the frame refresh rate increases, and a high-level inline total time reduction indicator is output. The clock multiplexing switching circuit 18 selects the output second clock signal with a higher frequency as the video stream processing clock signal, thereby processing the video data stream in a timely and efficient manner.

[0035] The aforementioned adaptive optimization circuit 100 for video stream processing clocks uses the inline horizontal blanking area statistics module 13 to count the first valid data identifiers and output the number of inline horizontal blanking areas. The RC ring oscillator controller 14 can reduce the oscillation frequency of the RC ring oscillator 15 based on the statistical results, thereby adaptively reducing the frequency of the video stream processing clock signal until the output inline horizontal blanking time is maintained at the minimum value required by the system. Therefore, power consumption is reduced to the maximum extent while ensuring system performance. Since the inline total time monitoring module 17 outputs an inline total time reduction identifier by counting the valid pixel area identifiers, the clock multiplexing switching circuit 18 outputs a clock signal based on this identifier. When this identifier indicates that the frame refresh rate remains stable, the clock multiplexing switching circuit 18 outputs a first clock signal with a lower frequency; when the identifier indicates that the frame refresh rate increases, the clock multiplexing switching circuit 18 immediately switches to a second clock signal with a higher frequency, which is sufficient to meet the system's requirements for processing the highest bandwidth video stream, thereby processing the video data stream in a timely and efficient manner, thus achieving a balance between system performance and power consumption.

[0036] In one embodiment, the inline horizontal blanking area statistics module 13 integrates a first register, which is used to store a configurable interval time parameter. The interval time parameter is used to determine the time range within which the inline horizontal blanking area statistics module 13 performs statistics on the first data valid identifier.

[0037] It is understandable that the first register is integrated inside the inline horizontal blanking area statistics module 13, and the first register stores the interval time parameter. The time interval refers to the length of time between the beginning and end of each frame in the video. This length of time can be adjusted through the first register to meet different needs and requirements of the system.

[0038] The inline horizontal blanking region statistics module 13 can directly access the first register, simplifying the interface and connection between modules and improving system integration. The interval time parameter can be set independently, thereby better controlling system time and processing speed to meet system requirements for real-time performance and efficiency.

[0039] In one embodiment, the RC ring oscillator circuit controller 14 integrates a second register, which stores a configurable first comparison threshold and a minimum frequency threshold. The first comparison threshold is used to trigger the adjustment of the oscillation frequency, and the minimum frequency threshold is the minimum protection value of the oscillation frequency.

[0040] It is understood that the second register is integrated inside the RC ring oscillator circuit controller 14. The second register stores a first comparison threshold and a minimum frequency threshold. The first comparison threshold is used to compare with the value of the horizontal blanking area in the row, thereby triggering the adjustment of the oscillation frequency. When the value of the horizontal blanking area in the row is less than the first comparison threshold, the oscillation frequency of the RC ring oscillator 15 remains unchanged; when the value of the horizontal blanking area in the row is greater than the first comparison threshold, the adjustable RC parameter of the RC ring oscillator 15 is controlled to reduce its oscillation frequency. The difference between the value of the horizontal blanking area in the row and the first comparison threshold determines the magnitude of the output frequency adjustment. Since the RC ring oscillator 15 has a response time requirement for parameter changes, reducing the oscillation frequency of the RC ring oscillator 15 is a gradual and slow adjustment process to prevent the oscillation frequency of the RC ring oscillator 15 from being adjusted too low due to a poor response time. At the same time, the RC ring oscillator circuit controller 14 also protects the minimum oscillation frequency of the RC ring oscillator 15. When the value to be adjusted is already less than the predetermined minimum frequency threshold, the oscillation frequency of the RC ring oscillator 15 will no longer be adjusted. The first comparison threshold and the minimum frequency threshold can be adjusted through the second register.

[0041] The RC ring oscillator circuit controller 14 can directly access the second register, simplifying the interface and connection between modules and improving system integration. By setting a minimum frequency threshold, the RC ring oscillator 15 is protected from being adjusted to an excessively low oscillation frequency, ensuring its normal operation. The first comparison threshold and the minimum frequency threshold can be set manually, allowing these parameters to be set and modified according to actual needs, increasing system flexibility.

[0042] In one embodiment, the in-line total time monitoring module 17 integrates a third register, which stores a configurable second comparison threshold. The second comparison threshold is used to trigger the setting of the in-line total time reduction flag to a high level.

[0043] It is understood that the third register is integrated inside the inline total time monitoring module 17. The third register stores the second comparison threshold. The inline total time monitoring module 17 calculates the difference between the total time of the last line of video image in the current frame and the total time of the last line of video image in the previous frame, and outputs an inline total time decrease indicator based on the difference. When the difference does not exceed the second comparison threshold, it indicates that the frame refresh rate remains stable, and a low-level inline total time decrease indicator is output. When the difference exceeds the set threshold, it indicates that the frame refresh rate increases, and a high-level inline total time decrease indicator is output. The second comparison threshold can be adjusted through the third register. When it is necessary to detect large or frequent changes in the frame refresh rate, a larger second comparison threshold can be set; when it is necessary to accurately detect small changes in the frame refresh rate, a smaller second comparison threshold can be set.

[0044] The in-line total time monitoring module 17 can directly access the third register, simplifying the interface and connection between modules and improving system integration. The second comparison threshold can be set to suit different application scenarios and requirements.

[0045] In one embodiment, such as Figure 2 As shown, the fixed frequency clock is a clock phase-locked loop 16.

[0046] It is understandable that the clock signal generated by the system's clock phase-locked loop 16 can be directly reused, as long as the frequency of the clock signal meets the maximum bandwidth of the video stream for system image signal processing, thereby reducing the complexity, cost and power consumption of chip design.

[0047] In one embodiment, the video image receiver 11 uses an eDP or MIPI interface to receive and process raw video stream signals.

[0048] eDP and MIPI interfaces enable low power consumption, so using these interfaces in the video image receiver 11 can further reduce the power consumption of the device and improve the standby time and lifespan of the device.

[0049] In some embodiments, to more intuitively and comprehensively illustrate the adaptive optimization circuit for the video stream processing clock described above, the following are application examples of this adaptive optimization circuit for the video stream processing clock. It should be noted that the embodiments given in this specification are merely illustrative and not the only limitation on specific embodiments of the present invention. Those skilled in the art can employ the above-described adaptive optimization circuit for the video stream processing clock based on the illustrative embodiments provided by the present invention to achieve a balance between performance and power consumption.

[0050] After the chip is powered on and initialized, the fixed frequency of the clock phase-locked loop and the oscillation frequency of the RC oscillator are configured and output through registers to meet the maximum bandwidth of the current application's image data stream.

[0051] After the video receiver receives a normal video stream, the horizontal timing controller starts working. Following the ping-pong principle, the two SRAM buffers alternately write odd and even rows of image data. The first row of image data (odd-numbered rows) is written to the Ping SRAM buffer, and the second row (even-numbered rows) is written to the Pong SRAM buffer. After the first row is written to the Ping SRAM buffer, the reading action from the Ping SRAM buffer begins, while the Pong SRAM buffer begins writing the next row. The time it takes for the Ping SRAM buffer to read data corresponds to the time it takes for the Pong SRAM buffer to write data. In this way, through the alternating reading and writing of the two SRAM buffers, continuous processing and output of video data can be achieved. When the Ping SRAM buffer is finished reading data, the read action becomes idle, waiting for the Pong SRAM buffer to finish writing. This process from the completion of reading from the Ping SRAM buffer to the completion of writing from the Pong SRAM buffer is the horizontal blanking region within the output video data stream. This process is repeated until a frame of image data has been completely output by the horizontal timing controller. There is a one-line time delay from image input to output.

[0052] The inline horizontal blanking area statistics module of the output video image data uses the video stream processing clock signal to count the number of inline horizontal blanking area clock cycles according to the time interval in frames (this time interval register is configurable) and outputs it to the RC ring oscillator circuit controller.

[0053] The RC ring oscillator circuit controller compares the number of clock cycles in the horizontal blanking region within a row with a threshold (configurable in a register). When the value exceeds the threshold, it controls the adjustable RC parameters of the RC ring oscillator to reduce its output frequency; otherwise, it maintains the RC ring oscillator's output frequency unchanged. Because the RC ring oscillator has a response time requirement for parameter changes, reducing the RC ring oscillator's output frequency is a gradual and slow process to prevent excessively low frequency adjustments due to poor response time. Simultaneously, this module also protects the RC ring oscillator circuit for a minimum output frequency. When the required adjustment value is already below the predetermined minimum frequency threshold (configurable in a register), no further adjustments are made to the RC ring oscillator circuit, and the clock remains at this minimum value.

[0054] Meanwhile, the in-line total time monitoring module operates on a frame-by-frame basis, calculating the total time for each frame. It uses the recovered data clock signal to calculate the total time within a specified line. In DP / eDP / HDMI / MIPI / LVDS Video Receiver image receiving systems, the recovered data clock signal remains unchanged after initialization. This module calculates the total time of the last line of video image in the vertical blanking zone each frame. When it detects that the total video image time of the current frame is less than the total video image time of the previous frame and the difference exceeds a set threshold (configurable by a register), the in-line total time reduction flag goes high; otherwise, it goes low.

[0055] The clock multiplexing module normally selects the RC ring oscillator circuit as the output clock. When the total line time reduction indicator goes high, it immediately switches to the clock output of the phase-locked loop circuit. This clock multiplexing module is designed to support dynamic clock switching and prevent glitches. Since the video stream processing clock only starts to be used on the second line of each frame, the total line time reduction indicator begins to change before the first line. This ensures that the clock has stably switched to the PLL circuit output clock before the video stream processing clock is used, preventing data loss. A high total line time reduction indicator indicates a higher input video image frame rate, requiring a faster video stream processing clock to process the video data stream promptly. If the clock switching is not timely, image data loss may occur. This invention avoids this risk.

[0056] Specifically, a 4K UHD (3840x2160, 4K indicates a horizontal resolution of approximately 4000 pixels, UHD stands for Ultra High Definition) progressive scan 60fps image processing system has a total of 4400 pixel clock cycles per line, of which 560 pixel clock cycles are for horizontal blanking within the line. First, timing is adjusted through two lines of SRAM cache to reduce the video stream processing clock from 594MHz to 148.5MHz, reducing the horizontal blanking within the line to 140 video stream processing clock cycles. Then, the frequency of the video stream processing clock is further compressed by dynamically and adaptively adjusting the parameters of the RC ring oscillator, resulting in a final video stream processing clock frequency of 131.76MHz. This significantly reduces the operating clock frequency required for image processing, reduces dynamic power consumption, and lowers the complexity of image processing design.

[0057] The calculation method for 4K UHD (3840x2160) progressive scan 60fps refresh rate is as follows:

[0058] The time unit "pixel" is one pixel clock cycle, and the pixel clock frequency (Pixel_Clock_Rate) is 594MHz.

[0059] Horizontal Total (Htotal) in a single line: 4400;

[0060] Effective pixel duration (Hactive, Horizontal Active) within a single row: 3840;

[0061] Horizontal blanking time within a single line (Hblank): 560;

[0062] Output the minimum horizontal blanking time Hblank_min (Min Horizontal Blank) within a single line: 16 (adjustable by register configuration);

[0063] Video stream processing clock frequency = (Hactive / 4 + Hblank_min) * Pixel_Clock_Rate / Htotal

[0064] =131.76MHz.

[0065] In one embodiment, this application provides a video stream processing device, including the adaptive optimization circuit 100 for video stream processing clock provided in any of the above embodiments.

[0066] It is understood that the specific structure and explanation of the adaptive optimization circuit 100 for the video stream processing clock in the video stream processing device can be understood by referring to the corresponding structure and explanation in the various embodiments of the adaptive optimization circuit 100 for the video stream processing clock described above, and will not be repeated here or hereafter. Those skilled in the art will understand that, in addition to the adaptive optimization circuit 100 for the video stream processing clock described above, the video stream processing device may also include other existing necessary structural components not mentioned in this specification. Specific details can be understood by referring to the structural composition of existing video stream processing devices in the art, and will not be elaborated upon here.

[0067] The aforementioned video stream processing device employs an adaptive optimization circuit 100 for the video stream processing clock. The inline horizontal blanking area statistics module 13 counts the first valid data identifiers and outputs the number of inline horizontal blanking areas. The RC ring oscillator controller 14 can reduce the oscillation frequency of the RC ring oscillator 15 based on the statistical results, thereby adaptively reducing the frequency of the video stream processing clock signal until the output inline horizontal blanking time is maintained at the minimum value required by the system. Therefore, power consumption is minimized while ensuring system performance. Since the inline total time monitoring module 17 outputs an inline total time reduction indicator by counting valid pixel area identifiers, the clock multiplexing switching circuit 18 outputs a clock signal based on this indicator. When this indicator indicates that the frame refresh rate remains stable, the clock multiplexing switching circuit 18 outputs a lower frequency first clock signal; when the indicator indicates that the frame refresh rate increases, the clock multiplexing switching circuit 18 immediately switches to a higher frequency second clock signal, whose frequency is sufficient to meet the system's requirements for processing the highest bandwidth video stream, thus processing the video data stream in a timely and efficient manner, achieving a balance between system performance and power consumption.

[0068] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0069] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0070] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. An adaptive optimization circuit for video stream processing clock, characterized in that, It includes a video image receiver, a horizontal timing adjustment controller, an inline horizontal blanking area statistics module, an RC ring oscillator circuit controller, an RC ring oscillator, a fixed frequency clock, an inline total time monitoring module, and a clock multiplexing switching circuit; The output of the video image receiver is connected to the input of the horizontal timing adjustment controller and the inline total time monitoring module, respectively. The first output of the horizontal timing adjustment controller is used to output the video stream. The second output of the horizontal timing adjustment controller is connected to the input of the inline horizontal blanking area statistics module. The output of the inline horizontal blanking area statistics module is connected to the input of the RC ring oscillator circuit controller. The output of the RC ring oscillator circuit controller is connected to the input of the RC ring oscillator and the fixed frequency clock, respectively. The outputs of the RC ring oscillator, the fixed frequency clock, and the inline total time monitoring module are connected to the input of the clock multiplexing switching circuit, respectively. The output of the clock multiplexing switching circuit is connected to the input of the horizontal timing adjustment controller and the inline horizontal blanking area statistics module, respectively. The video image receiver is used to receive and parse the raw video stream signal, and output timing control signals and data channel signals. The horizontal timing adjustment controller is used to alternately read and write the data channel signal through two SRAM buffers according to the timing control signal and the video stream processing clock signal generated by the clock multiplexing switching circuit, and output the video stream and the first data valid identifier. The horizontal blanking area statistics module is used to count the first data valid identifier according to the video stream processing clock signal and output the horizontal blanking area value. The RC ring oscillator circuit controller is used to adjust the oscillation frequency of the RC ring oscillator according to the horizontal blanking area value. The oscillator is used to output a first clock signal according to the oscillation frequency, the fixed frequency clock is used to output a second clock signal, the in-line total time monitoring module is used to count the effective pixel area identifiers according to the recovery data clock and output an in-line total time reduction identifier, the clock multiplexing switching circuit is used to output the video stream processing clock signal according to the in-line total time reduction identifier; the in-line total time reduction identifier is used to indicate whether the frame refresh rate remains stable or increases, the video stream processing clock signal includes the first clock signal corresponding to the frame refresh rate remaining stable and the second clock signal corresponding to the frame refresh rate increasing, and the timing control signal includes the recovery data clock and the effective pixel area identifier; The RC ring oscillator circuit controller integrates a second register, which stores a configurable first comparison threshold and a minimum frequency threshold. The first comparison threshold is used to trigger the adjustment of the oscillation frequency. When the number of horizontal blanking sections in a row is less than the first comparison threshold, the oscillation frequency of the RC ring oscillator remains unchanged. When the number of horizontal blanking sections in a row is greater than the first comparison threshold, the adjustable RC parameters of the RC ring oscillator are controlled to reduce the oscillation frequency. The difference between the number of horizontal blanking sections in a row and the first comparison threshold determines the magnitude of the output frequency adjustment. The minimum frequency threshold is the minimum protection value of the oscillation frequency.

2. The adaptive optimization circuit for video stream processing clock according to claim 1, characterized in that, The inline horizontal blanking area statistics module integrates a first register, which stores a configurable interval time parameter. The interval time parameter is used to determine the time range within which the inline horizontal blanking area statistics module performs statistics on the first data valid identifier.

3. The adaptive optimization circuit for video frequency stream processing clock according to claim 1, characterized in that, The in-line total time monitoring module integrates a third register, which stores a configurable second comparison threshold. The second comparison threshold is used to trigger the setting of the in-line total time reduction flag to a high level.

4. The adaptive optimization circuit for video stream processing clock according to any one of claims 1-3, characterized in that, The fixed-frequency clock is a phase-locked loop.

5. The adaptive optimization circuit for video stream processing clock according to claim 4, characterized in that, The video image receiver uses an eDP or MIPI interface to receive and process the raw video stream signal.

6. A video stream processing device, characterized in that, Includes an adaptive optimization circuit for the video stream processing clock according to any one of claims 1-5.

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