Coarse-grained depth testing method and graphics processing unit

Abstract

A coarse-grained depth test method includes: performing a coarse-grained depth test on the current draw-call command; after the coarse-grained depth test of the current draw-call passes, according to the configuration of the current draw-call, in the coarse-grained depth buffer, for the pixel region associated with the current draw-call, set the value of the first flag to indicate whether the coarse-grained depth test of the associated pixel region is disabled, and set the value of the second flag for the associated pixel region in the coarse-grained depth buffer to indicate whether the update of the coarse-grained depth buffer of the associated pixel region is disabled. Based on the above coarse-grained depth test (C-Z test) method, in the case where the coarse-grained depth test of the current draw-call in certain configurations affects the coarse-grained depth test of subsequent draw-calls, the disabling of the C-Z test and the C-Z buffer update is restricted to the pixel region corresponding to the flag, while for the remaining pixel regions where the coarse-grained depth test and the C-Z buffer update are not disabled, subsequent draw-calls can continue to perform the coarse-grained depth test and the C-Z buffer update. In this way, compared with the prior art where other subsequent draw-calls of the entire frame cannot perform the coarse-grained depth test and the C-Z buffer update after the current draw-call, the adverse impact on the effect of the coarse-grained depth test is minimized as much as possible, and the effect of the coarse-grained depth test is improved.

Description

Technical Field

[0001] This application relates to the technical field of Graphics Processing Unit (GPU), and particularly to a coarse-grained depth test method executed in a graphics processing unit. Background Art

[0002] In the current computer graphics system, a virtual 3D object is rendered on a 2D display screen in a graphics processing unit (GPU) by executing a graphics rendering pipeline. Specifically, the GPU receives commands (such as draw-call commands) and / or data (including rendering states, such as the material, texture, shader, etc. of the drawn object) from, for example, a CPU, and receives vertex data from an external system memory (not shown). Then, according to the commands (such as draw-call commands), primitive rendering is performed, and finally an output image on the display screen is generated.

[0003] Generally, a draw-call command performs a coarse-grained depth test (Coarse-Z test, i.e., C-Z test) before the pixel shader to eliminate unnecessary primitives or pixels in advance, so as to improve performance and reduce power consumption. Some draw-calls with special configurations will cause subsequent other draw-calls of the entire frame to be unable to perform the C-Z test, or affect the test effect of subsequent draw-calls. For example, if the drawn object of a draw-call is translucent, after this draw-call, all subsequent draw-calls of the current frame will be unable to update the coarse-grained depth buffer (C-Z buffer) until the current frame rendering ends. Moreover, if the configuration of a draw-call involves enabling the stencil test and the stencil mode is not KEEP, then all subsequent draw-calls of the entire frame after this current draw-call cannot perform the C-Z test and C-Z buffer update. In current GPU applications, a frame often needs to complete a large number of draw-calls, ranging from dozens to hundreds, or even thousands or more. The above situations seriously affect the depth test effect of the GPU. Summary of the Invention

[0004] Embodiments of this application provide a coarse-grained depth test method, which is used to at least solve one of the above-mentioned drawbacks in the prior art.

[0005] According to the first aspect of the present application, there is provided a coarse-grained depth test method executed in a graphics processing unit, including: performing a coarse-grained depth test for a current draw-call command; after the coarse-grained depth test for the current draw-call passes, according to the configuration of the current draw-call, setting the value of a first flag in the coarse-grained depth buffer for a pixel region associated with the current draw-call to indicate whether the coarse-grained depth test for the associated pixel region is disabled, and according to the configuration of the current draw-call, setting the value of a second flag in the coarse-grained depth buffer for the associated pixel region to indicate whether the update of the coarse-grained depth buffer for the associated pixel region is disabled.

[0006] Based on the above coarse-grained depth test (C-Z test) method, corresponding flags are set for the pixel region associated with the current draw-call. In the case where the current draw-call with certain configurations affects the coarse-grained depth test of subsequent draw-calls, the disabling of the C-Z test and the C-Z buffer update is restricted to the pixel region corresponding to the flag, while for the remaining pixel regions where the coarse-grained depth test and the C-Z buffer update are not disabled, subsequent draw-calls can continue to perform the coarse-grained depth test and the C-Z buffer update. In this way, compared with the prior art where subsequent draw-calls for the entire frame after the current draw-call cannot perform the coarse-grained depth test and the C-Z buffer update, the adverse impact on the effect of the coarse-grained depth test is minimized as much as possible, the effect of the coarse-grained depth test is improved, and the GPU performance is further enhanced.

[0007] Optionally, when the configuration of the current draw-call is that the stencil is enabled and the stencil mode is not KEEP, the value of the first flag is set to indicate that the coarse-grained depth test for the associated pixel region is disabled, and the value of the second flag is set to indicate that the update of the depth buffer for the associated pixel region is disabled.

[0008] Optionally, when the configuration of the current draw-call is a translucent rendering object, the value of the first flag is set to indicate that the coarse-grained depth test for the associated pixel region is not disabled, and the value of the second flag is set to indicate that the C-Z buffer update for the associated pixel region is disabled.

[0009] Optionally, after the current frame buffer writing is completed, the values of the first flag and the second flag in the coarse-grained depth buffer are cleared.

[0010] Optionally, before performing the coarse-grained depth test of the current draw-call, determine the value of the first flag of the associated pixel region. If it indicates that the coarse-grained depth test of the associated pixel region is not disabled, perform the coarse-grained depth test of the draw-call for the associated pixel region.

[0011] Optionally, after the coarse-grained depth test of the current draw-call passes, determine the value of the second flag of the associated pixel region. If it indicates that the coarse-grained depth buffer update is not disabled, perform the coarse-grained depth buffer update of the draw-call for the associated pixel region.

[0012] Optionally, before performing the coarse-grained depth test of the current draw-call, determine the value of the first flag of the associated pixel region. If it indicates that the coarse-grained depth test of the associated pixel region is disabled, end the coarse-grained depth test of the draw-call for the associated pixel region.

[0013] Optionally, after the coarse-grained depth test of the current draw-call passes, determine the value of the second flag of the associated pixel region. If it indicates that the depth buffer update of the associated pixel region is disabled, end the coarse-grained depth test of the draw-call for the associated pixel region and prohibit the execution of the coarse-grained depth buffer update.

[0014] Before all draw-calls of the current frame are cleared from the pipeline, the values of the first flag that disables the C-Z test or the second flag that disables the C-Z buffer update remain unchanged.

[0015] According to the first aspect, the pixel region associated with the draw-call includes a first set of pixel regions and a second set of pixel regions. Before performing the coarse-grained depth test of the current draw-call, determine the values of the first flags of the first set of pixel regions and the second set of pixel regions. If the first flag of the first set of pixel regions is set to disable the coarse-grained depth test and the first flag of the second set of pixel blocks is set to not disable the coarse-grained depth test, then: end the coarse-grained depth test of the draw-call for the first set of pixel regions, and perform the coarse-grained depth test of the draw-call for the second set of pixel regions.

[0016] According to the second aspect of the present application, there is provided a method for performing a coarse-grained depth test in a graphics processor, including:

[0017] When a graphics processing unit performs tiled rendering (TBR), in the tile pipeline of TBR, coarse-grained depth testing for the current draw-call command is performed; after the coarse-grained depth testing of the current draw-call passes, according to the configuration of the current draw-call, the value of a first flag is set in the coarse-grained depth buffer for the pixel region associated with the current draw-call, indicating whether the coarse-grained depth testing of the associated pixel region is disabled, and according to the configuration of the current draw-call, the value of a second flag is set in the coarse-grained depth buffer for the associated pixel region, indicating whether the update of the coarse-grained depth buffer of the associated pixel region is disabled.

[0018] Optionally, in the tile pipeline, the screen area is divided into multiple tiles, each tile is divided into multiple of the pixel regions, and in the coarse-grained depth buffer corresponding to each tile, the values of the first flag and the second flag corresponding to each pixel region are stored.

[0019] Optionally, in the coarse-grained depth testing in the rendering pipeline of TBR, before performing the coarse-grained depth testing of the current draw-call, the value of the first flag of the pixel region associated with the current draw-call is determined according to the coarse-grained depth buffer generated in the tile pipeline. If it indicates that the coarse-grained depth testing of the associated pixel region is disabled, the coarse-grained depth testing of the rendering pipeline of the current draw-call for the associated pixel region is ended.

[0020] Optionally, in the coarse-grained depth testing in the rendering pipeline of TBR, after the coarse-grained depth testing of the current draw-call passes, the value of the second flag of the associated pixel region is determined according to the coarse-grained depth buffer generated in the tile pipeline. If it indicates that the update of the coarse-grained depth buffer of the associated pixel region is disabled, the coarse-grained depth testing of the current draw-call for the associated pixel region is ended and the execution of the coarse-grained depth buffer update is prohibited.

[0021] According to a third aspect of the present application, a graphics processing unit is provided, including a memory for storing instructions, and a processing unit configured to execute any of the above methods when executing the instructions.

[0022] According to a fourth aspect of the present application, a computer-readable storage medium is provided. Program code is stored in the computer-readable storage medium, and when the program code is executed by a computer or a processor, any of the above methods is implemented.

[0023] According to the fifth aspect of the present application, there is provided a computer program product. When the program code included in the computer program product is executed by a computer or a processor, any one of the above methods is implemented.

[0024] According to the sixth aspect of the present application, there is provided a graphics processing system, including: a test unit configured to perform a coarse-grained depth test for a current draw-call command; a setting unit configured to: after the coarse-grained depth test of the current draw-call passes, according to the configuration of the current draw-call, set the value of a first flag in the coarse-grained depth buffer for the pixel region associated with the current draw-call to indicate whether the coarse-grained depth test of the associated pixel region is disabled, and according to the configuration of the current draw-call, set the value of a second flag in the coarse-grained depth buffer for the associated pixel region to indicate whether the update of the coarse-grained depth buffer of the associated pixel region is disabled.

[0025] Optionally, the setting unit is further configured to: after the current frame buffer writing is completed, clear the values of the first flag and the second flag in the coarse-grained depth buffer.

[0026] Optionally, the graphics processing system further includes a determination unit configured to: before performing the coarse-grained depth test of the current draw-call, determine the value of the first flag of the associated pixel region; the test unit is configured to: if it indicates that the coarse-grained depth test of the associated pixel region is not disabled, perform the coarse-grained depth test of the current draw-call for the associated pixel region.

[0027] Optionally, the determination unit is configured to: before performing the coarse-grained depth test of the current draw-call, determine the value of the first flag of the associated pixel region; the test unit is configured to: if the value of the first flag of the associated pixel region indicates that the coarse-grained depth test of the associated pixel region is disabled, end the coarse-grained depth test of the draw-call for the associated pixel region.

[0028] Optionally, the determination unit is configured to: after the coarse-grained depth test of the current draw-call passes, determine the value of the second flag of the associated pixel region; the test unit is configured to: if the value of the second flag of the associated pixel region indicates that the update of the depth buffer of the associated pixel region is disabled, end the coarse-grained depth test of the current draw-call for the associated pixel region and prohibit the execution of the coarse-grained depth buffer update.

[0029] Optionally, the setting unit is configured to: keep the values of the first flag for disabling coarse-grained depth testing and the second flag for disabling coarse-grained depth buffer update unchanged before the coarse-grained depth testing of all draw-calls in the current frame is completed.

[0030] Optionally, the pixel region associated with the current draw-call includes a first set of pixel regions and a second set of pixel regions. The determining unit is configured to: before performing the coarse-grained depth testing of the current draw-call, determine the value of the first flag of the first set of pixel regions and the second set of pixel regions; the testing unit is configured to: if the first flag of the first set of pixel regions is set to disable coarse-grained depth testing while the first flag of the second set of pixel blocks is set to not disable coarse-grained depth testing, end the coarse-grained depth testing of the current draw-call for the first set of pixel regions and perform the coarse-grained depth testing of the current draw-call for the second set of pixel regions.

[0031] According to a seventh aspect of the present application, there is provided a graphics processing system, including: a testing unit configured to: when the graphics processor performs tiled-based rendering (TBR), perform coarse-grained depth testing of the current draw-call command in the tile pipeline of TBR; a setting unit configured to: after the coarse-grained depth testing of the current draw-call passes, according to the configuration of the current draw-call, set the value of the first flag in the coarse-grained depth buffer for the pixel region associated with the current draw-call, indicating whether the coarse-grained depth testing of the associated pixel region is disabled, and according to the configuration of the current draw-call, set the value of the second flag in the coarse-grained depth buffer for the associated pixel region, indicating whether the coarse-grained depth buffer update of the associated pixel region is disabled.

[0032] Optionally, in the tile pipeline, the screen area is divided into several tiles, and each tile is divided into several of the pixel regions. In the coarse-grained depth buffer corresponding to each tile, the values of the first flag and the second flag corresponding to each pixel region are stored.

[0033] Optionally, the determining unit is configured to: in the coarse-grained depth testing in the rendering pipeline of TBR, before performing the coarse-grained depth testing of the current draw-call, determine the value of the first flag of the pixel region associated with the current draw-call according to the coarse-grained depth buffer generated in the tile pipeline; the testing unit is configured to: if it is indicated that the coarse-grained depth testing of the associated pixel region is disabled, end the coarse-grained depth testing of the current draw-call for the associated pixel region.

[0034] Optionally, the determining unit is configured to: in the coarse-grained depth test in the rendering pipeline of the TBR, after the coarse-grained depth test of the current draw-call passes, determine the value of the second flag of the pixel region associated with the current draw-call; the testing unit is configured to: if it is indicated that the depth buffer update of the associated pixel region is disabled, end the coarse-grained depth test of the current draw-call for the associated pixel region and prohibit the execution of the coarse-grained depth buffer update.

[0035] According to an eighth aspect of the present application, there is provided a graphics processor, including: a coarse-grained depth test unit configured to: perform a coarse-grained depth test of a current draw-call command; after the coarse-grained depth test of the current draw-call passes, according to the configuration of the current draw-call, set the value of a first flag in the coarse-grained depth buffer for the pixel region associated with the current draw-call, indicating whether the coarse-grained depth test of the associated pixel region is disabled, and according to the configuration of the current draw-call, set the value of a second flag in the coarse-grained depth buffer for the associated pixel region, indicating whether the coarse-grained depth buffer update of the associated pixel region is disabled; a coarse-grained depth buffer configured to store the values of the first flag and the second flag of the associated pixel region.

[0036] Optionally, the coarse-grained depth test unit is configured to: before performing the coarse-grained depth test of the current draw-call, read the value of the first flag for the associated pixel region from the coarse-grained depth buffer, and if it is indicated that the coarse-grained depth test of the associated pixel region is not disabled, perform the coarse-grained depth test of the draw-call for the associated pixel region.

[0037] Optionally, the coarse-grained depth test unit is configured to: after the coarse-grained depth test of the current draw-call passes, read the value of the second flag for the associated pixel region from the coarse-grained depth buffer, and if it is indicated that the coarse-grained depth buffer update is not disabled, perform the coarse-grained depth buffer update of the draw-call for the associated pixel region.

[0038] Optionally, the coarse-grained depth test unit is configured to: before performing the coarse-grained depth test of the current draw-call, read the value of the first flag for the associated pixel region from the coarse-grained depth buffer, and if it is indicated that the coarse-grained depth test of the associated pixel region is disabled, end the coarse-grained depth test of the draw-call for the associated pixel region.

[0039] Optionally, the coarse-grained depth test unit is configured to: after the coarse-grained depth test of the current draw-call passes, read the value of the second flag for the associated pixel region from the coarse-grained depth buffer, and if it is indicated that the depth buffer update of the associated pixel region is disabled, end the coarse-grained depth test of the draw-call for the associated pixel region and prohibit performing a coarse-grained depth buffer update.

[0040] Optionally, the pixel regions associated with the draw-call include a first set of pixel regions and a second set of pixel regions, and the coarse-grained depth test unit is configured to: before performing the coarse-grained depth test of the current draw-call, read the value of the first flag of the first set of pixel regions and the value of the first flag of the second set of pixel regions from the coarse-grained depth buffer respectively; if the first flag of the first set of pixel regions is set to disable the coarse-grained depth test and the first flag of the second set of pixel regions is set to not disable the coarse-grained depth test, then: end the coarse-grained depth test of the draw-call for the first set of pixel regions, and perform the coarse-grained depth test of the draw-call for the second set of pixel regions.

[0041] According to a ninth aspect of the present application, there is provided a graphics processor, including: a coarse-grained depth test unit configured to: during tile-based rendering (TBR), perform a coarse-grained depth test of a current draw call command in a tile pipeline of the TBR; after the coarse-grained depth test of the current draw-call passes, according to the configuration of the current draw-call, set the value of a first flag in the coarse-grained depth buffer for a pixel region associated with the current draw-call, indicating whether the coarse-grained depth test of the associated pixel region is disabled, and according to the configuration of the current draw-call, set the value of a second flag in the coarse-grained depth buffer for the associated pixel region, indicating whether the coarse-grained depth buffer update of the associated pixel region is disabled; a coarse-grained depth buffer configured to: store the value of the first flag and the value of the second flag for the pixel region.

[0042] Optionally, in the tile pipeline, the screen area is divided into a plurality of tiles, each tile is divided into a plurality of the pixel regions, and in the coarse-grained depth buffer corresponding to each tile, the values of the first flag and the second flag corresponding to each of the pixel regions are stored.

[0043] Optionally, a coarse-grained depth test unit is configured to: in the coarse-grained depth test in the rendering pipeline of the TBR, before performing the coarse-grained depth test of the current draw-call, read the value of the first flag of the pixel region associated with the current draw-call from the coarse-grained depth buffer generated by the tiling pipeline, and if it indicates that the coarse-grained depth test of the associated pixel region is disabled, end the coarse-grained depth test of the rendering pipeline of the current draw-call for the associated pixel region.

[0044] Optionally, a coarse-grained depth test unit is configured to: in the coarse-grained depth test in the rendering pipeline of the TBR, after the coarse-grained depth test of the current draw-call passes, read the value of the second flag of the associated pixel region from the coarse-grained depth buffer generated by the tiling pipeline, and if it indicates that the update of the coarse-grained depth buffer of the associated pixel region is disabled, end the coarse-grained depth test of the current draw-call for the associated pixel region and prohibit the execution of the coarse-grained depth buffer update.

[0045] Based on the C-Z test method proposed in the embodiments of the present application, in the case where the C-Z test of the current draw-call in certain configurations affects the C-Z test of subsequent draw-calls, by setting flags for the associated pixel regions, the disabling of the C-Z test and the C-Z buffer update is restricted to the affected pixel regions, while the unaffected pixel regions can still perform the C-Z test of subsequent draw-calls and the update of the coarse-grained depth buffer (C-Z buffer). In this way, compared with the prior art where the entire frame cannot continue to perform the C-Z test or the C-Z buffer update, the adverse impact on the C-Z test effect is minimized as much as possible. Description of the Drawings

[0046] Figure 1 Schematic diagram of a computing device for implementing the method of the embodiments of the present application.

[0047] Figure 2 Schematic diagram of a GPU for implementing the method of the embodiments of the present application.

[0048] Figure 3 An example of a rendering pipeline implemented in a GPU for implementing the method of the embodiments of the present application;

[0049] Figure 4 Schematic diagram of an implementation scenario of a coarse-grained depth test method provided in the first embodiment of the present application;

[0050] Figure 5 Flowchart of the coarse-grained depth test method provided in the embodiments of the present application;

[0051] Figure 6 Schematic diagram of an implementation scenario of the coarse-grained depth test method provided in the second embodiment of the present application;

[0052] Figure 7 Schematic diagram of tile-based rendering (TBR) applied to the coarse-grained depth test method provided in the third embodiment of the present application;

[0053] Figure 8 Schematic diagram of a graphics processing system for implementing the coarse-grained depth test method of the embodiments of the present application. Detailed implementation manners

[0054] The following describes in detail the technical solutions provided by the present application in conjunction with the accompanying drawings and embodiments. It should be understood that the system structure and application scenarios provided in the embodiments of the present application are mainly used to explain some possible implementation manners of the technical solutions of the present application, and should not be construed as the sole limitation of the technical solutions of the present application. Those of ordinary skill in the art can know that with the changes of the system and the emergence of updated application scenarios, the technical solutions provided by the present application are still applicable.

[0055] Terms such as "first", "second", and "third" in the embodiments of the present application and the accompanying drawings are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. In addition, the terms "include" and "have" and any variations thereof are intended to mean non-exclusive inclusion. For example, a series of steps or units are included. The method, system, product, or device does not necessarily have to be limited to the steps or units literally listed, but may include other steps or units not literally listed or inherent to these processes, methods, products, or devices.

[0056] It should be understood that in the present application, the magnitude of the step numbers does not mean the order of execution. The execution order of each step should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

[0057] The coarse-grained depth test method provided by the embodiments of the present application is implemented, for example, in a computing device. The overall architecture of the computing device is as Figure 1 shown.

[0058] Refer to Figure 1, which shows a computing device 100 configured to implement one or more aspects of embodiments of the present invention. The computing device 100 may include, but is not limited to, the following: a personal computer, such as a laptop computer, a desktop computer, a tablet computing device, etc., and may also be a wireless device, a mobile phone (including a smart phone), a personal digital assistant (PDA), a video game console (including a video display, a mobile video game device, a mobile video conferencing unit), a television set-top box, an in-vehicle intelligent system, a smart wearable device, an e-book reader, a fixed or mobile media player, etc.

[0059] In Figure 1 an embodiment, the computing device 100 may include a central processing unit (CPU) 102 and a system memory 101 that communicates via, for example, a memory bridge 104. The memory bridge 104 may be, for example, a northbridge chip, and is connected to an I / O (input / output) bridge 105 via a bus or other communication path 112 (such as a HyperTransport link). The I / O bridge 105 may be, for example, a southbridge chip, which receives user input from one or more input devices 107 (such as a keyboard, a mouse, a trackball, a touch screen of a display device, or other types of input devices) and forwards the input to the CPU 102 via the communication path 112 and the memory bridge 104. A graphics processing unit (GPU) 103 is coupled to the memory bridge 104 via a bus or other communication path 112 (such as PCI Express, Accelerated Graphics Port, or HyperTransport link) to communicate with the CPU 102 and the system memory 101. In one embodiment, the GPU 103 may perform graphics processing operations to generate pixel data and pass the pixel data to the display device 110.

[0060] The system disk 106 is also connected to the I / O bridge 105. The computing device 100 may also include other components (not explicitly shown), such as USB or other port connections, a CD drive, a DVD drive, and similar components, which may also be connected to the I / O bridge 105. The Figure 1 communication paths interconnecting the various components in may be implemented using any suitable protocol, such as PCI (Peripheral Component Interconnect), PCI-Express, AGP (Accelerated Graphics Port), HyperTransport, or any other bus or point-to-point communication protocol, and the connections between different devices may use different protocols known in the art.

[0061] Figure 1The configuration of the computing device 100 shown is merely an example, and those skilled in the art can understand that there may be computing devices 100 with other configurations. It should be understood that changes and modifications are possible. The connection topology, for example, the number and arrangement of bridges, the number of CPUs, and the number of GPUs can be modified as needed. In other embodiments, the computing device 100 may include two or more CPUs 102 and two or more GPUs 103.

[0062] In one embodiment, the GPU 103 includes circuitry optimized for graphics and video processing, including, for example, video output circuitry. The GPU 103 can be integrated with one or more other components, such as a memory bridge 104, a CPU 102, and an I / O bridge 105 to form a system-on-chip (SOC).

[0063] Figure 2 The computing device 100 in which the method of embodiments of the present invention can be implemented is shown Figure 1 A schematic block diagram of the GPU 103 in the computing device 100. In one embodiment, the GPU 103 includes circuitry for graphics processing and video processing.

[0064] The GPU 103 may include an array of processing cores 203, which may include a plurality of processing cores 2031-2036. Figure 4 Only 6 processing cores are shown as an example, and those skilled in the art can understand that the number of processing cores can vary. The shown processing cores can be, for example, general-purpose processing cores or fixed-function processing cores. Based on the plurality of general-purpose processing cores in the processing core array 203, the GPU 103 is capable of concurrently executing a large number of program tasks or computing tasks. Each general-purpose processing core can be programmed to execute processing tasks related to various programs, including but not limited to, graphics rendering operations, etc. The fixed-function processing cores may include hardware hard-wired to perform certain specific functions.

[0065] In embodiments of the present invention, the graphics memory 204 may be a part of the GPU 103. The GPU 103 can read data from the graphics memory 204 and write data to the graphics memory 204. That is, the GPU 103 can use a local storage device instead of an external memory to store data. In some cases, the GPU 103 can also read and write data using the system memory 101 via a bus, such as a communication path 112. The graphics memory 204 may include one or more volatile or non-volatile memories or storage devices, such as random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, magnetic data storage devices, or optical storage devices, etc.

[0066] The GPU 103 can be configured to perform the following various operations: receive graphic data from the CPU 102 and / or the system memory 101 via the memory bridge 104 and a bus, such as the communication path 112, and then process the graphic data to generate pixel data, interact with the local graphic memory 204 to store and update pixel data, transfer pixel data to the display device 110, etc.

[0067] In operation, the CPU 102 is the main processor of the computing device 100, which controls and coordinates the operations of other components. Specifically, the CPU 102 issues commands to control the operation of the GPU 103. In some embodiments, the CPU 102 writes a command stream for controlling the GPU 103 to, for example, the system memory 101, the graphic memory 204, or other storage locations accessible by both the CPU 102 and the GPU 103. The GPU 103 reads the command stream and can execute the commands asynchronously with respect to the operation of the CPU 102.

[0068] As Figure 2 shown, the GPU 103 includes an I / O (input / output) unit 202, which communicates with other components of the computing device 100 via the communication path 112 connected to the memory bridge 104. The connection of the GPU 103 to other components of the computing device 100 can also vary. In some embodiments, the GPU 103 can be implemented as an expansion card, for example, it can be inserted into an expansion slot of the computing device 100.

[0069] In one embodiment, the communication path 112 through which the GPU 103 is connected to the memory bridge 104 can be a PCI-EXPRESS link. As is known in the art, dedicated channels are allocated to the GPU 103 in a PCI-EXPRESS link. The I / O unit 202 receives all incoming data packets (or other signals) from the communication path 112, directs the incoming data packets to the appropriate components of the GPU 103, or transmits data packets (or other signals) via the communication path 112 to components external to the GPU 103. For example, the I / O unit 202 can direct commands related to processing tasks to the scheduler 201, while directing commands related to memory operations (e.g., reads or writes to the graphic memory 204) to the graphic memory 204.

[0070] The processing core array 203 can receive processing tasks to be executed from the scheduler 201. The scheduler 201 can independently schedule tasks for execution by the resources of the GPU 103 (e.g., one or more processing cores of the processing core array 203). In one embodiment, the scheduler 201 can be a hardware processor. In Figure 2In the illustrated embodiment, the scheduler 201 may be included in the GPU 103. In other embodiments, the scheduler 201 may also be a unit separate from the CPU 102 and the GPU 103. The scheduler 201 may also be any processor configured to receive a stream of commands and / or operations.

[0071] In operation, the CPU 102, via Figure 1 the GPU driver included in the system memory 101, may send a command stream including a series of operations to be executed by the GPU 103 to the scheduler 201. The scheduler 201 may receive the operation stream including the command stream through the I / O unit 202 and may process the operations of the command stream sequentially based on the order of operations in the command stream, and may schedule the operations in the command stream to be executed by one or more processing cores in the processing core array 230.

[0072] In practice, each general-purpose processing core may be programmed to perform processing tasks related to various programs, including but not limited to, various operations in a graphics rendering pipeline (e.g., vertex shader and / or pixel shader programs, etc.).

[0073] Figure 3 An example of a graphics rendering pipeline implemented by the GPU 103 is shown.

[0074] It should be noted here that the graphics rendering pipeline is a logical function formed by cascading the processing cores included in the processing core array (e.g., general-purpose processing cores and / or fixed-function processing cores). The scheduler 201, the graphics memory 204, the I / O unit 202, etc. included in the GPU 103 are peripheral circuits or devices for implementing the logical functions of the rendering pipeline. For example, the graphics rendering pipeline generally includes programmable modules and fixed-function modules. The programmable modules are executed by general-purpose processing cores, and the fixed-function modules are implemented by corresponding fixed-function processing cores.

[0075] As Figure 3 shown, for example, the rendering pipeline of the GPU 103 includes an Input Assembly (IA), a Vertex Shader (VS), a Primitive Assembly (PA), a rasterizer, a coarse-grained depth test unit (C-Z test unit), a pixel shader, a depth test unit, and an output unit.

[0076] The above rendering pipeline is only an example and is not limited to the above description. The rendering pipeline may also include other units or modules. The logical order of the above units or modules in the rendering pipeline is also not limited to Figure 3 the example in Figure 3The depth test unit shown is after the pixel shader and serves as a late depth test unit. An early depth test unit (not shown) can also be set before the pixel shader and after the C-Z test unit to perform an Early-Z Test.

[0077] Each of the above units or modules can be implemented in a separately designed fixed-function processor in the GPU 103, or can be implemented by executing a specific program in the processing cores of the GPU 103. For example, the vertex shader can be implemented in a separately designed fixed-function processor in the GPU 103, or can be implemented by executing a shader program in the processing cores of the GPU 103. Similarly, the input assembler can also be implemented in a separately designed fixed-function processor in the GPU 103, or can be implemented by executing a specific program in the processing cores of the GPU 103.

[0078] In addition, as Figure 3 described, there is also a vertex buffer (Vertex Buffer, VB) which is used to receive vertex data from the system memory 101 and then transfer the vertex data into the input assembler. Generally, the vertex buffer is stored in the graphics memory 204 on the GPU 103. In the GPU 103, a cache (not shown) can also be set between the graphics memory 204 and the processing core array 203. The vertex buffer can also be stored in the cache or other storage areas accessible by the processing cores (2031 - 2036). There are also a coarse-grained depth buffer (C-Z buffer), a depth buffer (Depth Buffer, DB), etc. These buffers can be stored in, for example Figure 2 the graphics memory 204 shown, or can be stored in the cache (not shown) or other storage areas accessible by the processing cores.

[0079] When the rendering pipeline is executed, the GPU 103 receives commands (such as draw-call commands) and / or data (including rendering states, such as the material, texture, shader program, etc. of the drawing object) from, for example, the CPU 102, and receives vertex data from the external system memory 101, performs primitive rendering according to the commands (such as draw-call commands), and finally generates an output image on the display screen.

[0080] Specifically, the Input Assembler (IA) receives vertex data (vertex coordinates and indices) from the vertex buffer and combines them into geometric primitives (such as triangles, lines, etc.).

[0081] Next, the vertex shader determines the attributes of the vertices (lighting, color, etc.) and provides the vertex data with completed shading to the primitive assembler. The primitive assembler generates primitives through operations such as clipping, perspective division, and viewport transformation. Then, the rasterizer is used to generate the pixels on the screen representing the corresponding primitives from the primitives generated by the primitive assembler (PA).

[0082] The pixel shader determines the color of each pixel by executing pixel shader instructions. Next, after the pixel shader generates the color of each pixel, the GPU 103 can perform further operations on the pixels, such as performing a depth test on the pixels, etc., and then outputs the finally rendered image to the display device.

[0083] The above description of the functions of each unit or module in the rendering pipeline is only exemplary and not restrictive.

[0084] When the GPU 103 calls the Draw-Call command for rendering, due to the rendering order of the rendering objects, the objects rendered later may be occluded by the objects rendered earlier. In the graphics rendering pipeline, after the rasterizer, a depth test is to be performed on the pixel data to cull the occluded primitives or pixels that no longer need to be rendered.

[0085] In the depth buffer, each pixel stores the corresponding depth value. During the depth test, the current depth value of a pixel is compared with the depth value stored in the current depth buffer corresponding to that pixel. If the current depth value of the pixel is greater than or equal to the depth value stored in the depth buffer, then the pixel is considered to be occluded, so the pixel is discarded, that is, the depth test for that pixel is considered to have failed; if the current depth value of the pixel is less than the depth value stored in the depth buffer, then the depth test for the pixel is considered to have passed, that is, the pixel is not occluded. Furthermore, the current depth value of the pixel is written into the depth buffer to update the depth value in the depth buffer.

[0086] As Figure 3 shown, after rasterization is completed in the rasterizer, the C-Z test can be performed in the C-Z test unit, that is, the depth test is performed at a coarser granularity. After pixel shading is completed in the pixel shader, the depth test can be performed in the depth test unit. When performing the corresponding depth test, the depth value is read from the corresponding buffer for the depth test. If the test passes, the depth value of the pixel is written into the depth buffer to update the depth value in the depth buffer for use in subsequent depth tests.

[0087] Generally speaking, the screen is divided into several equal-sized pixel blocks (usually 4x4 or 8x8, etc.), and each pixel block serves as the unit (granularity) for the C-Z test. The pixel blocks for the C-Z test are not limited to this and can be set to larger or smaller pixel blocks according to needs. In the C-Z test, the maximum depth value (Zmax) and the minimum depth value (Zmin) of the pixel block are calculated, and the average of the maximum depth and the minimum depth value is taken. Then, the average value is compared with the depth value in the coarse-grained depth buffer (C-Z buffer). If the average value is greater than or equal to the depth value in the coarse-grained depth buffer, the pixel block is discarded, that is, the C-Z test fails; if the average value is less than the depth value in the coarse-grained depth buffer, the corresponding pixel block cannot be culled, that is, the C-Z test passes, and then the depth value of the pixel block is written into the coarse-grained depth buffer to update the depth value in the coarse-grained depth buffer.

[0088] The above description of the rendering pipeline implemented for GPU 103 is only an example and not a limitation. For example, Figure 3 the shown rendering pipeline is a rendering pipeline in the immediate mode rendering (IMR) mode, for example. Those skilled in the art can understand that rendering pipelines with various other logical architectures are also possible.

[0089] This application aims to provide a coarse-grained depth test method. This method can be executed in, for example, Figure 3 the C-Z test unit in the shown GPU 103.

[0090] Generally speaking, during rendering, the draw-call commands called by the GPU are configured with specific rendering configurations. Certain specific configurations of draw-call usually have an adverse impact on the C-Z test results of the subsequent draw-call, such as affecting the accuracy of its C-Z test. Such specific configurations of draw-call include but are not limited to: semi-transparent rendering objects, stencil test enabled and the stencil mode is not KEEP, clearing the intermediate local depth buffer, etc. Here, KEEP, one of the stencil modes, means that the value in the corresponding stencil buffer remains unchanged after the stencil test. This is well-known to those skilled in the art and will not be elaborated here.

[0091] For the draw-call with such a configuration for a translucent rendering object, after the C-Z test of this draw-call passes, the C-Z buffer update for this draw-call will no longer be performed; for the pixel region associated with this draw-call, subsequent draw-calls can use the depth value in the previous C-Z buffer for C-Z testing, but C-Z buffer update cannot be performed either.

[0092] In addition, for another configuration of draw-call, for example, when the stencil test is enabled and the stencil mode is not KEEP, after the C-Z test of this draw-call passes, for the pixel region associated with this draw-call, subsequent draw-calls cannot perform C-Z testing nor C-Z buffer update.

[0093] These specific configurations listed above are well-known to those skilled in the art and will not be elaborated here. Such specific configurations of draw-call are not limited to the situations listed above. As long as the specific configuration of a draw-call affects the C-Z test of subsequent draw-calls and requires pausing or disabling the C-Z test or C-Z buffer update of subsequent draw-calls, it is within the scope of this application.

[0094] The coarse-grained depth test method of the embodiments of this application lies in that after the C-Z test of the current draw-call passes, according to the configuration of the current draw-call, set the value of the first flag (flag A) in the coarse-grained depth buffer for the pixel region associated with the current draw-call, indicating whether the C-Z test of the associated pixel region is disabled. Further, according to the configuration of the current draw-call, set the value of the second flag (flag B) in the coarse-grained depth buffer for the associated pixel region, indicating whether the C-Z buffer update of the associated pixel region is disabled.

[0095] Here, specifically, the value of the first flag indicating that the C-Z test of the associated pixel region is not disabled means that the C-Z test can be performed for the associated pixel region. The value of the second flag indicating that the C-Z buffer update of the associated pixel region is not disabled means that the C-Z buffer update can be performed for the associated pixel region. The value of the first flag indicating that the C-Z test of the associated pixel region is disabled means that the C-Z test is prohibited for the associated pixel region. The value of the second flag indicating that the depth buffer update of the associated pixel region is disabled means that the C-Z buffer update is prohibited for the associated pixel region.

[0096] For example, after the C-Z test of the current draw-call passes, according to the configuration of the current draw-call, set the values of the first flag and the second flag for the pixel area associated with the current draw-call in the coarse-grained depth buffer. If the value of the first flag indicates that the C-Z test for the associated pixel area is disabled, subsequent draw-calls cannot perform the C-Z test for this pixel area. If the value of the second flag indicates that the C-Z buffer update for the associated pixel is disabled, subsequent draw-calls cannot perform the C-Z buffer update for this pixel area.

[0097] Based on the above-mentioned coarse-grained depth test method, set the values of the first flag (flag A) and the second flag (flag B) for the pixel area associated with the current draw-call. In the case where the C-Z test of the current draw-call in certain configurations affects subsequent draw-calls, restrict the disabling of the C-Z test and the C-Z buffer update to the pixel area corresponding to the first flag (flag A) and the second flag (flag B). For the remaining pixel areas where the C-Z test and the C-Z buffer update are not disabled, subsequent draw-calls can continue to perform the C-Z test and the C-Z buffer update. In this way, compared with the prior art where all subsequent draw-calls of the entire frame cannot perform the C-Z test and the C-Z buffer update after a current draw-call with certain specific configurations, minimize the adverse impact on the C-Z test effect, improve the C-Z test effect, and further enhance the GPU performance.

[0098] Next, refer to Figures 4 - 5 Describe the coarse-grained depth test method proposed in the first embodiment of the present application in combination with a specific application scenario.

[0099] Example 1:

[0100] In this embodiment, divide the screen into several pixel areas. The size of the pixel area here is arbitrary and can be set to a smaller pixel area according to needs, such as an 8x8 pixel block, or a larger pixel area (for example, a pixel block larger than the 8x8 pixel block). Each pixel area may contain several C-Z test pixel granularities (such as an 8x8 pixel block). As Figure 4 shown, the current screen is divided into 16 pixel areas (t0 to t15). Each pixel area is, for example, an 8x8 pixel block.

[0101] Set the following variables in the coarse-grained depth buffer (C-Z buffer): oZmax, oCZTestStop, oCZUpdateStop. These variables are set for the pixel area and stored in the coarse-grained depth buffer (C-Z buffer).

[0102] These variables are specifically defined as shown in the following table:

[0103]

[0104] In the C-Z buffer, there is a corresponding depth value for each pixel granularity (e.g., an 8x8 pixel block). In an embodiment, in the C-Z buffer, a first flag (flag A), such as oCZTestStop, is set for each pixel region, indicating whether the C-Z test for the corresponding pixel region is disabled. For example, if it is set to 1, it indicates that the C-Z test for the pixel region is disabled; if it is set to 0 (e.g., the initial value), it indicates that the C-Z test for the pixel region is not disabled. Further, a second flag (flag B), such as oCZUpdateStop, can also be set for each pixel region, indicating whether the C-Z buffer update for the pixel region is disabled.

[0105] Specifically, the value of the first flag indicating that the C-Z test for the associated pixel region is not disabled means that the C-Z test can be performed for the associated pixel region. For example, if the draw-call involves drawing the pixel region, the C-Z test for the pixel region can be performed. The value of the second flag indicating that the C-Z buffer update for the associated pixel region is not disabled means that the C-Z buffer update can be performed for the associated pixel region. The value of the first flag indicating that the C-Z test for the associated pixel region is disabled means that the C-Z test is prohibited for the associated pixel region. The value of the second flag indicating that the depth buffer update for the associated pixel region is disabled means that the C-Z buffer update is prohibited for the associated pixel region.

[0106] The C-Z test unit reads the value of the first flag of the associated pixel region from the C-Z buffer to determine whether to perform the C-Z test for the pixel region, and reads the value of the second flag of the associated pixel region from the C-Z buffer to determine whether to perform the C-Z buffer update for the pixel region. If the C-Z buffer update can be performed, the C-Z test unit updates the depth value in the C-Z buffer of the associated pixel region by writing the depth value of the pixel region into the C-Z buffer. If the C-Z buffer update for the pixel region is disabled, the C-Z test unit does not perform the operation of writing to the C-Z buffer for the pixel region.

[0107] In an actual rendering scenario, if the configuration of the current draw call includes stencil test enabled and the stencil mode is not KEEP. In this case, after the C-Z test of the current draw-call passes, the C-Z test cannot be performed, and the C-Z buffer cannot be updated either.

[0108] Specifically, if the current draw-call involves the Stencil test being enabled and the Stencil mode is not KEEP, then in the depth buffer, a first flag is set for the pixel blocks associated with the draw-call, indicating that the C-Z test is disabled for the associated pixel blocks, and a second flag is set for the pixel blocks associated with the draw-call, indicating that the C-Z buffer update is disabled for the associated pixel blocks.

[0109] As Figure 4 shown, currently, 6 consecutive draw-call commands are to be executed to draw objects respectively, such as triangle primitives d1, d2, d3, d4, d5, and d6. The following describes in detail that the configurations of the first and second draw-calls include Stencil enabled and the Stencil mode not being KEEP, while the configurations of the third, fourth, fifth, and sixth draw-calls are cases where Stencil is disabled or the Stencil mode is KEEP.

[0110] As shown in the schematic diagrams (0-a) and (0-b), currently, all pixel regions (t0 to t15) can perform the C-Z test and C-Z buffer update normally. In the C-Z buffer, the values of the first flag oCZTestStop and the second flag oCZUpdateStop corresponding to all current pixel regions are both the initial value 0.

[0111] As shown in the schematic diagrams (1-a) and (1-b), the first draw-call and the second draw-call are to draw two triangles d1 and d2 in the pixel regions t0 and t6 respectively. The first draw-call and the second draw-call perform the C-Z test respectively, and neither d1 nor d2 is culled by the C-Z test, that is, they pass the C-Z test.

[0112] The configurations of the first draw-call and the second draw-call both include Stencil enabled and the Stencil mode not being KEEP. This configuration of the first draw-call and the second draw-call causes the pixel regions of t0 and t6 to be contaminated, that is, it affects the accuracy of the C-Z test of subsequent draw-calls. After that, the C-Z buffer update and the C-Z test cannot be performed in the t0 and t6 regions. At this time, in the C-Z buffer, for the pixel regions of t0 and t6, the first flag oCZTestStop is set to 1, and the second flag oCZUpdateStop is set to 1.

[0113] Next, as shown in the schematic diagram (2-a), for the third and fourth Draw-calls, two new triangles d3 and d4 will appear in the screen area. d3 covers the area t9, and d4 covers the areas t12 to t15. In the C-Z buffer, for the areas t9, t12 to t15, the first flag oCZTestStop is 0, and the second flag oCZUpdateStop is 0. Therefore, the C-Z test and C-Z buffer update for the third and fourth Draw-calls can be executed. After the C-Z test passes, the configuration of the third and fourth Draw-calls is that the stencil is closed or the stencil mode is KEEP, which has no impact on the C-Z test of subsequent draw-calls. Therefore, for the areas t9, t12 to t15, the initial values 0 of the first flag oCZTestStop and the second flag oCZUpdateStop are maintained.

[0114] Next, as shown in the schematic diagram (3-a), for the fifth draw-call (stencil closed or mode KEEP), the triangle d5 of the fifth draw-call will appear in the areas t0 to t3. In the areas t1 to t3, since oCZTestStop = 0 and oCZUpdateStop = 0, the C-Z test and C-Z buffer update can be carried out as normal. However, in the area t0, since oCZTestStop = 1 and oCZUpdateStop = 1, neither the C-Z test nor the C-Z buffer update can be carried out.

[0115] As shown in the schematic diagram (3-b), at this time, it can be understood that the pixel areas associated with the fifth draw-call include the first group of pixel areas (e.g., pixel areas t1 to t3) where the C-Z test is disabled and the C-Z buffer update is disabled, and the second group of pixel areas (e.g., t0) where the C-Z test is not set and the C-Z buffer update is disabled. At this time, for the fifth draw-call, for the first group of pixel blocks (e.g., pixel blocks t1 to t3), the test and update can be carried out as normal, and for the second group of pixel blocks (e.g., t0), the C-Z test and C-Z buffer update are no longer carried out.

[0116] As shown in the schematic diagram (4-a), for the sixth draw-call, the configuration of the sixth draw-call is that the stencil is closed or the mode is KEEP, and it is to draw triangle d6 in pixel regions t4, t6, and t7. For t4 and t7, the first flag oCZTestStop and the second flag oCZUpdateStop are respectively set to 0, that is, for t4 and t7, the C-Z test and C-Z buffer update of the sixth draw-call proceed normally. For t6, both the first flag oCZTestStop and the second flag oCZUpdateStop are set to 1. Therefore, for the sixth draw-call, the C-Z test and C-Z buffer update are performed for t4 and t7, while for t6, the C-Z test and C-Z buffer update are no longer performed. After the C-Z test passes, the configuration of the sixth draw-call is that the stencil is closed or the mode is KEEP, which has no impact on the C-Z test of subsequent draw-calls. Therefore, for t4 and t7, the first flag oCZTestStop and the second flag oCZUpdateStop maintain their initial value of 0.

[0117] Before all draw-calls of the current frame are emptied from the pipeline, the first flag and the second flag that are set to disable the C-Z test and C-Z buffer update remain 1 and are not cleared.

[0118] After all draw-calls of the current frame are emptied from the pipeline, the values of the first flag oCZTestStop and the second flag oCZUpdateStop for these pixel regions in the C-Z buffer can be cleared.

[0119] Figure 5 The flowchart of the C-Z test for the current draw-call is shown.

[0120] Specifically, when the C-Z test for the associated pixel region of the current draw-call starts, as shown in step S10, first determine whether the value of the first flag oCZTestStop corresponding to the associated pixel region is 0. If the value of the first flag oCZTestStop of this pixel region is not 0 but 1, then end the C-Z test of the current draw-call for this pixel region and enter the next level of its rendering pipeline.

[0121] If the value of the first flag oCZTestStop of this pixel region is 0, it indicates that the C-Z test is not disabled, and then the C-Z test for this pixel region can be performed. As shown in step S11, the C-Z test of the current draw-call is executed for this pixel region.

[0122] Next, as shown in step S12, determine whether the C-Z test for this pixel region passes. If the C-Z test fails, reject this pixel region, end the C-Z test for this pixel region, and do not execute the subsequent rendering pipeline of this draw-call. If it passes, then, as shown in step S13, according to the configuration of the current draw-call, set the values of the first flag and the second flag corresponding to this pixel region. For example, if the configuration of the current draw-call is that the stencil is enabled and the stencil mode is not KEEP, then set the values of the first flag oCZTestStop and the second flag oCZUpdateStop corresponding to this pixel region to 1. If the configuration of the current draw-call is normal, that is, it has no impact on the C-Z test of subsequent draw-calls, then keep the values of the first flag oCZTestStop and the second flag oCZUpdateStop corresponding to this pixel region as the initial value 0.

[0123] Next, as shown in step S14, determine whether the value of the second flag oCZUpdateStop corresponding to this pixel region is 0. If it is, then update the depth value of this pixel region in the depth buffer. For example, write the depth value of this pixel region into the depth buffer to overwrite the previous depth value. If not, then the depth value of this pixel region in the depth buffer cannot be updated, end the C-Z test of the current draw-call, and enter the next stage of its rendering pipeline.

[0124] Here, there can be multiple pixel regions associated with the current draw-call. For example, as Figure 4 shown, the pixel regions associated with d4 are t12 - t15. Therefore, the above Figure 5 shown flowchart can be executed for each pixel region.

[0125] Next, as shown in step S15, after performing the C-Z test and / or C-Z buffer update for all pixel regions corresponding to the current draw-call, complete the C-Z test of the current draw-call.

[0126] It can be understood that at the beginning of the current frame rendering, the values of the first flag and the second flag of all pixel regions are 0. Therefore, the C-Z test and the C-Z buffer update can be executed. Once the values of the first flag and the second flag are set to 1, which indicates that the C-Z test and the C-Z buffer update are disabled for this pixel region, then before all draw-calls of the current frame are emptied from the pipeline, the first flag and the second flag that are set to disable the C-Z test and the C-Z buffer update for this pixel region cannot be cleared, that is, cannot be restored to 0.

[0127] After all draw-calls in the current frame are cleared from the pipeline, the values of the first flag oCZTestStop and the second flag oCZUpdateStop for these pixel regions in the C-Z buffer can be cleared.

[0128] Example 2

[0129] See Figure 6 Describe this embodiment in detail. See Figure 6 , currently, 6 consecutive draw-call commands are to be executed to draw objects respectively, such as triangle primitives d1, d2, d3, d4, d5, and d6. The following is a detailed description of the case where the configurations of the first and second draw-calls include the objects being semi-transparent, while the configurations of the third, fourth, fifth, and sixth draw-calls are that the objects are opaque.

[0130] If the C-Z test of the current draw-call passes and the configuration of the current draw-call is that the transparency attribute of the object to be rendered is semi-transparent, it will cause the subsequent draw-calls to be unable to update the C-Z buffer for this pixel region, but the depth value in the previous depth buffer can be used for the C-Z test. Therefore, after the C-Z test of the current draw-call passes, the value of the second flag oCZUpdateStop in the C-Z buffer for the associated pixel region is set to indicate that the C-Z buffer update for the associated pixel region is disabled. Since the depth value in the previous C-Z buffer can still be used for the C-Z test, the value of the first flag for the associated pixel region in the C-Z buffer remains the initial value of 0, that is, the value of the first flag oCZTestStop is set to indicate that the C-Z test for the associated pixel region is not disabled.

[0131] As shown in the schematic diagrams (0-a) and (0-b), currently, initially, the C-Z test and the C-Z buffer update can be normally performed for all pixel regions (t0 to t15), that is, the values of the first flag and the second flag corresponding to all pixel regions are 0.

[0132] As shown in the schematic diagrams (1-a) and (1-b), two primitives, triangles d1 and d2 of the first and second draw-calls are to be drawn on pixel blocks t0 and t6. Neither d1 nor d2 in the first and second draw-calls is culled by the C-Z test, that is, the C-Z test passes. Objects d1 and d2 are semi-transparent. After that, C-Z update cannot be performed in the areas of t0 and t6, but the previous oZmax can still be used to perform the C-Z test on subsequent primitives. Therefore, in the C-Z buffer, for the pixel areas of t0 and t6, the second flag oCZUpdateStop is set to 1, while the first flag oCZTestStop is set to 0.

[0133] Here, the difference from Embodiment 1 is that here, objects d1 and d2 are semi-transparent. After passing the test, their depth values still cannot be updated to the depth buffer, but the previous oZmax is retained in the depth buffer for performing the C-Z test on the primitives of subsequent draw-calls.

[0134] As shown in the schematic diagram (2-a), for the third and fourth draw-calls, primitives, triangles d3 and d4 are to be drawn. Both d3 and d4 are ordinary triangles (opaque), where d3 covers the pixel area of t9, and d4 covers t12 to t15. In the depth buffer, for t9, t12 to t15, the first flag oCZTestStop is set to 0, and the second flag oCZUpdateStop is set to 0. Therefore, the C-Z test and C-Z buffer update can be carried out as normal for the third and third draw-calls.

[0135] As shown in the schematic diagram (3-a), for the fifth draw-call, triangle d5 (opaque) is to be drawn, which covers the pixel blocks of t0 to t3. In the depth buffer, for t1 to t3, since oCZTestStop = 0 and oCZUpdateStop = 0, the C-Z test and C-Z buffer update for the fourth draw-call can be carried out as normal for t1 to t3. For t0, due to the reason of the first draw-call before, the first flag oCZTestStop = 0 and the second flag oCZUpdateStop = 1. Therefore, for t0, the fourth draw-call can only perform the C-Z test, but the C-Z buffer update for t0 cannot be performed. Specifically, the C-Z test unit can perform the C-Z test on t0, but after the test is completed, the depth value of t0 is no longer written into the depth buffer for update.

[0136] Next, as shown in the schematic diagram (4-a), similar to the schematic diagram (3-a), for the sixth draw-call, the primitive triangle d6 (opaque) is to be drawn, which covers the pixel blocks t4, t6, and t7. In the areas of t4 and t7, oCZTestStop = 0 and oCZUpdateStop = 0. Therefore, for t4 and t7, the tests and updates of the sixth draw-call proceed normally. For t6, the Coarse-Z of the sixth draw-call can be performed, but the depth buffer update cannot be performed for t6.

[0137] Preferably, the values of the first flag and the second flag set for the pixel block in the C-Z buffer cannot be cleared before the end of the current frame rendering.

[0138] Figure 5 The flowchart shown also applies to the scenario where the draw-call configuration in this Embodiment 2 is a semi-transparent object. This will not be elaborated here.

[0139] In fact, the embodiments of the present application are not limited to the above situations. In addition to the above situations, for example, there may also be other situations that cause inaccurate or affected C-Z tests for subsequent draw-calls. These are all within the scope of the present application. For example, if the configuration of the current draw-call requires a clear operation on the depth buffer of a local pixel area, then after the C-Z test of such a draw-call passes, the values of the first and second flags are set to 1 for the associated pixel area.

[0140] It can be understood that the above Embodiment 1 and Embodiment 2 are coarse-grained depth test methods implemented in the rendering pipeline of the IMR mode. The coarse-grained depth test method of the embodiments of the present application is not limited to being applied in the IMR mode.

[0141] The following describes the situation where the coarse-grained depth test method of the embodiments of the present application is applied in tile-based rendering (TBR).

[0142] Example 3

[0143] The following combines Figure 5 and Figure 7 to describe the coarse-grained depth test method of this embodiment. This embodiment is directed to the C-Z test situation in TBR. Figure 7 Schematically shows an example of TBR. Figure 5 The flowchart of also applies to the C-Z test in TBR.

[0144] In this embodiment, Figure 5The flowchart is executed in the C-Z test unit of the tile pipeline in the TBR architecture. For example, the flowchart shown in Figure 5 is executed in the C-Z test unit of the tile pipeline.

[0145] As shown in Figure 7 , in TBR (Tile Based Rendering), when rendering, the entire frame is first divided into several tiles in the tile pipeline, a primitive list associated with each tile is generated, and it is stored in the memory.

[0146] Next, in the rendering pipeline, for each tile, the primitive list of the tile generated previously is read from the memory, and then all the primitives of the current tile are rendered according to the primitive list.

[0147] For example, as shown in Figure 7 , the tile pipeline includes: a vertex shader, a primitive assembler, a tiling unit, a rasterizer, and a C-Z test unit. In the tiling unit, the entire frame is divided into several tiles. Through the rasterizer and the C-Z test unit, data of the primitive list associated with each tile is generated, and the data of the primitive list associated with each tile is written into the memory. Here, the memory can be the graphics memory 204 in the GPU 103, or it can be a cache or other storage areas accessible by the processing core.

[0148] In the C-Z test unit in the tile pipeline here, during the C-Z test, a C-Z buffer for each tile is generated and stored in the graphics memory 204 or a cache or other storage areas accessible by the processing core.

[0149] Figure 7 The pipeline of TBR shown in Figure 3 is exemplary. Similar to Figure 3 , the pipeline of this TBR is a logical function formed by cascading the processing cores (such as general-purpose processing cores and / or fixed-function processing cores) included in the processing core array. The scheduler 201, the graphics memory 204, the I / O unit 202, etc. included in the GPU 103 are peripheral circuits or devices for implementing the logical functions of the rendering pipeline. For example, the graphics rendering pipeline usually includes programmable modules and fixed-function modules. The programmable modules are executed by general-purpose processing cores, and the fixed-function modules are implemented by corresponding fixed-function processing cores.

[0150] Other configured TBR pipelines can be adopted, or the above-mentioned rendering pipeline can further include other units or modules. The logical order of the above-mentioned units or modules in the rendering pipeline is not limited to the above description and can be changed as needed.

[0151] For TBR, for example, in the Tiling pipeline, after the tiling unit and rasterization, the coarse-grained depth test method of the embodiments of the present application can be executed, for example Figure 5 the above-mentioned coarse-grained depth test method, and store the corresponding depth value and the values of the first and second marks of the associated pixel region in the C-Z buffer.

[0152] After completing the Tiling pipeline of one frame, a C-Z buffer is generated, which includes the depth value of the pixels to be drawn in the current frame and the values of the first and second marks of the associated pixel region.

[0153] In the subsequent rendering pipeline, for each tile, directly use the values of the first and second marks in the previously generated C-Z buffer to perform C-Z tests and / or C-Z buffer updates for each draw-call. That is, in the following rendering pipeline as shown Figure 7 after performing step S12 for the current draw-call, after the C-Z test for the pixel region passes, step S13 is skipped and step S14 is executed, that is, there is no need to set the values of the first and second marks according to the draw-call.

[0154] Preferably, in the rendering pipeline, after completing the rendering pipeline of each tile, the first and second marks in the C-Z buffer corresponding to the tile can be cleared. It is also possible to clear the first and second marks in the C-Z buffer of the entire frame after completing the rendering pipelines of all tiles in the current frame.

[0155] Based on the C-Z test methods of the above-mentioned various embodiments of the present application, when setting the values of the first and second marks for the pixel region associated with the current draw-call, in the case where the current draw-call with certain configurations affects the C-Z tests of subsequent draw-calls, the disabling of C-Z tests or C-Z buffer updates is restricted to the pixel region corresponding to the flag, while for the remaining pixel regions where C-Z tests or C-Z buffer updates are not disabled, subsequent draw-calls can continue to perform C-Z tests or C-Z buffer updates. In this way, compared with the prior art where all other subsequent draw-calls of the entire frame cannot perform C-Z tests or C-Z buffer updates after the current draw-call, the adverse impact on the C-Z test effect is minimized as much as possible, the C-Z test effect is improved, and the GPU performance is further enhanced.

[0156] The method in the embodiments of the present application can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in the form of a computer program product in whole or in part. The computer program product includes one or more computer program codes or computer program instructions, which can be stored in a memory. When the computer program instructions are loaded and executed on a computer or a processor, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices.

[0157] The computer program code or computer program instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer program code or computer program instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire (such as coaxial cable, optical fiber, etc.) or wirelessly (such as infrared, radio, microwave, etc.). The computer-readable storage medium can be any available medium that the computer can access, or a data storage device such as a server or data center that includes one or more integrated available media. The available medium can be a magnetic medium, such as a floppy disk, a hard disk, and a magnetic tape; it can be an optical medium, such as a DVD; or it can be a semiconductor medium, such as a solid-state disk (SSD), etc.

[0158] The method of the present invention can include various other operations and / or variations of the shown operations. Similarly, the order of operations in the flowchart can be modified. It should be understood that not all operations in the flowchart can be executed. In various embodiments, one or more operations of the method can be controlled or managed by software, firmware, hardware, or any combination thereof, but not limited thereto. The method can include the processes of the embodiments of the present disclosure, which can be controlled or managed by a processor and / or electronic components under the control of computer or computing device-readable and executable instructions (or codes).

[0159] The following refers to Figure 8 Describe in detail the graphics processing system 120 for implementing the depth test method of any one of the above embodiments of the present application.

[0160] As Figure 8 shown, the graphics processing system 120 includes: a determination unit 121, a test unit 122, and a setting unit 123.

[0161] Specifically, when implementing the coarse-grained depth test method according to an embodiment of the present application, the test unit 122 is configured to: perform the coarse-grained depth test for the current draw-call; the setting unit 123 is configured to: after the coarse-grained depth test for the current draw-call passes, according to the configuration of the current draw-call, set the value of the first flag in the coarse-grained depth buffer for the pixel region associated with the current draw-call, indicating whether the coarse-grained depth test for the associated pixel region is disabled, and according to the configuration of the current draw-call, set the value of the second flag in the coarse-grained depth buffer for the associated pixel region, indicating whether the update of the coarse-grained depth buffer for the associated pixel region is disabled.

[0162] Further, when implementing the coarse-grained depth test method according to this embodiment of the present application, the setting unit 123 is further configured to: after the current frame buffer writing is completed, clear the values of the first flag and the second flag in the coarse-grained depth buffer.

[0163] Further, when implementing the coarse-grained depth test method according to this embodiment of the present application, the determining unit 121 is configured to: before performing the coarse-grained depth test for the current draw-call, determine the value of the first flag for the associated pixel region; the test unit 122 is configured to: if the value of the first flag indicates that the coarse-grained depth test for the associated pixel region is not disabled, then perform the coarse-grained depth test for the current draw-call for the associated pixel region.

[0164] Further, when implementing the coarse-grained depth test method according to this embodiment of the present application, the determining unit 121 is configured to: before performing the coarse-grained depth test for the current draw-call, determine the value of the first flag for the associated pixel region; the test unit 122 is configured to: if the value of the first flag for the associated pixel region indicates that the coarse-grained depth test for the associated pixel region is disabled, then end the coarse-grained depth test for the draw-call for the associated pixel region.

[0165] Further, when implementing the coarse-grained depth test method according to this embodiment of the present application, the determining unit 121 is configured to: after the coarse-grained depth test for the current draw-call passes, determine the value of the second flag for the associated pixel region; the test unit 122 is configured to: if the value of the second flag for the associated pixel region indicates that the update of the depth buffer for the associated pixel region is disabled, then end the coarse-grained depth test for the current draw-call for the associated pixel region and prohibit the execution of the coarse-grained depth buffer update.

[0166] Further, when implementing the coarse-grained depth test method of this embodiment of the present application, the setting unit 123 is configured to: keep the values of the first flag for disabling the coarse-grained depth test and the second flag for disabling the coarse-grained depth buffer update unchanged before the coarse-grained depth test of all draw-calls in the current frame is completed.

[0167] Further, when implementing the coarse-grained depth test method of this embodiment of the present application, the pixel region associated with the current draw-call includes a first group of pixel regions and a second group of pixel regions. The determining unit 121 is configured to: determine the value of the first flag of the first group of pixel regions and the second group of pixel regions before performing the coarse-grained depth test of the current draw-call; the testing unit 122 is configured to: if the first flag of the first group of pixel regions is set to disable the coarse-grained depth test while the first flag of the second group of pixel blocks is set to not disable the coarse-grained depth test, then end the coarse-grained depth test of the current draw-call for the first group of pixel regions and perform the coarse-grained depth test of the current draw-call for the second group of pixel regions.

[0168] Specifically, when implementing the coarse-grained depth test method of another embodiment of the present application, the coarse-grained depth test of the current draw-call is configured to: when the graphics processor executes TBR, in the tiled pipeline of TBR, perform the coarse-grained depth test of the current draw-call; the setting unit 123 is configured to: after the coarse-grained depth test of the current draw-call passes, according to the configuration of the current draw-call, set the value of the first flag in the coarse-grained depth buffer for the pixel region associated with the current draw-call to indicate whether the coarse-grained depth test of the associated pixel region is disabled, and according to the configuration of the current draw-call, set the value of the second flag in the coarse-grained depth buffer for the associated pixel region to indicate whether the coarse-grained depth buffer update of the associated pixel region is disabled.

[0169] Further, when implementing the method of this embodiment of the present application, in the tiled pipeline, the screen area is divided into several tiles, and each tile is divided into several pixel regions. The depth test unit 122 is configured to: store the values of the first flag and the second flag corresponding to each pixel region in the coarse-grained depth buffer corresponding to each tile.

[0170] Furthermore, when implementing the method of this embodiment of the present application, the determining unit 121 is configured to: in a coarse-grained depth test in a TBR rendering pipeline, before executing the coarse-grained depth test of the current draw-call, determine the value of the first flag of the pixel area associated with the current draw-call according to the coarse-grained depth buffer generated in the blocking pipeline; and the testing unit 122 is configured to: if it is indicated that the coarse-grained depth test of the associated pixel area is disabled, end the coarse-grained depth test of the current draw-call for the associated pixel area.

[0171] Furthermore, when implementing the method of this embodiment of the present application, the determining unit 121 is configured to: in a coarse-grained depth test in a TBR rendering pipeline, after the coarse-grained depth test of a current draw-call passes, determine the value of a second flag of the pixel area associated with the current draw-call; and the testing unit 122 is configured to: if it indicates that depth buffer updates for the associated pixel area are disabled, end the coarse-grained depth test of the draw-call for the associated pixel area and prohibit execution of coarse-grained depth buffer updates.

[0172] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A coarse-grained depth testing method, characterized in that, Including: Performing a coarse-grained depth test for the current draw-call command draw-call; After the coarse-grained depth test of the current draw-call passes, according to the configuration of the current draw-call, set the value of a first flag in the coarse-grained depth buffer for the pixel region associated with the current draw-call, indicating whether the coarse-grained depth test of the associated pixel region is disabled, and according to the configuration of the current draw-call, set the value of a second flag in the coarse-grained depth buffer for the associated pixel region, indicating whether the update of the coarse-grained depth buffer of the associated pixel region is disabled.

2. The coarse-grained depth test method according to claim 1, wherein If the configuration of the current draw-call is that stencil is enabled and the stencil mode is not KEEP, the value of the first flag is set to indicate that the coarse-grained depth test of the associated pixel region is disabled, and the value of the second flag is set to indicate that the update of the depth buffer of the associated pixel region is disabled.

3. The coarse-grained depth test method according to claim 1, wherein If the configuration of the current draw-call is a translucent rendering object, the value of the first flag is set to indicate that the coarse-grained depth test of the associated pixel region is not disabled, and the value of the second flag is set to indicate that the update of the coarse-grained depth buffer of the associated pixel region is disabled.

4. The coarse-grained depth testing method according to any one of claims 1-3, characterized in that After the current frame buffer writing is completed, clear the values of the first flag and the second flag in the coarse-grained depth buffer.

5. The coarse-grained depth test method according to claim 1, characterized in that, Before performing the coarse-grained depth test of the current draw-call, determine the value of the first flag of the associated pixel region. If it indicates that the coarse-grained depth test of the associated pixel region is not disabled, perform the coarse-grained depth test of the current draw-call for the associated pixel region.

6. The coarse-grained depth testing method according to claim 1, wherein Before the coarse-grained depth buffer update of the current draw-call, determine the value of the second flag of the associated pixel region. If it indicates that the update of the coarse-grained depth buffer of the associated pixel region is not disabled, perform the coarse-grained depth buffer update of the current draw-call for the associated pixel region.

7. The coarse-grained depth test method according to claim 1, characterized in that, Before performing the coarse-grained depth test of the current draw-call, determine the value of the first flag of the associated pixel region. If it indicates that the coarse-grained depth test of the associated pixel region is disabled, end the coarse-grained depth test of the draw-call for the associated pixel region.

8. The coarse-grained depth test method according to claim 1, wherein, Before the coarse-grained depth buffer update of the current draw-call, determine the value of the second flag of the associated pixel region. If it indicates that the update of the depth buffer of the associated pixel region is disabled, end the coarse-grained depth test of the current draw-call for the associated pixel region and prohibit the execution of the coarse-grained depth buffer update.

9. The coarse-grained depth testing method according to claim 1, wherein Before the coarse-grained depth tests of all draw-calls in the current frame are completed, the values of the first flag set to disable the coarse-grained depth test and the second flag set to disable the coarse-grained depth buffer update remain unchanged.

10. The coarse-grained depth testing method according to claim 1, wherein The pixel regions associated with the draw-call include a first set of pixel regions and a second set of pixel regions. Before performing the coarse-grained depth test of the current draw-call, determine the values of the first flags of the first set of pixel regions and the second set of pixel regions; if the first flag of the first set of pixel regions is set to disable the coarse-grained depth test and the first flag of the second set of pixel regions is set to not disable the coarse-grained depth test, then: end the coarse-grained depth test of the current draw-call for the first set of pixel regions, and perform the coarse-grained depth test of the current draw-call for the second set of pixel regions.

11. A coarse-grained depth testing method, characterized in that, Comprising: When the graphics processor performs tiled rendering TBR, in the tile pipeline of TBR, perform the coarse-grained depth test of the current draw-call command draw-call. After the coarse-grained depth test of the current draw-call passes, according to the configuration of the current draw-call, set the value of the first flag in the coarse-grained depth buffer for the pixel regions associated with the current draw-call, indicating whether the coarse-grained depth test of the associated pixel regions is disabled, and according to the configuration of the current draw-call, set the value of the second flag in the coarse-grained depth buffer for the associated pixel regions, indicating whether the update of the coarse-grained depth buffer of the associated pixel regions is disabled.

12. The coarse-grained depth test method according to claim 11, wherein, In the tile pipeline, divide the screen area into multiple tiles, and each tile is divided into multiple pixel regions. In the coarse-grained depth buffer corresponding to each tile, store the values of the first flag and the second flag corresponding to each pixel region.

13. The coarse-grained depth test method according to claim 11 or 12, characterized in that, In the coarse-grained depth test in the rendering pipeline of TBR, before performing the coarse-grained depth test of the current draw-call, determine the value of the first flag of the pixel regions associated with the current draw-call according to the coarse-grained depth buffer generated in the tile pipeline. If it indicates that the coarse-grained depth test of the associated pixel regions is disabled, then end the coarse-grained depth test of the rendering pipeline of the current draw-call for the associated pixel regions.

14. The coarse-grained depth test method according to claim 11, wherein In the coarse-grained depth test in the rendering pipeline of TBR, after the coarse-grained depth test of the current draw-call passes, determine the value of the second flag of the pixel regions associated with the current draw-call according to the coarse-grained depth buffer generated in the tile pipeline. If it indicates that the update of the coarse-grained depth buffer of the associated pixel regions is disabled, then end the coarse-grained depth test of the draw-call for the associated pixel regions and prohibit the execution of the coarse-grained depth buffer update.

15. A graphics processor, characterized in that, Comprising: A memory for storing instructions, and A processing unit configured to execute the method according to any one of claims 1-14 when executing the instructions.

16. A computer-readable storage medium, characterized in that, Program code is stored in the computer-readable storage medium, and when the program code is executed by a computer or a processor, the method according to any one of claims 1-14 is implemented.

17. A computer program product, characterized in that, The computer program product includes program code which, when executed by a computer or a processor, implements the method according to any one of claims 1-14.

18. A graphics processing system, characterized in that, Comprising: A test unit configured to perform a coarse-grained depth test on the current draw-call command; A setting unit configured to, after the coarse-grained depth test of the current draw-call passes, set the value of a first flag in the coarse-grained depth buffer for the pixel region associated with the current draw-call according to the configuration of the current draw-call, indicating whether the coarse-grained depth test of the associated pixel region is disabled, and set the value of a second flag in the coarse-grained depth buffer for the associated pixel region according to the configuration of the current draw-call, indicating whether the update of the coarse-grained depth buffer of the associated pixel region is disabled.

19. The graphics processing system according to claim 18, wherein, The setting unit is further configured to clear the values of the first flag and the second flag in the coarse-grained depth buffer after the current frame buffer writing is completed.

20. The graphics processing system according to any one of claims 18-19, characterized in that, Further comprising a determination unit configured to determine the value of the first flag of the associated pixel region before performing the coarse-grained depth test of the current draw-call; the test unit is configured to, if it indicates that the coarse-grained depth test of the associated pixel region is not disabled, perform the coarse-grained depth test of the current draw-call on the associated pixel region.

21. The graphics processing system according to claim 18, wherein, Comprising a determination unit; the determination unit is further configured to determine the value of the second flag of the associated pixel region before the coarse-grained depth buffer update of the current draw-call; the test unit is further configured to, if it indicates that the coarse-grained depth buffer update of the associated pixel region is not disabled, perform the coarse-grained depth buffer update of the draw-call on the associated pixel region.

22. The graphics processing system according to claim 18, wherein Comprising a determination unit; the determination unit is further configured to determine the value of the first flag of the associated pixel region before performing the coarse-grained depth test of the current draw-call; the test unit is further configured to, if it indicates that the coarse-grained depth test of the associated pixel region is disabled, end the coarse-grained depth test of the draw-call on the associated pixel region.

23. The graphics processing system according to claim 18, wherein, Comprising a determination unit; the determination unit is further configured to determine the value of the second flag of the associated pixel region before the coarse-grained depth buffer update of the current draw-call; the test unit is further configured to, if it indicates that the depth buffer update of the associated pixel region is disabled, end the coarse-grained depth test of the draw-call on the associated pixel region and prohibit the execution of the coarse-grained depth buffer update.

24. The graphics processing system according to claim 18, wherein, The setting unit is configured to keep the values of the first flag with the coarse-grained depth test disabled and the second flag with the coarse-grained depth buffer update disabled unchanged before the coarse-grained depth tests of all draw-calls in the current frame are completed.

25. The graphics processing system according to claim 18, wherein It includes a determination unit; the pixel region associated with the draw-call includes a first set of pixel regions and a second set of pixel regions, and the determination unit is further configured to: before performing the coarse-grained depth test of the current draw-call, determine the value of the first flag for the first set of pixel regions and the second set of pixel regions; the test unit is further configured to: if the first flag of the first set of pixel regions is set to disable the coarse-grained depth test and the first flag of the second set of pixel blocks is set to not disable the coarse-grained depth test, then end the coarse-grained depth test of the current draw-call for the first set of pixel regions and perform the coarse-grained depth test of the current draw-call for the second set of pixel regions.

26. A graphics processing system, characterized in that, It includes: A test unit, configured to: when the graphics processor performs tiled rendering TBR, perform the coarse-grained depth test of the current draw-call command in the tiled pipeline of TBR; A setting unit, configured to: after the coarse-grained depth test of the current draw-call passes, according to the configuration of the current draw-call, set the value of the first flag in the coarse-grained depth buffer for the pixel region associated with the current draw-call, indicating whether the coarse-grained depth test of the associated pixel region is disabled, and according to the configuration of the current draw-call, set the value of the second flag in the coarse-grained depth buffer for the associated pixel region, indicating whether the update of the coarse-grained depth buffer of the associated pixel region is disabled.

27. The graphics processing system according to claim 26, wherein In the coarse-grained depth test in the rendering pipeline of TBR, before performing the coarse-grained depth test of the current draw-call, determine the value of the first flag of the pixel region associated with the current draw-call according to the coarse-grained depth buffer generated in the tiled pipeline. If it indicates that the coarse-grained depth test of the associated pixel region is disabled, then end the coarse-grained depth test of the rendering pipeline of the current draw-call for the associated pixel region.

28. The graphics processing system according to any one of claims 26-27, characterized in that, The determination unit is configured to: in the coarse-grained depth test in the rendering pipeline of TBR, after the coarse-grained depth test of the current draw-call passes, determine the value of the second flag of the pixel region associated with the current draw-call according to the coarse-grained depth buffer generated in the tiled pipeline; the test unit is further configured to: if it indicates that the update of the coarse-grained depth buffer of the associated pixel region is disabled, then end the coarse-grained depth test of the current draw-call for the associated pixel region and prohibit the execution of the coarse-grained depth buffer update.

29. A graphics processor, characterized in that, It includes: A coarse-grained depth test unit, configured to: perform a coarse-grained depth test for the current draw-call command; after the coarse-grained depth test of the current draw-call passes, according to the configuration of the current draw-call, set the value of a first flag in the coarse-grained depth buffer for the pixel region associated with the current draw-call, indicating whether the coarse-grained depth test of the associated pixel region is disabled, and according to the configuration of the current draw-call, set the value of a second flag in the coarse-grained depth buffer for the associated pixel region, indicating whether the update of the coarse-grained depth buffer for the associated pixel region is disabled; A coarse-grained depth buffer, configured to store the values of the first flag and the second flag for the associated pixel region.

30. The graphics processor according to claim 29, wherein, The coarse-grained depth test unit is configured to: before performing the coarse-grained depth test for the current draw-call, read the value of the first flag for the associated pixel region from the coarse-grained depth buffer, and if it indicates that the coarse-grained depth test of the associated pixel region is not disabled, perform the coarse-grained depth test for the draw-call on the associated pixel region.

31. The graphics processor according to claim 29, wherein, The coarse-grained depth test unit is configured to: after the coarse-grained depth test of the current draw-call passes, read the value of the second flag for the associated pixel region from the coarse-grained depth buffer, and if it indicates that the update of the coarse-grained depth buffer is not disabled, perform the update of the coarse-grained depth buffer for the draw-call on the associated pixel region.

32. The graphics processor according to claim 29, wherein The coarse-grained depth test unit is configured to: before performing the coarse-grained depth test for the current draw-call, read the value of the first flag for the associated pixel region from the coarse-grained depth buffer, and if it indicates that the coarse-grained depth test of the associated pixel region is disabled, end the coarse-grained depth test for the draw-call on the associated pixel region.

33. The graphics processor according to claim 29, wherein, The coarse-grained depth test unit is configured to: after the coarse-grained depth test of the current draw-call passes, read the value of the second flag for the associated pixel region from the coarse-grained depth buffer, and if it indicates that the update of the depth buffer for the associated pixel region is disabled, end the coarse-grained depth test for the draw-call on the associated pixel region and prohibit the execution of the update of the coarse-grained depth buffer.

34. The graphics processor according to claim 29, wherein The pixel regions associated with the draw-call include a first set of pixel regions and a second set of pixel regions. The coarse-grained depth test unit is configured to: before performing the coarse-grained depth test of the current draw-call, read the values of the first flags of the first set of pixel regions and the values of the first flags of the second set of pixel regions from the coarse-grained depth buffer respectively; if the first flag of the first set of pixel regions is set to disable the coarse-grained depth test and the first flag of the second set of pixel regions is set to not disable the coarse-grained depth test, then: end the coarse-grained depth test of the draw-call for the first set of pixel regions, and perform the coarse-grained depth test of the draw-call for the second set of pixel regions.

35. A graphics processor, characterized in that, Comprising: A coarse-grained depth test unit, configured to: when the graphics processor performs tile-based rendering TBR, perform the coarse-grained depth test of the current draw-call command in the tile pipeline of TBR; after the coarse-grained depth test of the current draw-call passes, according to the configuration of the current draw-call, set the value of the first flag in the coarse-grained depth buffer for the pixel regions associated with the current draw-call, indicating whether the coarse-grained depth test of the associated pixel regions is disabled, and according to the configuration of the current draw-call, set the value of the second flag in the coarse-grained depth buffer for the associated pixel regions, indicating whether the update of the coarse-grained depth buffer of the associated pixel regions is disabled; A coarse-grained depth buffer, configured to: store the values of the first flag and the second flag for the associated pixel regions.

36. The graphics processor according to claim 35, wherein In the tile pipeline, the screen area is divided into multiple tiles, each tile is divided into multiple pixel regions, and in the coarse-grained depth buffer corresponding to each tile, the values of the first flag and the second flag corresponding to each pixel region are stored.

37. The graphics processor according to claim 35, wherein The coarse-grained depth test unit is configured to: in the coarse-grained depth test in the rendering pipeline of TBR, before performing the coarse-grained depth test of the current draw-call, read the value of the first flag of the pixel regions associated with the current draw-call from the coarse-grained depth buffer generated in the tile pipeline, and if it indicates that the coarse-grained depth test of the associated pixel regions is disabled, then end the coarse-grained depth test of the rendering pipeline of the current draw-call for the associated pixel regions.

38. The graphics processor according to claim 35, wherein, The coarse-grained depth test unit is configured to: in the coarse-grained depth test in the rendering pipeline of TBR, after the coarse-grained depth test of the current draw-call passes, read the value of the second flag of the pixel regions associated with the current draw-call from the coarse-grained depth buffer generated in the tile pipeline, and if it indicates that the update of the coarse-grained depth buffer of the associated pixel regions is disabled, then end the coarse-grained depth test of the draw-call for the associated pixel regions and prohibit the execution of the coarse-grained depth buffer update.

Images