Ldo circuit and chip

Abstract

The application discloses an LDO circuit and a chip, and the LDO circuit comprises a voltage dividing circuit, an error amplifier, an output control circuit, a first transient compensation circuit and / or a second transient compensation circuit. The voltage dividing circuit is used for voltage dividing an output voltage generated by the LDO circuit to generate a voltage dividing signal; and the output control circuit receives a differential amplification signal and generates an output voltage. According to the LDO circuit and the chip, the voltage change of the output end of the error amplifier is controlled based on the output voltage of the LDO circuit by the first transient compensation circuit, and the voltage change of the output end of the error amplifier is controlled based on the voltage change of the power supply by the second transient compensation circuit, so that the transient response is enhanced, the overshoot of the output voltage of the LDO circuit is effectively suppressed, and the LDO circuit is not only suitable for the transient state when the power supply voltage VIN is stepped, but also suitable for various transient scenarios, such as load stepping, which can cause the output voltage of the LDO circuit to overshoot.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuits, and in particular to an LDO circuit and chip. BACKGROUND

[0002] In an application system of an LDO chip, if the power supply voltage VIN of the LDO circuit instantaneously rises, there will be a large overshoot in the output voltage, especially for the LDO circuit working in the linear (dropout) zone, when the power supply voltage VIN rapidly rises from a lower value to a higher value, the output voltage is generally in a bypass state, and will always follow the power supply voltage VIN until the error amplifier EA loop responds, which will cause the internal devices in the subsequent circuit powered by the LDO circuit to be broken or not to function normally, so the transient state of the LDO circuit needs to be optimized.

[0003] The conventional transient optimization circuit usually optimizes the transient response speed of the error amplifier EA loop in the LDO, and is realized by increasing the bandwidth, but this will adversely affect the stability, especially when the capacitance of the output end changes in a large range; or by increasing the slew rate of the amplifier, due to the size of the power transistor, the parasitic capacitance between the gate and source of the power transistor is large, so a large current needs to be provided to the amplifier to enhance the slew rate, but the method of increasing the current is not suitable for low-power LDO circuits.

[0004] The information disclosed in this BACKGROUND section is only for the purpose of increasing the understanding of the background of the present application and should not be regarded as an acknowledgment or any form of suggestion that this information forms prior art that is publicly known. SUMMARY

[0005] The present application aims to provide an LDO circuit and chip which does not increase the power consumption of the LDO circuit, while effectively enhancing the loop response speed.

[0006] To achieve the above-mentioned purpose, the embodiment of the present application provides an LDO circuit, comprising: a voltage dividing circuit, an error amplifier, an output control circuit, and a first transient compensation circuit and / or a second transient compensation circuit.

[0007] The voltage dividing circuit is connected to the output end of the LDO circuit, and is used to divide the output voltage generated by the LDO circuit to generate a voltage dividing signal;

[0008] The error amplifier has a first input end, a second input end and an output end, the first input end of the error amplifier is connected to a reference voltage, the second input end of the error amplifier is connected to the voltage dividing signal, and the output end of the error amplifier is used to output a differential amplification signal;

[0009] The output control circuit is connected with the output end of the error amplifier to receive the differential amplified signal and is connected with the voltage dividing circuit to form the output end of the LDO circuit to generate an output voltage; and

[0010] The first transient compensation circuit and / or the second transient compensation circuit, the first transient compensation circuit being connected with the output end of the LDO circuit and the output end of the error amplifier, the first transient compensation circuit being used to control the change of the voltage of the output end of the error amplifier based on the change of the output voltage of the LDO circuit; the second transient compensation circuit being connected with the power supply voltage and the output end of the error amplifier, the second transient compensation circuit being used to control the change of the voltage of the output end of the error amplifier based on the change of the power supply voltage.

[0011] In one or more embodiments of the present application, the first transient compensation circuit comprises a first capacitor and a first current mirror circuit, a first end of the first capacitor being connected with the output end of the LDO circuit, a second end of the first capacitor being connected with the first current mirror circuit, the first current mirror circuit being connected with the output end of the error amplifier at the same time.

[0012] In one or more embodiments of the present application, the first current mirror circuit comprises a first current mirror unit and a second current mirror unit, the first current mirror unit being connected with the second end of the first capacitor and the second current mirror unit, the second current mirror unit being connected with the output end of the error amplifier.

[0013] In one or more embodiments of the present application, the first current mirror circuit comprises an isolation tube, a drain of the isolation tube being connected with the second current mirror unit, a source of the isolation tube being connected with the first current mirror unit.

[0014] In one or more embodiments of the present application, the second transient compensation circuit comprises a second capacitor and a second current mirror circuit, a first end of the second capacitor being connected with a ground voltage, a second end of the second capacitor being connected with the second current mirror circuit, the second current mirror circuit being connected with the power supply voltage and the output end of the error amplifier.

[0015] In one or more embodiments of the present application, the second current mirror circuit comprises a third current mirror unit and a fourth current mirror unit, the third current mirror unit being connected with the second end of the second capacitor, the power supply voltage and the fourth current mirror unit, the fourth current mirror unit being connected with the output end of the error amplifier.

[0016] In one or more embodiments of the present application, the output control circuit comprises a power tube and a current mirror unit, a source and a drain of the power tube being connected with the current mirror unit and the ground voltage, a gate of the power tube being connected with the output end of the error amplifier, the current mirror unit being connected with the voltage dividing circuit to form the output end of the LDO circuit.

[0017] In one or more embodiments of the present application, the current mirror unit comprises a third MOS transistor and a fifth MOS transistor, the source of the third MOS transistor and the source of the fifth MOS transistor are connected to the power supply voltage, the gate of the third MOS transistor and the gate of the fifth MOS transistor are connected to the drain of the third MOS transistor, the drain of the third MOS transistor is connected to the source of the power transistor or the drain of the power transistor, and the drain of the fifth MOS transistor is connected to the voltage dividing circuit to generate the output voltage.

[0018] In one or more embodiments of the present application, the LDO circuit further comprises a load capacitor, or the LDO circuit further comprises a load capacitor and an equivalent resistor, the first end of the load capacitor is connected to the output end of the LDO circuit, the second end of the load capacitor is connected to the ground voltage, and the load capacitor and the equivalent resistor are connected in series between the output end of the LDO circuit and the ground voltage.

[0019] The present application also discloses a chip comprising the LDO circuit.

[0020] Compared with the prior art, the LDO circuit and the chip according to the embodiments of the present application can control the change of the voltage at the output end of the error amplifier based on the change of the output voltage of the LDO circuit through the first transient compensation circuit, and control the change of the voltage at the output end of the error amplifier based on the change of the power supply voltage through the second transient compensation circuit, thereby enhancing the transient response, effectively suppressing the overshoot of the output voltage of the LDO circuit, and being applicable not only to the transient state when the power supply voltage VIN steps, but also to various transient scenarios such as load steps that can cause the output voltage of the LDO circuit to overshoot; the alternating current generated by the embodiments of the present application is fast and does not increase the static power consumption of the LDO circuit. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 is a circuit schematic diagram of the LDO circuit according to Embodiment One of the present application.

[0022] Figure 2 is a circuit schematic diagram of the LDO circuit according to Embodiment Two of the present application.

[0023] Figure 3 is a circuit schematic diagram of the LDO circuit according to Embodiment Three of the present application.

[0024] Figure 4 is a circuit schematic diagram of the LDO circuit according to Embodiment Four of the present application.

[0025] Figure 5 is a circuit schematic diagram of the LDO circuit according to Embodiment Five of the present application.

[0026] Figure 6 is a circuit schematic diagram of the LDO circuit according to Embodiment Six of the present application. DETAILED DESCRIPTION

[0027] The specific embodiments of the present application will be described in detail below with reference to the drawings, but the scope of protection of the present application is not limited by the specific embodiments.

[0028] Unless otherwise clearly indicated, throughout the specification and claims, the term "comprising" or variations such as "comprise" or "comprises" will be understood to encompass the inclusion of stated elements or components, but not the exclusion of any other elements or components.

[0029] In the specification, "coupling" or "connection" or "linked" includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrically conductive medium, which can have a parasitic inductance or a parasitic capacitance; indirect connection can also include a connection through other active devices or passive devices on the basis of achieving the same or similar functional purposes, such as a connection through circuits or components such as switches, follower circuits, etc. In addition, in the present application, words such as "first", "second", etc. are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply a certain actual relationship, quantity or order between the technical features.

[0030] Embodiment 1

[0031] As shown in Figure 1 , an LDO circuit includes a voltage dividing circuit 10, an error amplifier EA, an output control circuit 20, a load capacitor CL, an equivalent resistor R ESR , and a first transient compensation circuit 30.

[0032] Specifically, the voltage dividing circuit 10 is connected to the output end VOUT of the LDO circuit, and the voltage dividing circuit 10 is used to divide the output voltage generated by the LDO circuit to generate a voltage dividing signal Vfb.

[0033] The error amplifier EA has a first input end, a second input end and an output end VEA, the first input end of the error amplifier EA is connected with the reference voltage Vref, the second input end of the error amplifier EA is connected with the voltage dividing signal Vfb, and the output end VEA of the error amplifier EA is used to output a differential amplification signal based on the reference voltage Vref and the voltage dividing signal Vfb.

[0034] The output control circuit 20 is connected to the output end VEA of the error amplifier EA to receive the differential amplification signal and is connected to the voltage dividing circuit 10 to form the output end VOUT of the LDO circuit to generate the output voltage.

[0035] The first transient compensation circuit 30 is connected to the output terminal VOUT of the LDO circuit and the output terminal VEA of the error amplifier EA. The first transient compensation circuit 30 is used to control the change of the output voltage of the error amplifier EA based on the change of the output voltage of the LDO circuit.

[0036] like Figure 1 As shown, in one embodiment, the voltage divider circuit 10 includes a first resistor R1 and a second resistor R2. The first end of the first resistor R1 is connected to the output terminal VOUT of the LDO circuit, the second end of the first resistor R1 is connected to the first end of the second resistor R2 to generate a voltage divider signal Vfb, and the second end of the second resistor R2 is connected to ground voltage.

[0037] like Figure 1 As shown, in one embodiment, the output control circuit 20 includes a power transistor MP4 and a current mirror unit. The source of the power transistor MP4 is connected to the current mirror unit, the drain of the power transistor MP4 is connected to ground voltage, and the gate of the power transistor MP4 is connected to the output terminal VEA of the error amplifier EA. The current mirror unit is connected to the voltage divider circuit 10 to form the output terminal VOUT of the LDO circuit.

[0038] Figure 1 The illustrated current mirror unit includes a third MOSFET MP3 and a fifth MOSFET MP5. The sources of the third MOSFET MP3 and the fifth MOSFET MP5 are connected to the power supply voltage VIN. The gates of the third MOSFET MP3 and the fifth MOSFET MP5 are connected to the drain of the third MOSFET MP3. The drain of the third MOSFET MP3 is connected to the source of the power transistor MP4. The drain of the fifth MOSFET MP5 is connected to the first terminal of the first resistor R1 to generate an output voltage. In this embodiment, the power transistor MP4 is a P-channel MOSFET. In other embodiments, the power transistor MP4 can be an N-channel MOSFET, and other circuits are modified accordingly.

[0039] In one embodiment, the load capacitance CL and the equivalent resistance R ESR It is connected in series between the output terminal VOUT of the LDO circuit and the ground voltage. In other embodiments, the equivalent resistance R may not be provided. ESR .

[0040] The first transient compensation circuit 30 includes a first capacitor C1 and a first current mirror circuit. The first terminal of the first capacitor C1 is connected to the output terminal VOUT of the LDO circuit, and the second terminal of the first capacitor C1 is connected to the first current mirror circuit. The first current mirror circuit is also connected to the output terminal VEA of the error amplifier EA.

[0041] In an embodiment, the first current mirror circuit comprises a first current mirror unit, an isolation transistor MN3 and a second current mirror unit, the first current mirror unit is connected with the second end of the first capacitor C1 and the source of the isolation transistor MN3, the second current mirror unit is connected with the drain of the isolation transistor MN3 and the output terminal VEA of the error amplifier EA, and the gate of the isolation transistor MN3 is connected with the control voltage VDD. In other embodiments, the N-channel isolation transistor MN3 can be replaced by a P-channel MOS transistor, and other circuits are modified accordingly. In other embodiments, if the power supply voltage VIN is low, the isolation transistor MN3 can be omitted.

[0042] Specifically, the first current mirror unit comprises a first NMOS transistor MN1 and a second NMOS transistor MN2. The drain of the first NMOS transistor MN1 is connected with the second end of the first capacitor C1, the gate of the first NMOS transistor MN1 and the gate of the second NMOS transistor MN2, the source of the first NMOS transistor MN1 and the source of the second NMOS transistor MN2 are connected with the ground voltage, and the drain of the second NMOS transistor MN2 is connected with the source of the isolation transistor MN3. In other embodiments, the first NMOS transistor MN1 and the second NMOS transistor MN2 can be replaced by P-channel MOS transistors, and other circuits are modified accordingly.

[0043] The second current mirror unit comprises a first PMOS transistor MP1 and a second PMOS transistor MP2. The source of the first PMOS transistor MP1 and the source of the second PMOS transistor MP2 are connected with the power supply voltage VIN, the gate of the first PMOS transistor MP1 and the gate of the second PMOS transistor MP2 are connected with the drain of the first PMOS transistor MP1 and the drain of the isolation transistor MN3, and the drain of the second PMOS transistor MP2 is connected with the output terminal VEA of the error amplifier EA. In other embodiments, the first PMOS transistor MP1 and the second PMOS transistor MP2 can be replaced by N-channel MOS transistors, and other circuits are modified accordingly.

[0044] The specific principle is as follows:

[0045] As shown in Figure 1 When the power supply voltage VIN is stepped up from one value to another value at a very fast rate, since the LDO circuit works in the linear (dropout) region before the step, the output voltage of the LDO circuit always follows the power supply voltage VIN, and the gate voltage of the fifth MOS transistor MP5 is maintained at a low level. The rising of the gate voltage of the fifth MOS transistor MP5 needs the response of the loop formed by the error amplifier EA, and the response speed of the loop is usually lower than the step speed of the power supply voltage VIN. Therefore, the fifth MOS transistor MP5 remains in the open state for a period of time, resulting in that the output voltage of the LDO circuit always follows the power supply voltage VIN until the loop response comes.

[0046] In this embodiment, when the output voltage of the LDO circuit rapidly rises by a voltage ΔV following the power supply voltage VIN, the voltage at the second end of the first capacitor C1 also rises with the output voltage of the LDO circuit, and the parasitic capacitance C between the first capacitor C1 and the gate-source of the first NMOS transistor MN1 gsn1 generates a voltage drop, so that the gate-source voltage of the first NMOS transistor MN1 changes by a voltage ΔV gsn1 , which is part of the output voltage VOUT change ΔV OUT .

[0047]

[0048] When ΔV gsn1 is greater than the threshold voltage of the first NMOS transistor MN1, the first NMOS transistor MN1 is turned on, generating an alternating current (AC) on the first NMOS transistor MN1 and passing through the first current mirror unit and the second current mirror unit to the output terminal VEA of the error amplifier EA, thereby pulling up the gate voltage of the power transistor MP4 to the power supply voltage VIN, thereby raising the gate voltage of the fifth MOS transistor MP5 to weaken the on-state capability of the fifth MOS transistor MP5, achieving the effect of suppressing the overshoot of the output voltage of the LDO circuit.

[0049] Embodiment 2

[0050] As Figure 2 shown, in this embodiment, the power transistor MN4 connected to the output terminal VEA of the error amplifier EA is an N-channel MOS transistor, and then, on the basis of Embodiment 1, the isolation transistor MN3 and the second current mirror unit are no longer provided, and the drain of the second NMOS transistor MN2 is directly connected to the output terminal VEA of the error amplifier EA. The other structures of the LDO circuit are the same as those in Embodiment 1 and will not be described here.

[0051] And similarly, in Figure 2 , when the power supply voltage VIN steps up, the alternating current (AC) generated by the first transient compensation circuit 30 will pull down the voltage at the output terminal VEA of the error amplifier EA, raising the gate voltage of the fifth MOS transistor MP5, thereby weakening the on-state capability of the fifth MOS transistor MP5, achieving the effect of suppressing the overshoot of the output voltage of the LDO circuit.

[0052] Embodiment 3

[0053] As Figure 3 shown, an LDO circuit includes a voltage dividing circuit 10, an error amplifier EA, an output control circuit 20, a load capacitor CL, an equivalent resistor R ESR , and a second transient compensation circuit 40.

[0054] Specifically, the voltage divider circuit 10 is connected to the output terminal VOUT of the LDO circuit. The voltage divider circuit 10 is used to divide the output voltage generated by the LDO circuit to generate a voltage divider signal Vfb.

[0055] Error amplifier EA has a first input terminal, a second input terminal, and an output terminal VEA. The first input terminal of error amplifier EA is connected to the reference voltage Vref, the second input terminal of error amplifier EA is connected to the voltage divider signal Vfb, and the output terminal VEA of error amplifier EA is used to output a differential amplified signal based on the reference voltage Vref and the voltage divider signal Vfb.

[0056] The output control circuit 20 is connected to the output terminal VEA of the error amplifier EA to receive the differential amplified signal and is connected to the voltage divider circuit 10 to form the output terminal VOUT of the LDO circuit to generate the output voltage.

[0057] The second transient compensation circuit 40 is connected to the power supply voltage VIN and the output terminal VEA of the error amplifier EA. The second transient compensation circuit 40 is used to control the voltage change of the output terminal VOUT of the error amplifier EA based on the change of the power supply voltage VIN.

[0058] like Figure 3 As shown, in one embodiment, the voltage divider circuit 10 includes a first resistor R1 and a second resistor R2. The first end of the first resistor R1 is connected to the output terminal VOUT of the LDO circuit, the second end of the first resistor R1 is connected to the first end of the second resistor R2 to generate a voltage divider signal Vfb, and the second end of the second resistor R2 is connected to ground voltage.

[0059] like Figure 3 As shown, in one embodiment, the output control circuit 20 includes a power transistor MP4 and a current mirror unit. The source of the power transistor MP4 is connected to the current mirror unit, the drain of the power transistor MP4 is connected to ground voltage, and the gate of the power transistor MP4 is connected to the output terminal VEA of the error amplifier EA. The current mirror unit is connected to the voltage divider circuit 10 to form the output terminal VOUT of the LDO circuit.

[0060] Figure 3 The illustrated current mirror unit includes a third MOSFET MP3 and a fifth MOSFET MP5. The sources of the third MOSFET MP3 and the fifth MOSFET MP5 are connected to the power supply voltage VIN. The gates of the third MOSFET MP3 and the fifth MOSFET MP5 are connected to the drain of the third MOSFET MP3. The drain of the third MOSFET MP3 is connected to the source of the power transistor MP4. The drain of the fifth MOSFET MP5 is connected to the first terminal of the first resistor R1 to generate an output voltage. In this embodiment, the power transistor MP4 is a P-channel MOSFET. In other embodiments, the power transistor MP4 can be an N-channel MOSFET, and other circuits are modified accordingly.

[0061] In one embodiment, the load capacitance CL and the equivalent resistance R ESR It is connected in series between the output terminal VOUT of the LDO circuit and the ground voltage. In other embodiments, the equivalent resistance R may not be provided. ESR .

[0062] like Figure 3 As shown, the second transient compensation circuit 40 includes a second capacitor C2 and a second current mirror circuit. The first terminal of the second capacitor C2 is connected to the ground voltage, and the second terminal of the second capacitor C2 is connected to the second current mirror circuit. The second current mirror circuit is connected to the power supply voltage VIN and the output terminal VEA of the error amplifier EA.

[0063] Specifically, the second current mirror circuit includes a sixth PMOS transistor MP6 and a seventh PMOS transistor MP7. The sources of the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 are connected to the power supply voltage VIN. The gate of the sixth PMOS transistor MP6 is connected to its drain, the gate of the seventh PMOS transistor MP7, and the second terminal of the second capacitor C2. The drain of the seventh PMOS transistor MP7 is connected to the gate of the power transistor MP4 and the output terminal VEA of the error amplifier EA. In other embodiments, the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 can be replaced with N-channel MOS transistors, and other circuits are modified accordingly.

[0064] The specific principle is as follows:

[0065] like Figure 3 As shown, when the power supply voltage VIN rises rapidly from one value to another, because the loop response speed of the differential amplifier EA is much slower than the step speed of the power supply voltage VIN, the voltage difference between the gate and source of the fifth MOS transistor MP5 will be increased and maintained for a period of time. This causes the current supplied by the fifth MOS transistor MP5 to be much greater than the load current, and the output voltage of the LDO circuit to be boosted until the differential amplifier EA loop responds and pulls up the gate voltage of the fifth MOS transistor MP5. The structure proposed in this embodiment sets a second capacitor C2 between the gate and ground of the sixth PMOS transistor MP6. When the power supply voltage VIN rises rapidly, the parasitic capacitance C between the gate and source of the sixth PMOS transistor MP6... gsp2 The second capacitor C2 creates a voltage divider, causing the gate-source voltage change ΔV of the sixth PMOS transistor MP6. gsp2 The change in power supply voltage VIN is ΔV IN Part of: that is

[0066]

[0067] When ΔV gsp2When the voltage exceeds the threshold voltage of the sixth PMOS transistor MP6, the sixth PMOS transistor MP6 turns on and generates an alternating current (AC), which is transmitted to the output of the differential amplifier EA through the second current mirror circuit to pull up the gate voltage of the power transistor MP4 to the power supply voltage VIN, thereby increasing the gate voltage of the fifth MOS transistor MP5 and weakening the conduction capability of the fifth MOS transistor MP5, thus achieving the effect of suppressing the overshoot of the LDO circuit output voltage.

[0068] Example 4

[0069] like Figure 4 As shown, in this embodiment, the power transistor MN4 connected to the output terminal VEA of the error amplifier EA is an N-channel MOS transistor. In this case, based on embodiment 3, the second current mirror circuit includes a third current mirror unit and a fourth current mirror unit. The third current mirror unit is connected to the second terminal of the second capacitor C2, the power supply voltage VIN, and the fourth current mirror unit. The first terminal of the second capacitor C2 is connected to the ground voltage, and the fourth current mirror unit is connected to the output terminal of the error amplifier EA.

[0070] Specifically, the third current mirror unit includes a sixth PMOS transistor MP6 and a seventh PMOS transistor MP7. The drain of the sixth PMOS transistor MP6 is connected to the second terminal of the second capacitor C2, the gate of the sixth PMOS transistor MP6, and the gate of the seventh PMOS transistor MP7. The sources of the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 are connected to the power supply voltage. The drain of the seventh PMOS transistor MP7 is connected to the fourth current mirror unit. In other embodiments, the first NMOS transistor MN1 and the second NMOS transistor MN2 can be replaced with P-channel MOS transistors, and other circuits are modified accordingly.

[0071] The fourth current mirror unit includes a fifth NMOS transistor MN5 and a sixth NMOS transistor MN6. The sources of the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are connected to ground. The gates of the fifth NMOS transistor MN5 and MN6 are connected to the gates and drains of the sixth NMOS transistor MN6. The drain of the sixth NMOS transistor MN6 is connected to the output terminal VEA of the error amplifier EA and the gate of the power transistor MN4. In other embodiments, the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 can be replaced with N-channel MOS transistors, and the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 can be replaced with P-channel MOS transistors, with other circuits modified accordingly. The other structures of the LDO circuit are the same as those in Embodiment 3, and will not be described again here.

[0072] And similarly, in Figure 4When the power supply voltage VIN rises stepwise, the parasitic capacitance between the second capacitor C2 and the gate-source of the sixth PMOS transistor MP6 divides the voltage, causing the sixth PMOS transistor MP6 to conduct and generate an alternating current (AC). This AC current is then transmitted to the output of the differential amplifier EA through the third and fourth current mirror units to pull down the gate voltage of the power transistor MP4 and increase the gate voltage of the fifth MOS transistor MP5. This weakens the conduction capability of the fifth MOS transistor MP5 and achieves the effect of suppressing the overshoot of the LDO circuit output voltage.

[0073] Example 5

[0074] like Figure 5 As shown, in this embodiment, the power transistor MP4 connected to the output terminal VEA of the error amplifier EA is a P-channel MOSFET. The output terminal VOUT of the LDO circuit in this embodiment is equipped with the first transient compensation circuit 30 as described in Embodiment 1. The first transient compensation circuit 30 is connected to the output terminal VOUT of the LDO circuit and the output terminal VEA of the error amplifier EA. The first transient compensation circuit 30 is used to control the voltage change of the output terminal VOUT of the error amplifier EA based on the change in the output voltage of the LDO circuit. The output terminal VEA of the error amplifier EA and the power supply voltage VIN are equipped with the second transient compensation circuit 40 as described in Embodiment 3. The second transient compensation circuit 40 is connected to the power supply voltage VIN and the output terminal VEA of the error amplifier EA. The second transient compensation circuit 40 is used to control the voltage change of the output terminal VOUT of the error amplifier EA based on the change in the power supply voltage VIN.

[0075] like Figure 5 As shown, the first transient compensation circuit 30 in this embodiment has the same structure as the first transient compensation circuit in Embodiment 1, and the second transient compensation circuit 40 in this embodiment has the same structure as the second transient compensation circuit in Embodiment 3. Other structures of the LDO circuit are also the same as the corresponding structures in Embodiments 1 and 3.

[0076] In this embodiment, when the power supply voltage VIN jumps rapidly from one value to another, the LDO circuit operates in the dropout region before the jump, and the output voltage of the LDO circuit always follows the power supply voltage VIN. The gate voltage of the fifth MOSFET MP5 remains at a low level. The rise of the gate voltage of the fifth MOSFET MP5 requires the loop response formed by the error amplifier EA. The loop response speed is often lower than the step speed of the power supply voltage VIN. Therefore, the fifth MOSFET MP5 remains in the on state for a period of time, causing the output voltage of the LDO circuit to follow the power supply voltage VIN until the loop response comes through.

[0077] In the embodiment, when the output voltage of the LDO circuit follows the power supply voltage VIN and rises rapidly by a voltage ΔV, the voltage at the second end of the first capacitor C1 also rises with the output voltage of the LDO circuit, the parasitic capacitance C between the first capacitor C1 and the gate-source of the first NMOS transistor MN1 gsn1 generates a voltage drop, so that the gate-source voltage of the first NMOS transistor MN1 changes by a voltage ΔV gsn1 , which is a part of the output voltage VOUT change ΔV OUT : that is,

[0078]

[0079] When ΔV gsn1 is greater than the threshold voltage of the first NMOS transistor MN1, the first NMOS transistor MN1 is turned on, generating an alternating current (AC) on the first NMOS transistor MN1 and passing through the first current mirror unit and the second current mirror unit to the output terminal VEA of the error amplifier EA, thereby pulling up the gate voltage of the power transistor MP4 to the power supply voltage VIN, thereby raising the gate voltage of the fifth MOS transistor MP5 to weaken the conduction ability of the fifth MOS transistor MP5, achieving the effect of suppressing the overshoot of the output voltage of the LDO circuit.

[0080] When the power supply voltage VIN jumps from a certain value to another value at a very fast rate, because the loop response speed of the differential amplifier EA is much lower than the step speed of the power supply voltage VIN, the voltage difference between the gate and the source of the fifth MOS transistor MP5 will be enlarged and maintained for a period of time, causing the current provided by the fifth MOS transistor MP5 to be much larger than the load current, and the output voltage of the LDO circuit is boosted until the differential amplifier EA loop responds to pull up the gate voltage of the fifth MOS transistor MP5. The structure proposed in the embodiment is to set a second capacitor C2 between the gate of the sixth PMOS transistor MP6 and the ground, when the power supply voltage VIN rises rapidly, the parasitic capacitance C gsp2 between the gate and the source of the sixth PMOS transistor MP6 and the second capacitor C2 generate a voltage drop, so that the gate-source voltage of the sixth PMOS transistor MP6 changes by a voltage ΔV gsp2 , which is a part of the power supply voltage VIN change ΔV IN : that is,

[0081]

[0082] When ΔV gsp2When the threshold voltage of the sixth PMOS transistor MP6 is greater than the threshold voltage of the sixth PMOS transistor MP6, the sixth PMOS transistor MP6 is turned on and generates an alternating current (AC) and is transmitted to the output end of the differential amplifier EA through the second current mirror circuit to pull up the gate voltage of the power transistor MP4 to the power supply voltage VIN, increase the gate voltage of the fifth MOS transistor MP5, thereby weakening the turn-on ability of the fifth MOS transistor MP5, and achieving the effect of suppressing the overshoot of the output voltage of the LDO circuit.

[0083] The calculation formula of the first capacitor C1 in an embodiment is:

[0084]

[0085]

[0086]

[0087] wherein, I AC1 and I dsp1 are the alternating currents flowing through the first NMOS transistor MN1; μ N represents the mobility of electrons; dVOUT / dt represents the change speed of the voltage of the output end VOUT of the LDO circuit; C ox represents the ratio between the dielectric constant of silicon dioxide and the accumulation thickness of the gate oxide layer; represents the width-length ratio of the first NMOS transistor MN1; ΔV gsn1 represents the change size of the gate-source voltage of the first NMOS transistor MN1 with the change of the voltage of the output end VOUT of the LDO circuit; V TH1 represents the threshold voltage of the first NMOS transistor MN1; ΔV OUT represents the change value of the output end VOUT of the LDO circuit; C gsn1 represents the parasitic capacitance between the gate and the source of the first NMOS transistor MN1.

[0088] Similarly, the calculation formula of the second capacitor C2 is:

[0089]

[0090]

[0091]

[0092] wherein, wherein, I AC2 and I dsp2 are the alternating currents flowing through the sixth PMOS transistor MP6; μ P represents the mobility of holes; dVIN / dt represents the change speed of the power supply voltage VIN; C ox represents the ratio between the dielectric constant of silicon dioxide and the accumulation thickness of the gate oxide layer; Indicates the width-to-length ratio of the sixth PMOS transistor MP6; ΔV gsp2 This indicates the magnitude of the change in gate-source voltage of the sixth PMOS transistor MP6 as a function of the supply voltage VIN; V TH2 This represents the threshold voltage of the sixth PMOS transistor, MP6; ΔV IN This indicates the change in power supply voltage VIN; C gsp2 This represents the parasitic capacitance between the gate and source of the sixth PMOS transistor, MP6.

[0093] The calculation of the first capacitor C1 described above can also be applied to Embodiments 1, 2 and 6; the calculation of the second capacitor C2 described above can also be applied to Embodiments 3, 4 and 6.

[0094] Example 6

[0095] like Figure 6 As shown, in this embodiment, the power transistor MN4 connected to the output terminal VEA of the error amplifier EA is an N-channel MOSFET. The output terminal VOUT of the LDO circuit in this embodiment is equipped with the first transient compensation circuit 30 as described in Embodiment 2. The first transient compensation circuit 30 is connected to the output terminal VOUT of the LDO circuit and the output terminal VEA of the error amplifier EA. The first transient compensation circuit 30 is used to control the voltage change of the output terminal VOUT of the error amplifier EA based on the change in the output voltage of the LDO circuit. The output terminal VEA of the error amplifier EA and the power supply voltage VIN are equipped with the second transient compensation circuit 40 as described in Embodiment 4. The second transient compensation circuit 40 is connected to the power supply voltage VIN and the output terminal VEA of the error amplifier EA. The second transient compensation circuit 40 is used to control the voltage change of the output terminal VOUT of the error amplifier EA based on the change in the power supply voltage VIN.

[0096] like Figure 6 As shown, the first transient compensation circuit 30 in this embodiment has the same structure as the first transient compensation circuit in embodiment 2, and the second transient compensation circuit 40 in this embodiment has the same structure as the second transient compensation circuit in embodiment 4. Other structures of the LDO circuit are also the same as the corresponding structures in embodiments 2 and 4.

[0097] like Figure 6As shown, if the power voltage VIN steps up, the parasitic capacitance Cgs between the first capacitor C1 and the gate-source of the first NMOS MN1 generates a voltage division, thereby generating an alternating current (AC) on the first NMOS MN1 and transmitting to the output terminal VEA of the error amplifier EA through the first current mirror unit and the second current mirror unit to pull down the gate voltage of the power transistor MP4 and raise the gate voltage of the fifth MOS MP5, thereby weakening the conduction ability of the MP5, achieving the effect of suppressing the overshoot of the output voltage of the LDO circuit.

[0098] If the power voltage VIN steps up, the parasitic capacitance between the second capacitor C2 and the gate-source of the sixth PMOS MP6 generates a voltage division, the sixth PMOS MP6 is turned on and generates an alternating current (AC) and transmits to the output terminal of the differential amplifier EA through the third current mirror unit and the fourth current mirror unit to pull down the gate voltage of the power transistor MP4 and increase the gate voltage of the fifth MOS MP5, thereby weakening the conduction ability of the fifth MOS MP5, achieving the effect of suppressing the overshoot of the output voltage of the LDO circuit.

[0099] The application further discloses a chip comprising the LDO circuit.

[0100] The foregoing description of specific exemplary embodiments of the application is intended to be illustrative only and is not intended to limit the application to the precise forms described. Many modifications and variations are possible in light of the above teachings without departing from the spirit and scope of the application. It is, therefore, to be understood that it is intended to cover all modifications and variations of this application that come within the scope of the following claims and their equivalents. It is intended that each element of claim set forth herein is independent and that no claim element is dependent is another claim element unless the clause "means for" is specifically recited in the claim.

Claims

1. An LDO circuit, characterized in that, include: A voltage divider circuit is connected to the output terminal of an LDO circuit to divide the output voltage generated by the LDO circuit and generate a voltage divider signal. An error amplifier has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the error amplifier is connected to a reference voltage, the second input terminal of the error amplifier is connected to a voltage divider signal, and the output terminal of the error amplifier is used to output a differential amplified signal. The output control circuit is connected to the output terminal of the error amplifier to receive the differential amplified signal and is connected to the voltage divider circuit to form the output terminal of the LDO circuit to generate the output voltage. as well as A first transient compensation circuit and / or a second transient compensation circuit, wherein the first transient compensation circuit is connected to the output terminal of the LDO circuit and the output terminal of the error amplifier, and the first transient compensation circuit is used to control the voltage change at the output terminal of the error amplifier based on the change in the output voltage of the LDO circuit; the second transient compensation circuit is connected to the power supply voltage and the output terminal of the error amplifier, and the second transient compensation circuit is used to control the voltage change at the output terminal of the error amplifier based on the change in the power supply voltage.

2. The LDO circuit as described in claim 1, characterized in that, The first transient compensation circuit includes a first capacitor and a first current mirror circuit. The first terminal of the first capacitor is connected to the output terminal of the LDO circuit, and the second terminal of the first capacitor is connected to the first current mirror circuit. The first current mirror circuit is also connected to the output terminal of the error amplifier.

3. The LDO circuit as described in claim 2, characterized in that, The first current mirror circuit includes a first current mirror unit and a second current mirror unit. The first current mirror unit is connected to the second terminal of the first capacitor and the second current mirror unit. The second current mirror unit is connected to the output terminal of the error amplifier.

4. The LDO circuit as described in claim 3, characterized in that, The first current mirror circuit includes an isolation tube, the drain of which is connected to a second current mirror unit, and the source of which is connected to the first current mirror unit.

5. The LDO circuit as described in claim 1, characterized in that, The second transient compensation circuit includes a second capacitor and a second current mirror circuit. The first terminal of the second capacitor is connected to ground voltage, and the second terminal of the second capacitor is connected to the second current mirror circuit. The second current mirror circuit is connected to the power supply voltage and the output terminal of the error amplifier.

6. The LDO circuit as described in claim 5, characterized in that, The second current mirror circuit includes a third current mirror unit and a fourth current mirror unit. The third current mirror unit is connected to the second terminal of the second capacitor, the power supply voltage, and the fourth current mirror unit. The fourth current mirror unit is connected to the output terminal of the error amplifier.

7. The LDO circuit as described in claim 1, characterized in that, The output control circuit includes a power transistor and a current mirror unit. The source and drain of the power transistor are connected to the current mirror unit and ground voltage. The gate of the power transistor is connected to the output terminal of the error amplifier. The current mirror unit is connected to a voltage divider circuit to form the output terminal of the LDO circuit.

8. The LDO circuit as described in claim 7, characterized in that, The current mirror unit includes a third MOSFET and a fifth MOSFET. The source of the third MOSFET and the source of the fifth MOSFET are connected to the power supply voltage. The gate of the third MOSFET and the gate of the fifth MOSFET are connected to the drain of the third MOSFET. The drain of the third MOSFET is connected to the source of the power transistor or the drain of the power transistor. The drain of the fifth MOSFET is connected to a voltage divider circuit to generate an output voltage.

9. The LDO circuit as described in claim 1, characterized in that, The LDO circuit further includes a load capacitor, or the LDO circuit further includes a load capacitor and an equivalent resistor. The first end of the load capacitor is connected to the output terminal of the LDO circuit, the second end of the load capacitor is connected to ground voltage, and the load capacitor and the equivalent resistor are connected in series between the output terminal of the LDO circuit and ground voltage.

10. A chip, characterized in that, Includes the LDO circuit as described in any one of claims 1 to 9.

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