An ASIC layout optimization method based on hybrid integer programming

Abstract

This invention provides an ASIC layout optimization method based on hybrid integer programming, comprising: Step 1, mathematically modeling the layout problem in the ASIC layout; Step 2, establishing MIP equations for the line length of each network using a lightweight RST model; Step 3, linearizing the nonlinear equations using integer variables; Step 4, introducing a single-flow algorithm to ensure the correctness of the RST line length model. The proposed solution transforms the layout conditions into constraints of a linear programming problem by modeling the positions of standard ASIC cells and accurately modeling the RST of their networks. It transforms reducing the line length of the layout into the objective function of the linear programming problem. During the solution of the linear programming equations, the line length of the layout is continuously reduced, thus continuously optimizing the initial layout. This solution simultaneously addresses the two major challenges of layout and routing in integrated circuit design.

Description

Technical Field

[0001] This invention relates to an ASIC layout optimization method based on hybrid shaping programming. Background Technology

[0002] Placement quality can be measured by many things, the most important being the net length. In placement, the net length is the RST net length of the right-angled Steiner tree connecting all pins, such as... Figure 1a As shown, p0, p1... are all pins in a network. When the estimation method for the length of the wires connecting these pins is RST, the bus length is 13.

[0003] Finding the shortest possible line length requires solving the rectilinear Steiner minimal tree (RSMT) problem. Both the layout problem and the RSMT problem are NP problems (NP stands for Non-deterministic Polynomial). Although FLUTE (reference: C. Chu and Y.-C. Wong, “FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 1, pp. 70–83, 2008.) proposes a fast and efficient algorithm for the RSMT problem, this algorithm can only be used when the positions of all pins are fixed. In 2000, Kumar proposed a placement algorithm (reference: R. Kumar, W. Kit, L. Robert, and J. Heath, “An Integer Programming Approach to Placement and Routing in Circuit Layout,” pp. 1–22, 2000.) that maps the RSMT model to a mesh-based mixed integer programming (MIP) formula. To achieve this placement, the mesh granularity needs to be smaller than the cell size in the placement, which means many variables are required in the MIP equation. In the final testing of this work, only a placement with fewer than 40 cells was used. Reference “E. Althaus, T. Polzin, and SV Daneshmand, “Improving linear programming approaches for the Steiner tree problem,” International Conference on Experimental and Efficient Algorithms, p. 1–14, 2003” proposes a MIP equation for the RSMT problem. However, like FLUTE, this equation only applies to the case of fixed pins.The reference “S. Li and C.-K. Koh, “Mixed integer programming models for detailed placement,” ACM International Symposium on International Symposium on Physical Design, p. 87–94, 2012” proposes a detailed placement algorithm based on MIP. However, they use the half perimeter wirelength (HPWL), which degrades routing quality, as the wire length estimation method, as shown in Figure 1b, instead of the more accurate RST wire length. Furthermore, this work only targets detailed placement, where the movement range of cells within the placement is very small, making it difficult for this algorithm to find better placement results. In 2021, Fontana and Aghaeeekiasaraee proposed ILP-GRC (reference: TA Fontana, E. Aghaeekiasaraee, R. Netto, SF Almeida, U. Gandh, AF Tabrizi, D. Westwick, L. Behjat, and JL G ̈untzel, “ILP-Based Global Routing Optimization with Cell Movements,” IEEE Computer Society Annual Symposium on VLSI, pp. 25–30, 2021), a MIP-based layout algorithm that can achieve better layout results given a known layout. In this algorithm, the RST is derived from the existing layout. While this avoids the conventional RSMT problem, the likelihood of obtaining a good layout result is very limited. Summary of the Invention

[0004] Objective of the Invention: The technical problem to be solved by this invention is to address the shortcomings of existing technologies by providing a method for optimizing ASIC (Application Specific Integrated Circuit) layout based on hybrid shaping planning, comprising the following steps:

[0005] Step 1: Perform mathematical modeling of the layout problem in the ASIC layout;

[0006] Step 2: Establish MIP equations for the line length of each network using a lightweight RST model (i.e., based on the L-shaped connection between pins);

[0007] Step 3: Use integer variables to linearize the nonlinear equations;

[0008] Step 4: Introduce a single-flow algorithm to ensure the correctness of the lightweight RST line length model.

[0009] Step 1 includes: The ASIC layout has m cells, which are... The unit is a rectangle with different widths but the same height, and the width of the g-th rectangle is... The coordinates of the bottom left vertices of the m rectangles are respectively Since the cells have the same height, Y is set to an integer.

[0010] The coordinates of each element satisfy the following conditions: (1),

[0011] in These are the left, right, bottom, and top boundaries of the map.

[0012] In step 1, since the two cells cannot overlap in the layout, the following distance constraints must be met:

[0013] (2).

[0014] In step 2, for any given cell, there are several pins on the cell and several networks in the layout. Each network contains several pins. The pins on each network are connected by the same wire and have the same potential. The pins on a cell are independent of each other, and different pins belonging to the same cell can belong to different networks. The relative positions of the pins on the cell are fixed.

[0015] Step 2 also includes: considering only the L-shaped connection between pins, an L-shaped connection consisting of a horizontal line and a vertical line;

[0016] Introducing binary variables , This indicates whether a pin has a line pointing towards another pin, along the positive / negative x-axis. If so, then... The value is 1 if it is 1, otherwise it is 0.

[0017] Introducing binary variables , This indicates whether there is a line along the positive / negative direction of the y-axis; if so, then... The value is 1 if it is 1, otherwise it is 0.

[0018] Depending on the relative positions of the two pins, a binary variable is used. This indicates the relative positional relationship between two pins. For two pins p i and p j ,if A value of 0 represents p i In p j On the left, if If it is 1, then it represents p i In p j The right side of the equation is represented as:

[0019] (3),

[0020] in They represent p respectively i x-coordinate and p j The x-coordinate; and , The relationship is as follows:

[0021] (4),

[0022] Furthermore, due to the special nature of L-shaped connections, if there is a line along the x-direction, there must also be a line along the y-direction. Therefore, the following rules must be satisfied:

[0023] (5)

[0024] At the same time, there can be at most one L-type connection between the two pins, so it is also necessary to satisfy:

[0025] .

[0026] In step 3, by introducing an integer variable e, if the requirement is... absolute value Construct the following equations:

[0027] (6),

[0028] Where B is a local maximum; Equation (2) can be rewritten as:

[0029] (7),

[0030] in and Follow the restrictions of equation (6);

[0031] At the same time, use the following equation to transform formula (4) into a linear equation:

[0032] (8).

[0033] Step 4 includes: The single-flow algorithm enables pins in the network to be connected as nodes into a tree. An arbitrary pin serves as the source of the network flow, and the source flow is considered an integer. Each pin consumes one unit of flow, and the source node flows out n-1 units of flow. Therefore, all... , or , The sum is n-1, where n is the number of pins in the network;

[0034] (10)

[0035] Except for the source node, for each pin, the number of incoming flows is one more flow than the number of outgoing flows;

[0036] use Indicates from p i to p j If the flow rate is such that the flow rate satisfies the following equation:

[0037] (11).

[0038] The present invention also provides a storage medium storing a computer program or instructions, which, when the computer program or instructions are run, implement the ASIC layout optimization method based on hybrid integer programming.

[0039] In digital ASIC design, placement is a crucial part of physical design, with one goal being to reduce trace length. A layout consists of several nets, each containing interconnected pins. Optimizing trace length aims to find a layout that minimizes the sum of the trace lengths in all nets. This invention focuses on reducing placement time while achieving higher placement quality by reducing trace length, thereby effectively reducing the area of ​​large-scale hardware designs. This invention utilizes Mixed Integer Programming (MIP) to further optimize the layout, and further enhances placement performance by modeling with a rectangular Steiner tree (RST) to better predict trace lengths. The algorithm proposed in this invention is the first to combine MIP with finding the shortest RST trace length for placement.

[0040] Beneficial Effects: The proposed solution transforms the layout conditions into constraints of a linear programming problem by modeling the locations of standard ASIC cells and accurately modeling the RST (Redirect Strokes) of their networks. It also transforms reducing the layout line length into the objective function of the linear programming problem. During the solution process of the linear programming equations, the layout line length is continuously reduced, thus continuously optimizing the initial layout. This solution simultaneously addresses the two major challenges of placement and routing in integrated circuit design.

[0041] This invention also proposes a novel lightweight MIP equation based on RST. Instead of using the traditional grid-based modeling approach, a new connection-based modeling strategy is proposed, making the integer variables introduced in linear programming independent of the relative positions of the pins. This significantly reduces the number of variables used in constructing the RST equation, decreasing the number of variables from O(n^2) for Hanan networks. 4 The reduction from O(n) to O(n) 2 (n is the number of pins in a network).

[0042] This invention also proposes a novel method for transforming nonlinear equations into linear equations. By introducing a binary variable, the method transforms absolute value equations into linear equations and conditional constraint equations into linear equations, cleverly utilizing the properties of integers. Attached Figure Description

[0043] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments, and the advantages of the present invention in the above and / or other aspects will become clearer.

[0044] Figure 1a This is an example diagram showing the lengths of RST and HPWL.

[0045] Figure 1b This is an example diagram showing the lengths of RST and HPWL.

[0046] Figure 2a This is a schematic diagram of the arrangement of units (gray squares) on the layout.

[0047] Figure 2b This is a schematic diagram of an illegal layout.

[0048] Figure 3a This is a schematic diagram of the method of routing.

[0049] Figure 3b yes and Example diagram.

[0050] Figure 3c This is a schematic diagram of a single-flow algorithm. Detailed Implementation

[0051] This invention provides an ASIC placement optimization method based on hybrid integer programming, specifically including: First, a placement problem has m cells, which are... These units are rectangles with different widths but the same height. The widths of these rectangles are respectively... The coordinates of the bottom left vertex of these rectangles are For any given cell, there are several pins; for example, for... He will Pins. In this layout, there are several nets, each containing several pins. These pins are connected by the same wire and have equal potential. Note that the pins on a single cell are independent of each other; different pins belonging to the same cell can belong to different nets. The relative positions of the pins on the cell are considered fixed. For example... Figure 2a Circles represent pins, and different connections represent different networks. The red line connects a network that contains { } Pins. The length of the lines in these networks is measured in terms of RST. The goal of the linear programming method in this invention is to minimize the sum of the line lengths of all networks.

[0052] These units need to be placed appropriately in the layout. First, since these units are placed on different layers, their y-coordinates in the layout should be arranged in different layers. To measure their line length later, these different layers are abstracted into different rows in the layout, such as... Figure 2a As shown. So these It should be an integer variable. Similarly, each unit should adhere to boundary conditions and should not exceed the boundaries, such as... Figure 2b In C2 and C6, the coordinates of each element must meet the following conditions:

[0053] (1),

[0054] in These are the left, right, bottom, and top boundaries of the map. ;

[0055] At the same time, these units cannot overlap, just like in Figure 2a , Figure 2b c3 and c4 are the same. Therefore, for any two cells, they will overlap if they belong to the same row and the distance between them (based on the cell's midpoint) is less than half the sum of their widths. This means that to prevent overlap, the following constraints must be met:

[0056] (2).

[0057] in ;

[0058] However, this restriction is non-linear because it includes absolute values. To transform equation (2) into a linear equation, this invention proposes a new approach. First, an integer variable e is introduced; if the requirement is... absolute value Construct the following equations:

[0059] (3),

[0060] Where B is a local maximum. In this case, regardless of the value of e, It must equal Therefore, equation (2) can be rewritten as:

[0061] (4),

[0062] in and Follow the restrictions of equation (3);

[0063] Combined with (1), (3) and (4), these units can be legally placed on the layout.

[0064] Similarly, MIP equations need to be established for the RST of each network. This invention proposes a routing method based on L-shaped connections. If a connection is set between two pins, then the connection must have only two possibilities, such as... Figure 3a As shown, p0 and p1 are connected, which can only be either method 1 or method 2 in the diagram. However, even if these three pairs of pins are always connected, the resulting wire lengths will differ depending on the connection method. This is because in some connection methods, a segment of the wire length will overlap, thus affecting the network bus length. For example... Figure 3a If both p0 and p1, and p0 and p2, use method 2 simultaneously, a section of the wire length will overlap; however, this will not happen with other combinations. To accurately estimate the wire length between pins, it is necessary to know whether there is a connection between the two pins and how they are connected.

[0065] An L-shaped connection is formed by connecting a horizontal line and a vertical line. Indicates a from p i Starting from point p, determine whether there exists a line leading to p. i And along the positive x-axis line, Indicates a from p i Starting from point p, determine whether there exists a line leading to p. i And along the negative x-axis. If it exists, then... The value is 1, if it does not exist. The value is 0.

[0066] Similarly and This indicates whether a line exists along the positive or negative y-axis. or and It should be a binary variable (it can only take the values ​​0 and 1). Note that... It is impossible for both to be 1 at the same time, for example, in Figure 3b In the middle, because p3 is to the left of p0, It is 1, and It is 0.

[0067] It depends on the relative positions of the two pins. Using binary variables... This indicates the relative positional relationship between two pins. If A value of 0 represents p i In p j On the left, if If it is 1, then it represents p i In p j On the right, similarly, Similarly, the relationship between these values ​​and the pin coordinates is expressed as follows:

[0068] (5),

[0069] in They represent p respectively i x-coordinate and p j The x-coordinate. and , The relationship is as follows:

[0070] (6),

[0071] in ;

[0072] The above formula is not a linear relationship. Formula (6) can be transformed into a linear equation using the following formula:

[0073] (7),

[0074] because and They always exist in pairs within an L-shaped connection, for example in Figure 3b In the middle, if If it is 1, then The value must be 1. Therefore, these variables need to satisfy the following relationship:

[0075] (8),

[0076] Furthermore, any two pins can only have one type of L-shaped connection, because having two different connections would result in redundancy. Therefore... and The following conditions should also be met:

[0077] (9),

[0078] Finally, to ensure all pins are connected without redundancy, a single-flow algorithm is introduced (reference: N. Fan and M. Golari, “Integer Programming Formulations for Minimum Spanning Forests and Connected Components in Sparse Graphs,” International Conference on Combinatorial Optimization and Applications, p. 613–622, 2014). This algorithm is applied to network-based flows, ensuring that pins in the network can be connected as nodes to form a tree. An arbitrary pin acts as the source of the flow, and n-1 units of flow flow out (n is the number of pins in the network). For each pin, the number of inflows is exactly one unit more than the number of outflows. Simultaneously, n-1 L-shaped connections are needed to prevent redundancy, which means that all... , or , The sum is n-1:

[0079] (10)

[0080] Simultaneously use Indicates from p i to p j Traffic ( (The value must be non-negative). The flow rate must satisfy the following equation:

[0081] (11).

[0082] The first formula in formula (11) here indicates that if p i and p j If there is no connection between them, then f ij The value must be 0; if there is a connection, the maximum flow will not exceed n-1. The second equation indicates that p0 is the source of the flow, with a total flow of n-1. The third equation indicates the flow relationship for each pin other than p0. For example, in... Figure 3a , Figure 3b In the diagram, the arrows represent the direction of flow. The flow rate from p0 is 3, and the flow rate from p0 to p3 is (f...). 03 The flow (f) from p1 to p2 is 1. 02The input / output flow condition is 2, and the flow from p2 to p1 is 1. If a loop occurs or one of the pins is not connected, the input / output flow condition will not be met. With these constraints, an RST uses... To indicate that if it is necessary to know the length of the RST line, we introduce... to represent when The line lengths when they exist, and the relationship between them, can be expressed by the following equation:

[0083] (12)

[0084] Similarly, formula (12) is transformed into the following linear equation:

[0085] (13)

[0086] However, these may overlap; for a single pin, only the longest wire length needs to be considered in each direction. For example, for... Figure 3b In this context, p0 has two L-shaped connected y-direction portions in the negative y-axis direction. and When calculating the wire length, only the longest one needs to be calculated. Therefore, we only need to know the longest wire length in each direction for a single pin:

[0087] (14)

[0088] in pin p i The maximum length that can be extended outward along the positive x-axis is found by max(), which means finding all the maximum lengths that can be extended outward along the positive x-axis. The maximum value in. Similarly, the following... p i The maximum length that extends outward in the negative x-axis direction.

[0089] The goal of MIP is to minimize the RST line length for all networks. The line length for each network is:

[0090] (15)

[0091] Because the optimization objective of each MIP is to reduce this value, Written as:

[0092] (16)

[0093] Thus, although the maximum value function is not directly expressed, It will also become during the optimization process. Similarly, That's also the case. Combining all the constraints, and inputting formulas (5), (7), (9), (10), (11), (13), and (16) into the MIP solver, we obtain a layout with the shortest RST line length. Because... All When a network has a large number of pins, it will consume too many variables and affect the solution speed. This invention also combines the network segmentation algorithm in FLUTE and applies it to networks with a large number of pins to reduce the number of variables.

[0094] PGA (Power Generation Automation) tools use timing-driven ASIC placement algorithms. These algorithms employ simulated annealing (SA) to minimize a weighted average of latency and wire length, exhibiting high stability. Unlike the method described in this invention, SA does not prioritize optimizing wire length, limiting its potential for achieving a good placement. Google is also researching the use of neural networks for design placement, mapping placement parameters to machine learning. However, this algorithm relies on large training datasets, suffers from low stability, and has low overall layout utilization, making practical application difficult.

[0095] MIP is also widely used in the field of network layout, employing more variables in its RST modeling of the network than this invention. Previous algorithms decomposed the layout into a mesh, such as... Figure 1a , Figure 1b As shown, the resulting line length represents the number of unit grids. To achieve better results with this grid-based layout, the grid must be set very densely, meaning many variables need to be introduced to represent different positions and connection methods. Later layout algorithms introduced the Hanan grid, which ignores grid lines that do not pass through any pins, and the distance between grid lines varies. This method can effectively reduce grid density, but as the positions of units and pins change, each layout sequence corresponds to a different Hanan grid, which means... The variables need to be introduced to establish the RST line length model.

[0096] Existing solutions not only utilize MIP to model the cell positions but also establish precise RST line length models for each network pin. This invention, through a method-based RST modeling approach, reduces the number of variables required to establish the RST line length model. This improves the solution speed of MIP compared to previous modeling methods.

[0097] Example

[0098] This embodiment uses Cadence's INNOWUS 18.1 placement software to perform initial placement on some modules. Then, GUROBI 10.0 is used as the MIP solver. The solver platform is a 40-core Intel Xeon Silver 4210R CPU, and the method execution time is 3000 seconds. These modules contain 300-1000 cells, and the cell size is based on the ASAP 7nm library. The initial placement and final routing results for these modules are shown in Table 1 below.

[0099] Table 1

[0100]

[0101] As can be seen from the table above, the routing results obtained by the method of the present invention achieve an improvement of 1.18% and 1.79% in detailed routing and global routing, respectively, compared with the initial results.

[0102] In its specific implementation, this application provides a computer storage medium and a corresponding data processing unit. The computer storage medium is capable of storing a computer program, which, when executed by the data processing unit, can run the invention's content regarding an ASIC layout optimization method based on hybrid integer programming, as well as some or all of the steps in various embodiments. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0103] Those skilled in the art will clearly understand that the technical solutions in the embodiments of the present invention can be implemented using computer programs and their corresponding general-purpose hardware platforms. Based on this understanding, the technical solutions in the embodiments of the present invention, or the parts that contribute to the prior art, can be embodied in the form of computer programs, i.e., software products. These computer program software products can be stored in a storage medium and include several instructions to cause a device containing a data processing unit (which may be a personal computer, server, microcontroller, MUU, or network device, etc.) to execute the methods described in various embodiments or certain parts of the embodiments of the present invention.

[0104] This invention provides an ASIC layout optimization method based on hybrid shaping programming. Many methods and approaches exist for implementing this technical solution; the above description is merely a preferred embodiment of the invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of this invention, and these improvements and modifications should also be considered within the scope of protection of this invention. All components not explicitly stated in this embodiment can be implemented using existing technologies.

Claims

1. A method for ASIC layout optimization based on hybrid shape planning, characterized in that, Includes the following steps: Step 1: Perform mathematical modeling of the layout problem in the ASIC layout: Step 2: Establish MIP equations for the line length of each network using a lightweight RST model; In step 2, for any given cell, there are several pins on the cell and several networks in the layout. Each network contains several pins. The pins on each network are connected by the same wire and have the same potential. The pins on a cell are independent of each other, and different pins belonging to the same cell can belong to different networks. The relative positions of the pins on the cell are fixed. Step 2 also includes: considering only the L-shaped connection between pins, an L-shaped connection consisting of a horizontal line and a vertical line; Introducing binary variables , represents whether a pin has a line going towards another pin, and in the positive / negative direction of the x-axis, if so value is 1, otherwise 0; Introducing binary variables , This indicates whether there is a line along the positive / negative direction of the y-axis; if so, then... The value is 1 if it is 1, otherwise it is 0. Depending on the relative positions of the two pins, a binary variable is used. This indicates the relative positional relationship between two pins. For two pins p i and p j ,if A value of 0 represents p i In p j On the left, if If it is 1, then it represents p i In p j The right side of the equation is represented as: （3）， Where B is a local maximum; They represent p respectively i x-coordinate and p j The x-coordinate; and , The relationship is as follows: （4）， If there exists a line along the x-direction, there must also exist a line along the y-direction. Therefore, the following rule must be satisfied: （5）， There can be at most one L-type connection between the two pins, so the following must also be satisfied: （17）； Step 3: Use integer variables to linearize the nonlinear equations; In step 3, formula (4) is simultaneously transformed into a linear equation using the following equation: （8）； Step 4: Introduce a single-flow algorithm to ensure the correctness of the lightweight RST line length model; In step 4, the single-flow algorithm enables pins in the network to be connected as nodes into a tree. An arbitrary pin acts as the source of the network's flow, and the source flow is considered an integer. Each pin consumes one unit of flow, and the source node flows out n-1 units of flow. Therefore, all... , or , The sum is n-1, where n is the number of pins in the network; （10）， Except for the source node, for each pin, the number of incoming flows is one more flow than the number of outgoing flows; use Indicates from p i to p j If the flow rate is such that the flow rate satisfies the following equation: （11）； Step 5 requires further information about the length of the RST line, which is then introduced. to represent when The line lengths when they exist, and the relationship between them, can be expressed by the following equation: ， Similarly, formula (12) is transformed into the following linear equation: ， However, these may overlap, so it is only necessary to know the longest wire length in each direction of a single pin: ， in, pin p i The maximum length that can be extended outward along the positive x-axis is found by max(). The maximum value in, similarly, is as follows: p i The maximum length extending outward in the negative x-axis direction; the goal of MIP is to minimize the RST line length of all networks, with the line length of each network being: ， Because the optimization objective of each MIP is to reduce this value, Written as: ； Step 6: Combine all constraints and input formulas (3), (8), (17), (10), (11), (13) and (16) into the MIP solver to obtain a layout with the shortest RST line length.

2. The method according to claim 1, characterized in that, Step 1 includes: The ASIC layout has m cells, which are... The unit is a rectangle with different widths but the same height, and the width of the g-th rectangle is... The coordinates of the bottom left vertices of the m rectangles are respectively Since the units have the same height, Y is set to an integer; the coordinates of each unit satisfy the following conditions: (1), in These are the left, right, bottom, and top boundaries of the map.

3. The method according to claim 2, characterized in that, In step 1, since the two cells cannot overlap in the layout, the following distance constraints must be met: （2）。 4. The method according to claim 3, characterized in that, In step 3, by introducing an integer variable e, if the requirement is... absolute value Construct the following equations: （6）， In this case, regardless of the value of e, It must equal Therefore, equation (2) can be rewritten as: （7）， in and Follow the restrictions of equation (6).

5. A storage medium, characterized in that, It stores a computer program or instructions that, when executed, implement the method as described in any one of claims 1 to 4.

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