Comparators, chips and electronic devices

Abstract

The present invention discloses a comparator, a chip and an electronic device, wherein the comparator comprises: a pre-amplifier circuit, a latch circuit and a correction circuit, the correction circuit comprises a first correction unit, a storage unit and a second correction unit, the first correction unit is connected to the differential input end of the pre-amplifier circuit, the differential output end of the pre-amplifier circuit is connected to the differential input end of the latch circuit through the storage unit, and the second correction unit is connected to the differential input end of the latch circuit, wherein in the offset storage stage, the input offset voltage of the pre-amplifier circuit is stored in the storage unit through the first correction unit, and the input offset voltage of the latch circuit is stored in the storage unit through the second correction unit, so that in the signal comparison stage, the input offset voltage of the pre-amplifier circuit and the input offset voltage of the latch circuit are corrected by the voltage of the storage unit, thereby making the comparator have higher comparison accuracy.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a comparator, a chip and an electronic device. Background Art

[0002] In an integrated circuit, a comparator is an important analog circuit module that can compare and judge different input voltages. At present, the comparator circuit in the related technology is usually composed of a pre-amplifier + a latch, wherein the pre-amplifier is mainly used to amplify the input voltage, and the latch is used to latch and output the comparison result, thereby realizing the comparison function of the input signal. At the same time, in the related technology, switching capacitors are respectively set on the output pair of tubes of the pre-amplifier, and the offset voltage of the pre-amplifier is stored in the pre-amplifier through a certain timing control, so as to realize the sampling of the offset voltage and improve the comparison accuracy of the comparator.

[0003] The disadvantage of the comparator in the above-mentioned related technology is that there is no circuit in the comparator to eliminate the offset voltage in the latch, so the offset voltage in the latch can only be suppressed by relying on the gain of the pre-amplifier. In the high-speed designed circuit, in order to achieve high bandwidth, the gain of the pre-amplifier is limited, resulting in low accuracy of the comparator in the related technology. Therefore, the comparator cannot be used in high-speed and high-precision scenarios, thereby reducing the applicability of the comparator. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems in the related art to a certain extent. To this end, the first purpose of the present invention is to provide a comparator, by setting a correction circuit between a pre-amplifier circuit and a latch circuit, in the offset storage stage, the first correction unit in the correction circuit stores the input offset voltage of the pre-amplifier circuit in the storage unit, and at the same time, the second correction unit in the correction circuit stores the input offset voltage of the latch circuit in the storage unit, so that when the comparator is in the signal comparison stage, the voltage in the storage unit can simultaneously realize the offset voltage correction function of the pre-amplifier circuit and the latch circuit, effectively improving the comparison accuracy of the comparator, broadening the application scenarios of the comparator, and thus improving the applicability of the comparator.

[0005] The second objective of the present invention is to provide a chip.

[0006] A third object of the present invention is to provide an electronic device.

[0007] To achieve the above-mentioned purpose, a first embodiment of the present invention proposes a comparator, comprising: a pre-amplifier circuit, a latch circuit and a correction circuit, the correction circuit comprising a first correction unit, a storage unit and a second correction unit, the first correction unit is connected to the differential input end of the pre-amplifier circuit, the differential output end of the pre-amplifier circuit is connected to the differential input end of the latch circuit through the storage unit, and the second correction unit is connected to the differential input end of the latch circuit, wherein, in the offset storage stage, the input offset voltage of the pre-amplifier circuit is stored in the storage unit through the first correction unit, and the input offset voltage of the latch circuit is stored in the storage unit through the second correction unit, so that in the signal comparison stage, the input offset voltage of the pre-amplifier circuit and the input offset voltage of the latch circuit are corrected through the voltage of the storage unit.

[0008] According to the comparator of the embodiment of the present invention, by setting a correction circuit between the pre-amplifier circuit and the latch circuit, in the offset storage stage, the first correction unit in the correction circuit stores the input offset voltage of the pre-amplifier circuit in the storage unit, and the second correction unit in the correction circuit stores the input offset voltage of the latch circuit in the storage unit, so that when the comparator is in the signal comparison stage, the voltage in the storage unit can simultaneously realize the offset voltage correction function for the pre-amplifier circuit and the latch circuit, effectively improving the comparison accuracy of the comparator, broadening the application scenarios of the comparator, and thus improving the applicability of the comparator.

[0009] According to one embodiment of the present invention, the latch circuit includes a first differential input pair of tubes, the first differential input pair of tubes includes a first switch tube and a second switch tube, wherein, in the offset storage stage, the input and output ends of the first switch tube are short-circuited by the second correction unit, and the input and output ends of the second switch tube are short-circuited, so as to store the input offset voltage of the latch circuit in the storage unit.

[0010] According to one embodiment of the present invention, the second correction unit includes: a first resistor, one end of the first resistor is connected to a first preset power supply; a third switch tube, a first end of the third switch tube is connected to the other end of the first resistor, and a second end of the third switch tube is connected to a first control signal end; a fourth switch tube, a first end of the fourth switch tube and a third end of the third switch tube are respectively connected to the first end of the first switch tube, a second end of the fourth switch tube is connected to the second control signal end, and a third end of the fourth switch tube and a second end of the first switch tube are respectively connected to a first differential input end of a latch circuit; wherein the first end of the first switch tube serves as an output end of the first switch tube, and the second end of the first switch tube serves as an input end of the first switch tube.

[0011] According to one embodiment of the present invention, the second correction unit also includes: a second resistor, one end of the second resistor is connected to the first preset power supply; a fifth switch tube, the first end of the fifth switch tube is connected to the other end of the second resistor, and the second end of the fifth switch tube is connected to the first control signal end; a sixth switch tube, the first end of the sixth switch tube and the third end of the fifth switch tube are respectively connected to the first end of the second switch tube, the second end of the sixth switch tube is connected to the second control signal end, and the third end of the sixth switch tube and the second end of the second switch tube are respectively connected to the second differential input end of the latch circuit; wherein the first end of the second switch tube serves as the output end of the second switch tube, and the second end of the second switch tube serves as the input end of the second switch tube.

[0012] According to one embodiment of the present invention, in the offset storage stage, the third switch tube, the fourth switch tube, the fifth switch tube and the sixth switch tube are controlled to be turned on through the first control signal provided by the first control signal terminal and the second control signal provided by the second control signal terminal, so as to short-circuit the input and output terminals of the first switch tube and the input and output terminals of the second switch tube.

[0013] According to one embodiment of the present invention, the pre-amplifier circuit includes a second differential input pair of tubes, and the second differential input pair of tubes includes a seventh switch tube and an eighth switch tube, wherein, in the offset storage stage, the input end of the seventh switch tube and the input end of the eighth switch tube are short-circuited by the first correction unit to store the input offset voltage of the pre-amplifier circuit in the storage unit.

[0014] According to one embodiment of the present invention, the first correction unit includes: a ninth switch tube, the first end of the ninth switch tube and the second end of the seventh switch tube are respectively connected to the first differential input end of the pre-amplifier circuit, the second end of the ninth switch tube is connected to the first control signal end, and the third end of the ninth switch tube is connected to the first preset common-mode power supply; wherein the second end of the seventh switch tube serves as the input end of the seventh switch tube, and the first end of the seventh switch tube is connected to the first differential output end of the pre-amplifier circuit.

[0015] According to one embodiment of the present invention, the first correction unit also includes: a tenth switch tube, the first end of the tenth switch tube and the second end of the eighth switch tube are respectively connected to the second differential input end of the pre-amplifier circuit, the second end of the tenth switch tube is connected to the first control signal end, and the third end of the tenth switch tube is connected to the first preset common mode power supply; wherein the second end of the eighth switch tube serves as the input end of the eighth switch tube, and the first end of the eighth switch tube is connected to the second differential output end of the pre-amplifier circuit.

[0016] According to an embodiment of the present invention, in the offset storage stage, the ninth switch tube and the tenth switch tube are controlled to be turned on by the first control signal provided by the first control signal terminal to short-circuit the input terminal of the seventh switch tube and the input terminal of the eighth switch tube.

[0017] According to one embodiment of the present invention, the comparator also includes an input unit, which includes: an eleventh switch tube, a first end of the eleventh switch tube is connected to the first differential input end of the pre-amplifier circuit, a second end of the eleventh switch tube is connected to the third control signal end, and a third end of the eleventh switch tube is connected to the first differential input end of the comparator; a twelfth switch tube, a first end of the twelfth switch tube is connected to the second differential input end of the pre-amplifier circuit, a second end of the twelfth switch tube is connected to the third control signal end, and a third end of the twelfth switch tube is connected to the second differential input end of the comparator; wherein, through the third control signal provided by the third control signal end, in the offset storage stage, the eleventh switch tube and the twelfth switch tube are controlled to be disconnected; in the signal comparison stage, the eleventh switch tube and the twelfth switch tube are controlled to be turned on, so as to input the differential comparison signal between the first differential input end and the second differential input end of the comparator into the pre-amplifier circuit for pre-amplification.

[0018] According to one embodiment of the present invention, the storage unit includes: a first capacitor, one end of the first capacitor is connected to the first differential output end of the pre-amplifier circuit, and the other end of the first capacitor is connected to the first differential input end of the latch circuit; a second capacitor, one end of the second capacitor is connected to the second differential output end of the pre-amplifier circuit, and the other end of the second capacitor is connected to the second differential input end of the latch circuit.

[0019] According to one embodiment of the present invention, the latch circuit also includes: a thirteenth switch tube, the third end of the first switch tube and the third end of the second switch tube are respectively connected to the first end of the thirteenth switch tube, the second end of the thirteenth switch tube is connected to the bias voltage signal end, and the third end of the thirteenth switch tube is grounded; wherein, the bias voltage signal provided by the bias voltage signal end controls the thirteenth switch tube to provide a bias voltage for the first switch tube and the second switch tube.

[0020] According to one embodiment of the present invention, the latch circuit further includes: a fourteenth switch tube, a first end of the fourteenth switch tube is connected to the first differential output end of the latch circuit, a second end of the fourteenth switch tube is connected to the fourth control signal end, and a third end of the fourteenth switch tube is connected to the first end of the first switch tube; a fifteenth switch tube, a first end of the fifteenth switch tube is connected to the second differential output end of the latch circuit, a second end of the fifteenth switch tube is connected to the fourth control signal end, and a third end of the fifteenth switch tube is connected to the first end of the second switch tube; a sixteenth switch tube, a first end of the sixteenth switch tube is connected to the first differential output end of the latch circuit, a second end of the sixteenth switch tube is connected to the fifth control signal end, and a third end of the fifteenth switch tube is connected to the first end of the second switch tube. The first terminal of the latch circuit is connected to the second differential output terminal of the latch circuit, the second terminal of the seventeenth switch tube is connected to the fifth control signal terminal, and the third terminal of the seventeenth switch tube is connected to the first preset power supply; the first terminal of the latch circuit is connected to the second differential output terminal of the latch circuit, the second terminal of the seventeenth switch tube is connected to the fifth control signal terminal, and the third terminal of the seventeenth switch tube is connected to the first preset power supply; wherein, in the signal comparison stage, the fourteenth switch tube, the fifteenth switch tube, the sixteenth switch tube and the seventeenth switch tube are controlled to be turned on through the fourth control signal terminal provided by the fourth control signal terminal and the fifth control signal provided by the fifth control signal terminal, so as to output the pre-amplified differential comparison signal output by the pre-amplification circuit to the first differential output terminal and the second differential output terminal of the latch circuit.

[0021] According to one embodiment of the present invention, the latch circuit further includes: an eighteenth switch tube, a first end of the eighteenth switch tube is connected to the first differential output end of the latch circuit, a second end of the eighteenth switch tube is connected to the second differential output end of the latch circuit, and a third end of the eighteenth switch tube is connected to the first preset power supply; a nineteenth switch tube, a first end of the nineteenth switch tube is connected to the first differential output end of the latch circuit, a second end of the nineteenth switch tube is connected to the second differential output end of the latch circuit; a twentieth switch tube, a first end of the twentieth switch tube is connected to the second differential output end of the latch circuit, a second end of the twentieth switch tube is connected to the first differential output end of the latch circuit, and a third end of the twentieth switch tube is connected to the first preset power supply; a twenty-first switch tube tube, the first end of the twenty-first switch tube is connected to the second differential output end of the latch circuit, and the second end of the twenty-first switch tube is connected to the first differential output end of the latch circuit; a twenty-second switch tube, the third end of the nineteenth switch tube and the third end of the twenty-first switch tube are connected to the first end of the twenty-second switch tube, the second end of the twenty-second switch tube is connected to the fifth control signal terminal, and the third end of the twenty-second switch tube is grounded; wherein, in the signal comparison stage, the fourteenth switch tube, the fifteenth switch tube, the sixteenth switch tube and the seventeenth switch tube are controlled to be turned off, and the twenty-second switch tube is controlled to be turned on, so as to output the comparison result of the differential input signal.

[0022] According to one embodiment of the present invention, the pre-amplification circuit also includes: a twenty-third switch tube, the third end of the seventh switch tube and the third end of the eighth switch tube are respectively connected to the first end of the twenty-third switch tube, the second end of the twenty-third switch tube is connected to the bias voltage signal end, and the third end of the twenty-third switch tube is grounded; wherein, the bias voltage signal provided by the bias voltage signal end controls the twenty-third switch tube to provide a bias voltage for the seventh switch tube and the eighth switch tube.

[0023] According to one embodiment of the present invention, the pre-amplification circuit also includes: a current mirror, a first end of the current mirror is connected to the first preset power supply, a second end of the current mirror is connected to the first end of the seventh switch tube, and a third end of the current mirror is connected to the first end of the eighth switch tube.

[0024] To achieve the above-mentioned object, a second embodiment of the present invention provides a chip, including the aforementioned comparator.

[0025] The chip according to the embodiment of the present invention can realize a high-precision comparison function through the aforementioned comparator, thereby improving the comparison performance of the chip.

[0026] To achieve the above-mentioned purpose, a third aspect of the present invention provides an electronic device, including the aforementioned comparator, or the aforementioned chip.

[0027] The electronic device according to the embodiment of the present invention can realize a high-precision comparison function through the aforementioned comparator, thereby improving the comparison performance of the electronic device.

[0028] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a schematic structural diagram of a comparator according to an embodiment of the present invention;

[0030] Figure 2 is a circuit diagram of a second correction unit according to an embodiment of the present invention;

[0031] Figure 3 is a schematic diagram of a control signal of a comparator according to an embodiment of the present invention;

[0032] Figure 4 is a circuit diagram of a pre-amplification unit according to an embodiment of the present invention;

[0033] Figure 5a - Figure 5b is a circuit diagram of a comparator according to an embodiment of the present invention;

[0034] Figure 6is a schematic structural diagram of a chip according to an embodiment of the present invention;

[0035] Figure 7a - Figure 7b FIG. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0036] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0037] The comparator, chip and electronic device provided by the embodiments of the present invention are described below with reference to the accompanying drawings.

[0038] Figure 1 FIG. 1 is a schematic diagram of a comparator 100 according to an embodiment of the present invention. Figure 1 As shown, the comparator 100 includes: a pre-amplification circuit 110 , a latch circuit 120 and a correction circuit 130 .

[0039] The correction circuit 130 includes a first correction unit 131, a storage unit 132 and a second correction unit 133. The first correction unit 131 is connected to the differential input terminal (VIP1, VIN1) of the pre-amplifier circuit 110. The differential output terminal (VOP1, VON1) of the pre-amplifier circuit 110 is connected to the differential input terminal (VIP2, VIN2) of the latch circuit 120 through the storage unit 132. The second correction unit 133 is connected to the differential input terminal (VIP2, VIN2) of the latch circuit 120. In the offset storage stage, the input offset voltage of the pre-amplifier circuit 110 is stored in the storage unit 132 through the first correction unit 131, and the input offset voltage of the latch circuit 120 is stored in the storage unit 132 through the second correction unit 133, so that in the signal comparison stage, the input offset voltage of the pre-amplifier circuit 110 and the input offset voltage of the latch circuit 120 are corrected through the voltage of the storage unit 132.

[0040] Specifically, refer to Figure 1As shown, the signal comparison function of the comparator 100 is mainly realized by the pre-amplifier circuit 110 and the latch circuit 120, and the specific process is as follows: in the signal comparison stage, two input signals are input into the comparator 100 from the differential input terminals (VIP1, VIN1) of the pre-amplifier circuit 110, and then the pre-amplifier circuit 110 pre-amplifies the input signal and outputs it in the form of a differential signal through the differential output terminals (VOP1, VON1) of the pre-amplifier circuit 110 to the differential input terminals (VIP2, VIN2) of the latch circuit 120, the differential signal is compared and latched in the latch circuit 120, and then the latch circuit 120 outputs the comparison result, thereby realizing the comparison function of the comparator 100 for the two input signals. It can be seen from the above process that the offset voltage that affects the comparison accuracy of the comparator 100 in the embodiment of the present invention mainly includes two partial factors. The first partial factor is the input offset voltage of the pre-amplifier circuit 110 when the pre-amplifier circuit 110 converts the input signal into a differential signal output, and the second partial factor is the input offset voltage of the latch circuit 120 when the latch circuit 120 receives and transmits the differential signal.

[0041] In this regard, there is a related technology that adds storage capacitors to the differential output ends of the pre-amplifier circuit 110, and adds an offset storage stage before the signal comparison stage of the comparator 100. In this stage, the input offset voltage of the pre-amplifier circuit 110 is first stored by the storage capacitor, so that the comparator 100 can correct the input offset voltage in the pre-amplifier circuit 110 when entering the signal comparison stage, thereby improving the comparison accuracy of the comparator to a certain extent. However, this related technology ignores the input offset voltage in the latch circuit 120. Therefore, the comparison accuracy of the comparator 100 will still be greatly limited.

[0042] In the embodiment of the present invention, in the offset voltage storage stage, not only can the input offset voltage of the pre-amplifier circuit 110 be stored in the storage unit 132 through the first correction unit 131, but the input offset voltage in the latch circuit can also be stored in the storage unit 132 through the second correction unit 133. Therefore, in the signal comparison stage, the storage unit 132 can simultaneously correct the input offset voltage of the pre-amplifier circuit 110 and the input offset voltage of the latch circuit 120, thereby further improving the comparison accuracy of the comparator 100. When facing a high-precision, high-speed comparison scenario, the comparator 100 of the embodiment of the present invention can also meet the comparison requirements of the scenario, thereby improving the applicability of the comparator.

[0043] It should be noted that in the comparator 100 of the embodiment of the present invention, the pre-amplification circuit 100 may include one or more stages of amplification circuits, which can be configured according to actual needs and are not specifically limited here.

[0044] In the above embodiment, by setting a correction circuit between the pre-amplifier circuit and the latch circuit, in the offset storage stage, the first correction unit in the correction circuit stores the input offset voltage of the pre-amplifier circuit in the storage unit, and at the same time, the second correction unit in the correction circuit stores the input offset voltage of the latch circuit in the storage voltage, so that when the comparator is in the signal comparison stage, the voltage in the storage unit can simultaneously realize the offset voltage correction function for the pre-amplifier circuit and the latch circuit, effectively improving the comparison accuracy of the comparator, broadening the application scenarios of the comparator, and thus improving the applicability of the comparator.

[0045] In some embodiments, reference Figure 2 As shown, the latch circuit 120 includes a first differential input pair of tubes 121, and the first differential input pair of tubes 121 includes a first switch tube Q1 and a second switch tube Q2, wherein, in the offset storage stage, the input and output ends of the first switch tube Q1 are short-circuited, and the input and output ends of the second switch tube Q2 are short-circuited through the second correction unit 133, so as to store the input offset voltage of the latch circuit 120 in the storage unit 132.

[0046] Specifically, refer to Figure 2 As shown, the first switch tube Q1 and the second switch tube Q2 can be NMOS tubes. In this case, the input end of these switch tubes refers to the gate of the switch tube, and the output end refers to the drain of the switch tube. At the same time, in order to ensure the normal operation of the first differential input pair tube 121, the source of the first switch tube Q1 and the second switch tube Q2 can be connected to the equipotential VSS. When the first differential input pair tube 121 is operating normally, the pre-amplification circuit 110 inputs a differential voltage to the input end of the first switch tube Q1 and the second switch tube Q2 to adjust the conduction degree of the first switch tube Q1 and the second switch tube Q2, thereby changing the output end current of the first switch tube Q1 and the second switch tube Q2, thereby converting the differential voltage into a differential current and transmitting it to the back-end circuit of the first differential input pair tube 121.

[0047] In the above process, the input offset voltage of the latch circuit 120 refers to the input offset voltage of the first switch tube Q1 and the second switch tube Q2. The input offset voltage will affect the comparison accuracy of the comparator 100. In the embodiment of the present invention, in the offset storage stage, the second correction unit 133 can short-circuit the input and output ends of the first switch tube Q1 and the input and output ends of the second switch tube Q2, and the second correction unit 133 is combined to form a closed-loop amplifier with a unit gain, so that the transmitted differential signal can be returned to the input end and stored in the storage unit 132. Since the transmitted differential signal contains the offset voltage of the first switch tube Q1 and the second switch tube Q2 with a unit gain, the offset voltage is also the input offset voltage of the latch circuit 120, so that the storage unit 132 can realize the correction function of the input offset voltage of the latch circuit 120 in the signal comparison stage, thereby improving the comparison accuracy and applicability of the comparator.

[0048] In some embodiments, reference Figure 2 As shown, the second correction unit 133 includes: a first resistor R1, a third switch tube Q3 and a fourth switch tube Q4, wherein one end of the first resistor R1 is connected to the first preset power supply VDD1; the first end of the third switch tube Q3 is connected to the other end of the first resistor R1, and the second end of the third switch tube Q3 is connected to the first control signal terminal K1; the first end of the fourth switch tube Q4 and the third end of the third switch tube Q3 are respectively connected to the first end of the first switch tube Q1, the second end of the fourth switch tube Q4 is connected to the second control signal terminal K2, and the third end of the fourth switch tube Q4 and the second end of the first switch tube Q1 are respectively connected to the first differential input terminal VIP2 of the latch circuit 120; wherein the first end of the first switch tube Q1 serves as the output end of the first switch tube Q1, and the second end of the first switch tube Q1 serves as the input end of the first switch tube Q1.

[0049] Furthermore, the second correction unit 133 also includes: a second resistor R2, a fifth switch tube Q5 and a sixth switch tube Q6, wherein one end of the second resistor R2 is connected to the first preset power supply VDD1; the first end of the fifth switch tube Q5 is connected to the other end of the second resistor R2, and the second end of the fifth switch tube Q5 is connected to the first control signal terminal K1; the first end of the sixth switch tube Q6 and the third end of the fifth switch tube Q5 are respectively connected to the first end of the second switch tube Q2, the second end of the sixth switch tube Q6 is connected to the second control signal terminal K2, and the third end of the sixth switch tube Q6 and the second end of the second switch tube Q2 are respectively connected to the second differential input terminal VIN2 of the latch circuit 120; wherein the first end of the second switch tube Q2 serves as the output end of the second switch tube Q2, and the second end of the second switch tube Q2 serves as the input end of the second switch tube Q2.

[0050] Furthermore, in the offset storage stage, the third switch tube Q3, the fourth switch tube Q4, the fifth switch tube Q5 and the sixth switch tube Q6 are controlled to be turned on through the first control signal provided by the first control signal terminal K1 and the second control signal provided by the second control signal terminal K2, so as to short-circuit the input and output ends of the first switch tube Q1 and the input and output ends of the second switch tube Q2.

[0051] Optional, reference Figure 2 As shown, the storage unit 132 includes: a first capacitor C1 and a second capacitor C2, wherein one end of the first capacitor C1 is connected to the first differential output terminal VOP1 of the pre-amplifier circuit 110, and the other end of the first capacitor C1 is connected to the first differential input terminal VIP2 of the latch circuit 120; one end of the second capacitor C2 is connected to the second differential output terminal VON1 of the pre-amplifier circuit 110, and the other end of the second capacitor C2 is connected to the second differential input terminal VIN2 of the latch circuit 120.

[0052] Specifically, refer to Figure 2 As shown, the third to sixth switch tubes (Q3-Q6) can be NMOS tubes. In this case, the first end of these switch tubes is the drain, the second end is the gate, and the third end is the source. In this case, the control signal output by the first control signal terminal K1 and the second control signal terminal K2 can be as follows: Figure 3 As shown, in the offset storage stage, the first control signal is at a high level, so that the third switch tube Q3 and the fifth switch tube Q5 are turned on. At this time, the voltage of the first preset power supply VDD1 can be given to the drain of the first switch tube Q1 through the first resistor R1 and the third switch tube Q3. At the same time, the voltage of the first preset power supply VDD1 can also be given to the drain of the second switch tube Q2 through the second resistor R2 and the fifth switch tube R5, thereby forming an open-loop voltage amplifier, that is, the differential current signal output at the drain of the first switch tube Q1 and the second switch tube Q2 is converted into a differential voltage signal due to the existence of the first resistor R1 and the second resistor R2; at the same time, continue to refer to Figure 3 As shown, since the second control signal is also at a high level, the fourth switch tube Q4 and the sixth switch tube Q6 are also turned on, so that the gate and the drain of the first switch tube Q1 are short-circuited, and the gate and the drain of the second switch tube Q2 are short-circuited, so that the above-mentioned voltage amplifier becomes a unity gain amplifier. Therefore, when only the input offset voltage on the latch circuit 120 is considered, the following formula (1) can be obtained:

[0053] VI2=(VI2+VOS2)*A2 (1)

[0054] Wherein, VI2 is the gate voltage difference between the first switch tube Q1 and the second switch tube Q2, that is, VI2=VIP2-VIN2, VIP2 is the gate voltage of the first switch tube Q1, VIN2 is the gate voltage of the second switch tube Q2, VOS2 is the input offset voltage of the first differential input pair tube 121, and A2 is the open-loop gain of the voltage amplifier composed of the first resistor R1, the second resistor R2, the first preset power supply VDD1, the first switch tube Q1, and the second switch tube Q2. After simplifying the above formula (1), the following formula (2) can be obtained:

[0055] VI2=-VOS2*A2 / (1+A2)≈-VOS2 (2)

[0056] It can be seen from the above formula (2) that at this time, the difference between the gate voltages of the first switch tube Q1 and the second switch tube Q2 is equal to the negative input offset voltage of the differential pair tube 121. Since the gate of the first switch tube Q1 is the first differential input terminal VIP2 of the latch circuit and is connected to the second end of the first capacitor C1, the gate voltage of the first switch tube Q1 can be stored on the first capacitor. At the same time, the circuit structure of the second switch tube Q2 is the same as that of the first switch tube Q1, and the input gate voltage of the second switch tube Q2 can also be stored on the second capacitor C2. Therefore, at the end of the offset storage stage, if the input offset voltage on the pre-amplifier circuit 110 is not considered, the voltage difference stored on the first capacitor C1 and the second capacitor C2 is equal to the offset voltage value of the input differential pair tube 121 in the latch circuit 120. Therefore, the second correction unit 133 realizes the function of storing the input offset voltage of the latch circuit 120.

[0057] refer to Figure 3 As shown, when the comparator 100 enters the signal comparison stage, the first control signal and the second control signal are at a low level, so that the third to sixth switch tubes (Q3~Q6) are all turned off. At this time, the above-mentioned unity gain amplifier disappears, but the first capacitor C1 and the second capacitor C2 do not have a charge and discharge loop, and the input offset voltage stored thereon will not change. Therefore, when entering the signal comparison stage, when the pre-amplification circuit inputs a differential voltage to the first differential input pair tube 121 through the first capacitor C1 and the second capacitor C2, the input offset voltage stored on the first capacitor C1 and the second capacitor C2 will offset the input offset voltage on the first switch tube Q1 and the second switch tube Q2, that is, offset the input offset voltage of the latch circuit 120, thereby effectively improving the comparison accuracy of the comparator.

[0058] In some embodiments, reference Figure 4As shown, the pre-amplifier circuit 110 includes a second differential input pair of tubes 111, and the second differential input pair of tubes 111 includes a seventh switch tube Q7 and an eighth switch tube Q8, wherein, in the offset storage stage, the input end of the seventh switch tube Q7 and the input end of the eighth switch tube Q8 are short-circuited by the first correction unit 131 to store the input offset voltage of the pre-amplifier circuit 110 in the storage unit 132.

[0059] Further, the first correction unit 131 includes: a ninth switch tube Q9, a first end of the ninth switch tube Q9 and a second end of the seventh switch tube Q7 are respectively connected to the first differential input end of the pre-amplifier circuit 110, a second end of the ninth switch tube Q9 is connected to the first control signal end K1, and a third end of the ninth switch tube Q9 is connected to the first preset common-mode power supply VCMI; wherein, the second end of the seventh switch tube Q7 serves as the input end of the seventh switch tube Q7, and the first end of the seventh switch tube Q7 is connected to the first differential output end VOP1 of the pre-amplifier circuit 110.

[0060] Furthermore, the first correction unit 131 also includes: a tenth switch tube Q10, the first end of the tenth switch tube Q10 and the second end of the eighth switch tube Q8 are respectively connected to the second differential input end of the pre-amplifier circuit 110, the second end of the tenth switch tube Q10 is connected to the first control signal end K1, and the third end of the tenth switch tube Q10 is connected to the first preset common mode power supply VCMI; wherein the second end of the eighth switch tube Q8 serves as the input end of the eighth switch tube Q8, and the first end of the eighth switch tube Q8 is connected to the second differential output end VON1 of the pre-amplifier circuit 110.

[0061] Furthermore, in the imbalance storage stage, the first control signal provided by the first control signal terminal K1 controls the ninth switch tube Q9 and the tenth switch tube Q10 to be turned on, so as to short-circuit the input end of the seventh switch tube Q7 and the input end of the eighth switch tube Q8.

[0062] Furthermore, the pre-amplifier circuit 110 also includes: a current mirror 112, a first end of the current mirror 112 is connected to the first preset power supply VDD1, a second end of the current mirror 112 is connected to the first end of the seventh switch tube Q7, and a third end of the current mirror 112 is connected to the first end of the eighth switch tube Q8.

[0063] Specifically, the second differential input pair tube 111 and the current mirror 112 are mainly used to realize the pre-amplification function of the input differential comparison signal (the differential comparison signal is a voltage signal), and the specific implementation process is as follows: Figure 4As shown, the seventh switch tube Q7 and the eighth switch tube Q8 can be NMOS tubes. In this case, the gates of the seventh switch tube Q7 and the eighth switch tube Q8 are the first differential input terminal VIP1 and the second differential input terminal VIN1 of the pre-amplifier circuit 110. Since the sources of the seventh switch tube Q7 and the eighth switch tube Q8 are connected to each other and to the equipotential VSS, the conduction degree of the seventh switch tube Q7 and the eighth switch tube Q8 depends only on the voltage of the first differential input terminal VIP1 and the second differential input terminal VIN1. Figure 4 As shown, the current mirror 112 can be composed of four PMOS tubes. The current mirror 112 can output the same stable current to the drains of the seventh switch tube Q7 and the eighth switch tube Q8. Therefore, the conduction degree of the seventh switch tube Q7 and the eighth switch tube Q8 can determine the voltage of the first differential output terminal VOP1 and the second differential output terminal VON1 of the pre-amplifier circuit 110, so that the differential comparison signal can be amplified into a differential voltage. Therefore, through the cooperation of the second differential input pair tube and the current mirror, the pre-amplifier circuit realizes the pre-amplification function of the input differential comparison signal.

[0064] At the same time, the first correction unit 131 is mainly used to correct the input offset voltage of the pre-amplifier circuit 110. In the specific process, the ninth switch tube Q9 and the tenth switch tube Q10 can be NMOS tubes. According to the working process of the pre-amplifier circuit 110, the input offset voltage of the pre-amplifier circuit 110 refers to the input offset voltage of the seventh switch tube Q7 and the eighth switch tube Q8. Therefore, referring to Figure 3 As shown, in the offset voltage storage stage, the first control signal is at a high level, so that the ninth switch tube Q9 and the tenth switch tube Q1 are turned on, and then the input ends of the seventh switch tube Q7 and the eighth switch tube Q8 are simultaneously connected to the first preset common-mode power supply VCMI, so that the first preset common-mode power supply VCMI provides a preset common-mode voltage to the gates of the seventh switch tube Q7 and the eighth switch tube Q8, so that the gates of the seventh switch tube Q7 and the eighth switch tube Q8 are short-circuited. At this time, the output voltage of the pre-amplifier circuit 110 can be expressed as the following formula (3):

[0065] VO1=A1*VOS1 (3)

[0066] Among them, VO1 is the output voltage of the pre-amplifier circuit 110 (referring to the difference between the voltages of the first differential output terminal VOP1 and the second differential output terminal VON1), A1 is the amplification gain of the pre-amplifier circuit 110; VOS1 is the input offset voltage of the seventh switch tube Q7 and the eighth switch tube Q8, which can be stored in the first capacitor C1 and the second capacitor C2. Therefore, when the differential voltage output from the pre-amplifier circuit 110 is transmitted to the first differential input pair tube 121 of the latch circuit 120 through the first capacitor C1 and the second capacitor C2, the first capacitor C1 and the second capacitor C2 can offset the output voltage change caused by the input offset voltage of the seventh switch tube Q7 and the eighth switch tube Q8, thereby realizing the correction function of the input offset voltage of the pre-amplifier circuit, thereby improving the accuracy of the comparator.

[0067] It should be noted that when the offset storage phase is about to end, the reference Figure 3 As shown, the second control signal can be first controlled to become a low level, and then the first control signal can be controlled to become a low level, so that the fourth switch tube Q4 and the sixth switch tube Q6 are turned off before the ninth switch tube Q9 and the tenth switch tube Q10, so as to avoid the charge injection effect from affecting the input offset voltage stored on the first capacitor C1 and the second capacitor C2, thereby optimizing the correction effect of the second correction unit on the input offset voltage of the latch circuit, and further improving the comparison accuracy of the comparator.

[0068] In some embodiments, reference Figure 5a As shown, the comparator 100 further includes an input unit 140, and the input unit 140 includes: an eleventh switch tube Q11 and a twelfth switch tube Q12, wherein a first end of the eleventh switch tube Q11 is connected to a first differential input terminal VIP1 of the pre-amplifier circuit 110, a second end of the eleventh switch tube Q11 is connected to a third control signal terminal K3, and a third end of the eleventh switch tube Q11 is connected to a first differential input terminal VIP of the comparator 100; a first end of the twelfth switch tube Q12 is connected to a second differential input terminal VIN1 of the pre-amplifier circuit 110, and a third end of the eleventh switch tube Q11 is connected to a first differential input terminal VIP of the comparator 100; The second end of the switch tube Q12 is connected to the third control signal terminal K3, and the third end of the twelfth switch tube Q12 is connected to the second differential input terminal VIN of the comparator 100; wherein, through the third control signal provided by the third control signal terminal K3, in the offset storage stage, the eleventh switch tube Q11 and the twelfth switch tube Q12 are controlled to be disconnected; in the signal comparison stage, the eleventh switch tube Q11 and the twelfth switch tube Q12 are controlled to be turned on, so as to input the differential comparison signal of the first differential input terminal VIP and the second differential input terminal VIN of the comparator 100 into the pre-amplification circuit 110 for pre-amplification.

[0069] Specifically, refer to Figure 3 and Figure 5aAs shown, the eleventh switch tube Q11 and the twelfth switch tube Q12 can be NMOS tubes. In the offset storage stage, the third control signal is at a low level, and the eleventh switch tube Q11 and the twelfth switch tube Q12 are disconnected, thereby preventing the external input differential comparison signal from affecting the offset voltage storage of the comparator 100, thereby improving the comparison accuracy of the comparator 100; in the signal comparison stage, the third control signal is at a high level, and the eleventh switch tube Q11 and the twelfth switch tube Q12 are turned on. At this time, the external input differential comparison signal can be input to the pre-amplification circuit 110 through the eleventh switch tube Q11 and the twelfth switch tube Q12 for pre-amplification, so that the comparator 100 can work normally.

[0070] At the same time, at the beginning of the signal comparison stage, due to the existence of the first correction unit 131 and the second correction unit 132, when the second control signal controls the fourth switch tube Q4 and the sixth switch tube Q6 to turn off, the input offset voltages of the pre-amplifier circuit 110 and the latch circuit 120 have been sampled and stored in the first capacitor C1 and the second capacitor C2 at the same time. At this time, according to the above formulas (2) and (3), the following formula (4) can be obtained:

[0071] VI2 total =-VO1+VI2=-A1×VOS1-VOS2 (4)

[0072] Among them, VI2 total is the voltage difference stored on the first capacitor C1 and the second capacitor C2, VO1 is the output voltage of the pre-amplifier circuit 110 (referring to the voltage difference between the first differential output terminal VOP1 and the second differential output terminal VON1), VI2 is the gate voltage difference between the first switch tube Q1 and the second switch tube Q2, A1 is the amplification gain of the pre-amplifier circuit 110, VOS1 is the input offset voltage of the seventh switch tube Q7 and the eighth switch tube Q8, and VOS2 is the input offset voltage of the first differential input pair tube 121. It can be seen from the above formula (4) that when the external input differential comparison signal is transmitted to the output terminal of the first differential input pair tube 121, the first capacitor C1 and the second capacitor C2 can offset the input offset voltage of the pre-amplifier circuit 110 and the latch circuit 120, thereby effectively improving the comparison accuracy of the comparator.

[0073] Optional, reference Figure 5a As shown, the latch circuit 120 also includes: a thirteenth switch tube Q13, the third end of the first switch tube Q1 and the third end of the second switch tube Q2 are respectively connected to the first end of the thirteenth switch tube Q13, the second end of the thirteenth switch tube Q13 is connected to the bias voltage signal terminal VB, and the third end of the thirteenth switch tube Q13 is grounded GND; wherein, the bias voltage signal provided by the bias voltage signal terminal VB controls the thirteenth switch tube Q13 to provide a bias voltage for the first switch tube Q1 and the second switch tube Q2.

[0074] Specifically, refer to Figure 5a As shown, the thirteenth switch tube Q13 can be an NMOS tube, and the voltage value of the bias voltage signal can be preset to adjust the conduction degree of the thirteenth switch tube Q13, thereby providing a suitable source voltage for the first switch tube Q1 and the second switch tube Q2 to ensure that the first switch tube Q1 and the second switch tube Q2 can operate in the amplification area, avoiding the failure of the first switch tube Q1 and the second switch tube Q2 due to excessive or too small gate-source voltage, thereby improving the reliability of the comparator.

[0075] In some embodiments, reference Figure 5a to Figure 5b As shown, the latch circuit 120 also includes: a fourteenth switch tube to a seventeenth switch tube (Q14-Q17), wherein a first end of the fourteenth switch tube Q14 is connected to the first differential output terminal VOP2 of the latch circuit 120, a second end of the fourteenth switch tube Q14 is connected to the fourth control signal terminal K4, and a third end of the fourteenth switch tube Q14 is connected to the first end of the first switch tube Q1; a first end of the fifteenth switch tube Q15 is connected to the second differential output terminal VON2 of the latch circuit 120, a second end of the fifteenth switch tube Q15 is connected to the fourth control signal terminal K4, and a third end of the fifteenth switch tube Q15 is connected to the first end of the second switch tube Q2; a first end of the sixteenth switch tube Q16 is connected to the first differential output terminal VOP2 of the latch circuit 120, and a second end of the sixteenth switch tube Q16 is connected to the fifth control signal terminal K4. The first terminal of the sixteenth switch tube Q17 is connected to the second differential output terminal VON2 of the latch circuit 120, the second terminal of the seventeenth switch tube Q17 is connected to the fifth control signal terminal K5, and the third terminal of the seventeenth switch tube Q17 is connected to the first preset power supply VDD1; wherein, in the signal comparison stage, the fourteenth switch tube Q14, the fifteenth switch tube Q15, the sixteenth switch tube Q16 and the seventeenth switch tube Q17 are controlled to be turned on through the fourth control signal terminal K4 and the fifth control signal provided by the fifth control signal terminal K5, so as to output the pre-amplified differential comparison signal output by the pre-amplifier circuit 110 to the first differential output terminal VOP2 and the second differential output terminal VON2 of the latch circuit 120.

[0076] Further, referring to FIG5 , the latch circuit 120 further includes: an eighteenth switch tube to a twenty-second switch tube (Q18-Q22), wherein a first end of the eighteenth switch tube Q18 is connected to a first differential output terminal VOP2 of the latch circuit 120, a second end of the eighteenth switch tube Q18 is connected to a second differential output terminal VON2 of the latch circuit 120, and a third end of the eighteenth switch tube Q18 is connected to a first preset power supply VDD1; a first end of a nineteenth switch tube Q19 is connected to the first differential output terminal VOP2 of the latch circuit 120, a second end of the nineteenth switch tube Q19 is connected to the second differential output terminal VON2 of the latch circuit 120; a first end of a twentieth switch tube Q20 is connected to the second differential output terminal VON2 of the latch circuit 120, a second end of the twentieth switch tube Q20 is connected to the first differential output terminal VOP2 of the latch circuit 120, and a third end of the twentieth switch tube Q20 is connected to the first preset power supply VDD1; a preset power supply VDD1; a first end of the twenty-first switch tube Q21 is connected to the second differential output terminal VON2 of the latch circuit 120, and a second end of the twenty-first switch tube Q21 is connected to the first differential output terminal VOP2 of the latch circuit 120; a third end of the nineteenth switch tube Q19 and a third end of the twenty-first switch tube Q21 are connected to the first end of the twenty-second switch tube Q22, a second end of the twenty-second switch tube Q22 is connected to the fifth control signal terminal K5, and a third end of the twenty-second switch tube Q22 is grounded GND; wherein, in the signal comparison stage, the fourteenth switch tube Q14, the fifteenth switch tube Q15, the sixteenth switch tube Q16 and the seventeenth switch tube Q17 are controlled to be turned off, and the twenty-second switch tube Q22 is controlled to be turned on, so as to output the comparison result of the differential input signal.

[0077] Specifically, the fourteenth switch tube Q14 to the twenty-second switch tube Q22 are mainly used to implement the differential comparison and latching functions of the latch circuit 120. The specific process is as follows: Figure 5a and Figure 5b As shown, the fourteenth switch tube Q14, the fifteenth switch tube Q15, the nineteenth switch tube Q19, the twenty-first switch tube Q21 and the twenty-second switch tube Q22 may be NMOS tubes, and the sixteenth switch tube Q16, the seventeenth switch tube Q18, the eighteenth switch tube Q18 and the twentieth switch tube Q20 may be PMOS tubes. Figure 3As shown, the signal comparison stage can be divided into a tracking stage and a decision stage. In the tracking stage, the fourth control signal is at a high level and the fifth control signal is at a low level. At this time, the latch circuit 120 is in a reset state. The fourteenth switch tube Q14 and the fifteenth switch tube Q15 are turned on under the control of the fourth control signal. The sixteenth switch tube Q16 and the seventeenth switch tube Q17 become partially turned on under the control of the fifth control signal to reset the eighteenth switch tube Q18 to the twenty-first switch tube Q21. At the same time, the sixteenth switch tube Q16 and the seventeenth switch tube Q17 can be regarded as switch resistors. The differential current output by the first differential input pair tube 121 is converted into a corresponding voltage difference and injected into the first differential output terminal VOP2 and the second differential output terminal VON2 of the latch circuit 120. The voltage difference can change according to the change of the differential comparison signal of the external input comparator 100, thereby realizing the signal tracking function. In addition, the -A1*VOS1-VOS2 stored on the first capacitor C1 and the second capacitor C2 in the signal chain offsets the input offset voltage of the pre-amplifier circuit 110 and the first differential input pair tube 121, so the accuracy of the signal tracking function is relatively high. In the judgment stage, the fourth control signal becomes a low level, the fourteenth switch tube Q14 and the fifteenth switch tube Q15 are disconnected, and the fifth control signal becomes a high level. At this time, the sixteenth switch tube Q16 and the seventeenth switch tube Q17 are turned off, and the eighteenth switch tube Q18 to the twenty-first switch tube Q21 become a cross-coupled amplifier composed of two inverters, so that the voltage at the higher end of the output voltage of the first differential output terminal VOP2 and the second differential output terminal VON2 of the latch circuit 120 can gradually increase the voltage of the first preset power supply VDD1, while the voltage at the lower end gradually decreases to 0. The specific principle of the cross-coupled amplifier is not expanded here. At this time, the output voltage of the first differential output terminal VOP2 and the second differential output terminal VON2 of the latch circuit 120 is the comparison result of the comparator 100 on the differential comparison signal, thereby realizing the latch circuit latching and output of the comparison result.

[0078] It should be noted that the twenty-second switch tube Q22 is mainly used to provide a suitable source voltage for the nineteenth switch tube Q19 and the twenty-first switch tube Q21 under the control of the fifth control signal to ensure the normal operation of the nineteenth switch tube Q19 and the twenty-first switch tube Q21. The specific principle is similar to that of the aforementioned thirteenth switch tube Q13, and will not be elaborated here.

[0079] In some embodiments, reference Figure 5aAs shown, the pre-amplifier circuit 110 also includes: a twenty-third switch tube Q23, the third end of the seventh switch tube Q7 and the third end of the eighth switch tube Q8 are respectively connected to the first end of the twenty-third switch tube Q23, the second end of the twenty-third switch tube Q23 is connected to the bias voltage signal end VB, and the third end of the twenty-third switch tube Q23 is grounded GND; wherein, in the offset storage stage, the bias voltage signal provided by the bias voltage signal end VB controls the twenty-third switch tube Q23 to provide a bias voltage for the seventh switch tube Q7 and the eighth switch tube Q8.

[0080] Specifically, refer to Figure 5a As shown, the twenty-third switch tube Q23 is mainly used to provide a suitable bias voltage to the seventh switch tube Q7 and the eighth switch tube Q8 to ensure that the first switch tube Q1 and the second switch tube Q2 can operate in the amplification area. The specific principle is similar to the aforementioned thirteenth switch tube Q13 and will not be repeated here.

[0081] It should be noted that the first switch tube Q1 to the twenty-third switch tube Q23 in the above embodiments can all be different types of switch tubes, including MOS tubes, IGBT modules, etc. The use of PMOS tubes or NMOS tubes as the first switch tubes Q1 to the twenty-third switch tubes Q23 is exemplary and not a limitation of the present invention.

[0082] In summary, according to the comparator of the embodiment of the present invention, by setting a correction circuit between the pre-amplifier circuit and the latch circuit, in the offset storage stage, the first correction unit in the correction circuit stores the input offset voltage of the pre-amplifier circuit in the storage unit, and at the same time, the second correction unit in the correction circuit stores the input offset voltage of the latch circuit in the storage voltage, so that when the comparator is in the signal comparison stage, the voltage in the storage unit can simultaneously realize the offset voltage correction function for the pre-amplifier circuit and the latch circuit, effectively improving the comparison accuracy of the comparator, broadening the application scenarios of the comparator, and thus improving the applicability of the comparator.

[0083] Corresponding to the above embodiment, the embodiment of the present invention further provides a chip, referring to Figure 6 As shown, the chip 1000 includes the aforementioned comparator 100 .

[0084] The chip according to the embodiment of the present invention can realize a high-precision comparison function through the aforementioned comparator 100, thereby improving the comparison performance of the chip.

[0085] Corresponding to the above embodiment, the embodiment of the present invention further provides an electronic device, referring to Figure 7a - Figure 7b As shown, the electronic device 10000 includes the aforementioned comparator 100 , or the aforementioned chip 1000 .

[0086] The electronic device according to the embodiment of the present invention can realize a high-precision comparison function through the aforementioned comparator, thereby improving the comparison performance of the electronic device.

[0087] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or otherwise processing in a suitable manner if necessary, and then stored in a computer memory.

[0088] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0089] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0090] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0091] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0092] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A comparator, characterized in that: include: A preamplifier circuit, a latch circuit and a correction circuit, wherein the correction circuit comprises a first correction unit, a storage unit and a second correction unit, wherein the first correction unit is connected to the differential input end of the preamplifier circuit, the differential output end of the preamplifier circuit is connected to the differential input end of the latch circuit through the storage unit, and the second correction unit is connected to the differential input end of the latch circuit, wherein: In the offset storage stage, the input offset voltage of the pre-amplifier circuit is stored in the storage unit through the first correction unit, and the input offset voltage of the latch circuit is stored in the storage unit through the second correction unit, so that in the signal comparison stage, the input offset voltage of the pre-amplifier circuit and the input offset voltage of the latch circuit are corrected by the voltage of the storage unit; The latch circuit includes a first differential input pair of tubes, which include a first switch tube and a second switch tube. In the offset storage stage, the input and output ends of the first switch tube are short-circuited, and the input and output ends of the second switch tube are short-circuited through the second correction unit to store the input offset voltage of the latch circuit in the storage unit.

2. The comparator according to claim 1, characterized in that: The second correction unit comprises: A first resistor, one end of which is connected to a first preset power source; a third switch tube, wherein a first end of the third switch tube is connected to the other end of the first resistor, and a second end of the third switch tube is connected to the first control signal end; a fourth switch tube, wherein a first end of the fourth switch tube and a third end of the third switch tube are respectively connected to the first end of the first switch tube, a second end of the fourth switch tube is connected to the second control signal end, and a third end of the fourth switch tube and a second end of the first switch tube are respectively connected to the first differential input end of the latch circuit; The first end of the first switch tube serves as the output end of the first switch tube, and the second end of the first switch tube serves as the input end of the first switch tube.

3. The comparator according to claim 2, characterized in that: The second correction unit further includes: a second resistor, one end of which is connected to the first preset power source; a fifth switch tube, wherein a first end of the fifth switch tube is connected to the other end of the second resistor, and a second end of the fifth switch tube is connected to the first control signal end; a sixth switch tube, wherein a first end of the sixth switch tube and a third end of the fifth switch tube are respectively connected to a first end of the second switch tube, a second end of the sixth switch tube is connected to the second control signal end, and a third end of the sixth switch tube and a second end of the second switch tube are respectively connected to a second differential input end of the latch circuit; The first end of the second switch tube serves as the output end of the second switch tube, and the second end of the second switch tube serves as the input end of the second switch tube.

4. The comparator according to claim 3, characterized in that: In the offset storage stage, the third switch tube, the fourth switch tube, the fifth switch tube and the sixth switch tube are controlled to be turned on through the first control signal provided by the first control signal terminal and the second control signal provided by the second control signal terminal, so as to short-circuit the input and output terminals of the first switch tube and the input and output terminals of the second switch tube.

5. The comparator according to claim 1, characterized in that: The pre-amplifier circuit includes a second differential input pair of tubes, which include a seventh switch tube and an eighth switch tube. In the offset storage stage, the input end of the seventh switch tube and the input end of the eighth switch tube are short-circuited by the first correction unit to store the input offset voltage of the pre-amplifier circuit in the storage unit.

6. The comparator according to claim 5, characterized in that: The first correction unit comprises: a ninth switch tube, wherein a first end of the ninth switch tube and a second end of the seventh switch tube are respectively connected to the first differential input end of the pre-amplifier circuit, a second end of the ninth switch tube is connected to the first control signal end, and a third end of the ninth switch tube is connected to the first preset common mode power supply; The second end of the seventh switch tube serves as the input end of the seventh switch tube, and the first end of the seventh switch tube is connected to the first differential output end of the pre-amplifier circuit.

7. The comparator according to claim 6, characterized in that: The first correction unit further includes: a tenth switch tube, wherein a first end of the tenth switch tube and a second end of the eighth switch tube are respectively connected to the second differential input end of the pre-amplifier circuit, a second end of the tenth switch tube is connected to the first control signal end, and a third end of the tenth switch tube is connected to the first preset common-mode power supply; The second end of the eighth switch tube serves as the input end of the eighth switch tube, and the first end of the eighth switch tube is connected to the second differential output end of the pre-amplifier circuit.

8. The comparator according to claim 7, characterized in that: In the offset storage stage, the ninth switch tube and the tenth switch tube are controlled to be turned on through the first control signal provided by the first control signal terminal, so as to short-circuit the input terminal of the seventh switch tube and the input terminal of the eighth switch tube.

9. The comparator according to claim 1, characterized in that: The comparator further includes an input unit, wherein the input unit includes: an eleventh switch tube, wherein a first end of the eleventh switch tube is connected to the first differential input end of the pre-amplifier circuit, a second end of the eleventh switch tube is connected to the third control signal end, and a third end of the eleventh switch tube is connected to the first differential input end of the comparator; a twelfth switch tube, wherein a first end of the twelfth switch tube is connected to the second differential input end of the pre-amplifier circuit, a second end of the twelfth switch tube is connected to the third control signal end, and a third end of the twelfth switch tube is connected to the second differential input end of the comparator; Among them, through the third control signal provided by the third control signal terminal, in the offset storage stage, the eleventh switch tube and the twelfth switch tube are controlled to be disconnected; in the signal comparison stage, the eleventh switch tube and the twelfth switch tube are controlled to be turned on, so as to input the differential comparison signal of the first differential input terminal and the second differential input terminal of the comparator into the pre-amplification circuit for pre-amplification.

10. The comparator according to claim 1, characterized in that: The storage unit comprises: a first capacitor, one end of the first capacitor being connected to the first differential output end of the pre-amplifier circuit, and the other end of the first capacitor being connected to the first differential input end of the latch circuit; A second capacitor, one end of the second capacitor is connected to the second differential output end of the pre-amplifier circuit, and the other end of the second capacitor is connected to the second differential input end of the latch circuit.

11. The comparator according to claim 3, characterized in that: The latch circuit further comprises: a thirteenth switch tube, wherein the third end of the first switch tube and the third end of the second switch tube are respectively connected to the first end of the thirteenth switch tube, the second end of the thirteenth switch tube is connected to the bias voltage signal end, and the third end of the thirteenth switch tube is grounded; The thirteenth switch tube is controlled to provide a bias voltage for the first switch tube and the second switch tube through the bias voltage signal provided by the bias voltage signal terminal.

12. The comparator according to claim 3, characterized in that: The latch circuit further comprises: a fourteenth switch tube, wherein a first end of the fourteenth switch tube is connected to the first differential output end of the latch circuit, a second end of the fourteenth switch tube is connected to the fourth control signal end, and a third end of the fourteenth switch tube is connected to the first end of the first switch tube; a fifteenth switch tube, wherein a first end of the fifteenth switch tube is connected to the second differential output end of the latch circuit, a second end of the fifteenth switch tube is connected to the fourth control signal end, and a third end of the fifteenth switch tube is connected to the first end of the second switch tube; a sixteenth switch tube, wherein a first end of the sixteenth switch tube is connected to the first differential output end of the latch circuit, a second end of the sixteenth switch tube is connected to the fifth control signal end, and a third end of the sixteenth switch tube is connected to the first preset power supply; a seventeenth switch tube, wherein a first end of the seventeenth switch tube is connected to the second differential output end of the latch circuit, a second end of the seventeenth switch tube is connected to the fifth control signal end, and a third end of the seventeenth switch tube is connected to the first preset power supply; Among them, in the signal comparison stage, the fourteenth switch tube, the fifteenth switch tube, the sixteenth switch tube and the seventeenth switch tube are controlled to be turned on through the fourth control signal provided by the fourth control signal terminal and the fifth control signal provided by the fifth control signal terminal, so as to output the pre-amplified differential comparison signal output by the pre-amplifier circuit to the first differential output terminal and the second differential output terminal of the latch circuit.

13. The comparator according to claim 12, characterized in that: The latch circuit further comprises: an eighteenth switch tube, wherein a first end of the eighteenth switch tube is connected to the first differential output end of the latch circuit, a second end of the eighteenth switch tube is connected to the second differential output end of the latch circuit, and a third end of the eighteenth switch tube is connected to the first preset power supply; a nineteenth switch tube, wherein a first end of the nineteenth switch tube is connected to the first differential output end of the latch circuit, and a second end of the nineteenth switch tube is connected to the second differential output end of the latch circuit; a twentieth switch tube, wherein a first end of the twentieth switch tube is connected to the second differential output end of the latch circuit, a second end of the twentieth switch tube is connected to the first differential output end of the latch circuit, and a third end of the twentieth switch tube is connected to the first preset power supply; a twenty-first switch tube, wherein a first end of the twenty-first switch tube is connected to the second differential output end of the latch circuit, and a second end of the twenty-first switch tube is connected to the first differential output end of the latch circuit; a twenty-second switch tube, a third end of the nineteenth switch tube and a third end of the twenty-first switch tube are connected to a first end of the twenty-second switch tube, a second end of the twenty-second switch tube is connected to the fifth control signal end, and a third end of the twenty-second switch tube is grounded; Among them, in the signal comparison stage, the fourteenth switch tube, the fifteenth switch tube, the sixteenth switch tube and the seventeenth switch tube are controlled to be turned off, and the twenty-second switch tube is controlled to be turned on, so as to output the comparison result of the differential input signal.

14. The comparator according to claim 5, characterized in that The pre-amplification circuit also includes: a twenty-third switch tube, wherein the third end of the seventh switch tube and the third end of the eighth switch tube are respectively connected to the first end of the twenty-third switch tube, the second end of the twenty-third switch tube is connected to the bias voltage signal end, and the third end of the twenty-third switch tube is grounded; The bias voltage signal provided by the bias voltage signal terminal controls the twenty-third switch tube to provide a bias voltage for the seventh switch tube and the eighth switch tube.

15. The comparator according to claim 5, characterized in that The pre-amplification circuit also includes: A current mirror, wherein a first end of the current mirror is connected to a first preset power supply, a second end of the current mirror is connected to a first end of the seventh switch tube, and a third end of the current mirror is connected to a first end of the eighth switch tube.

16. A chip, characterized in that: Comprising a comparator according to any one of claims 1-15.

17. An electronic device, characterized in that: Comprising the comparator according to any one of claims 1-15, or the chip according to claim 16.

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