Pcie link fault repairing method and device, electronic equipment and storage medium

Abstract

The application provides a PCIE link fault repairing method and device, electronic equipment and a storage medium. An initial PCIE link is acquired, target data is transmitted through link training on the initial PCIE link, and a data state corresponding to the target data is obtained. Whether the initial PCIE link has target data abnormality is determined through the data state, a pending PCIE link having target data abnormality is obtained, and the PCIE switch is controlled to enter a waiting valid data state in the case that the pending PCIE link has target data abnormality. Then, whether the PCIE switch receives valid data is determined, and the pending PCIE link in which the PCIE switch does not receive valid data is confirmed as an abnormal PCIE link. Finally, for the abnormal PCIE link, a recovery mechanism is started to jump out of the waiting valid data state and reset, and a target PCIE link opposite to the abnormal PCIE link after the reset is obtained.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to a PCIE link fault repair method, a PCIE link fault repair device, an electronic device and a computer readable storage medium. BACKGROUND

[0002] PCIE (peripheral component interconnect express) is a high-speed serial computer expansion bus standard, and PCIE devices are essential components in servers. The performance, calculation and function of the server are related to the PCIE device, and the calculation, storage and network of the server are involved. In the server startup process, the PCIE device establishes a connection with the CPU, and in the server running process, the PCIE needs to maintain a stable connection state, so that the data can be normally transmitted. In order to ensure the stability of the PCIE link, a series of connection training and state machine rules are defined in the PCIE protocol, and there is also a PCIE error reporting method. In a complex PCIE link, each device processes PCIE data in accordance with the PCIE protocol, but due to the algorithm and processing mechanism of each device, the device may appear in a situation not defined in the PCIE protocol or in a situation violating the PCIE protocol when connected. Especially in the link with a PCIE signal equalization enhancement chip, the CPU port and the terminal device are not directly connected, but the CPU, the signal equalization enhancement chip and the PCIE device and more than three devices negotiate to process data. When the situation violating the PCIE protocol appears, due to the abnormal processing mechanism, the signal equalization enhancement chip may appear in an abnormal state, causing the PCIE link to fail to connect. SUMMARY

[0003] The embodiments of the present application provide a PCIE link fault repair method, device, electronic device and computer readable storage medium to solve the problem of PCIE link connection failure caused by abnormal processing mechanism of the signal equalization enhancement chip.

[0004] The embodiments of the present application disclose a PCIE link fault repair method applied to a server, wherein the server comprises a signal equalization enhancement chip, a central processing unit and a PCIE switch, and the method comprises the following steps:

[0005] An initial PCIE link is obtained, target data is transmitted by link training on the initial PCIE link, and the data state corresponding to the target data is obtained, wherein the transmission comprises direct transmission and indirect transmission;

[0006] determining whether the initial PCIE link has target data abnormality according to the data state, obtaining a pending PCIE link having target data abnormality, and controlling the PCIE switch to enter a valid data waiting state when the pending PCIE link has target data abnormality.

[0007] determining whether the PCIE switch receives valid data, and confirming a pending PCIE link in which the PCIE switch does not receive the valid data as an abnormal PCIE link;

[0008] starting a recovery mechanism to jump out of the valid data waiting state and reset for the abnormal PCIE link, and obtaining a target PCIE link opposite to the abnormal PCIE link after the reset.

[0009] Optionally, the obtaining of the initial PCIE link, the transmission of target data through link training on the initial PCIE link, and the obtaining of a data state corresponding to the target data include:

[0010] controlling the initial PCIE link to perform link training in the order of detection, polling, configuration, and link, and obtaining a data state corresponding to target data transmitted after the link training of the initial PCIE link.

[0011] Optionally, the determining whether the initial PCIE link has target data abnormality according to the data state, the obtaining of a pending PCIE link having target data abnormality, and the controlling of the PCIE switch to enter a valid data waiting state when the pending PCIE link has target data abnormality include:

[0012] confirming the initial PCIE link in which the directly transmitted target data is in an unlocked state as the pending PCIE link having target data abnormality, and controlling the PCIE switch to enter the valid data waiting state;

[0013] confirming the initial PCIE link in which the target data having a time difference value not in a preset interval as the pending PCIE link having target data abnormality, and controlling the PCIE switch to enter the valid data waiting state.

[0014] Optionally, the confirming the initial PCIE link in which the directly transmitted target data is in an unlocked state as the pending PCIE link having target data abnormality, and the controlling of the PCIE switch to enter the valid data waiting state include:

[0015] If the target data is in a locked state, it is determined that the initial PCIE link does not have target data abnormality;

[0016] If the target data is in an unlocked state, it is determined that the initial PCIE link has target data abnormality, the initial PCIE link having target data abnormality is confirmed as a pending PCIE link, and the PCIE switch is controlled to enter a valid data waiting state.

[0017] Optionally, the initial PCIE link having target data abnormality is confirmed as a pending PCIE link by determining whether the time difference between the indirectly transmitted target data is within a preset interval, and the PCIE switch is controlled to enter a valid data waiting state, including:

[0018] If the time difference between the target data transmitted by the PCIE switch is 0, it is determined that the PCIE link does not have target data abnormality.

[0019] If the time difference between the target data transmitted by the PCIE switch is not 0, it is determined that the PCIE link has target data abnormality, the initial PCIE link having data abnormality is confirmed as a pending PCIE link, and the PCIE switch is controlled to enter a valid data waiting state.

[0020] Optionally, the determination of whether the PCIE switch receives valid data includes confirming the pending PCIE link in which the PCIE switch does not receive the valid data as an abnormal PCIE link.

[0021] For the valid data waiting state, the state of the PCIE switch is acquired after timing 24 ms.

[0022] If the PCIE switch receives valid data, the pending PCIE link in which the PCIE switch receives the valid data is not an abnormal PCIE link.

[0023] If the PCIE switch does not receive valid data, the pending PCIE link in which the PCIE switch does not receive the valid data is confirmed as an abnormal PCIE link.

[0024] Optionally, if the PCIE switch does not receive valid data, the pending PCIE link in which the PCIE switch does not receive the valid data is confirmed as an abnormal PCIE link, including:

[0025] For the abnormal PCIE link, the central processor and the PCIE switch not receiving the valid data enter a polling test state.

[0026] The application further discloses a PCIE link fault repairing device.

[0027] The transmission data acquisition module is configured to acquire an initial PCIE link, transmit target data by performing link training on the initial PCIE link, and obtain a data state corresponding to the target data, wherein the transmission comprises direct transmission and indirect transmission.

[0028] The abnormal data judgment module is configured to judge whether the initial PCIE link has target data abnormality according to the data state, obtain a pending PCIE link having target data abnormality, and control the PCIE switch to enter a waiting valid data state when the pending PCIE link has target data abnormality.

[0029] The abnormal link judgment module is configured to judge whether the PCIE switch receives valid data, and confirm a pending PCIE link in which the PCIE switch does not receive the valid data as an abnormal PCIE link.

[0030] The abnormal link reset module is configured to start a recovery mechanism to jump out of the waiting valid data state and reset the abnormal PCIE link, and obtain a target PCIE link opposite to the abnormal PCIE link after the reset.

[0031] Optionally, the transmission data acquisition module is specifically configured to:

[0032] Control the initial PCIE link to perform link training in the order of detection, polling, configuration and link, and obtain a data state corresponding to target data transmitted by the initial PCIE link after the link training.

[0033] Optionally, the abnormal data judgment module is specifically configured to:

[0034] Judge whether the target data of the direct transmission is in a locked state, confirm the initial PCIE link in which the target data is in an unlocked state as the pending PCIE link having target data abnormality, and control the PCIE switch to enter the waiting valid data state.

[0035] Judge whether a time difference between the target data of the indirect transmission is within a preset interval, confirm the initial PCIE link in which the target data is not within the preset interval as the pending PCIE link having target data abnormality, and control the PCIE switch to enter the waiting valid data state.

[0036] Optionally, the abnormal data judgment module is specifically configured to:

[0037] If the target data is in a locked state, it is determined that the initial PCIE link does not have target data exception.

[0038] If the target data is in an unlocked state, it is determined that the initial PCIE link has target data exception, the initial PCIE link with target data exception is confirmed as a pending PCIE link, and the PCIE switch is controlled to enter a valid data waiting state.

[0039] Optionally, the abnormal data judgment module is specifically configured to:

[0040] If the time difference between the target data transmitted through the PCIE switch is 0, it is determined that the PCIE link does not have target data exception.

[0041] If the time difference between the target data transmitted through the PCIE switch is not 0, it is determined that the PCIE link has target data exception, the initial PCIE link with data exception is confirmed as a pending PCIE link, and the PCIE switch is controlled to enter a valid data waiting state.

[0042] Optionally, the abnormal link judgment module is specifically configured to:

[0043] For the valid data waiting state, the state of the PCIE switch is acquired after 24 ms of timing.

[0044] If the PCIE switch receives valid data, the pending PCIE link where the PCIE switch receiving the valid data is not an abnormal PCIE link.

[0045] If the PCIE switch does not receive valid data, the pending PCIE link where the PCIE switch not receiving the valid data is confirmed as an abnormal PCIE link.

[0046] Optionally, the abnormal link judgment module is specifically configured to:

[0047] For the abnormal PCIE link, the central processor and the PCIE switch not receiving the valid data enter a polling test state.

[0048] Embodiments of the application also disclose an electronic device, characterized by comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory complete communication with each other through the communication bus.

[0049] The memory is used to store a computer program.

[0050] The processor is used for executing the program stored on the memory, and the method is realized.

[0051] The embodiment of the application further discloses a computer readable storage medium, which stores instructions, and the instructions make the processor execute the method when executed by one or more processors.

[0052] The embodiment of the application has the following advantages:

[0053] In the embodiment of the application, for PCIE link fault repair, the initial PCIE link is acquired, target data is transmitted through link training on the initial PCIE link, and the data state corresponding to the target data is obtained; then whether the initial PCIE link has target data abnormality is judged through the data state, the pending PCIE link with target data abnormality is obtained, and the PCIE switch is controlled to enter the waiting valid data state in the case that the pending PCIE link has target data abnormality; whether the PCIE switch receives valid data is judged, the pending PCIE link in which the PCIE switch does not receive the valid data is confirmed as an abnormal PCIE link; for the abnormal PCIE link, the recovery mechanism is started to jump out of the waiting valid data state and reset, the target PCIE link opposite to the abnormal PCIE link after reset is obtained, and the PCIE fault link is actively repaired, thereby solving the problem that the signal equalization enhancement chip is in an abnormal state due to the abnormality of the processing mechanism when the phenomenon of violating the PCIE protocol occurs, and the PCIE link connection fails. BRIEF DESCRIPTION OF DRAWINGS

[0054] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed in the embodiments or the prior art description. Obviously, the drawings in the following description only show some embodiments of the application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0055] Figure 1 It is a step flow chart of a PCIE link fault repair method provided in the embodiment of the application.

[0056] Figure 2 It is a structural block diagram of a PCIE link fault repair device provided in the embodiment of the application.

[0057] Figure 3 It is a topology diagram of a hardware device provided in the embodiment of the application.

[0058] Figure 4is an execution flow diagram of a PCIE link fault repair method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0059] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0060] PCIE is a high-speed serial computer expansion bus standard, and PCIE devices are essential components in a server. The performance, calculation, function, etc. of the server are related to the PCIE devices, and the calculation, storage, network, etc. of the server are involved. In the server startup process, the PCIE device establishes a connection with the CPU. In the server running process, the PCIE device needs to maintain a stable connection state, and data can be normally transmitted. In order to ensure the stability of the PCIE link, a series of connection training and state machine rules are defined in the PCIE protocol, and a PCIE error reporting method is also defined. In a complex PCIE link, each device processes PCIE data in a manner complying with the PCIE protocol. However, since each device has its own algorithm and processing mechanism, when the devices are connected, undefined situations in the PCIE protocol or phenomena contrary to the PCIE protocol may occur. Especially in the link with a PCIE signal equalization enhancement chip, the CPU port and the terminal device are not directly connected, but the CPU, the signal equalization enhancement chip, the PCIE device, and more than three devices negotiate to process data. When the phenomenon contrary to the PCIE protocol occurs, due to the abnormal processing mechanism, the signal equalization enhancement chip may be in an abnormal state, causing the PCIE link to fail to connect.

[0061] To this end, the application provides a PCIE link fault repair method and device, electronic equipment and a storage medium, applied to the technical field of computers, specifically comprising the following steps: obtaining an initial PCIE link, performing link training transmission of target data on the initial PCIE link, and obtaining the data state corresponding to the target data; then determining whether the initial PCIE link has target data abnormality through the data state, obtaining a pending PCIE link having target data abnormality, and controlling the PCIE switch to enter a waiting valid data state in the case that the pending PCIE link has target data abnormality; determining whether the PCIE switch receives valid data, and confirming the pending PCIE link in which the PCIE switch does not receive the valid data as an abnormal PCIE link; finally, starting a recovery mechanism to jump out of the waiting valid data state and reset for the abnormal PCIE link, obtaining a target PCIE link opposite to the abnormal PCIE link after resetting, and actively repairing the PCIE fault link, thereby solving the problem of PCIE link connection failure caused by the abnormal state of a signal equalization enhancement chip due to the abnormality of a processing mechanism when the phenomenon of violating the PCIE protocol occurs.

[0062] Referring to Figure 1 , a step flowchart of a PCIE link fault repair method provided in the embodiment of the application is shown, which can specifically comprise the following steps:

[0063] Step 101, obtaining an initial PCIE link, performing link training transmission of target data on the initial PCIE link, and obtaining the data state corresponding to the target data, wherein the transmission comprises direct transmission and indirect transmission;

[0064] In an optional embodiment, the initial PCIE link is controlled to perform link training in the order of detection, polling, configuration and linking, and the data state corresponding to the target data transmitted after the initial PCIE link performs link training is obtained.

[0065] The model structure of PCIE is application layer, transaction layer, data link layer and physical layer from top to bottom. The link training of PCIE link refers to the process of initializing the physical layer of PCIE link, port configuration information, sending and receiving module and the state of related link, understanding the topology structure of the peer of PCIE link, and realizing the data communication of the devices at both ends of PCIE link. The hardware logic of link training depends on the physical layer to realize. The whole process is completed by the link training state machine and does not need the participation of other layers. The goal of link training is bit lock, symbol lock, block lock, link width determination, lane reversal, polarity inversion, data rate determination and lane-to-lane de-skew. Among them, bit lock refers to that PCIE bus needs to use clock for synchronization when transmitting data, but the clock signal is not provided in PCIE link, so the receiving end needs to extract the receiving clock from the data packet of the sending end during link training. Symbol lock refers to that in the link training process, PCIE link first needs to determine the COM character, which marks the start of link training or the start of retraining. Link width refers to that the link bandwidth provided by a PCIE bus includes x1, x2, x4 and x8, but the devices connected on the bus do not completely use these links. For example, an x4 device may be connected to an x8 link, so the actual link state must be notified to the peer during link training. Lane reversal refers to that the serial lanes used by the devices at both ends of PCIE link can be connected in reverse order. Link data rate refers to that the initial link training and initialization of link are based on 2.5G T / S, that is, GEN1 speed. If both ends of the link support higher speed, the link will be automatically retrained to a higher speed. Lane alignment refers to that the serial lanes on the link may not arrive at the same time, some may arrive early and some may arrive late, so the link needs to be adjusted and compensated.

[0066] When PCIE performs link training, some special character sequences need to be sent, which are also called physical layer packet (PLP). These character sequences mainly include: TS1 and TS2 sequences, wherein the TS1 (training sequence 1) sequence is mainly used for detecting the configuration information of the PCIE link, and the TS2 (training sequence 2) sequence is used for confirming the detection result of the TS1 sequence; the Idle sequence is used for sending the EIOS sequence to the opposite end before the sending end enters the Electrical Idle; the FTS (Fast training sequence) sequence is composed of 1 COM character and 3 FTS characters, and the main purpose is to make the receiving logic reacquire the byte lock or character lock; the SKIP sequence is composed of 1 COM and 3 SKP characters, and is used for clock compensation.

[0067] The link training state machine includes 11 states: Detect, Polling, Configuration, Recovery, L0, L0s, L1, L2, Hot Reset, Loopback, and Disable. The 11 states can also be divided into 5 categories: Training States, Re-Training State, PowerMgt States, ASPM States, and Other States.

[0068] Among them, the link training state transition process is: Detect->Polling->Configuration->L0, Detect is the initial state of the physical layer, is used only at Gen1 2.5GT / s rate, or is converted from the data link layer, or after reset, or from other states (such as Disable, Polling, Configuration, Recovery, etc.), Detect state is the beginning of PCIE link training, because in this state, the sending end TX needs to detect whether the receiving end RX exists and can work normally, and only if the detection is normal, can it enter other states, so Detect can perform detection work, Detect state mainly includes two sub-states: Detect-Quiet and Detect-Active.

[0069] The purpose of Polling state is to "speak the same language" so as to realize barrier-free communication. After entering this state, TS1, TS2 and OS sequences are sent between TX and RX to determine byte lock, character lock and solve the problem of channel polarity reversal. Byte lock refers to the process of locking TX clock frequency by RX PLL during byte transmission. Character lock refers to the process of distinguishing a valid 10-bit character by RX serial-parallel converter. Polling state mainly includes three sub-states: Polling-Active, Polling-Configuration and Polling-Compliance. Polling-Active is the state entered by the link after exiting Detect. In this state, byte lock or character lock is realized by RX receiving TS1 sequence. TX needs to send at least 1024 TS1 sequences in all channels. Since TX and RX do not exit Detect state at the same time, TS1 sequence communication may not be synchronized. At this time, 1024 TS1 sequences (16 symbols) need to be sent in Gen1 (2.5 GT / s), Symbol time = 4 ns (10b / 2.5 Gb / s), and at least 64 us (1024*16*4 ns) are needed. Polling-Configuration refers to the case that TX sends at least 1024 TS1 and RX continuously receives 8 TS1 or TS2. Link / Lane area in TS1 and TS2 is filled by PAD. When TX stops sending TS1 sequence and starts sending TS2 sequence, Link / Lane area is still filled by PAD. This process also solves the problem of polarity reversal and prepares for entering the next state. Polling-Compliance is used to test whether the sending end and device connection meet the requirements by sending different models.

[0070] The work content of Configuration state is to determine the number of channels by sending TS1 and TS2. After confirming that there is no exception, the next state is prepared to enter.

[0071] L0 is the power state in which PCIE link can work normally. When entering this state, PCIE link works normally. This state can transmit TLP, DLLP and other messages. L0s / L1 / L2 are low power management states.

[0072] When the PCIE link needs to be retrained, the Recovery state is entered, the Recovery state including: the PCIE link signal discovery data is abnormal, the byte lock and the character lock need to be adjusted; the L0s or L1 low-power supply state is exited; the rate is 2.5GT / s when entering the L0 state for the first time, but the rate needs to be adjusted to 5.0GT / s or 8.0GT / s.

[0073] The Hot Reset is a reset of a device through software when an error occurs in the device, the Hot Reset being triggered through setting a Secondary Bus Reset in a register, after the Hot Reset is triggered, the link training state machine entering the Recovery and Hot Reset states, and then entering the Detect state, and the PCIE link starting to be retrained.

[0074] In step 102, whether the initial PCIE link exists target data abnormality is judged through the data state, an initial PCIE link existing target data abnormality is obtained as a pending PCIE link, and in the case that the pending PCIE link exists target data abnormality, the PCIE switch is controlled to enter a valid data waiting state.

[0075] In an optional embodiment, whether the directly transmitted target data is in a lock state is judged, the initial PCIE link in which the target data in an unlock state is confirmed as the pending PCIE link existing target data abnormality, and the PCIE switch is controlled to enter the valid data waiting state.

[0076] Specifically, if the target data is in the lock state, it is judged that the initial PCIE link does not exist target data abnormality; if the target data is in the unlock state, it is judged that the initial PCIE link exists target data abnormality, the initial PCIE link existing target data abnormality is confirmed as the pending PCIE link, and the PCIE switch is controlled to enter the valid data waiting state.

[0077] In an optional embodiment, whether the time difference value between the indirectly transmitted target data is in a preset interval is judged, the initial PCIE link in which the target data not in the preset interval is confirmed as the pending PCIE link existing target data abnormality, and the PCIE switch is controlled to enter the valid data waiting state.

[0078] Specifically, if the time difference between the target data transmitted through the PCIE switch is 0, it is judged that the PCIE link does not exist target data exception; if the time difference between the target data transmitted through the PCIE switch is not 0, it is judged that the PCIE link exists target data exception, the initial PCIE link with data exception is confirmed as a pending PCIE link, and the PCIE switch is controlled to enter the waiting valid data state.

[0079] The PCIE link performs normal data transmission in the L0 state. When a data transmission error occurs in the process of data transmission, the Recovery function is executed, and a speed reduction instruction or a bandwidth reduction instruction is issued. After the signal equalization enhancement chip receives the Recovery instruction, the corresponding instruction is executed. At this time, if a certain serial channel of the signal equalization enhancement chip has received the Recovery instruction and the idle electrical signal first, after a millisecond level of time, the remaining serial channels receive the Recovery instruction and the idle electrical signal, that is, there is a time difference between the Recovery instruction and the idle electrical signal of the serial channels, and it is confirmed that the data transmitted by the PCIE link exists exception; or the data transmitted by the PCIE link is in an unlocked state, and it can also be confirmed that the data transmitted by the PCIE link exists exception. At this time, the signal equalization enhancement chip enters the waiting valid data state.

[0080] Step 103, judging whether the PCIE switch receives valid data, confirming the pending PCIE link where the PCIE switch without receiving the valid data as an abnormal PCIE link;

[0081] In an optional embodiment, for the waiting valid data state, the state of the PCIE switch is acquired after timing 24 ms; if the PCIE switch receives valid data, the pending PCIE link where the PCIE switch receiving the valid data is not an abnormal PCIE link; if the PCIE switch does not receive valid data, the pending PCIE link where the PCIE switch without receiving the valid data is confirmed as an abnormal PCIE link.

[0082] For the abnormal PCIE link, the central processor and the PCIE switch without receiving the valid data enter the polling test state.

[0083] After the signal equalization enhancement chip enters the waiting valid data state, the clock times 24 ms, and if the signal equalization enhancement chip still does not receive valid data after 24 ms, it is determined that the PCIE link is an abnormal link.

[0084] Step 104, for the abnormal PCIE link, starting the recovery mechanism to jump out of the waiting valid data state and resetting, obtaining the target PCIE link opposite to the abnormal PCIE link after resetting.

[0085] When the abnormal PCIE link is confirmed, the signal equalization enhancement chip starts a recovery mechanism, automatically exits the valid data waiting state, and records the abnormality in the signal equalization enhancement chip log. After that, the signal equalization enhancement chip is reset, the CPU and the PCIE device linked at both ends of the signal equalization enhancement chip are restarted, the link training process is initiated, the CPU re-identifies the PCIE device and establishes a link, and the normal transmission of the PCIE link is restored, that is, the PCIE link is reset to the L0 state.

[0086] It should be noted that for the method embodiments, in order to simply describe, they are all expressed as a series of action combinations, but those skilled in the art should know that the embodiments of the present application are not limited by the order of the described actions, because according to the embodiments of the present application, certain steps can be performed in other order or simultaneously. Secondly, those skilled in the art should know that the embodiments described in the specification all belong to preferred embodiments, and the actions involved are not necessarily necessary for the embodiments of the present application.

[0087] Referring to Figure 2 , a structure block diagram of a PCIE link fault repair device provided in an embodiment of the present application is shown, which can specifically include the following modules:

[0088] The transmission data acquisition module 201 is configured to acquire an initial PCIE link, transmit target data through link training on the initial PCIE link, and obtain a data state corresponding to the target data, wherein the transmission includes direct transmission and indirect transmission.

[0089] The abnormal data judgment module 202 is configured to judge whether the initial PCIE link has target data abnormality through the data state, obtain a pending PCIE link having target data abnormality, and control the PCIE switch to enter a valid data waiting state in the case that the pending PCIE link has target data abnormality.

[0090] The abnormal link judgment module 203 is configured to judge whether the PCIE switch receives valid data, and confirm a pending PCIE link in which the PCIE switch does not receive the valid data as an abnormal PCIE link.

[0091] The abnormal link reset module 204 is configured to start a recovery mechanism to exit the valid data waiting state and reset the abnormal PCIE link, and obtain a target PCIE link opposite to the abnormal PCIE link after the reset.

[0092] In an optional embodiment, the transmission data acquisition module 201 is specifically configured to:

[0093] The initial PCIE link is controlled to perform link training in the order of detection, polling, configuration, and linking, and a data state corresponding to target data transmitted after the initial PCIE link performs the link training is obtained.

[0094] In an optional embodiment, the abnormal data judging module 202 is specifically configured to:

[0095] By judging whether the directly transmitted target data is in the locked state, the initial PCIE link in which the target data in the unlocked state is located is confirmed as a pending PCIE link in which the target data is abnormal, and the PCIE switch is controlled to enter the waiting valid data state;

[0096] By judging whether the time difference between the indirectly transmitted target data is in the preset interval, the initial PCIE link in which the target data whose time difference is not in the preset interval is located is confirmed as a pending PCIE link in which the target data is abnormal, and the PCIE switch is controlled to enter the waiting valid data state.

[0097] In an optional embodiment, the abnormal data judging module 202 is specifically configured to:

[0098] If the target data is in the locked state, it is judged that the initial PCIE link does not have target data abnormality;

[0099] If the target data is in the unlocked state, it is judged that the initial PCIE link has target data abnormality, the initial PCIE link in which the target data is abnormal is confirmed as a pending PCIE link, and the PCIE switch is controlled to enter the waiting valid data state.

[0100] In an optional embodiment, the abnormal data judging module 202 is specifically configured to:

[0101] If the time difference between the target data transmitted through the PCIE switch is 0, it is judged that the PCIE link does not have target data abnormality;

[0102] If the time difference between the target data transmitted through the PCIE switch is not 0, it is judged that the PCIE link has target data abnormality, the initial PCIE link in which the data is abnormal is confirmed as a pending PCIE link, and the PCIE switch is controlled to enter the waiting valid data state.

[0103] In an optional embodiment, the abnormal link judging module 203 is specifically configured to:

[0104] For the waiting valid data state, the state of the PCIE switch is obtained after 24 ms of timing;

[0105] If the PCIE switch receives valid data, the pending PCIE link where the PCIE switch receiving the valid data is not an abnormal PCIE link;

[0106] If the PCIE switch does not receive valid data, the pending PCIE link where the PCIE switch not receiving the valid data is confirmed as an abnormal PCIE link.

[0107] In an optional embodiment, the abnormal link judging module 203 is specifically configured to:

[0108] For the abnormal PCIE link, the central processing unit and the PCIE switch not receiving the valid data enter a polling test state.

[0109] In an optional embodiment, the abnormal link resetting module 204 is specifically configured to:

[0110] After confirming the abnormal PCIE link, the signal equalization enhancement chip starts a recovery mechanism, automatically exits the state of waiting for valid data, and records this abnormality in the log of the signal equalization enhancement chip, after which the signal equalization enhancement chip is reset, initiates the Detect drive signal equalization enhancement chip to restart the link training process of the CPU and the PCIE device linked at both ends, makes the CPU re-identify the PCIE device and establish a link, and restores the normal transmission of the PCIE link, that is, the resetting makes the PCIE link return to the L0 state.

[0111] For the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the related parts refer to the part of the method embodiment.

[0112] In addition, the embodiment of the application also provides an electronic device, which comprises a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements each process of the above-mentioned PCIE link fault repair method embodiment and achieves the same technical effects. To avoid repetition, details are not repeated here.

[0113] The embodiment of the application also provides a computer readable storage medium, which stores a computer program, and the computer program, when executed by the processor, implements each process of the above-mentioned PCIE link fault repair method embodiment and achieves the same technical effects. To avoid repetition, details are not repeated here. The computer readable storage medium is, for example, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0114] Figure 3To realize the topology of the hardware device provided in the embodiment of the present application.

[0115] The hardware device provided by the present application includes but is not limited to a central processing unit 301, a signal equalization enhancement chip 302, a PCIE switch 303, a network card 304, image processors 305-1 and 305-2.

[0116] It should be understood that in the embodiment of the present application, the central processing unit (CPU) 301 can be used to interpret computer instructions and process data in computer software, specifically, control the execution order of instructions in a program, generate corresponding operation control signals according to the function of the instructions, and send the operation control signals to corresponding components, so as to control the components to act according to the requirements of the instructions, finally perform arithmetic operation and logical operation on data, or perform other information processing, and transmit the data to the signal equalization enhancement chip 302 for processing; in addition, timing of various operations in time is implemented. Generally, the signal equalization enhancement chip is connected with at least one central processing unit and at least one PCIE switch at both ends.

[0117] The PCIE switch 303 supports one upstream port (connected to a host or an RC), (2-n) downstream ports (expansion ports), and it needs to identify data from the upstream, including the following cases: whether the data is data transmitted to itself, if so, the data is received; whether the data is data of its downstream port, if so, the data is forwarded, if not, the data is rejected; the data transmitted from the downstream port to the RC is also checked and forwarded by the PCIE switch.

[0118] The network card 304 is a network card with a PCIE interface, which is used as an expansion port in the mainboard level connection. Specifically, the PCIE-based expansion card can be inserted into the PCIE slot in the mainboard of the central processing unit 301 and the PCIE switch 303 and other devices. The PCIE network card 304 can control the data flow direction through a series of point-to-point connections of the PCIE switch 303, and after the PCIE network card is inserted, a logical connection will be formed between the slot and the network card for mutual communication. This logical connection is called a link, which supports a point-to-point communication channel between two PCIE ports and allows them to send and receive ordinary requests or interrupts. The PCIE slot has at least one channel, for example, in an x2 link, each channel contains two pairs of different data transmission groups, one pair for transmitting data and the other pair for receiving data. Therefore, each channel contains four wires or signal lines.

[0119] The circuit board of the graphic processor (305-1, 305-2) is generally a 6-layer or 4-layer PCB circuit board. All components of the graphic processor (305-1, 305-2) are integrated on its circuit board, and the circuit board affects the quality of the graphic processor (305-1, 305-2). The circuit board of the graphic processor (305-1, 305-2) has a cooling fin and a fan. As the core of processing data, the graphic processor (305-1, 305-2) mostly adopts a single-chip design, and a professional graphic processor (305-1, 305-2) also adopts multiple graphic processor chips. Another important chip on the circuit board of the graphic processor (305-1, 305-2) is a digital-to-analog converter (RAMDAC). Its function is to convert digital signals in the video memory into analog signals that can be recognized by the display. The speed is measured in MHz. The faster the speed, the more stable the image. It determines the highest refresh rate that the graphic processor (305-1, 305-2) can support. The data of the graphic processor (305-1, 305-2) is stored in the video memory. The video memory is used to store graphic data information waiting for processing. The capacity of the video memory determines the resolution and color depth supported by the graphic processor (305-1, 305-2). The higher the resolution, the more pixel points displayed, and the larger the required video memory capacity.

[0120] Figure 4 is an execution flowchart of a PCIE link fault repair method provided in an embodiment of the application, and the specific operation is as follows:

[0121] In step 401, the server is started, the initial PCIE link is acquired, the initial PCIE link is subjected to link training to make the CPU and the PCIE device at both ends of the signal enhancement chip reach an L0 state, the target data is transmitted, and the data state corresponding to the target data is obtained.

[0122] Step 402, judge whether the initial PCIE link exists target data abnormality through data state, if the target data is in the locked state, it is judged that the initial PCIE link does not exist target data abnormality, if the target data is in the unlocked state, it is judged that the initial PCIE link exists target data abnormality, the initial PCIE link existing target data abnormality is confirmed as the pending PCIE link, and the PCIE switch is controlled to enter the waiting valid data state to obtain the pending PCIE link existing target data abnormality, and in the case that the pending PCIE link exists target data abnormality, the PCIE switch is controlled to enter the waiting valid data state, if the time difference between the target data transmitted through the PCIE switch is 0, it is judged that the PCIE link does not exist target data abnormality, if the time difference between the target data transmitted through the PCIE switch is not 0, it is judged that the PCIE link exists target data abnormality, the initial PCIE link existing data abnormality is confirmed as the pending PCIE link, and the PCIE switch is controlled to enter the waiting valid data state.

[0123] Step 403, for the waiting valid data state, the state of the PCIE switch is acquired after timing 24 ms, if the PCIE switch receives valid data, the pending PCIE link where the PCIE switch receiving valid data is not an abnormal PCIE link, and the target data is processed normally according to the PCIE protocol (403-1 is executed), if the PCIE switch does not receive valid data, the pending PCIE link where the PCIE switch not receiving valid data is confirmed as an abnormal PCIE link (403-2 is executed).

[0124] Steps 404 and 405, for the abnormal PCIE link, start the recovery mechanism to jump out of the waiting valid data state and reset.

[0125] Step 406, after resetting, PCIE link link training is performed again, so that the PCIE link link of the device at both ends of the signal equalization enhancement chip is in the L0 state, so that the PCIE fault has been repaired, and the data can be transmitted and processed normally.

[0126] Step 407, the PCIE link is continuously stable in the L0 state for data transmission.

[0127] It should be noted that, in the present document, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element preceded by "comprises... a" does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0128] Those skilled in the art can clearly understand that the above-mentioned embodiment method can be realized by means of software and necessary general hardware platform, of course, it can also be realized by hardware, but in many cases, the former is a better embodiment. Based on such understanding, the technical solutions of the present application can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes a plurality of instructions for making a terminal (which can be a mobile phone, computer, server, air conditioner, or network device, etc.) execute the method described in each embodiment of the present application.

[0129] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific embodiments, and the above-mentioned specific embodiments are only illustrative, not restrictive, and those skilled in the art can make many forms under the inspiration of the present application without departing from the purpose of the present application and the scope protected by the claims.

[0130] Those skilled in the art can realize that the units and algorithm steps of each example described in conjunction with the embodiments disclosed in the embodiments of the present application can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solutions. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0131] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the above-described system, device and unit can refer to the corresponding process in the foregoing method embodiments, which will not be described here.

[0132] In the embodiments of the present application, it should be understood that the disclosed apparatus and method can be implemented in other manners. For example, the embodiments of the apparatus described above are merely schematic, and the division of the units is merely logical function division, and there can be another division manner in actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections can be indirect couplings or communication connections through some interfaces, devices or units, and can be in electrical, mechanical or other forms.

[0133] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e., can be located in one place, or can be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiments of the present application.

[0134] In addition, each functional unit in each embodiment of the present application can be integrated into a processing unit, or each unit can be physically present separately, or two or more units can be integrated into one unit.

[0135] If the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application or the parts of the present application that essentially contribute to the prior art or the parts of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a ROM, a RAM, a magnetic disk or an optical disk, and various storage media that can store program codes.

[0136] The above description is merely a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for repairing PCIe link faults, characterized in that, Applied to a server, the server including a signal equalization and enhancement chip, a central processing unit, and a PCIe switch, the method includes: Obtain an initial PCIe link, transmit target data by performing link training on the initial PCIe link, and obtain the data status corresponding to the target data. The transmission includes direct transmission and indirect transmission. The initial PCIe link is determined based on its data status to identify any PCIe links with abnormal target data. If such PCIe links have abnormal target data, the PCIe switch is controlled to enter a state of waiting for valid data. By determining whether the target data to be directly transmitted is in a locked state, if the target data is in a locked state, it is determined that there is no target data anomaly in the initial PCIe link; if the target data is in an unlocked state, it is determined that there is target data anomaly in the initial PCIe link, the initial PCIe link with target data anomaly is identified as a pending PCIe link, and the PCIe switch is controlled to enter a waiting state for valid data. By determining whether the time difference between indirectly transmitted target data is within a preset range, if the time difference between the target data transmitted through the PCIe switch is 0, it is determined that there is no target data anomaly in the PCIe link; if the time difference between the target data transmitted through the PCIe switch is not 0, it is determined that there is target data anomaly in the PCIe link, the initial PCIe link with target data anomaly is identified as a pending PCIe link, and the PCIe switch is controlled to enter a waiting state for valid data. Determine whether the PCIe switch has received valid data, and identify the PCIe link where the PCIe switch that has not received the valid data is located as an abnormal PCIe link. For the abnormal PCIe link, a recovery mechanism is initiated to exit the waiting for valid data state and perform a reset, thereby obtaining the target PCIe link that is opposite to the abnormal PCIe link after the reset.

2. The method according to claim 1, characterized in that, The step of obtaining the initial PCIe link, transmitting target data through link training on the initial PCIe link, and obtaining the data status corresponding to the target data includes: The initial PCIe link is controlled to perform link training in the order of detection, polling, configuration, and linking, and the data status corresponding to the target data transmitted after the initial PCIe link has undergone link training is obtained.

3. The method according to claim 1, characterized in that, The step of determining whether the PCIe switch has received valid data, and identifying the pending PCIe link where the PCIe switch has not received valid data as an abnormal PCIe link, includes: For the state of waiting for valid data, the status of the PCIe switch is obtained after a 24ms timer. If the PCIe switch receives valid data, then the PCIe link to which the PCIe switch that received the valid data is located is not an abnormal PCIe link. If the PCIe switch does not receive valid data, the pending PCIe link where the PCIe switch that did not receive valid data is identified as an abnormal PCIe link.

4. The method according to claim 3, characterized in that, If the PCIe switch does not receive valid data, the pending PCIe link where the PCIe switch that did not receive the valid data is located is identified as an abnormal PCIe link, including: For the abnormal PCIe link, the central processing unit and the PCIe switch that has not received the valid data enter a polling test state.

5. A PCIe link fault repair device, characterized in that, include: The data acquisition module is used to acquire an initial PCIe link, transmit target data by performing link training on the initial PCIe link, and obtain the data status corresponding to the target data. The transmission includes direct transmission and indirect transmission. The abnormal data judgment module is used to determine whether there is a target data anomaly in the initial PCIe link based on the data status, obtain the pending PCIe link with target data anomaly, and control the PCIe switch to enter the waiting for valid data state when there is a target data anomaly in the pending PCIe link. The abnormal link judgment module is used to determine whether the PCIe switch has received valid data, and to identify the pending PCIe link where the PCIe switch that has not received the valid data is an abnormal PCIe link. The abnormal link reset module is used to initiate a recovery mechanism for the abnormal PCIE link, exit the waiting for valid data state and reset it to obtain the target PCIE link relative to the abnormal PCIE link after the reset. Optionally, the abnormal data judgment module is specifically used for: By determining whether the target data to be directly transmitted is in a locked state, if the target data is in a locked state, it is determined that there is no target data anomaly in the initial PCIE link; If the target data is in an unlocked state, it is determined that there is an abnormality in the target data of the initial PCIe link. The initial PCIe link with the abnormal target data is confirmed as a pending PCIe link, and the PCIe switch is controlled to enter the waiting state for valid data. By determining whether the time difference between indirectly transmitted target data is within a preset range, if the time difference between target data transmitted through the PCIE switch is 0, it is determined that there is no target data anomaly in the PCIE link. If the time difference between the target data transmitted through the PCIe switch is not 0, it is determined that there is an anomaly in the target data of the PCIe link. The initial PCIe link with the data anomaly is identified as a pending PCIe link, and the PCIe switch is controlled to enter the waiting state for valid data.

6. An electronic device, characterized in that, It includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; The memory is used to store computer programs; When the processor executes a program stored in the memory, it implements the method described in any one of claims 1-4.

7. A computer-readable storage medium having instructions stored thereon that, when executed by one or more processors, cause the processors to perform the method of any one of claims 1-4.

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