Semiconductor memory

Abstract

The present application relates to the technical field of semiconductor memory, and provides a semiconductor memory. The semiconductor memory comprises a substrate, a connection layer arranged on the substrate, and a capacitor structure arranged on the connection layer. The connection layer comprises a connection pad array, a peripheral structure adjacent to the connection pad array, and a plurality of first extension pads arranged between the peripheral structure and the connection pad array, wherein a part of a bottom electrode of the capacitor structure is arranged on the first extension pads, so that a peripheral part of the capacitor structure obtains more support and the defect of deformation or collapse is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor memory technology, and in particular to a semiconductor memory including an interconnect layer and a capacitor structure disposed on the interconnect layer. Background Technology

[0002] Dynamic random access memory (DRAM) is a type of volatile memory, comprising an array area consisting of multiple memory cells and a peripheral area consisting of control circuitry. Each memory cell consists of a transistor and a capacitor electrically connected to the transistor. The transistor controls the storage and release of charge in the capacitor to store data. The control circuitry addresses each memory cell and controls data access to that cell via word lines (WL) and bit lines (BL) that span the array area and are electrically connected to each memory cell.

[0003] To reduce the size of memory cells and create chips with higher density, memory cell structures have evolved towards three-dimensional designs, such as using buried word lines and stacked capacitors. Stacked capacitors are vertically positioned above the substrate, thereby saving substrate area occupied by the capacitors and allowing for larger capacitances by easily increasing the electrode height. However, with increased height, the capacitor structure, especially the portion near the periphery, often experiences tilting. Summary of the Invention

[0004] In view of this, the present invention provides a semiconductor memory including a stacked capacitor, wherein the bottom electrode of the capacitor structure is electrically connected to circuit elements of a substrate through a connection layer disposed below the capacitor structure. This semiconductor memory can solve the problem in the prior art where the capacitor structure, especially the portion adjacent to the periphery, often tilts as the height increases.

[0005] An embodiment of the present invention provides a semiconductor memory, including a substrate, a connection layer disposed on the substrate, and a capacitor structure disposed on the connection layer. The connection layer includes a connection pad array comprising a plurality of connection pads arranged along a first direction and a second direction, a peripheral structure including a first edge and a second edge adjacent to adjacent sides of the connection pad array, and a plurality of first extension pads arranged between the first edge and the connection pad array. The capacitor structure includes a plurality of bottom electrodes, wherein each connection pad has one bottom electrode, and each of the first extension pads has two bottom electrodes.

[0006] Another embodiment of the present invention provides a semiconductor memory, including a substrate, an interconnect layer disposed on the substrate, and a capacitor structure disposed on the interconnect layer. The interconnect layer includes an interconnect pad array comprising a plurality of interconnect pads arranged along a first direction and a second direction, a peripheral structure including a first edge and a second edge adjacent to adjacent sides of the interconnect pad array, and a plurality of first extension pads and a plurality of second extension pads alternately arranged between the first edge and the interconnect pad array. Along the first direction, the length of the first extension pad is greater than the length of the second extension pad. The capacitor structure includes a plurality of bottom electrodes, wherein each interconnect pad has one bottom electrode, each of the first extension pads has N+1 bottom electrodes, and each of the second extension pads has N bottom electrodes.

[0007] Beneficial effects

[0008] This invention provides an extension pad in the connection layer and selectively places the bottom electrode (dummy bottom electrode) of the outer part of the capacitor structure on the extension pad, so that the outer part of the capacitor structure can obtain more support, reduce defects such as deformation or collapse, obtain a capacitor structure with better integrity, and improve the stability and quality of the overall semiconductor memory. Attached Figure Description

[0009] The accompanying drawings are provided to give a more in-depth understanding of this embodiment and are incorporated herein by reference as a whole. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams for illustrative and drafting purposes, and relative dimensions and scales have been adjusted. The same symbols represent corresponding or similar features in different embodiments.

[0010] Figure 1 This is a planar schematic diagram of a semiconductor memory according to an embodiment of the present invention.

[0011] Figure 2 for Figure 1 The diagram shows a partially enlarged schematic of the semiconductor memory.

[0012] Figure 3 for Figure 2 The diagram shows a cross-sectional view of the semiconductor memory along the AA' tangent.

[0013] Figure 4 for Figure 2 The diagram shows a cross-sectional view of the semiconductor memory along the BB' tangent.

[0014] Figure 5 This is a partially enlarged schematic diagram of a semiconductor memory according to an embodiment of the present invention.

[0015] Figure 6 This is a partially enlarged schematic diagram of a semiconductor memory according to an embodiment of the present invention.

[0016] Figure 7 This is a partially enlarged schematic diagram of a semiconductor memory according to an embodiment of the present invention.

[0017] Figure 8 This is a partially enlarged schematic diagram of a semiconductor memory according to an embodiment of the present invention.

[0018] The reference numerals in the attached figures are explained as follows:

[0019]

[0020] Detailed Implementation

[0021] To enable those skilled in the art to further understand this invention, several preferred embodiments are listed below, and the composition and desired effects of the invention are explained in detail with reference to the accompanying drawings. Those skilled in the art can, without departing from the spirit of the invention, substitute, recombine, or mix features from the following embodiments to complete other embodiments.

[0022] Please refer to Figure 1 This is a schematic plan view of a semiconductor memory 100 according to an embodiment of the present invention. The semiconductor memory 100 includes a substrate 10, such as a silicon (Si) substrate, an epitaxial silicon (epi-Si) substrate, a silicon-germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or a silicon-on-insulator (SOI) substrate, but is not limited thereto. The substrate 10 includes at least one cell region CA and a peripheral region PA adjacent to the edge of the cell region CA. The cell region CA is the area where memory cells are disposed, and is separated from other circuit areas of the substrate 10 by the peripheral region PA. In some embodiments, the cell region CA is completely surrounded by the peripheral region PA.

[0023] Please refer to Figure 2 , Figure 3 and Figure 4 . Figure 2 for Figure 1 This is an enlarged planar schematic diagram of region A of the semiconductor memory 100. Region A includes a corner portion of cell region CA and the nearby peripheral region PA. Figure 3 For along Figure 2 A cross-sectional view of semiconductor memory 100, showing the AA' tangent line. Figure 4 For along Figure 2 The diagram shows a cross-sectional view of semiconductor memory 100, with the BB' tangent line shown. For simplicity, Figure 3 and Figure 4 Some components shown in the cross-sectional view (such as contact plug 14, capacitor structure CAP, support layer 18, capacitor dielectric layer 34, top electrode 36, and planarization layer 40) are not shown in the diagram. Figure 2 In the plan view.

[0024] Semiconductor memory 100 is a dynamic random access memory (DRAM) including stacked capacitors, comprising an interconnect layer 20 disposed on a substrate 10 and a capacitor structure CAP disposed on the interconnect layer 20. Circuit elements for controlling read and write operations of memory cells, such as transistors, embedded word lines, bit lines, and conductive plugs, may be included in or on the substrate 10. For simplicity, these circuit elements are not shown in the figures.

[0025] The capacitor structure CAP is a bump structure disposed on the connection layer 20, overlapping directly above the cell region CA and extending to partially overlap with the peripheral region PA. The capacitor structure CAP includes a plurality of bottom electrodes 32 vertically erected on the connection layer 20, a capacitor dielectric layer 34 covering the surface of the bottom electrodes 32, and a top electrode 36 located on the capacitor dielectric layer 34 and capacitively coupled to the bottom electrodes 32 through the capacitor dielectric layer 34. The bottom electrodes 32 and the top electrode 36 respectively include conductive materials, such as metals, suitable metals such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or compounds, alloys, and / or composite layers of the aforementioned metal materials, but are not limited thereto. In some embodiments, the top electrode 36 may include a semiconductor material, such as polycrystalline silicon. The material of the capacitor dielectric layer 34 may include silicon oxide (SiO2), silicon nitride (SiN), or a high-k dielectric, but is not limited thereto.

[0026] The capacitor structure CAP further includes at least one support layer 18, extending horizontally between the bottom electrodes 32 of the capacitor structure CAP, directly contacting and supporting each bottom electrode 32. In some embodiments, an etch stop layer 16 may be provided between the capacitor structure CAP and the connection layer 20, wherein the bottom of the bottom electrode 32 penetrates the etch stop layer 16 and directly contacts the conductive structure (e.g., connection pad 22) of the connection layer 20. The support layer 18 and the etch stop layer 16 respectively comprise dielectric materials, such as silicon nitride (SiN), silicon carbide (SiC), silicon nitride carbide (SiCN), and nitrogen-doped silicon carbide (NDC), but are not limited thereto.

[0027] A planarization layer 40 is disposed on the interconnect layer 20 to planarize the surface topography caused by the capacitor structure CAP, and its top surface is substantially flush with the top surface of the capacitor structure CAP. The planarization layer 40 may include a dielectric material, such as silicon oxide (SiO2), but is not limited thereto. In some embodiments, when the etch stop layer 16 outside the capacitor structure CAP is still retained on the interconnect layer 20, the planarization layer 40 may be located on the etch stop layer 16.

[0028] A connection layer 20 is disposed between the capacitor structure CAP and the substrate 10, and includes a dielectric layer and conductive structures disposed within the dielectric layer. For example, such as Figure 2 , Figure 3 and Figure 4 As shown, the connection layer 20 may include a first dielectric layer 12, a contact plug 14 disposed in the first dielectric layer 12, a second dielectric layer 26, a connection pad 22 disposed in the second dielectric layer 26, a peripheral structure 24, and an extension pad 25 located between the connection pad 22 and the peripheral structure 24. The first dielectric layer 12 and the second dielectric layer 26 include dielectric materials, such as silicon oxide (SiO2) and silicon nitride (SiN), but are not limited thereto. The contact plug 14, the connection pad 22, the peripheral structure 24, and the extension pad 25 (including the first extension pad P1, the second extension pad P2, the third extension pad P3, the fourth extension pad P4, and the fifth extension pad P5) include conductive materials, such as metals. Suitable metals may include tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or compounds, alloys, and / or composite layers of the aforementioned metal materials, but are not limited thereto. According to an embodiment of the present invention, the connection pad 22, the peripheral structure 24, and the extension pad 25 are obtained by patterning the same conductive layer.

[0029] The connection pads 22 are located approximately directly above the cell region CA of the substrate 10, forming a separate island-like structure, and are arranged along the first direction DR1 and the second direction DR2 to form a connection pad array 22A. Each connection pad 22 contacts a bottom electrode 32 of the capacitor structure CAP, and then connects to a contact plug 14 in the first dielectric layer 12, electrically connecting the bottom electrode 32 to a corresponding circuit element in or on the substrate 10. The bottom electrodes 32 contacting the connection pads 22 are storage nodes of the semiconductor memory 100.

[0030] The peripheral structure 24 is generally located directly above the peripheral region PA of the substrate 10, and preferably extends continuously along the outer side of the connector pad array 22A to partially or completely surround the connector pad array 22A. For ease of illustration, this document will... Figure 2 The adjacent edges of the adjacent connecting pad array 22A of the shown peripheral structure 24 are defined as the first edge 24a and the second edge 24b, and the portion connecting the first edge 24a and the second edge 24b is defined as the third edge 24c. The first edge 24a, the second edge 24b, and the third edge 24c extend in different directions and may have the same or different profiles. In some embodiments, the extending directions of the first edge 24a and the second edge 24b are perpendicular to each other. In some embodiments, the first edge 24a has a straight profile, the second edge 24b has a wavy profile, and the third edge 24c may have a straight profile or an arcuate profile.

[0031] The extension pad 25 is disposed between the peripheral structure 24 and the connecting pad array 22A, and may have different shapes and lengths depending on its location. For ease of explanation, the extension pad 25 is further divided into a first extension pad P1, a second extension pad P2, a third extension pad P3, a fourth extension pad P4, and a fifth extension pad P5 according to its position and shape, and their features are described below.

[0032] First extension pad P1 and second extension pad P2 are alternately arranged between the first edge 24a and the connecting pad array 22A, each being a long segment structure with its long axis extending along a first direction DR1 and aligned with the connecting pad 22 along the first direction DR1. The first extension pad P1 is separated from the first edge 24a by a second dielectric layer 26 and does not directly contact it. The second extension pad P2 is connected at one end to the first edge 24a, and its other end is aligned with the end of the adjacent first extension pad P1 along a second direction DR2. The long axis of the first extension pad P1 has a length L1, and the long axis of the second extension pad P2 has a length L2. In some embodiments, length L1 is greater than length L2.

[0033] The third extension pad P3 is disposed between the third edge 24c and the connecting pad array 22A, and is separated from the third edge 24c by the second dielectric layer 26 without direct contact. The third extension pad P3 has an elongated structure with its long axis extending along the first direction DR1, and is aligned with the connecting pad 22 along the first direction DR1. The long axis of the third extension pad P3 has a length L3. In some embodiments, the length L1 is greater than the length L3. In some embodiments, both the length L1 and the length L2 are greater than the length L3.

[0034] A fourth extension pad P4 is arranged between the second edge 24b and the connecting pad array 22A, separated from the second edge 24b by a second dielectric layer 26 and not in direct contact. The fourth extension pad P4 may be an island-like structure with indistinguishable major and minor axes, or a short segment structure with a major axis slightly longer than its minor axis. In some embodiments, the fourth extension pad P4 is arranged along the wavy profile of the second edge 24b and is alternately positioned with its major axis parallel to either the first direction DR1 or the second direction DR2. The major axis of the fourth extension pad P4 has a length L4. In some embodiments, the length L3 is greater than the length L4.

[0035] A fifth extension pad P5 is disposed between the first extension pad P1 and the third extension pad P3, and one end is connected to the third edge 24c. The fifth extension pad P5 is an elongated structure with its long axis extending along the first direction DR1, aligned with the connecting pad 22 along the first direction DR1. The long axis of the fifth extension pad P5 has a length L5. In some embodiments, the length L5 is greater than the length L3 and less than the length L1. In some embodiments, the length L5 is less than both the length L1 and the length L2.

[0036] In some embodiments, the peripheral structure 24 and the extension pads 25 (including the first extension pad P1, the second extension pad P2, the third extension pad P3, the fourth extension pad P4, and the fifth extension pad P5) are not electrically connected to the outside and are electrically floating.

[0037] The present invention is characterized in that by selectively setting a bottom electrode 32 (an electrically floating dummy bottom electrode) on the extension pad 25, the portion of the peripheral area PA of the capacitor structure CAP can obtain more support, reducing the defects of deformation or collapse of the capacitor structure CAP in this area, resulting in a capacitor structure CAP with better integrity, and improving the overall stability of the semiconductor memory 100.

[0038] Furthermore, the number of bottom electrodes 32 disposed on the extension pads can vary depending on the length and position of the extension pads. For example, when the second extension pad P2 has N bottom electrodes 32, the first extension pad P1, which is longer than the second extension pad P2, can have N+1 bottom electrodes 32. As for the third extension pad P3, the fourth extension pad P4, and the fifth extension pad P5, which are shorter than the second extension pad P2, they can each have N or N-1 bottom electrodes 32, or none at all. According to an embodiment of the present invention, N is preferably equal to 0, 1, or 2. The following will describe some layout embodiments of the bottom electrodes 32 and the extension pads 25 to help those skilled in the art understand the present invention.

[0039] Please refer to Figure 2 In the illustrated embodiment, the first extension pad P1 is provided with two bottom electrodes 32, the second extension pad P2 and the fifth extension pad P5 are each provided with one bottom electrode 32, the fourth extension pad P4 is provided with one bottom electrode 32 at intervals, and the third extension pad P3 is not provided with any bottom electrodes 32. In this embodiment, N equals 1.

[0040] Please refer to Figure 5 In the illustrated embodiment, the first extension pad P1 is provided with two bottom electrodes 32, the second extension pad P2 and the fifth extension pad P5 are each provided with one bottom electrode 32, and the fourth extension pad P4 and the third extension pad P3 are not provided with any bottom electrodes 32. In this embodiment, N equals 1.

[0041] Please refer to Figure 6 In the illustrated embodiment, the first extension pad P1 is provided with one bottom electrode 32, while the second extension pad P2 and the fifth extension pad P5 are not provided with any bottom electrodes 32, nor are the fourth extension pad P4 and the third extension pad P3. In this embodiment, N equals 0.

[0042] Please refer to Figure 7 In the illustrated embodiment, the first extension pad P1 is provided with three bottom electrodes 32, the second extension pad P2 and the fifth extension pad P5 are each provided with two bottom electrodes 32, the fourth extension pad P4 is provided with one bottom electrode 32 at intervals, and the third extension pad P3 is not provided with any bottom electrodes 32. In this embodiment, N equals 2.

[0043] Please refer to Figure 8 In the illustrated embodiment, the first extension pad P1 is provided with three bottom electrodes 32, the second extension pad P2 and the fifth extension pad P5 are provided with two bottom electrodes 32, and the fourth extension pad P4 and the third extension pad P3 are not provided with any bottom electrodes 32. In this embodiment, N equals 2.

[0044] In summary, the semiconductor memory of the present invention provides more support for the peripheral region of its capacitor structure, reducing defects such as deformation or collapse, thereby achieving a capacitor structure with better integrity, improving the quality of the semiconductor memory, and enhancing the overall stability of the semiconductor memory.

[0045] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A semiconductor memory, characterized in that, include: A substrate; A bonding layer, disposed on the substrate, comprising: An array of connector pads comprising a plurality of connector pads arranged along a first direction and a second direction; A peripheral structure, including a first edge and a second edge adjacent to the two sides of the connecting pad array; and A plurality of first extension pads are arranged between the first edge and the connecting pad array; and A capacitor structure includes multiple bottom electrodes disposed on the connection layer, wherein each connection pad has one bottom electrode and each first extension pad has two bottom electrodes. The capacitor structure further includes at least one support layer that extends horizontally between the bottom electrodes of the capacitor structure and directly contacts the bottom electrodes.

2. The semiconductor memory as described in claim 1, characterized in that, The first edge and the second edge extend in different directions and are connected by a third edge. The semiconductor memory further includes: A third extension pad is disposed between the third edge and the connecting pad array; and Multiple fourth extension pads are arranged between the second edge and the connecting pad array, wherein along the first direction, the length of the first extension pad is greater than the length of the third extension pad, and the length of the third extension pad is greater than the length of the fourth extension pad.

3. The semiconductor memory as described in claim 2, characterized in that, The fourth extension pad is provided with one bottom electrode at intervals.

4. The semiconductor memory as described in claim 2, characterized in that, Also includes: A fifth extension pad is disposed between the first extension pad and the third extension pad and connected to the third edge, wherein along the first direction, the length of the fifth extension pad is greater than the length of the third extension pad and less than the length of the first extension pad.

5. The semiconductor memory as described in claim 4, characterized in that, The fifth extension pad is provided with one bottom electrode.

6. The semiconductor memory as claimed in claim 1, characterized in that, Also includes: Multiple second extension pads are alternately arranged between the first extension pad and the connecting pad array, wherein each of the second extension pads is provided with a bottom electrode.

7. The semiconductor memory as claimed in claim 6, characterized in that, Along the first direction, the length of the first extension pad is greater than the length of the second extension pad.

8. The semiconductor memory as claimed in claim 6, characterized in that, The second extension pad is attached to the first edge, and the first extension pad is completely separated from the first edge by a dielectric layer.

9. The semiconductor memory as claimed in claim 6, characterized in that, The first edge and the second edge extend in different directions and are connected by a third edge. The semiconductor memory further includes: A third extension pad is disposed between the third edge and the connecting pad array; and A plurality of fourth extension pads are arranged between the second edge and the connecting pad array, wherein along the first direction, the length of the second extension pad is greater than the length of the third extension pad, and the length of the third extension pad is greater than the length of the fourth extension pad.

10. The semiconductor memory as claimed in claim 9, characterized in that, Also includes: A fifth extension pad is disposed between the first extension pad and the third extension pad and connected to the third edge, wherein along the first direction, the length of the fifth extension pad is greater than the length of the third extension pad and less than the length of the second extension pad.

11. The semiconductor memory as claimed in claim 1, characterized in that, The first edge has a straight profile, and the second edge has a wavy profile.

12. A semiconductor memory, characterized in that, include: A substrate; A bonding layer, disposed on the substrate, comprising: An array of connector pads comprising a plurality of connector pads arranged along a first direction and a second direction; A peripheral structure, including a first edge and a second edge adjacent to the two sides of the connecting pad array; and A plurality of first extension pads and a plurality of second extension pads are alternately arranged between the first edge and the connecting pad array, wherein along the first direction, the length of the first extension pad is greater than the length of the second extension pad; and A capacitor structure includes multiple bottom electrodes disposed on the connection layer, wherein each connection pad has one bottom electrode, each first extension pad has N+1 bottom electrodes, and each second extension pad has N bottom electrodes; wherein N is equal to 0, 1, or 2; The capacitor structure further includes at least one support layer that extends horizontally between the bottom electrodes of the capacitor structure and directly contacts the bottom electrodes.

13. The semiconductor memory as claimed in claim 12, characterized in that, The second extension pad is attached to the first edge, and the first extension pad and the first edge are completely separated by a dielectric layer.

14. The semiconductor memory as claimed in claim 12, characterized in that, The first edge has a straight profile, and the second edge has a wavy profile.

15. The semiconductor memory as claimed in claim 12, characterized in that, The first edge and the second edge extend in different directions and are connected by a third edge. The semiconductor memory further includes: A third extension pad is disposed between the third edge and the connecting pad array; and Multiple fourth extension pads are arranged between the second edge and the connecting pad array, wherein along the first direction, the length of the first extension pad is greater than the length of the third extension pad, and the length of the third extension pad is greater than the length of the fourth extension pad.

16. The semiconductor memory as claimed in claim 15, characterized in that, The length of the second extension pad is greater than the length of the third extension pad.

17. The semiconductor memory as claimed in claim 15, characterized in that, The fourth extension pad is provided with one bottom electrode at intervals.

18. The semiconductor memory as claimed in claim 15, characterized in that, Also includes: A fifth extension pad is disposed between the first extension pad and the third extension pad and connected to the third edge, wherein along the first direction, the length of the second extension pad is greater than the length of the fifth extension pad, and the length of the fifth extension pad is greater than the length of the third extension pad.

19. The semiconductor memory as claimed in claim 18, characterized in that, The fifth extension pad is provided with N bottom electrodes.

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