Semiconductor structure and method of manufacturing the same

Abstract

The embodiment of the present disclosure relates to the field of semiconductor, and provides a semiconductor structure and a manufacturing method thereof, the manufacturing method of the semiconductor structure comprises: providing a substrate, the substrate comprises an array region, the array region comprises a plurality of array-arranged initial active regions and isolation structures for spacing adjacent initial active regions, the array region has an etching stop layer, and the isolation structures penetrate the etching stop layer; etching the initial active regions and the isolation structures until the etching stop layer under the initial active regions is exposed to form word line trenches, and the initial active regions are divided into at least two adjacent active pillars by the word line trenches; at least removing the etching stop layer exposed by the bottom surface of the word line trenches; forming an epitaxial layer on the substrate exposed by the bottom surface of the word line trenches, and the epitaxial layer is in contact with the side surface of the active pillars; recrystallizing the epitaxial layer and the active pillars to form single-crystal active regions; and forming a word line structure in the word line trenches. At least the uniformity of the depth of the word line structure is improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and a method for manufacturing the same. Background Technology

[0002] Dynamic random access memory (DRAM) is a semiconductor memory that allows for high-speed, random writing and reading of data, and is widely used in data storage devices. DRAM consists of multiple repeating memory cells, each typically including a capacitor and a transistor. The transistor's gate is connected to the word line (WL), its drain to the bit line (BL), and its source to the capacitor. Voltage signals on the word line control the transistor to turn on or off, thereby allowing data to be read from the capacitor via the bit line or written to the capacitor via the bit line for storage.

[0003] As semiconductor device density increases, buried word lines are widely used in DRAM to reduce the area occupied by the gate transistor. The use of buried word lines greatly reduces the area occupied by the word lines in the active region (compared to non-buried word lines, buried word lines reduce the area occupied by the active region by 40% to 60%).

[0004] However, there are still some problems in the process of making embedded letter lines. Summary of the Invention

[0005] This disclosure provides a semiconductor structure and its manufacturing method, which at least helps to improve the uniformity of word line structure depth.

[0006] According to some embodiments of this disclosure, one aspect of this disclosure provides a method for manufacturing a semiconductor structure, comprising: providing a substrate, the substrate including an array region, the array region including a plurality of initially active regions arranged in an array and an isolation structure separating adjacent initially active regions, the array region having an etch stop layer, the isolation structure penetrating the etch stop layer; etching the isolation structure and the initial active regions until the etch stop layer below the initial active regions is exposed to form a word line trench, the initial active regions being divided into at least two adjacent active pillars by the word line trench; removing at least the etch stop layer exposed at the bottom surface of the word line trench; forming an epitaxial layer on the substrate exposed at the bottom surface of the word line trench, the top surface of the epitaxial layer being higher than the bottom surface of the active pillars, and the epitaxial layer being in contact with the side surfaces of at least two adjacent active pillars; recrystallizing the epitaxial layer and the active pillars to form a single-crystal active region; and forming a word line structure within the word line trench.

[0007] In some embodiments, the thickness of the etching stop layer is 5 nm-15 nm.

[0008] In some embodiments, forming an epitaxial layer on the substrate exposed at the bottom surface of the word groove includes: forming an epitaxial barrier layer located on the sidewall of the active post exposed by the word groove; forming a first epitaxial layer located on the substrate exposed at the bottom surface of the word groove and also in contact with the epitaxial barrier layer on the sidewall of the word groove; removing the epitaxial barrier layer on the sidewall of the word groove; forming a second epitaxial layer on the first epitaxial layer, the second epitaxial layer being in contact with the sidewalls of the at least two adjacent active posts, wherein the first epitaxial layer and the second epitaxial layer constitute the epitaxial layer.

[0009] In some embodiments, forming the epitaxial barrier layer includes: forming an initial epitaxial barrier layer that conformally covers the word line trench; removing the initial epitaxial barrier layer located at the bottom surface of the word line trench, and using the remaining initial epitaxial barrier layer as the epitaxial barrier layer.

[0010] In some embodiments, providing the substrate includes: providing a semiconductor substrate, the etch stop layer, and a semiconductor layer stacked sequentially, the semiconductor substrate including an array region; etching the semiconductor layer, the etch stop layer, and the semiconductor substrate in the array region to form the isolation trench, the semiconductor layer being divided by the isolation trench into a plurality of initially active regions arranged in an array; and forming the isolation structure in the isolation trench, the semiconductor substrate, the plurality of initially active regions, and the isolation structure constituting the substrate.

[0011] In some embodiments, the substrate further includes a peripheral region surrounding the periphery of the array region, and the etch stop layer is also located in a portion of the region between the array region and the peripheral region.

[0012] In some embodiments, providing the substrate includes: providing a semiconductor substrate, the semiconductor substrate including an array region and a peripheral region; etching the semiconductor substrate in the array region to form an array trench; forming an etch stop film that conformally covers one side surface of the semiconductor substrate having the array trench; forming a semiconductor layer covering the surface of the etch stop film located within the array trench, the semiconductor layer filling the array trench; removing the etch stop film located in the peripheral region, the remaining etch stop film serving as the etch stop layer; etching the semiconductor layer, the etch stop layer, and the semiconductor substrate in the array region to form the isolation trench, the semiconductor layer being divided by the isolation trench into a plurality of initially active regions arranged in an array; and forming the isolation structure in the isolation trench, the semiconductor substrate, the plurality of initially active regions, and the isolation structure constituting the substrate.

[0013] In some embodiments, forming the character line structure includes: forming a dielectric layer that conformally covers the character line groove; forming a character line layer located on a portion of the dielectric layer away from the substrate, and the character line layer filling a portion of the character line groove; and forming a character line capping layer located on the surface of the character line layer away from the substrate, and the character line capping layer filling the character line groove.

[0014] According to some embodiments of this disclosure, another aspect of this disclosure provides a semiconductor structure, including: a substrate including an array region, the array region including a plurality of active regions arranged in an array and an isolation structure defining the plurality of active regions, each active region including at least two adjacent first active pillars and a second active pillar located between the at least two adjacent first active pillars; an etch stop layer disposed within the substrate, including a plurality of first etch stop portions, each first etch stop portion located directly below a first active pillar, the bottom surface of the first active pillar being between the top surface and the bottom surface of the second active pillar, and the second active pillar covering the side surface of the first etch stop portion; a word line structure, the word line structure spanning the active regions and the isolation structure, the word line structure covering the side surface of the first active pillar and the top surface of the second active pillar.

[0015] In some embodiments, the substrate further includes: a peripheral region surrounding the array region; the etch stop layer further includes a second etch stop portion located at the boundary between the array region and the peripheral region.

[0016] The technical solutions provided in this disclosure have at least the following advantages:

[0017] The semiconductor structure manufacturing method provided in this disclosure first provides a substrate, which includes an array region. The array region includes multiple initially active regions arranged in an array and isolation structures that separate adjacent initially active regions. The array region has an etch stop layer, and the isolation structures penetrate the etch stop layer. The isolation structures and the initial active regions are etched until the etch stop layer below the initial active regions is exposed to form word line trenches. The initial active regions are divided into at least two adjacent active pillars by the word line trenches. At least the etch stop layer exposed at the bottom surface of the word line trenches is removed. An epitaxial layer is formed on the substrate exposed at the bottom surface of the word line trenches. The top surface of the epitaxial layer is higher than the bottom surface of the active pillars, and the epitaxial layer is in contact with the sides of at least two adjacent active pillars. The epitaxial layer and the active pillars are recrystallized to form a single-crystal active region, and a word line structure is formed in the word line trenches. In related technologies, during the etching process to form word line trenches on a substrate, limitations in the etching process make it difficult to control the uniformity of the depth of each word line trench. This results in uneven depths of the ultimately fabricated embedded word lines, leading to non-uniform switching current and voltage in the semiconductor structure, electrical instability, and ultimately, a reduced lifespan for the semiconductor structure. However, in this embodiment, an etching stop layer is provided within the substrate array region. When etching the substrate to form word line trenches, etching stops at the top surface of the etching stop layer. This ensures that the depth of each word line trench within the substrate tends to be consistent, thereby improving the uniformity of the word line structure depth, enhancing the electrical stability of the semiconductor structure, and increasing its lifespan. Attached Figure Description

[0018] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a top view schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0020] Figures 2 to 6 A schematic cross-sectional view of each step in the manufacturing method of the semiconductor structure provided in this embodiment of the disclosure;

[0021] Figure 7 This is a top view schematic diagram of a semiconductor structure provided in another embodiment of the present disclosure;

[0022] Figures 8 to 38A schematic diagram of the structure corresponding to each step in the manufacturing method of the semiconductor structure provided in the embodiments of this disclosure;

[0023] Figure 39 This is a cross-sectional structural diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0024] Figure 40 This is another cross-sectional view of a semiconductor structure provided in an embodiment of the present disclosure;

[0025] Figure 41 This is a cross-sectional structural diagram of a semiconductor structure provided in another embodiment of the present disclosure;

[0026] Figure 42 This is another cross-sectional schematic diagram of a semiconductor structure provided in another embodiment of the present disclosure. Detailed Implementation

[0027] As can be seen from the background technology, current semiconductor structure manufacturing methods produce semiconductor structures with uneven depth of word line structure.

[0028] This disclosure provides a method for manufacturing a semiconductor structure. The provided substrate has an etch stop layer within an array region. The array region also includes multiple initially active regions arranged in an array and isolation structures separating adjacent initial active regions. The isolation structures penetrate the etch stop layer. When etching the substrate to form word line trenches, etching can be performed up to the top surface of the etch stop layer, using it as a reference. This ensures that the depth of the word line trenches within the substrate tends to be consistent, thereby ensuring a consistent depth of the word line structure, improving the uniformity of the word line structure depth, enhancing the electrical stability of the semiconductor structure, and increasing the lifespan of the semiconductor structure.

[0029] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the various embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been presented in the various embodiments of the present disclosure to enable the reader to better understand the present disclosure. However, the technical solutions claimed in the present disclosure can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0030] refer to Figures 1 to 16 A substrate 100 is provided, the substrate 100 includes an array region 101, the array region 101 includes a plurality of initial active regions 110 arranged in an array and an isolation structure 140 that separates adjacent initial active regions 110, the array region 101 has an etch stop layer 130, and the isolation structure 140 penetrates the etch stop layer 130.

[0031] refer to Figure 1Multiple discrete active regions 200 are arranged in an array within an array region 101 on a substrate 100, and an isolation structure 140 surrounds the active regions 200, with an isolation structure 140 between every two adjacent active regions 200. Figure 1 In the AA1 direction shown, the width of the isolation structure 140 between any two adjacent active regions 200 is inconsistent; some isolation structures 140 between adjacent active regions 200 are narrower, while others are wider. The active regions 200 may be made of silicon and are used to form transistors in a semiconductor structure in subsequent steps. The isolation structures 140 may be made of silicon oxide and are used to isolate the different active regions 200.

[0032] In some embodiments, the thickness of the etch stop layer 130 can be 5nm-15nm. For example, the thickness of the etch stop layer 130 can be 5nm, 10nm, 15nm, etc. The etch stop layer 130 serves as the etching reference when etching word line trenches in the semiconductor structure manufacturing method; that is, etching stops when the word line trenches are etched to the etch stop layer 130. If the thickness of the etch stop layer 130 is too small, in the actual process steps, if over-etching occurs, the etch stop layer 130 may be etched away and etching may continue to the part of the substrate 100 below the etch stop layer, making it impossible to maintain a high degree of uniformity in the depth of the word line trenches. If the thickness of the etch stop layer 130 is too large, the size occupied by the etch stop layer 130 in the semiconductor structure will be too large, which will increase the size of the semiconductor structure, which is not conducive to the development of semiconductor structures towards miniaturization and micro-miniaturization, and will also cause a certain amount of material waste. Therefore, the thickness of the etch stop layer 130 needs to be selected within a suitable range. When the thickness of the etch stop layer 130 is 5nm-15nm, it can keep the depth of the word line trenches uniform and keep the semiconductor structure small in size without wasting material.

[0033] Figure 1 This is a top view schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure. Figure 2 The method for manufacturing a semiconductor structure according to embodiments of this disclosure includes steps for providing a semiconductor substrate, an etch stop layer, and a semiconductor layer. Figure 1 A schematic diagram of the cross-sectional structure along the CC1 or AA1 direction. Figure 3 The step of etching isolation trenches in the semiconductor structure manufacturing method provided in this disclosure embodiment is along Figure 1 A schematic diagram of the cross-sectional structure along the CC1 direction. Figure 4 The step of etching isolation trenches in the semiconductor structure manufacturing method provided in this disclosure embodiment is along Figure 1 A schematic diagram of the cross-sectional structure along the AA1 direction. Figure 5The step of forming an isolation structure in the method for manufacturing a semiconductor structure provided in this disclosure is along... Figure 1 A schematic diagram of the cross-sectional structure along the CC1 direction. Figure 6 The step of forming an isolation structure in the method for manufacturing a semiconductor structure provided in this disclosure is along... Figure 1 A schematic diagram of the cross-sectional structure along the AA1 direction.

[0034] In some embodiments, providing the substrate 100 may include: a reference Figure 2 The system provides a semiconductor substrate 102, an etch stop layer 130, and a semiconductor layer 111 stacked sequentially. The semiconductor substrate 102 includes an array region 101. The semiconductor substrate 102 and the semiconductor layer 111 can be made of the same material. The semiconductor layer 111, located on the top surface of the etch stop layer 130, can be used in subsequent steps to form the active region 200 in the semiconductor structure. The etch stop layer 130 serves as an etch stop structure in the word trench etching step. For example, the semiconductor substrate can be a monocrystalline silicon substrate, and the semiconductor layer can be an amorphous silicon layer or a polycrystalline silicon layer, but is not limited thereto.

[0035] refer to Figures 3 to 4 The semiconductor layer 111, etch stop layer 130, and semiconductor substrate 102 of array region 101 are etched to form isolation trench 141. The semiconductor layer 111 is divided into multiple initial active regions 110 arranged in an array by the isolation trench 141. The initial active regions 110 separated by the isolation trench 141 are part of the active region 200 in the semiconductor structure. The isolation trench 141 is used to form the isolation structure 140 in subsequent steps. The isolation trench 141 penetrates the etch stop layer 130. Since the distances between adjacent initial active regions 110 are different in the AA1 direction, some adjacent initial active regions 110 are closer together and others are closer together. As a result, some isolation trenches 141 have a larger cross-sectional area on the surface of the semiconductor layer 111 and others have a smaller cross-sectional area on the surface of the semiconductor layer 111. Due to the nature of the etching process, the isolation structure 141 with a larger cross-sectional area on the surface of the semiconductor layer 111 is also deeper, and the isolation trench 141 with a smaller cross-sectional area on the surface of the semiconductor layer 111 is also shallower.

[0036] refer to Figures 5 to 6An isolation structure 140 is formed in an isolation trench 141. The semiconductor substrate 102, multiple initial active regions 110, and the isolation structure 140 constitute the substrate 100. The isolation structure 140 can fill the isolation trench 141, and the isolation structure 140 separates the multiple discrete initial active regions 110 in the semiconductor structure. Since different isolation trenches 141 have different depths in the AA1 direction, with some isolation trenches 141 being shallower and others being deeper, the depth of the formed isolation structure 140 also varies, with some isolation structures 140 being shallower and others being deeper.

[0037] In some embodiments, the isolation structure 140 may include a first isolation layer 142 and a second isolation layer 143. Forming the isolation structure 140 may include: forming the first isolation layer 142 conformally within the isolation trench 141, and forming the second isolation layer 143 on the surface of the first isolation layer 142 away from the substrate 100. The first isolation layer 142 and the second isolation layer 143 together fill the isolation trench 141. Since the isolation trench 141 has different depths in the AA1 direction, with some isolation trenches being deeper and others being shallower, when forming the first isolation layer 142, the first isolation layer 142 will first fill the shallower isolation trenches 141 in the AA1 direction, while the deeper isolation trenches 141 will also have certain gaps for forming the second isolation layer 143. Therefore, in the isolation structure 140 along the AA1 direction, the deeper isolation structure 140 has two isolation layers: a first isolation layer 142 and a second isolation layer 143, while the shallower isolation structure 140 may only have a single isolation layer, the first isolation layer 142. In the isolation structure 140 along the CC1 direction, each isolation structure 140 has a roughly uniform depth, and each isolation structure 140 may have two isolation layers: a first isolation layer 142 and a second isolation layer 143. The materials of the first isolation layer 142 and the second isolation layer 143 may be different; the first isolation layer 142 may be made of silicon oxide, and the second isolation layer 143 may be made of silicon nitride. Forming two isolation layers as the isolation structure 140 can improve the isolation effect of the isolation structure 140.

[0038] Figure 7 This is a top view schematic diagram of another semiconductor structure provided in an embodiment of this disclosure. Figures 8 to 12 Each step in the method for manufacturing a semiconductor structure provided in the embodiments of this disclosure is along Figure 7 A schematic diagram of the cross-sectional structure along the CC1 or AA1 direction. Figure 13 The step of forming isolation trenches in the semiconductor structure manufacturing method provided in this disclosure embodiment is along Figure 7 A schematic diagram of the cross-sectional structure along the CC1 direction. Figure 14 The step of forming isolation trenches in the semiconductor structure manufacturing method provided in this disclosure embodiment is along Figure 7 A schematic diagram of the cross-sectional structure along the AA1 direction. Figure 15 The step of forming an isolation structure in the method for manufacturing a semiconductor structure provided in this disclosure is along... Figure 7 A schematic diagram of the cross-sectional structure along the CC1 direction. Figure 16 The step of forming an isolation structure in the semiconductor structure manufacturing method provided in this disclosure embodiment is along Figure 7 A schematic diagram of the cross-sectional structure along the AA1 direction.

[0039] refer to Figures 7 to 16 In some embodiments, the substrate 100 may further include a peripheral region 103, which may surround the periphery of the array region 101, and the etch stop layer 130 may also be located in a portion of the region between the array region 101 and the peripheral region 103. The peripheral region 103 may be used to house peripheral circuit structures in the semiconductor structure, which can electrically connect the active region 200 to other components. In other embodiments, the semiconductor structure may not have a peripheral region 103, but only an array region 101. In this case, the peripheral circuit may be located in other regions and electrically connected to the active region 200 in the array region 101 of the semiconductor structure in other steps after the semiconductor structure is manufactured.

[0040] In some embodiments, the substrate 100 includes a peripheral region 103 and an array region 101. Providing the substrate 100 may include: a reference Figure 8 A semiconductor substrate 102 is provided, which includes an array region 101 and a peripheral region 103. The positions of the array region 101 and the peripheral region 103 in the semiconductor substrate 102 are the same as the positions of the array region 101 and the peripheral region 103 in the substrate 100.

[0041] refer to Figure 9 The semiconductor substrate 102 of the array region 101 is etched to form an array trench 112. The array trench 112 is where the active region 200 and the isolation structure 140 of the array region 101 are to be formed. Since an etch stop layer 130 needs to be formed in the array trench 112 in a subsequent step, and the top surface of the etch stop layer 130 is the area of ​​the word line trench 151, the depth of the array trench 112 can be close to the depth of the word line trench 151, that is, the depth of the array trench 112 formed can be close to the depth of the word line structure to be formed.

[0042] refer to Figure 10 An etch stop film 131 is formed, which conformally covers one side surface of the semiconductor substrate 102 having the array trench 112. The etch stop film 131 can be located in the array region 101 and the peripheral region 103.

[0043] refer to Figure 11 A semiconductor layer 111 is formed covering the surface of the etch stop film 131 located within the array trench 112, and the semiconductor layer 111 fills the array trench 112. During the formation of the semiconductor layer 111 within the array trench 112, a semiconductor layer 111 is also formed on the surface of the etch stop film 131 in the peripheral region 103 away from the semiconductor substrate 102. The semiconductor layer 111 is used to form the active region 200 of the array region 101.

[0044] refer to Figure 12 Remove the etch stop film 131 located in the peripheral region 103, and the remaining etch stop film 131 serves as the etch stop layer 130. If the semiconductor layer 111 formed in the above steps is still located on the surface of the etch stop film 131 in the peripheral region 103 away from the semiconductor substrate 102, then when removing the etch stop film 131 in the peripheral region 103, the semiconductor layer 111 located in the peripheral region 103 is also removed.

[0045] refer to Figures 13 to 14 The semiconductor layer 111, etch stop layer 130, and semiconductor substrate 102 of array region 101 are etched to form isolation trench 141. The semiconductor layer 111 is divided into multiple initial active regions 110 arranged in an array by the isolation trench 141. The initial active regions 110 separated by the isolation trench 141 are part of the active region 200 in the semiconductor structure. The isolation trench 141 is used to form the isolation structure 140 in subsequent steps. The isolation trench 141 penetrates the etch stop layer 130. Since the distances between adjacent initial active regions 110 are different in the AA1 direction, some adjacent initial active regions 110 are closer together and others are closer together. As a result, some isolation trenches 141 have a larger cross-sectional area on the surface of the semiconductor layer 111 and others have a smaller cross-sectional area on the surface of the semiconductor layer 111. Due to the nature of the etching process, the isolation structure 141 with a larger cross-sectional area on the surface of the semiconductor layer 111 is also deeper, and the isolation trench 141 with a smaller cross-sectional area on the surface of the semiconductor layer 111 is also shallower.

[0046] refer to Figures 15 to 16An isolation structure 140 is formed in an isolation trench 141. The semiconductor substrate 102, multiple initial active regions 110, and the isolation structure 140 constitute the substrate 100. The isolation structure 140 can fill the isolation trench 141, and the isolation structure 140 separates the multiple discrete initial active regions 110 in the semiconductor structure. Since different isolation trenches 141 have different depths in the AA1 direction, with some isolation trenches 141 being shallower and others being deeper, the depth of the formed isolation structure 140 also varies, with some isolation structures 140 being shallower and others being deeper.

[0047] In some embodiments, the isolation structure 140 may include a first isolation layer 142 and a second isolation layer 143. Forming the isolation structure 140 may include: forming the first isolation layer 142 conformally within the isolation trench 141, and forming the second isolation layer 143 on the surface of the first isolation layer 142 away from the substrate 100, wherein the first isolation layer 142 and the second isolation layer 143 together fill the isolation trench 141. The materials of the first isolation layer 142 and the second isolation layer 143 may be different; the first isolation layer 142 may be made of silicon oxide, and the second isolation layer 143 may be made of silicon nitride. Forming two isolation layers as the isolation structure 140 can improve the isolation effect of the isolation structure 140.

[0048] The following describes the subsequent steps using the example of a substrate 100 including a peripheral region 103 and an array region 101. The subsequent steps for a substrate 100 that only includes an array region 101 are generally similar to those for a substrate 100 that includes both a peripheral region 103 and an array region 101, and will not be repeated here. Figure 17 The word line trench etching step in the semiconductor structure manufacturing method provided in this disclosure embodiment is along Figure 7 A schematic diagram of the cross-sectional structure along the CC1 direction. Figure 18 The word line trench etching step in the semiconductor structure manufacturing method provided in this disclosure embodiment is along Figure 7 A schematic diagram of the cross-sectional structure along the AA1 direction.

[0049] refer to Figures 17 to 18 The isolation structure 140 and the initial active region 110 are etched until the etch stop layer 130 beneath the initial active region 110 is exposed, forming a word line trench 151. The initial active region 110 is divided into at least two adjacent active pillars 113 by the word line trench 151. The word line trench 151 extends along... Figure 7Extending along the AA1 direction shown, the initial active region 110 and the isolation structure 140 on the top surface of the etch stop layer 130 are both etched away in the AA1 direction, and the portion of the isolation structure 140 below the bottom surface of the etch stop layer 130 is also etched away to form a word line trench 151. In the CC1 direction, the portion of the initial active region 110 on the top surface of the etch stop layer 130 is removed to form the word line trench 151, and the removed portion of the initial active region 110 is located on both sides of the isolation structure 140. Since etching can be stopped once the top surface of the etch stop layer 130 is reached during the etching process to form the word line trench 151, the uniformity of the depth of the word line trench 151 can be ensured, thereby ensuring the uniformity of the word line structure depth, improving the electrical stability of the semiconductor structure, and increasing the lifespan of the semiconductor structure.

[0050] Figure 19 The step of removing part of the etch stop layer in the semiconductor structure manufacturing method provided in the embodiments of this disclosure is along Figure 7 A schematic diagram of the cross-sectional structure along the CC1 direction. Figure 20 The step of removing part of the etch stop layer in the semiconductor structure manufacturing method provided in the embodiments of this disclosure is along Figure 7 A schematic diagram of the cross-sectional structure along the AA1 direction.

[0051] To enable electrical connection between the semiconductor layer 111 located above the top surface of the etch stop layer 130 and the semiconductor substrate 102 located below the etch stop layer 130, some processing is required. (See reference...) Figures 19 to 20 At least the etch stop layer 130 exposed on the bottom surface of the word line trench 151 is removed. In the CC1 direction, while removing the etch stop layer 130 exposed on the bottom surface of the word line trench 151, a portion of the etch stop layer 130 located between the active pillar 113 and the semiconductor substrate 102 may also be removed. In the AA1 direction, the etch stop layer 130 located within the word line trench 151 is removed.

[0052] Figure 21 The method for manufacturing a semiconductor structure provided in this disclosure includes a step of forming an initial epitaxial layer along... Figure 7 A schematic diagram of the cross-sectional structure along the CC1 direction. Figure 22 The method for manufacturing a semiconductor structure provided in this disclosure includes a step of forming an initial epitaxial layer along... Figure 7 A schematic diagram of the cross-sectional structure along the AA1 direction. Figure 23 The method for manufacturing a semiconductor structure according to embodiments of this disclosure includes a step of forming an epitaxial layer along... Figure 7 A schematic diagram of the cross-sectional structure along the CC1 direction. Figure 24 The method for manufacturing a semiconductor structure according to embodiments of this disclosure includes a step of forming an epitaxial layer along... Figure 7 A schematic diagram of the cross-sectional structure along the AA1 direction. Figure 25In the method for manufacturing a semiconductor structure provided in this disclosure, the step of forming the first epitaxial layer is along... Figure 7 A schematic diagram of the cross-sectional structure along the CC1 direction. Figure 26 In the method for manufacturing a semiconductor structure provided in this disclosure, the step of forming the first epitaxial layer is along... Figure 7 A schematic diagram of the cross-sectional structure along the AA1 direction. Figure 27 The step of removing the epitaxial barrier layer in the semiconductor structure manufacturing method provided in this disclosure embodiment is along Figure 7 A schematic diagram of the cross-sectional structure along the CC1 direction. Figure 28 The step of removing the epitaxial barrier layer in the semiconductor structure manufacturing method provided in this disclosure embodiment is along Figure 7 A schematic diagram of the cross-sectional structure along the AA1 direction. Figure 29 In the method for manufacturing a semiconductor structure provided in this disclosure, the step of forming the second epitaxial layer is along... Figure 7 A schematic diagram of the cross-sectional structure along the CC1 direction. Figure 30 In the method for manufacturing a semiconductor structure provided in this disclosure, the step of forming the second epitaxial layer is along... Figure 7 A schematic diagram of the cross-sectional structure along the AA1 direction. Figure 31 The recrystallization step in the semiconductor structure manufacturing method provided in the embodiments of this disclosure follows Figure 7 A schematic diagram of the cross-sectional structure along the CC1 direction. Figure 32 The recrystallization step in the semiconductor structure manufacturing method provided in the embodiments of this disclosure follows Figure 7 A schematic diagram of the cross-sectional structure along the AA1 direction.

[0053] refer to Figures 21 to 32 An epitaxial layer 163 is formed on the substrate 100 exposed at the bottom surface of the word line trench 151. The top surface of the epitaxial layer 163 is higher than the bottom surface of the active pillar 113, and the epitaxial layer 163 is in contact with the side surfaces of at least two adjacent active pillars 113. The epitaxial layer 163 can connect the active pillars 113 and the semiconductor substrate 102.

[0054] In some embodiments, forming an epitaxial layer 163 on the substrate 100 exposed at the bottom surface of the word line trench 151 includes: referencing Figures 21 to 24 An epitaxial barrier layer 170 is formed, which is located on the sidewall of the active pillar 113 exposed in the word trench 151. The epitaxial barrier layer 170 is used to ensure that when an epitaxial layer is formed in a subsequent step using an epitaxial growth method, the epitaxial layer is grown only on the bottom surface of the semiconductor substrate 102 within the word trench 151, preventing the epitaxial layer from growing into other areas.

[0055] In some embodiments, forming the epitaxial barrier layer 170 includes: a reference Figures 21 to 22This forms an initial epitaxial barrier layer 171 that conforms to the shape of the character line groove 151. The initial epitaxial barrier layer 171 can cover the bottom and sides of the character line groove 151.

[0056] refer to Figures 23 to 24 The initial epitaxial barrier layer 171 located on the bottom surface of the word line trench 151 is removed, and the remaining initial epitaxial barrier layer 171 serves as the epitaxial barrier layer 170. Since an epitaxial layer 163 needs to be grown at the bottom surface of the word line trench 151 so that the active pillar 113 and the semiconductor substrate 102 can be connected, the initial epitaxial barrier layer 171 located on the bottom surface of the word line trench 151 needs to be removed, while the initial epitaxial barrier layer 171 located on the side surface of the word line trench 151 is retained, so that the epitaxial layer is grown only on the bottom surface of the word line trench 151.

[0057] refer to Figures 25 to 26 A first epitaxial layer 161 is formed, which is located on the substrate 100 exposed at the bottom surface of the word line trench 151 and is also in contact with the epitaxial barrier layer 170 on the sidewall of the word line trench 151. The material of the first epitaxial layer 161 can be polycrystalline silicon, and the method for forming the first epitaxial layer 161 can be epitaxial growth.

[0058] In other embodiments, a deposition process may also be used to form the first epitaxial layer 161.

[0059] Because an epitaxial barrier layer 170 exists between the first epitaxial layer 161 and the active pillar 113, electrical connection between the first epitaxial layer 161 and the active pillar 113 cannot be achieved. Therefore, further processing is required. (Reference) Figures 27 to 28 The epitaxial barrier layer 170 on the sidewall of the word line trench 151 is removed. The method for removing the epitaxial barrier layer 170 on the sidewall of the word line trench 151 can be a wet etching method. However, removing the epitaxial barrier layer 170 on the sidewall of the word line trench 151 may cause some damage to the side surface of the active pillar 113.

[0060] refer to Figures 29 to 30 A second epitaxial layer 162 is formed on the first epitaxial layer 161. The second epitaxial layer 162 is in contact with at least two adjacent active pillars 113. The first epitaxial layer 161 and the second epitaxial layer 162 constitute an epitaxial layer 163. The material of the second epitaxial layer 162 can be polycrystalline silicon, and the method for forming the second epitaxial layer 162 can be epitaxial growth. The second epitaxial layer 162 can connect the first epitaxial layer 161 and the active pillars 113, thereby connecting the semiconductor substrate 102 and the active pillars 113. Furthermore, during the formation of the second epitaxial layer 162, a portion of polycrystalline silicon can be grown on the sidewalls of the active pillars 113, thereby repairing the sidewall surfaces of the active pillars 113 damaged in the previous wet etching process.

[0061] refer to Figures 31 to 32 The epitaxial layer 163 and the active pillar 113 are recrystallized to form a single-crystal active region. Before recrystallization, the active pillar 113 and the epitaxial layer 163 in the semiconductor structure are both amorphous or polycrystalline, while the recrystallized active region 200 is single-crystal. The recrystallized active region 200 includes a first active region 114 and a second active region 160, wherein the recrystallized active pillar 113 is the first active region 114, and the recrystallized epitaxial layer 163 is the second active region 160. For example, the materials of the first epitaxial layer 161, the second epitaxial layer 162, and the active pillar 113 can be amorphous silicon or polycrystalline silicon, and after the recrystallization step, the materials of the first active region 114 and the second active region 160 can be single-crystal silicon. Both the single-crystal first active region 114 and the second active region 160 can serve as the active region 200 in the semiconductor structure. The recrystallization process can be an annealing process, and the annealing temperature can be greater than or equal to 900℃. For example, the annealing temperature for recrystallization can be 900℃, 1000℃, 1100℃, 1200℃, etc.

[0062] Figure 33 The step of forming a dielectric layer in the manufacturing method of the semiconductor structure provided in the embodiments of this disclosure is along Figure 7 A schematic diagram of the cross-sectional structure along the CC1 direction. Figure 34 The step of forming a dielectric layer in the manufacturing method of the semiconductor structure provided in the embodiments of this disclosure is along Figure 7 A schematic diagram of the cross-sectional structure along the AA1 direction. Figure 35 The step of forming a word line layer in the manufacturing method of the semiconductor structure provided in the embodiments of this disclosure is along Figure 7 A schematic diagram of the cross-sectional structure along the CC1 direction. Figure 36 The step of forming a word line layer in the manufacturing method of the semiconductor structure provided in the embodiments of this disclosure is along Figure 7 A schematic diagram of the cross-sectional structure along the AA1 direction. Figure 37 In the method for manufacturing a semiconductor structure provided in this disclosure, the step of forming a word line capping layer is along... Figure 7 A schematic diagram of the cross-sectional structure along the CC1 direction. Figure 38 In the method for manufacturing a semiconductor structure provided in this disclosure, the step of forming a word line capping layer is along... Figure 7 A schematic diagram of the cross-sectional structure along the AA1 direction.

[0063] refer to Figures 33 to 38 A word line structure 150 is formed within the word line trench 151. The word line structure 150 is used for electrical connection with the gate in the active region 200.

[0064] In some embodiments, the step of forming the word line structure 150 may include: referring to Figures 33 to 34A dielectric layer 152 is formed to cover the word line trench 151 in a conformal manner. The dielectric layer 152 is located between the active region 200 and the word line layer 153, and the material of the dielectric layer 152 may include silicon oxide.

[0065] refer to Figures 35 to 36 A word line layer 153 is formed, which is located on a portion of the surface of the dielectric layer 152 away from the substrate 100, and fills a portion of the word line trench 151. In the CC1 direction, the word line layer 153 is located on the top surface of the second active region 160, and also in a portion of the region between two adjacent first active regions 114. In the AA1 direction, the word line layer 153 fills the gaps in the word line trench 151 in the semiconductor substrate 102 and the second active region 160, and also fills a portion of the word line trench 151 extending along the AA1 direction.

[0066] refer to Figures 37 to 38 A word line capping layer 154 is formed, which is located on the surface of the word line layer 153 away from the substrate 100, and fills the word line trench 151. The word line capping layer 154 fills the word line trench 151, and the material of the word line capping layer 154 may include silicon nitride.

[0067] This disclosure provides a method for manufacturing a semiconductor structure. First, a substrate including an array region is provided. The array region includes multiple initially active regions arranged in an array and isolation structures separating the initial active regions. An etch stop layer is also provided within the array region. The isolation structures penetrate the etch stop layer. When etching the substrate to form word line trenches, etching can be performed with the etch stop layer as a reference, stopping the etching of the word line trenches when the top surface of the etch stop layer is reached. This ensures that the depth of each word line trench within the substrate tends to be consistent, thereby improving the uniformity of the word line structure depth, enhancing the electrical stability of the semiconductor structure, and increasing the lifespan of the semiconductor structure.

[0068] Accordingly, another embodiment of this disclosure also provides a semiconductor structure, which is manufactured by the semiconductor structure manufacturing method described above. The semiconductor structure provided by another embodiment of this disclosure will be described in detail below with reference to the accompanying drawings. For parts that are the same as or corresponding to the previous embodiment, please refer to the corresponding descriptions of the foregoing embodiments; detailed descriptions will not be repeated below.

[0069] refer to Figure 1 , Figure 7 as well as Figures 39 to 42The semiconductor structure includes: a substrate 100, including an array region 101, the array region 101 including a plurality of active regions 200 arranged in an array and an isolation structure 140 defining the plurality of active regions 200, each active region 200 including at least two adjacent first active pillars 210 and a second active pillar 220 located between at least two adjacent first active pillars 210; an etch stop layer 130 disposed within the substrate 100, including a plurality of first etch stop portions 132, each first etch stop portion 132 located directly below a first active pillar 210, the bottom surface of the first active pillar 210 being between the top surface and the bottom surface of the second active pillar 220, and the second active pillar 220 covering the side surface of the first etch stop portion 132; and a word line structure 150, the word line structure 150 spanning the active regions 200 and the isolation structure 140, the word line structure 150 covering the side surface of the first active pillars 210 and the top surface of the second active pillars 220.

[0070] The second active pillar 220 enables the first active pillar 210 to connect with the substrate 100 below. Furthermore, since the substrate 100 has an etch stop layer 130 (forming a first etch stop portion 132 after etching) during the formation of the semiconductor structure, the uniformity of the depth of the word line structure 150 in the semiconductor structure is high, and the depth of the word line structure 150 extending into the substrate 100 tends to be consistent.

[0071] Figure 1 This is a top view schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure. Figure 39 for Figure 1 A schematic diagram of the cross-sectional structure along the CC1 direction. Figure 40 for Figure 1 A schematic diagram of the cross-sectional structure along the AA1 direction.

[0072] refer to Figure 1 as well as Figures 39 to 40 The substrate 100 may only have an array region 101. Multiple discrete active regions 200 are arranged in an array within the array region 101 on the substrate 100, and an isolation structure 140 surrounds the active regions 200, with an isolation structure 140 between every two adjacent active regions 200. The active regions 200 are transistors in a semiconductor structure. The material of the isolation structure 140 may include one or more of silicon oxide or silicon nitride.

[0073] Figure 7 This is a top view schematic diagram of another semiconductor structure provided in an embodiment of this disclosure. Figure 41 for Figure 7 A schematic diagram of the cross-sectional structure along the CC1 direction. Figure 42 for Figure 7 A schematic diagram of the cross-sectional structure along the AA1 direction.

[0074] refer to Figure 7as well as Figures 41 to 42 In some embodiments, the substrate 100 may further include a peripheral region 103 surrounding the array region 101; the etch stop layer 130 further includes a second etch stop portion 133 located at the boundary between the array region 101 and the peripheral region 103. The peripheral region 103 can be used to house peripheral circuit structures in the semiconductor structure, which can electrically connect the active region 200 to other components. In other embodiments, the semiconductor structure may not have a peripheral region 103, but only an array region 101. In this case, the peripheral circuit can be located in other regions and electrically connected to the active region 200 in the array region 101 of the semiconductor structure in other steps after the semiconductor structure is manufactured.

[0075] In some embodiments, the isolation structure 140 may include a first isolation layer 142 and a second isolation layer 143. Forming the isolation structure 140 may include: forming the first isolation layer 142 conformally within the isolation trench 141, and forming the second isolation layer 143 on the surface of the first isolation layer 142 away from the substrate 100, wherein the first isolation layer 142 and the second isolation layer 143 together fill the isolation trench 141. The materials of the first isolation layer 142 and the second isolation layer 143 may be different; the first isolation layer 142 may be made of silicon oxide, and the second isolation layer 143 may be made of silicon nitride. Forming two isolation layers as the isolation structure 140 can improve the isolation effect of the isolation structure 140.

[0076] When the second etch stop portion 133 and the first etch stop portion 132 are in a substrate 100 having a peripheral region 103 and an array region 101, the etch stop layer 130 left in the semiconductor structure after the semiconductor structure is manufactured using the semiconductor structure manufacturing method provided in this embodiment can maintain the uniformity of the depth of the word line trench 151 when forming the word line trench 151, thereby enabling the depth of the word line structure 150 in the manufactured semiconductor structure to have high uniformity, making the electrical properties of the semiconductor structure more stable, and enabling the semiconductor structure to have a longer service life.

[0077] In some embodiments, the word line structure 150 may include a dielectric layer 152, a word line layer 153, and a word line capping layer 154. The dielectric layer 152 is located between the word line layer 150 and the first active post 210, and between the word line layer 153 and the second active post 220. The word line capping layer 154 is located on the surface of the word line layer 153 away from the second active post 220. The word line structure 150 along... Figure 1 or Figure 7 The AA1 direction shown extends as indicated.

[0078] This disclosure provides a semiconductor structure including a substrate, an array region within the substrate, and multiple active regions arranged in an array within the array region, as well as isolation structures defining the multiple active regions. Each active region includes at least two adjacent first active pillars and a second active pillar located between the at least two adjacent first active pillars. The substrate also includes an etch stop layer, which includes multiple first etch stop portions located directly below each first active pillar. A word line structure spans the active regions and the isolation structures. Since the etch stop layer serves as a reference structure for etching word line trenches during the fabrication of the semiconductor structure provided in this disclosure, etching stops when the word line trenches reach the etch stop portions. This ensures that the depth of each etched word line trench within the substrate tends to be consistent, thereby improving the uniformity of the word line structure depth, enhancing the electrical stability of the semiconductor structure, and increasing the lifespan of the semiconductor structure.

[0079] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including an array region, the array region including a plurality of initial active regions arranged in an array and an isolation structure separating adjacent initial active regions, the array region having an etch stop layer, and the isolation structure penetrating the etch stop layer; The isolation structure and the initial active region are etched until the etch stop layer below the initial active region is exposed to form a word line trench, wherein the initial active region is divided into at least two adjacent active pillars by the word line trench. At least the etch stop layer exposed at the bottom surface of the word line trench must be removed; An epitaxial layer is formed on the substrate exposed at the bottom surface of the word line groove, the top surface of the epitaxial layer is higher than the bottom surface of the active post, and the epitaxial layer is in contact with the side surfaces of at least two adjacent active posts. The epitaxial layer and the active pillar are recrystallized to form a single-crystal active region; A character line structure is formed within the character line groove.

2. The manufacturing method according to claim 1, characterized in that, The thickness of the etching stop layer is 5nm-15nm.

3. The manufacturing method according to claim 1, characterized in that, Forming an epitaxial layer on the substrate exposed at the bottom surface of the character line groove includes: An epitaxial barrier layer is formed, the epitaxial barrier layer being located on the sidewall of the active post exposed by the word line groove; A first epitaxial layer is formed on the substrate exposed at the bottom surface of the word line trench, and is also in contact with the epitaxial barrier layer of the sidewall of the word line trench; Remove the extended barrier layer from the sidewall of the word line groove; A second epitaxial layer is formed on the first epitaxial layer, and the second epitaxial layer is in contact with the side surfaces of the at least two adjacent active pillars. The first epitaxial layer and the second epitaxial layer constitute the epitaxial layer.

4. The manufacturing method according to claim 3, characterized in that, Forming the epitaxial barrier layer includes: An initial epitaxial barrier layer is formed to conformally cover the word line grooves; Remove the initial epitaxial barrier layer located at the bottom of the word line groove, and the remaining initial epitaxial barrier layer serves as the epitaxial barrier layer.

5. The manufacturing method according to claim 1, characterized in that, The substrate includes: A semiconductor substrate, an etch stop layer, and a semiconductor layer are provided in sequence, wherein the semiconductor substrate includes an array region; The semiconductor layer, the etch stop layer, and the semiconductor substrate of the array region are etched to form an isolation trench, wherein the semiconductor layer is divided by the isolation trench into a plurality of initial active regions arranged in an array; The isolation structure is formed in the isolation trench, and the semiconductor substrate, the plurality of initial active regions, and the isolation structure constitute the substrate.

6. The manufacturing method according to claim 1, characterized in that, The substrate also includes a peripheral region surrounding the periphery of the array region, and the etch stop layer is located in a portion of the region between the array region and the peripheral region.

7. The manufacturing method according to claim 6, characterized in that, The substrate includes: A semiconductor substrate is provided, the semiconductor substrate including an array region and a peripheral region; The semiconductor substrate of the array region is etched to form array trenches; An etch stop film is formed, which conformally covers one side surface of the semiconductor substrate having the array trenches; A semiconductor layer is formed covering the surface of the etch stop film located within the array trenches, the semiconductor layer filling the array trenches; Remove the etching stop film located in the peripheral region, and the remaining etching stop film serves as the etching stop layer; The semiconductor layer, the etch stop layer, and the semiconductor substrate of the array region are etched to form an isolation trench, wherein the semiconductor layer is divided by the isolation trench into a plurality of initial active regions arranged in an array; The isolation structure is formed in the isolation trench, and the semiconductor substrate, the plurality of initial active regions, and the isolation structure constitute the substrate.

8. The manufacturing method according to claim 1, characterized in that, Forming the word line structure includes: A dielectric layer is formed that conformally covers the word line grooves; A word line layer is formed, the word line layer being located on a portion of the surface of the dielectric layer away from the substrate, and the word line layer filling a portion of the word line trench; A character line capping layer is formed, the character line capping layer being located on the surface of the character line layer away from the substrate, and the character line capping layer filling the character line groove.

9. A semiconductor structure, characterized in that, include: The substrate includes an array region, which includes multiple active regions arranged in an array and an isolation structure defining the multiple active regions. Each active region includes at least two adjacent first active pillars and a second active pillar located between the at least two adjacent first active pillars. An etch stop layer is disposed within the substrate and includes a plurality of first etch stop portions. Each first etch stop portion is located directly below a first active post. The bottom surface of the first active post is located between the top and bottom surfaces of the second active post. The second active post covers the side surface of the first etch stop portion. A word line structure, which spans the active area and the isolation structure, and covers the side surface of the first active post and the top surface of the second active post.

10. The semiconductor structure according to claim 9, characterized in that, The substrate further includes a peripheral region that surrounds the array region; The etching stop layer also includes a second etching stop portion located at the boundary between the array region and the peripheral region.

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