Receiver, electronic device, and eye pattern detection method in receiver

Abstract

The present application provides a receiver, an electronic device, and an eye diagram detection method in the receiver, which relates to the field of electronic technology and is used to solve the problem of the inability to display sudden bit errors in the prior art. The receiver includes two signal paths, namely a first signal path and a second signal path. The first signal path is a signal conversion path for normal business; the second signal path is an eye diagram detection path for drawing an eye diagram. In the receiver, the second signal path uses the clock signal recovered by the clock data recovery unit in the first signal path to perform phase shift, and draws an eye diagram by collecting the digital signal sampled and output by the second signal path, which can intuitively reflect the quality of the received signal. By processing the eye diagram, a corresponding control signal is obtained, and the parameters of the signal processing system are adjusted, thereby reducing the bit error rate of the signal and improving the reliability of the signal system.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a receiver, an electronic device, and an eye diagram detection method in the receiver. Background Art

[0002] In high-speed serial digital signal systems, noise such as inter-symbol interference (ISI) and crosstalk can affect the bit error rate (BER) during signal reception. To measure the performance of digital signal systems, eye diagrams can be used to observe the waveform of received signals and analyze the impact of ISI and other noise on signal system performance.

[0003] Some current receivers use probabilistic principles to draw eye diagrams, but instead of using the original sampled data, they have statistical errors and cannot display sudden bit errors in the eye diagram. Some receivers use a single analog-to-digital converter (ADC) architecture to draw eye diagrams, but cannot draw eye diagrams when there is a frequency offset between the transmit digital-to-analog converter (TX_DAC) and the receive analog-to-digital converter (RX_ADC). Summary of the Invention

[0004] The present application provides a receiver, an electronic device, and an eye diagram detection method in the receiver, which are used to solve the problems in the prior art of being unable to display sudden bit errors and unable to draw eye diagrams. By directly drawing the eye diagram using a sampled signal, the signal processing parameters are adjusted according to the quality of the eye diagram, thereby reducing the signal bit error rate and improving the performance and reliability of the receiver.

[0005] In a first aspect, the present application provides a receiver. The receiver includes a first signal path and a second signal path. The first signal path includes a first analog-to-digital converter and a first clock data recovery unit. The input end of the first clock data recovery unit is connected to the output end of the first analog-to-digital converter, and is used to generate a first phase control word based on the digital signal output by the first analog-to-digital converter. The second signal path includes a second analog-to-digital converter, a second phase interpolator, and a second eye diagram monitor. The input end of the second phase interpolator is connected to the output end of the first clock data recovery unit, and is used to receive the first phase control word and generate a second clock based on the first phase control word. The clock input end of the second analog-to-digital converter is connected to the output end of the second phase interpolator, and is used to receive the second clock and output a digital signal based on the second clock sampling. The input end of the second eye diagram monitor is connected to the output end of the second analog-to-digital converter, and is used to collect the digital signal output by the second analog-to-digital converter based on the second clock sampling, and draw an eye diagram based on the digital signal output by the second analog-to-digital converter.

[0006] This receiver includes two signal paths: a first signal path and a second signal path. The first signal path is a signal conversion path for normal services; the second signal path is an eye diagram detection path for drawing eye diagrams. In this receiver, the second signal path uses the clock signal recovered by the clock data recovery unit in the first signal path to perform phase adjustment. By sampling the digital signal sampled and output by the second signal path, an eye diagram is drawn, which can intuitively reflect the quality of the received signal. By processing the eye diagram, corresponding control signals are generated, which are used to adjust the parameters of the signal processing system, thereby reducing the signal bit error rate and improving the reliability of the signal system.

[0007] Optionally, the first signal path may further include a first phase interpolator. The input end of the first phase interpolator is connected to the output end of the first clock data recovery unit, and is used to receive the first phase control word and generate the first clock according to the first clock bias signal and the first phase control word. The clock input end of the first analog-to-digital converter is connected to the output end of the first phase interpolator, and is used to receive the first clock and output a digital signal according to the first clock sampling. In this way, the first signal path that handles normal signal conversion business can adjust the sampling clock in the analog-to-digital converter in real time through the eye diagram status information fed back by the second signal path, thereby improving the performance and reliability of the receiver.

[0008] In one possible implementation, the second signal path may further include a second clock data recovery unit. The input of the second clock data recovery unit is connected to the output of the second analog-to-digital converter and is configured to generate a second phase control word based on the digital signal output by the second analog-to-digital converter. The outputs of the first and second clock data recovery units are connected to the input of a second phase interpolator via a first selector. This allows the second signal path to perform signal conversion for normal service when not serving as an eye pattern detection path, thereby increasing the signal processing flexibility of the receiver.

[0009] Optionally, the first signal path may further include a first eye diagram monitor. The output of the first clock data recovery unit and the output of the second clock data recovery unit are connected to the input of the first phase interpolator via a second selector. The input of the first eye diagram monitor is connected to the output of the first analog-to-digital converter, and is used to collect the digital signal output by the first analog-to-digital converter and draw an eye diagram based on the digital signal output by the first analog-to-digital converter. In this way, the first signal path and the second signal path can serve as eye diagram detection paths for each other, providing signal quality adjustment guidance for normal service paths, thereby improving the quality of signal transmission and enhancing the performance and reliability of the receiver.

[0010] Optionally, the first signal path may further include a first equalizer. The first equalizer is connected to the output of the first analog-to-digital converter. A first eye diagram monitor is also connected to the output of the first equalizer and is configured to collect the digital signal output by the first equalizer and draw an eye diagram based on the digital signal output by the first equalizer. This allows the eye diagrams of the digital signals output before and after the first equalizer to be compared to determine the signal conditioning benefit achieved by the equalizer. The equalization parameters of the equalizer in the signal conversion path for normal services can then be adjusted based on the equalization parameters in the first equalizer.

[0011] Optionally, the second signal path may further include a second equalizer. The second equalizer is connected to the output of the second analog-to-digital converter. A second eye diagram monitor is also connected to the output of the second equalizer and is configured to collect the digital signal output by the second equalizer and draw an eye diagram based on the digital signal output by the second equalizer. This allows the eye diagrams of the digital signals output before and after the second equalizer to be compared to determine the signal conditioning benefit achieved by the equalizer. The equalization parameters of the equalizer in the signal conversion path for normal service can then be adjusted based on the equalization parameters in the second equalizer.

[0012] In one possible implementation, the second ADC may include at least one sub-ADC, where the sub-ADC in the second ADC is identical to the sub-ADC in the first ADC. This allows eye diagram detection to be performed without affecting normal signal conversion.

[0013] In a second aspect, the present application provides an electronic device comprising: a transceiver chip and any possible receiver as described in the first aspect above, wherein the receiver is provided in the transceiver chip.

[0014] Optionally, the electronic device may further include a baseband processing chip coupled to the transceiver chip.

[0015] In a third aspect, the present application provides an eye diagram detection method in a receiver. The method is applied to any possible receiver as described in the first aspect above. The method includes: a first analog-to-digital converter and a second analog-to-digital converter receive the same analog signal. A second phase interpolator receives a first phase control word output by a first clock data recovery unit. The second phase interpolator generates a second clock based on a second clock bias signal and the first phase control word. The second clock bias signal is used to adjust the sampling clock of the second analog-to-digital converter. The second analog-to-digital converter samples and outputs a digital signal based on the second clock. A second eye diagram monitor collects the digital signal output by the second analog-to-digital converter and draws a first eye diagram based on the second clock bias signal and the digital signal output by the second analog-to-digital converter.

[0016] Optionally, the second clock offset signal includes a plurality of signals, and a value range of the second clock offset signal may be -0.5 unit interval UI to 0.5 UI.

[0017] Optionally, the step size of the second clock bias signal may be 0.01 UI.

[0018] In one possible implementation, the method may further include: a first phase interpolator receiving a first phase control word output by a first clock data recovery unit. The first phase interpolator generates a first clock based on a first clock offset signal and the first phase control word. A first analog-to-digital converter samples and outputs a digital signal based on the first clock. The first clock offset signal is determined based on a first eye diagram.

[0019] In one possible implementation, the second signal path may further include a second equalizer connected to the output of the second analog-to-digital converter; and the second eye pattern monitor is further connected to the output of the second equalizer. The method may further include: the second equalizer receiving the digital signal output by the second analog-to-digital converter and generating multiple sets of equalized digital signals; the second eye pattern monitor collecting the equalized digital signal output by the second equalizer; the second eye pattern monitor drawing a second eye pattern based on the second clock offset signal and the equalized digital signal; and the second eye pattern monitor comparing the first eye pattern with the second eye pattern.

[0020] It can be understood that any of the electronic devices and eye diagram detection methods in the receiver provided above can be implemented by the corresponding receiver provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the receiver provided in the first aspect above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 Schematic diagram of the structure of the electronic device provided in the embodiment of the present application Figure 1 ;

[0022] Figure 2 Schematic diagram of the structure of the electronic device provided in the embodiment of the present application Figure 2 ;

[0023] Figure 3 Schematic diagram of the structure of the electronic device provided in the embodiment of the present application Figure 3 ;

[0024] Figure 4 Schematic diagram of the circuit structure of the receiver provided in the embodiment of the present application Figure 1 ;

[0025] Figure 5 Schematic diagram of the circuit structure of the receiver provided in the embodiment of the present application Figure 2 ;

[0026] Figure 6 Schematic diagram of the circuit structure of the receiver provided in the embodiment of the present application Figure 3 ;

[0027] Figure 7 Schematic diagram of the circuit structure of the receiver provided in the embodiment of the present application Figure 4 ;

[0028] Figure 8 Schematic diagram of the receiver circuit provided in the embodiment of the present application Figure 5 ;

[0029] Figure 9 A flowchart of an eye diagram detection method in a receiver provided in an embodiment of the present application;

[0030] Figure 10 A flowchart of drawing an eye diagram in a receiver is provided in an embodiment of the present application.

[0031] Among them, 100-first signal path; 200-second signal path; 101-first analog-to-digital converter; 102-first clock data recovery unit; 103-first phase interpolator; 104-first equalizer; 105-first eye diagram monitor; 106-first control module; 107-second selector; 108-first adder; 201-second analog-to-digital converter; 202-second clock data recovery unit; 203-second phase interpolator; 204-second equalizer; 205-second eye diagram monitor; 206-second control module; 207-first selector; 208-second adder. DETAILED DESCRIPTION

[0032] The following describes the technical terms involved in the embodiments of the present application.

[0033] (1) Eye diagram

[0034] The digital communication symbols displayed on an oscilloscope screen are formed by overlapping waveforms, resembling an eye. A large eye indicates good signal quality; a small eye indicates high noise levels, such as intersymbol interference, leading to poor signal quality.

[0035] (2) Eye diagram analysis method

[0036] To measure the performance of digital signal transmission systems, an oscilloscope is often used to observe the received signal waveform to analyze signal quality, paying particular attention to the impact of inter-symbol interference, optoelectronic noise, and other noise on system performance. This is the eye diagram analysis method.

[0037] In the present application, "at least one" means one or more, and "more" means two or more. "And / or" describes the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, ab, ac, bc or abc, where a, b and c can be single or multiple. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. In addition, in the embodiments of the present application, the words "first", "second" and so on do not limit the quantity and execution order.

[0038] It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0039] In this application, unless otherwise specified or limited, the term "connection" should be understood broadly. For example, "connection" can mean fixed connection, detachable connection, or integration; it can mean direct connection or indirect connection through an intermediate medium. In addition, the term "coupling" can refer to the method of electrical connection for signal transmission. "Coupling" can mean direct electrical connection or indirect electrical connection through an intermediate medium.

[0040] Figure 1 Schematic diagram of the structure of the electronic device provided in the embodiment of the present application Figure 1 The electronic device may be a router or a switch. Figure 1 As shown, the electronic device includes at least one signal sending channel and at least one signal receiving channel.

[0041] For the signal transmission channel, the electrical signal passes through the digital to analog converter (DAC) in the optical module and then sends the signal to the transmitter optical subassembly (TOSA). The TOSA converts the electrical signal into an optical signal and then transmits the optical signal through the optical fiber.

[0042] For the signal receiving channel, when the optical signal sent by the optical fiber is received, the received optical signal is converted into an electrical signal by the receiver optical subassembly (ROSA), and then received by the analog to digital converter (ADC) in the optical module to realize the signal reception processing. Figure 1 The electronic equipment can realize the mutual conversion between optical signals and electrical signals, and can send and receive signals through optical fibers.

[0043] Figure 2 Schematic diagram of the structure of the electronic device provided in the embodiment of the present application Figure 1 The electronic device may be a terminal or a base station. Figure 2 As shown, the electronic device may include an application subsystem, memory, massive storage, a baseband subsystem, a radio frequency integrated circuit (RFIC), a radio frequency front end (RFFE) device, and an antenna (ANT), which may be coupled through various interconnection buses or other electrical connection methods.

[0044] Figure 2 In the figure, ANT_1 represents the first antenna, ANT_N represents the Nth antenna, and N is a positive integer greater than 1. Tx represents the transmit path, Rx represents the receive path, and different numbers represent different paths. FBRx represents the feedback receive path, PRx represents the main receive path, and DRx represents the diversity receive path. HB represents high frequency, and LB represents low frequency, both of which refer to the relative high and low frequencies. BB represents baseband. It should be understood that Figure 1 The marks and components are for illustration purposes only and are only used as one possible implementation method. The embodiments of the present application also include other implementation methods.

[0045] The application subsystem can serve as the main control system or main computing system of the wireless communication device, running the main operating system and application programs, managing the software and hardware resources of the entire wireless communication device, and providing a user interface for the user. The application subsystem may include one or more processing cores. In addition, the application subsystem may also include driver software related to other subsystems (such as the baseband subsystem). The baseband subsystem may also include one or more processing cores, as well as a hardware accelerator (HAC) and cache.

[0046] Figure 2In the figure, RFFE devices, RFIC 1 (and optional RFIC 2) can together constitute the RF subsystem. The RF subsystem can be further divided into an RF receive path and an RF transmit path. The RF receive path can receive RF signals through an antenna, process the RF signals (such as amplification, filtering and down-conversion) to obtain baseband signals, and pass them to the baseband subsystem. The RF transmit path can receive baseband signals from the baseband subsystem, perform RF processing (such as up-conversion, amplification and filtering) on ​​the baseband signals to obtain RF signals, and finally radiate the RF signals into space through the antenna. Specifically, the RF subsystem may include electronic devices such as an antenna switch, an antenna tuner, a low noise amplifier (LNA), a power amplifier (PA), a mixer, a local oscillator (LO), and a filter. These electronic devices can be integrated into one or more chips as needed. The antenna can sometimes also be considered as part of the RF subsystem.

[0047] The baseband subsystem extracts useful information or data bits from baseband signals or converts them into baseband signals to be transmitted. These information or data bits can represent user data such as voice, text, and video, or control information. For example, the baseband subsystem performs signal processing operations such as modulation and demodulation, encoding, and decoding. Different radio access technologies, such as 5G NR and 4G LTE, often have different baseband signal processing operations. Therefore, to support the convergence of multiple mobile communication modes, the baseband subsystem may include multiple processing cores or multiple HACs.

[0048] Furthermore, since RF signals are analog, and the signals processed by the baseband subsystem are primarily digital, wireless communication devices also require analog-to-digital converters (ADCs), which convert analog signals into digital signals, and digital-to-analog converters (DACs), which convert digital signals into analog signals.

[0049] It should be understood that in the embodiments of the present application, the processing core may represent a processor, which may be a general-purpose processor or a processor designed for a specific field. For example, the processor may be a central processing unit (CPU) or a digital signal processor (DSP). The processor may also be a microcontroller (MCU), a graphics processing unit (GPU), an image signal processor (ISP), an audio signal processor (ASP), and a processor specially designed for artificial intelligence (AI) applications. AI processors include but are not limited to neural network processing units (NPUs), tensor processing units (TPUs), and processors referred to as AI engines.

[0050] Hardware accelerators can be used to implement sub-functions with high processing overhead, such as data packet assembly and parsing, and data packet encryption and decryption. These sub-functions can also be implemented using general-purpose processors, but hardware accelerators may be more appropriate due to performance or cost considerations. Therefore, the type and number of hardware accelerators can be selected based on specific needs. In specific implementations, one or a combination of field programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs) can be used. Of course, one or more processing cores can also be used in hardware accelerators.

[0051] Memory can be divided into volatile memory and non-volatile memory (NVM). Volatile memory refers to memory that loses its stored data if the power supply is interrupted. Currently, volatile memory is mainly random access memory (RAM), including static random access memory (SRAM) and dynamic random access memory (DRAM). Non-volatile memory refers to memory that maintains its stored data even if the power supply is interrupted. Common non-volatile memories include read-only memory (ROM), optical disks, magnetic disks, and various memories based on flash memory technology. Generally speaking, volatile memory can be used for memory, and non-volatile memory, such as magnetic disks or flash memory, can be used for large-capacity storage.

[0052] In an embodiment of the present application, the baseband subsystem and the radio frequency subsystem together constitute a communication subsystem, which provides wireless communication functions for wireless communication devices. Generally, the baseband subsystem is responsible for managing the software and hardware resources of the communication subsystem, and can configure the operating parameters of the radio frequency subsystem. One or more processing cores of the baseband subsystem can be integrated into one or more chips, which can be referred to as a baseband processing chip or a baseband chip. Similarly, an RFIC can be referred to as a radio frequency processing chip or a radio frequency chip. In addition, as technology evolves, the functional division of the radio frequency subsystem and the baseband subsystem in the communication subsystem can also be adjusted. For example, part of the functions of the radio frequency subsystem can be integrated into the baseband subsystem, or part of the functions of the baseband subsystem can be integrated into the radio frequency subsystem. In actual applications, based on the needs of the application scenario, wireless communication devices can adopt a combination of different numbers and types of processing cores.

[0053] In an embodiment of the present application, the RF subsystem may include an independent antenna, an independent RF front-end (RF frontend, RFFE) device, and an independent RF chip. RF chips are sometimes also referred to as receivers, transmitters, transceivers, or transceiver chips. Antennas, RF front-end devices, and RF processing chips can all be manufactured and sold separately. Of course, the RF subsystem can also use different devices or different integration methods based on power consumption and performance requirements. For example, some devices belonging to the RF front end are integrated into the RF chip, or even the antenna and RF front-end devices are integrated into the RF chip. The RF chip can also be called an RF antenna module or antenna module.

[0054] In the embodiments of the present application, the baseband subsystem can be implemented as an independent chip, which can be referred to as a modem chip. The hardware components of the baseband subsystem can be manufactured and sold as a unit of a modem chip. A modem chip is sometimes also referred to as a baseband chip or baseband processor. In addition, the baseband subsystem can be further integrated into a SoC chip and manufactured and sold as a unit of a SoC chip. The software components of the baseband subsystem can be built into the hardware components of the chip before the chip leaves the factory, or can be imported from other non-volatile memories into the hardware components of the chip after the chip leaves the factory, or these software components can be downloaded and updated online via a network.

[0055] Figure 3 Schematic diagram of the structure of the electronic device provided in the embodiment of the present application Figure 2 . Figure 3 The following figure shows some common devices used for radio frequency signal processing in electronic devices, including baseband signal processing chips and radio frequency signal processing chips, which can also be called transceiver chips. Figure 3 Although only one RF receiving channel and one RF transmitting channel are shown in the RF signal processing chip, the wireless communication device in the embodiment of the present application is not limited to this. The wireless communication device may include one or more RF receiving channels and RF transmitting channels.

[0056] In the RF receive channel, the RF signal received from the antenna is fed into the channel after being selected by the antenna switch. Since the RF signal received from the antenna is typically very weak, it is typically amplified by a low-noise amplifier (LNA). The amplified signal is first down-converted by a mixer, then passes through a filter and an analog-to-digital converter (ADC) for baseband signal processing. In the RF transmit channel, the baseband signal is converted to an analog signal by a digital-to-analog converter (DAC). This analog signal is then up-converted by a mixer to an RF signal. This RF signal is processed by a filter and a power amplifier (PA), and finally, after being selected by the antenna switch, is radiated from the appropriate antenna.

[0057] In the mixer, the input signal and the local oscillator (LO) signal are mixed to achieve up-conversion (corresponding to the RF transmission channel) or down-conversion (corresponding to the RF reception channel) operations. The local oscillator (LO) is a common term in the RF field, usually referred to as the local oscillator. The local oscillator is sometimes also called a frequency synthesizer or a frequency synthesizer (frequency synthesizer), referred to as a frequency synthesizer. The main function of the local oscillator or frequency synthesizer is to provide the specific frequency required for RF processing, such as the frequency of the carrier. Higher frequencies can be achieved using devices such as a phase-locked loop (PLL) or a delay-locked loop (DLL). Lower frequencies can be achieved by directly using a crystal oscillator or by dividing the high-frequency signal generated by devices such as the PLL.

[0058] In the embodiments of the present application, Figure 1 The signal receiving channel of the electronic equipment in Figure 2 RF subsystems in electronic devices, Figure 3 The radio frequency signal processing chips in the electronic devices all need to use receivers to realize the conversion of analog signals to digital signals. A receiver includes at least one signal path, which may include an analog to digital converter (ADC), a clock data recovery unit (CDR), an equalizer (EQ) module and a forward error correction (FEC) module. Among them, the analog to digital converter ADC is used to convert the analog signal into a digital signal. The clock data recovery unit CDR is used to detect the phase error of the digital signal output by the analog to digital conversion module, and to generate a phase control word (pi_code) after filtering the phase error. The phase control word is the filtered phase error, which is used to control the clock phase in the phase interpolator (PI). The multi-phase clock generated by the phase interpolator PI is used for the analog to digital converter ADC to perform data sampling to obtain a digital signal. The equalizer EQ module is used to filter the input signal and adjust the signal quality. The forward error correction (FEC) module is used to encode the signal according to a certain algorithm before it is sent into the transmission channel, and add redundant codes with the characteristics of the signal itself. At the receiving end, the received signal is decoded according to the corresponding algorithm, so as to detect the error codes generated during the signal transmission process and correct the error codes, thereby improving the reliability of signal transmission and conversion.

[0059] To determine the performance and reliability of a signal system, an eye diagram is typically used to observe the waveform of a received signal and analyze the impact of noise, such as intersymbol interference, on the performance of the signal system. Therefore, an embodiment of the present application provides a receiver having a built-in eye diagram detection circuit.

[0060] The following is a description of a receiver provided in an embodiment of the present application.

[0061] For example, Figure 4 The circuit structure of the receiver provided in the embodiment of the present application is shown Figure 1 Please refer to Figure 4 The receiver includes two signal paths: a first signal path 100 and a second signal path 200. The first signal path 100 is a signal conversion path for normal services; the second signal path 200 is an eye diagram detection path for drawing eye diagrams. In this receiver, the second signal path 200 uses the clock signal recovered by the clock data recovery unit in the first signal path 100 to perform phase adjustment. By collecting the digital signal from the second signal path 200 and drawing an eye diagram, it can intuitively reflect the quality of the received signal, thereby improving the reliability of the signal system. Conversely, the eye diagram quality drawn by the second signal path 200 is fed back to the first signal path 100 as a basis for adjusting the clock offset signal and equalization parameters in the first signal path. By analyzing and processing the eye diagram quality, a corresponding control signal is generated, which is used to adjust the parameters of the signal processing system, thereby reducing the bit error rate of the transmitted signal and improving the performance and reliability of the receiver.

[0062] Specifically, the first signal path 100 includes a first analog-to-digital converter 101 and a first clock data recovery unit 102. The input end of the first clock data recovery unit 102 is connected to the output end of the first analog-to-digital converter 101, and is used to perform clock recovery on the digital signal output by the first analog-to-digital converter 101 and generate a first phase control word. In other words, the digital signal output by the first analog-to-digital converter 101 is detected by the first clock data recovery unit 102 to obtain a phase error, and the phase error is filtered to generate a first phase control word. The above-mentioned first phase control word can be used to control the clock phase in the first signal path 100 and the second signal path 200, thereby ensuring that the clock signal used by the analog-to-digital converter in the second signal path 200 is consistent with that in the first signal path 100.

[0063] The second signal path 200 includes a second analog-to-digital converter 201, a second phase interpolator 203, and a second eye diagram monitor 205. The first analog-to-digital converter 101 and the second analog-to-digital converter 201 can receive the same analog signal. The input of the second phase interpolator 203 is connected to the output of the first clock data recovery unit 102, and is used to receive the first phase control word and generate a second clock based on the second clock offset signal and the first phase control word. The clock input of the second analog-to-digital converter 201 is connected to the output of the second phase interpolator 203, and is used to receive the second clock and output a digital signal based on the second clock sampling. The input of the second eye diagram monitor 205 is connected to the output of the second analog-to-digital converter 201, and is used to collect the digital signal sampled and output by the second analog-to-digital converter 201 based on the second clock sampling, and draw an eye diagram based on the digital signal.

[0064] The analog-to-digital converters, such as the first analog-to-digital converter 101 and the second analog-to-digital converter 201, may include a plurality of sub-analog-to-digital converters (such as Figure 4 Multiple sub-ADCs (subADC_1, ..., subADC_n) are arranged in parallel. This converts high-frequency signals from serial to parallel, reducing the frequency of each channel. For example, a 10G input signal is processed by 10 parallel sub-ADCs, so each sub-ADC only needs to process a 1G signal.

[0065] Furthermore, the ADC may also include a multi-phase clock for receiving the multi-phase clock signal recovered by the phase interpolator, for sampling by the multiple sub-ADCs in the ADC to output digital signals. In other words, the second ADC 201 described above uses the clock recovered by the second phase interpolator 203 to perform phase adjustment, output a multi-phase clock, perform data sampling, and cause the second ADC 201 to output a digital signal.

[0066] A phase interpolator, such as the second phase interpolator 203, may include two input signals and one output signal. The two input signals are a phase control word and a reference clock, respectively. The output signal is a clock signal obtained by adjusting the reference clock according to the phase control word. The reference clock may be obtained by a clock generator, such as a phase locked loop (PLL) circuit.

[0067] A clock data recovery unit, such as the first clock data recovery unit 102, may include a feedforward equalizer (FFE), a phase detector (PD), a low pass filter (LPF), and / or an accumulator (ACC). The feedforward equalizer is used to filter the digital signal converted by the analog-to-digital converter, the phase detector is used to detect the clock phase error of the digital signal, and the low pass filter and / or the integrator are used to filter the phase error.

[0068] The clock data recovery unit in the embodiment of the present application may also include other functional devices, and the embodiment of the present application does not impose any special restrictions.

[0069] It should also be noted that the second clock bias signal can be configured by the second control module 206, and the second clock bias signal is used to change the value of the phase control word input to the second phase interpolator 203, that is, Figure 4 In the receiver shown, when the second phase interpolator 203 receives the first phase control word and the second clock bias signal, it superimposes the second clock bias signal on the first phase control word, thereby achieving the purpose of adjusting the clock phase, so as to realize signal sampling at different clock positions, and use the sampled data to draw an eye diagram to observe the quality of signal transmission.

[0070] The range of the second clock offset signal is generally at least one unit interval (UI), such as -0.5UI to 0.5UI. To ensure the accuracy of the eye diagram after sampling, the adjustment step size of the second clock offset signal can be set to 0.01UI or even smaller, which is not specifically limited in the embodiments of the present application.

[0071] When configuring the second clock offset signal, the second control module 206 can pre-configure a range for the second clock offset signal, such as -0.5UI to 0.5UI, and configure an adjustment step of 0.01UI, such as 0.01UI. Each time the second eye diagram monitor 205 collects a set of digital signals, it can notify the second control module 206 to change the value of the second clock offset signal, such as from 0.1UI to 0.11UI. When the value of the second clock offset signal has changed by one unit interval, UI, the second eye diagram monitor can be notified to draw the eye diagram.

[0072] It should be understood that the second control module 206 can be set inside the second eye pattern monitor 205. As a control module inside the second eye pattern monitor 205, the second control module 206 can also be set outside the second eye pattern monitor. This embodiment of the application does not impose any special restrictions.

[0073] When the second clock bias signal is superimposed on the first phase control word, the following method can be used: Figure 4 The second adder 208 shown can be set outside the second phase interpolator or inside the second phase interpolator, which is not particularly limited in the embodiment of the present application.

[0074] For further information, please refer to Figure 4 The first signal path 100 further includes a first phase interpolator 103. The input of the first phase interpolator 103 is connected to the output of the first clock data recovery unit 102, and is configured to receive the first phase control word output by the first clock data recovery unit 102 and generate a first clock based on the first clock offset signal and the first phase control word. The clock input of the first analog-to-digital converter 101 is connected to the output of the first phase interpolator 103, and is configured to receive the first clock and output a digital signal based on the first clock sampling.

[0075] It should be noted that, similar to the second signal path 200, in the first signal path 100, when the first phase interpolator 103 generates the first clock, upon receiving the first phase control word, the first adder 108 can superimpose the first clock offset signal on the first phase control word to adjust the clock phase offset of the signal conversion. The first clock offset signal can be adjusted based on the eye diagram drawn by the second eye diagram monitor 205 in the second signal path 200. Specifically, the eye diagram drawn by the second eye diagram monitor 205 can be sent to upper-layer eye diagram analysis software, which can analyze the eye diagram to obtain eye diagram status information (such as eye height, eye height, whether the eye is slanted, etc.). Alternatively, the eye diagram status information can be analyzed by the eye diagram analysis module of the second eye diagram monitor itself. The analyzed eye diagram status information can then be fed back to the first control module 106 in the first signal path 100, which can then adjust the value of the first clock offset signal. In this way, the first signal path 100 that processes normal signal conversion services can adjust the clock in the first analog-to-digital converter 101 in real time to adjust the quality of the output digital signal, thereby improving the performance and reliability of the receiver.

[0076] The first control module 106 may be disposed inside the first clock data recovery unit 102 of the first signal path 100 or outside the first clock data recovery unit 102 , and this embodiment of the present application does not impose any special limitation thereto.

[0077] Figure 5 The circuit structure of the receiver provided in the embodiment of the present application is shown Figure 2 Please refer to Figure 5 , and combined with Figure 3The second signal path 200 may further include a second clock data recovery unit 202. The input of the second clock data recovery unit 202 is connected to the output of the second analog-to-digital converter 201 and is configured to generate a second phase control word based on the digital signal output by the second analog-to-digital converter 201. The outputs of the first clock data recovery unit 102 and the second clock data recovery unit 202 are connected to the input of the second phase interpolator 203 via a first selector 207. This allows the second signal path 200 to perform signal conversion for normal services when not serving as an eye pattern detection path, thereby improving the signal processing flexibility of the receiver.

[0078] It should be understood that in the second signal path 200, the structure of the second clock data recovery unit 202 can be consistent with the structure of the first clock data recovery unit 102 in the first signal path 100, or it can be other structures that can achieve corresponding functions. The embodiments of the present application do not impose any special restrictions.

[0079] exist Figure 5 In the example, the input end of the second phase interpolator 203 can selectively receive the first phase control word output by the output end of the first clock data recovery unit 102, or the second phase control word output by the output end of the second clock data recovery unit 202. When the second signal path 200 functions as an eye pattern detection path, the input end of the second phase interpolator 203 receives the first phase control word output by the first clock data recovery unit 102, enabling the second phase interpolator 203 in the second signal path 200 to use the clock signal recovered in the first signal path 100 to detect and draw the eye pattern. When the second signal path 200 functions as a signal conversion path for normal services, the input end of the second phase interpolator 203 receives the second phase control word output by the second clock data recovery unit 202, enabling the second phase interpolator 203 in the second signal path 200 to use the clock signal recovered in the second signal path 200 to perform signal conversion and processing for normal services. This allows the second channel path to perform signal conversion and processing for normal signals even when it is not used as an eye pattern detection path.

[0080] For example, Figure 5As shown, the selection control end of the first selector 207 can be connected to the second control module 206. When the selection control signal of the first selector 207 is 1, the input end of the second phase interpolator 203 receives the first phase control word of the first clock data recovery unit 102. After the first phase control word is superimposed on the second clock bias signal, and based on the reference clock, the second phase interpolator 203 outputs the second clock, continuously adjusts the value of the second clock bias signal, such as from -0.5UI to 0.5UI, and collects the output of the second analog-to-digital converter 201 under different conditions of the second clock bias signal, so that an eye diagram can be drawn to observe the quality of signal processing.

[0081] When the selection control signal of first selector 207 is 0, the input of second phase interpolator 203 receives the second phase control word from second clock-data recovery unit 202. After superimposing this second phase control word with the second clock offset signal, second phase interpolator 203 outputs the second clock based on the reference clock. At this point, second analog-to-digital converter 201 performs normal signal conversion and processing. When normal signal conversion and processing are achieved, the second clock offset signal can be used to adjust signal quality based on eye diagram detection.

[0082] Figure 6 The circuit structure of the receiver provided in the embodiment of the present application is shown Figure 3 Please refer to Figure 6 Combined with Figure 5 The first signal path 100 may further include a first eye pattern monitor 105. The output of the first clock data recovery unit 102 and the output of the second clock data recovery unit 202 are connected to the input of the first phase interpolator 103 via the second selector 107. The input of the first eye pattern monitor 105 is connected to the output of the first analog-to-digital converter 101 and is used to collect the digital signal output by the first analog-to-digital converter 101 and draw an eye pattern based on the digital signal output by the first analog-to-digital converter 101.

[0083] It should be understood that Figure 6 The connection relationship between other circuit units in Figure 5 The circuit connection relationship is consistent with that in , and will not be repeated here.

[0084] exist Figure 6In the embodiment, the output end of the first clock data recovery unit 102 and the output end of the second clock data recovery unit 202 are connected to the input end of the second phase interpolator 203 through the first selector, and the output end of the first clock data recovery unit 102 and the output end of the second clock data recovery unit 202 are connected to the input end of the first phase interpolator 103 through the second selector 107. The selection control end of the second selector 107 can be connected to the first control module 106. The connection relationship between the output end of the first clock data recovery unit 102, the output end of the second clock data recovery unit 202, the first selector 207, the second selector 107, the input end of the first phase interpolator 103 and the input end of the second phase interpolator 203 can be referred to. Figure 5 The connection method shown can also be used to achieve Figure 6 Other connection methods of the functions shown are not limited in the embodiments of the present application.

[0085] like Figure 6 As shown, when the input end of the first phase interpolator 103 and the input end of the second phase interpolator 203 both choose to receive the output end data of the first clock data recovery unit 102, the first signal path 100 serves as a normal service path and the second signal path 200 serves as an eye diagram detection path to observe signal quality.

[0086] When the input end of the first phase interpolator 103 and the input end of the second phase interpolator 203 both choose to receive the output end data of the second clock data recovery unit 202, the first signal path 100 serves as an eye diagram detection path to observe the quality of signal conversion; the second signal path 200 serves as a normal service path.

[0087] In this way, the first signal path 100 and the second signal path 200 can be made eye diagram detection paths of each other, and used to provide signal quality adjustment guidance for the signal conversion path of normal business, so that the signal conversion path of normal business can generate corresponding control signals (such as clock bias signals and equalization parameters, etc.) to adjust the output quality of the signal, thereby reducing the bit error rate of signal transmission, and further improving the performance and reliability of the receiver.

[0088] Figure 7 The circuit structure of the receiver provided in the embodiment of the present application is shown Figure 4 .exist Figure 7 In the embodiment, the second signal path 200 may be a signal conversion path of a sub-ADC added inside the first signal path 100. The second signal path 200 may include at least one sub-ADC, wherein the sub-ADC in the second ADC 201 is the same as the sub-ADC in the first ADC 101.

[0089] As mentioned above, the first analog-to-digital converter 101 may include multiple sub-analog-to-digital converters, each of which processes a portion of the signal, thereby improving the signal conversion efficiency. Figure 7 In the embodiment, the second analog-to-digital converter 201 can be implemented by using one of the sub-analog-to-digital converters (such as subADC_n+1) in the first analog-to-digital converter 101. The sub-analog-to-digital converter uses the second clock generated by the second phase interpolator 203 so that the second eye diagram monitor can use the sampled data to draw the eye diagram, thereby observing the quality of signal transmission and providing a reference basis for signal adjustment for the signal conversion of normal business in the first signal path 100.

[0090] It should be understood that the second signal path 200 is set inside the chip of the first signal path 100, and the second signal path 200 only serves as an eye diagram detection path for the first signal path 100, so that the eye diagram detection does not affect the signal conversion of normal business.

[0091] It should be noted that in Figure 4 、 Figure 5 、 Figure 6 and Figure 7 The first signal path 100 further includes a first equalizer 104. The first equalizer 104 is connected to the output end of the first analog-to-digital converter 101 to achieve balanced output during signal conversion.

[0092] like Figure 6 As shown, when the first signal path 100 is used as an eye diagram detection path, the first eye diagram monitor 105 is also connected to the output end of the first equalizer 104, and is used to collect the digital signal output by the first equalizer 104. Based on the digital signal output by the first equalizer 104, the eye diagrams of the digital signals output before and after the first equalizer 104 can be compared to determine the signal adjustment benefit brought by the equalizer, so as to adjust the equalization parameters of the equalizer in the signal conversion path of the normal business according to the equalization parameters in the first equalizer 104.

[0093] In addition, Figure 4 、 Figure 5 、 Figure 6 and Figure 7The second signal path 200 also includes a second equalizer 204. The second equalizer 204 is connected to the output of the second analog-to-digital converter 201 to achieve balanced output during signal conversion. When the second signal path 200 functions as an eye pattern detection path, a second eye pattern monitor 205 is also connected to the output of the second equalizer 204 to collect the digital signal output by the second equalizer 204. Based on the digital signal output by the second equalizer 204, the eye pattern monitor 205 can be compared with the digital signal output before and after the second equalizer 204 to determine the signal conditioning benefit achieved by the equalizer. The equalization parameters of the equalizer in the signal conversion path for normal service can then be adjusted based on the equalization parameters in the second equalizer 204.

[0094] It should be understood that the above description only describes the functions of the first equalizer 104 and the second equalizer 204 as equalizers in the eye diagram detection path. When the first equalizer 104 and the second equalizer 204 are used as equalizers in the signal conversion path of normal business, the first equalizer 104 and the second equalizer 204 can adjust their equalization parameters in the signal conversion process of normal business according to the eye diagram status in the eye diagram detection path.

[0095] Figure 8 The circuit structure of the receiver provided in the embodiment of the present application is shown Figure 5 When a receiver includes at least two signal paths for signal conversion for normal business, reference can be made to Figure 8 .exist Figure 8 In each signal path used for normal business, an eye diagram detection path is set. The structure of the eye diagram detection path can be referred to Figure 7 The second signal path 200 in the receiver can be configured so that each signal path used for normal services has a corresponding eye diagram detection path for adjusting signal quality, thereby improving the performance and reliability of the receiver.

[0096] It should be understood that in the receiver provided in the embodiment of the present application, the first signal path and the second signal path can be set inside the same chip or separately set in two different chips, and the embodiment of the present application does not make special limitations.

[0097] Combination of the above Figure 4-Figure 8 The circuit structure of the receiver provided by the embodiment of the present application is described below. Figure 9 The eye diagram detection method in a receiver provided in an embodiment of the present application is described.

[0098] Figure 9 The flowchart of the eye diagram detection method in the receiver provided by the embodiment of the present application is shown. Figure 4-Figure 8 Any possible receiver. It should be understood that Figure 9The method shown is based on a scenario where the first signal path 100 is a signal conversion path for normal services and the second signal path 200 is an eye diagram detection path.

[0099] Please refer to Figure 9 , the eye diagram detection method comprises the following steps:

[0100] S901: A first analog-to-digital converter and a second analog-to-digital converter receive the same analog signal.

[0101] In an embodiment of the present application, in order to realize the drawing of the eye diagram and adjust the signal path according to the eye diagram, it is necessary to be based on the same sampling signal. Therefore, the first signal path 100 and the second signal path 200 receive the same analog signal, that is, the first analog-to-digital converter 101 and the second analog-to-digital converter 201 receive the same analog signal.

[0102] S902: The second phase interpolator receives the first phase control word output by the first clock data recovery unit.

[0103] like Figure 4-Figure 8 In the receiver shown, the second phase interpolator 203 receives the first phase controller output by the first clock unit, which can enable the second signal path 200, which serves as an eye diagram detection path, to use the clock signal recovered by the clock data recovery unit in the first signal path 100. The clock signal recovered by the clock data recovery unit is the first phase control word, thereby causing the second signal path 200 to shift the phase and draw an eye diagram based on the digital signals sampled and outputted at different clocks.

[0104] S903: The second phase interpolator generates a second clock according to the second clock offset signal and the first phase control word.

[0105] In particular, multiple second clock bias signals can be set, and the multiple second clock bias signals are used to adjust the clock of the second analog-to-digital converter 201. That is, multiple different clocks can be obtained through multiple second clock bias signals, and multiple groups of digital signals can be output according to the multiple different clocks. The above-mentioned multiple second clock bias signals can be within a unit interval range, for example, a value between -0.5UI and 0.5UI. When adjusting the second clock bias signal, the step size can be 0.01UI. That is, the value of the next second clock bias signal can be 0.01UI increased based on the value of the previous second clock bias signal.

[0106] When all values ​​within the value range of -0.5UI to 0.5UI of the second clock bias signal are taken, an eye diagram can be drawn based on the digital signals sampled and output at different clocks.

[0107] S904: The second analog-to-digital converter samples and outputs a digital signal according to the second clock.

[0108] In step S903, the plurality of second clock offset signals can generate a plurality of different clocks, which are respectively input into the second analog-to-digital converter 201 to generate a plurality of different digital signals.

[0109] S905 , the second eye diagram monitor collects the digital signal output by the second analog-to-digital converter, and draws an eye diagram according to the second clock offset signal and the digital signal output by the second analog-to-digital converter.

[0110] It should be understood that each time a second clock offset signal is set, the second phase interpolator 203 can obtain a clock signal, and the second analog-to-digital converter 201 can sample and output a set of digital signals based on the clock signal. After the second eye pattern monitor 205 collects multiple sets of different digital signals, it can draw an eye pattern based on the correspondence between the multiple clock offset signals and the multiple sets of different digital signals, as the first eye pattern.

[0111] Exemplarily, the first eye diagram may be drawn with the second clock bias signal as the abscissa and the digital signal obtained from the second clock bias signal as the ordinate.

[0112] In one possible implementation, the method may further include: a first phase interpolator 103 receiving a first phase control word output by the first clock data recovery unit 102. The first phase interpolator 103 generates a first clock based on the first clock offset signal and the first phase control word. The first analog-to-digital converter 101 samples and outputs a digital signal based on the first clock. The first clock offset signal is determined based on the first eye diagram.

[0113] That is, after the first eye diagram is drawn through the second signal path 200, the relevant information of the first eye diagram can be fed back to the first signal path 100 so that the first signal path 100 adjusts the first clock bias signal and equalization parameters, thereby improving the performance and reliability of the receiver.

[0114] More specifically, Figure 10 A flowchart of drawing an eye diagram in a receiver provided in an embodiment of the present application is shown.

[0115] Please refer to Figure 10 , the methods for drawing eye diagrams include:

[0116] S1001: Update and fix the equalization parameters and the first clock offset signal in the first signal path.

[0117] After updating the equalization parameters and the first clock bias signal in the first signal path, when the clock recovery in the first signal path is stable, the equalization parameters and the first clock bias signal of the first signal path are fixed so that the second signal path uses the first phase control word recovered by the first clock data recovery unit.

[0118] S1002, the second signal path selects to use the first phase control word output by the first clock data recovery unit in the first signal path;

[0119] S1003: Superimpose a second clock offset signal on the first phase control word.

[0120] For the description of the instruction fetch range of the second clock bias signal, etc., reference may be made to the relevant description in the above step S803, which will not be repeated here.

[0121] S1004, a second eye pattern monitor collects a set of digital signals;

[0122] S1005 , determining whether the second clock offset signal covers one UI cycle.

[0123] If yes, execute step S1006; if no, execute step S1003.

[0124] S1006: Draw an eye diagram based on the collected digital signal.

[0125] Regarding how to draw the eye diagram, please refer to the relevant description in the above step S1005, which will not be repeated here.

[0126] S1007, determining whether the eye diagram is skewed and whether the sampling point is not in the center of the eye diagram.

[0127] If the eye diagram is skewed or the sampling point is not in the center of the eye diagram, step S1001 is executed.

[0128] In one possible implementation, the second signal path may further include a second equalizer 204 connected to the output of the second analog-to-digital converter 201; a second eye pattern monitor 205 is also connected to the output of the second equalizer 204. The method may further include: the second equalizer 204 receiving the digital signal generated by the second analog-to-digital converter 201 and generating multiple equalized digital signals. The second eye pattern monitor 205 collects the equalized digital signals output by the second equalizer 204. The second eye pattern monitor 205 draws an eye pattern based on the second clock offset signal and the equalized digital signals as a second eye pattern. The second eye pattern monitor 205 compares the first eye pattern with the second eye pattern.

[0129] Similarly, for Figure 6In the receiver shown, if the first signal path is used as an eye diagram detection path, the first eye diagram monitor can also collect multiple groups of equalized digital signals output by the first equalizer in the first signal path, so as to compare the eye diagrams before and after the first equalizer.

[0130] It should be understood that by comparing the first eye diagram and the second eye diagram, the difference in signal quality between the digital signal converted by the analog-to-digital converter and the signal equalized or not can be known, thereby judging the signal conditioning benefit brought by the equalizer (such as the second equalizer 204), and then adjusting the equalization parameters in the signal conversion path of the normal business according to the signal conditioning benefit brought by the equalizer to improve the signal quality and improve the performance and reliability of the receiver.

[0131] In the several embodiments provided in this application, it should be understood that the disclosed circuits and methods can be implemented in other ways. For example, the circuit embodiments described above are merely illustrative. For example, the division of modules or units described is merely a logical function division. In actual implementation, other division methods may be used. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not performed.

[0132] The units described as separate components may or may not be physically separate, and the components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place or distributed in multiple places. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0133] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A receiver, characterized in that: comprising a first signal pathway and a second signal pathway; The first signal path includes a first analog-to-digital converter and a first clock data recovery unit; The input end of the first clock data recovery unit is connected to the output end of the first analog-to-digital converter, and is used to generate a first phase control word according to the digital signal output by the first analog-to-digital converter; The second signal path includes a second analog-to-digital converter, a second phase interpolator, and a second eye monitor; The input end of the second phase interpolator is connected to the output end of the first clock data recovery unit, and is used to receive the first phase control word and generate a second clock according to the first phase control word; The clock input terminal of the second analog-to-digital converter is connected to the output terminal of the second phase interpolator, and is used to receive the second clock and output a digital signal according to sampling of the second clock; The input end of the second eye diagram monitor is connected to the output end of the second analog-to-digital converter, and is used to collect the digital signal output by the second analog-to-digital converter according to the second clock sampling, and draw an eye diagram based on the digital signal output by the second analog-to-digital converter.

2. The receiver according to claim 1, wherein The first signal path further includes a first phase interpolator; The input end of the first phase interpolator is connected to the output end of the first clock data recovery unit, and is used to receive the first phase control word and generate a first clock according to the first clock offset signal and the first phase control word; The clock input terminal of the first analog-to-digital converter is connected to the output terminal of the first phase interpolator, and is used to receive the first clock and output a digital signal according to sampling of the first clock.

3. The receiver according to claim 1 or 2, characterized in that The second signal path further includes a second clock data recovery unit; The input end of the second clock data recovery unit is connected to the output end of the second analog-to-digital converter, and is used to generate a second phase control word according to the digital signal output by the second analog-to-digital converter; The output end of the first clock data recovery unit and the output end of the second clock data recovery unit are connected to the input end of the second phase interpolator through a first selector.

4. The receiver according to claim 3, wherein: The first signal path further includes a first eye monitor; The output end of the first clock data recovery unit and the output end of the second clock data recovery unit are connected to the input end of the first phase interpolator through a second selector; The input end of the first eye diagram monitor is connected to the output end of the first analog-to-digital converter, and is used to collect the digital signal output by the first analog-to-digital converter and draw an eye diagram according to the digital signal output by the first analog-to-digital converter.

5. The receiver according to claim 4, wherein: The first signal path further includes a first equalizer connected to an output terminal of the first analog-to-digital converter; The first eye diagram monitor is also connected to the output end of the first equalizer, and is used to collect the digital signal output by the first equalizer and draw an eye diagram according to the digital signal output by the first equalizer.

6. The receiver according to claim 1 or 2, characterized in that The second signal path further includes a second equalizer connected to the output end of the second analog-to-digital converter; The second eye diagram monitor is also connected to the output end of the second equalizer, and is used to collect the digital signal output by the second equalizer and draw an eye diagram according to the digital signal output by the second equalizer.

7. The receiver according to claim 1 or 2, characterized in that The second analog-to-digital converter includes at least one sub-analog-to-digital converter, and the sub-analog-to-digital converter in the second analog-to-digital converter is the same as the sub-analog-to-digital converter in the first analog-to-digital converter.

8. An electronic device, characterized in that: include: A transceiver chip, and a receiver according to any one of claims 1 to 7; The receiver is disposed in the transceiver chip.

9. The electronic device according to claim 8, wherein: It also includes a baseband processing chip, which is coupled to the transceiver chip.

10. A method for detecting an eye diagram in a receiver, characterized in that: Applied to the receiver according to any one of claims 1 to 7, the method comprises: The first analog-to-digital converter and the second analog-to-digital converter receive the same analog signal; The second phase interpolator receives the first phase control word output by the first clock data recovery unit; The second phase interpolator generates a second clock according to a second clock bias signal and the first phase control word; wherein the second clock bias signal is used to adjust the clock of the second analog-to-digital converter; The second analog-to-digital converter samples and outputs a digital signal according to the second clock; The second eye diagram monitor collects the digital signal output by the second analog-to-digital converter and draws a first eye diagram according to the second clock bias signal and the digital signal output by the second analog-to-digital converter.

11. The method according to claim 10, characterized in that The second clock offset signal includes a plurality of signals, and a value range of the second clock offset signal is from -0.5 unit interval UI to 0.5 UI.

12. The method according to claim 11, characterized in that The step size of the second clock bias signal is 0.01 UI.

13. The method according to any one of claims 10 to 12, characterized in that The method further comprises: The first phase interpolator of the first signal path receives the first phase control word output by the first clock data recovery unit; The first phase interpolator generates a first clock according to a first clock bias signal and the first phase control word; wherein the first clock bias signal is determined according to the first eye diagram; The first analog-to-digital converter samples and outputs a digital signal according to the first clock.

14. The method according to any one of claims 10 to 12, characterized in that The method further comprises: The second equalizer of the second signal path receives the digital signal output by the second analog-to-digital converter and generates an equalized digital signal; The second eye pattern monitor collects the equalized digital signal output by the second equalizer; The second eye diagram monitor draws a second eye diagram according to the second clock bias signal and the equalized digital signal; The second eye pattern monitor compares the first eye pattern and the second eye pattern.

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