Bipolar power device and method for manufacturing the same

Abstract

The present application discloses a bipolar power device and a preparation method thereof, wherein a well region embedded with a doped sub-region is made between an epitaxial layer on a high-quality silicon carbide single crystal substrate and a stripping layer therein, and a bonding is performed once with a low-quality intermediate silicon carbide substrate; a portion of the device structure including the silicon carbide single crystal substrate is stripped along the stripping layer and the stripping surface is post-processed to expose the second surface of the stripped epitaxial layer and conduct a conductive treatment thereon to form a second device structure; a silicon substrate with a double-sided injection layer is bonded to the inverted second device structure for a second time; the intermediate silicon carbide substrate is removed and the bonding interface is activated, and an electrode layer is prepared to form a bipolar power device. Thus, on the basis of overcoming the difficulty of preparing silicon carbide materials on a silicon basis, the cost of silicon carbide monolithic wafers is reduced, and a solution for low-cost preparation of high-voltage bipolar power devices is provided.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a bipolar power device and a method for preparing the same. Background Art

[0002] Silicon carbide (SiC), as a representative material of the third-generation semiconductors, combines many excellent properties such as wide band gap (2.4eV-3.2eV), high physical strength, high thermal conductivity, high corrosion resistance, high melting point, wide light transmission window (0.37-5.6μm) and wide-area defect luminescence window (visible light to mid-infrared). It is an ideal material for high-voltage power devices.

[0003] In addition, silicon carbide materials have more than 200 crystal forms, among which 3C-SiC, 4H-SiC and 6H-SiC are the most widely used. 3C-SiC thin films are mainly deposited on the surface of silicon substrates by atmospheric pressure chemical vapor deposition (APCVD) and reduced pressure chemical vapor deposition (RPCVD). However, the 3C-SiC thin films prepared by this method are mainly polycrystalline thin films, and the crystal quality cannot reach single crystals. Although relatively pure single crystal materials can be prepared by PVT (Physical Vapor Transport) method, since the growth temperature of 4H-SiC prepared by PVT method is greater than the melting point of silicon, it is impossible to grow single crystal silicon carbide thin films on silicon substrates by traditional thin film deposition heteroepitaxial method. In addition, it is difficult to dope silicon carbide as a whole (such as P-type doping) like silicon materials during the single crystal growth process, which has caused great obstacles to the preparation of bipolar power devices with higher withstand voltage (such as insulated gate bipolar transistors IGBT) based on silicon carbide. Summary of the invention

[0004] In view of at least one technical problem in the prior art, the purpose of the present application is to provide a bipolar power device and a method for preparing the same.

[0005] In order to solve the above technical problems, on the one hand, the present application provides a method for preparing a bipolar power device, comprising the following steps:

[0006] Providing a silicon carbide single crystal substrate, and homoepitaxially growing an epitaxial layer on the silicon carbide single crystal substrate;

[0007] Performing a first ion implantation on the exposed first surface of the epitaxial layer to form a peeling layer in the epitaxial layer;

[0008] Making a well region embedded with doped sub-regions between the first surface and the peeling layer to form a first device structure;

[0009] Providing an intermediate silicon carbide substrate, and performing a bonding operation with the first device structure based on the first surface; the substrate quality of the silicon carbide single crystal substrate is higher than the substrate quality of the intermediate silicon carbide substrate;

[0010] Along the layer direction of the peeling layer, peeling off a part of the device structure including the silicon carbide single crystal substrate and performing post-processing on the peeling surface to expose the second surface of the peeled epitaxial layer;

[0011] performing a conductive treatment on the second surface to form a second device structure;

[0012] Obtaining a silicon substrate having a double-sided implantation layer, and performing secondary bonding with the inverted second device structure based on the second surface;

[0013] removing the intermediate silicon carbide substrate and activating the bonding interface to form a third device structure;

[0014] An electrode layer is prepared on the third device structure to form a bipolar power device.

[0015] In an optional implementation manner, obtaining a silicon substrate having a double-sided implantation layer comprises:

[0016] providing an initial silicon substrate;

[0017] Performing ion implantation treatment on the top surface and the back surface of the initial silicon substrate respectively to obtain the silicon substrate with double-sided implantation layers;

[0018] Wherein, the conductivity types of the ions injected into the double-sided injection layers are opposite.

[0019] In an optional embodiment, the step of performing ion implantation on the top surface and the back surface of the initial silicon substrate to obtain the silicon substrate having a double-sided implantation layer comprises:

[0020] Performing ion implantation of a first conductivity type on the top surface of the initial silicon substrate to form a first implantation layer;

[0021] Performing ion implantation of a second conductivity type on the back side of the initial silicon substrate to form a second implantation layer;

[0022] The double-sided injection layer is formed based on the second injection layer and the first injection layer, thereby obtaining the silicon substrate with the double-sided injection layer;

[0023] wherein the ion implantation energy of the first conductivity type and the ion implantation energy of the second conductivity type are both lower than the ion implantation energy of the first ion implantation;

[0024] In the case where the second conductivity type is different from the conductivity type of the silicon carbide single crystal substrate, ion implantation energy of the second conductivity type is higher than ion implantation energy of the first conductivity type.

[0025] In an optional implementation, the first conductivity type is an N-type conductivity type, and the second conductivity type is a P-type conductivity type;

[0026] And in the secondary bonding process, the first injection layer is close to the second device structure, and the second injection layer is far away from the second device structure.

[0027] In an optional embodiment, the ion implantation energy of the first conductive type is 5keV to 30keV, and the implantation dose is 1E15 to 1E17 / cm 2 ;

[0028] The ion implantation energy of the second conductivity type is 50keV-200keV, and the implantation dose is 1E16-1E18 / cm2.

[0029] In an optional embodiment, the implantation parameters of the first ions include at least one of the following:

[0030] The implanted element of the first ion includes one or more of hydrogen ions and helium ions;

[0031] The implantation dose of the first ion is in the range of 1E17 / cm 2 ~1E20 / cm 2 ;

[0032] The implantation energy of the first ions ranges from 2 MeV to 10 MeV.

[0033] In an optional embodiment, the doping element of the epitaxial layer includes one or more of nitrogen and phosphorus, and the doping concentration range is 1E12-1E15 / cm 3 ;

[0034] The measurement dimensions of the substrate quality include one or more of the substrate crystal type quantity, substrate crystal type, and substrate defect density.

[0035] In an optional embodiment, the post-processing of the peeled surface to expose the second surface of the peeled epitaxial layer comprises:

[0036] Based on a preset thinning thickness, the peeling surface is thinned;

[0037] Using the exposed peeled surface after the thinning process as the second surface in the peeled epitaxial layer;

[0038] The preset thinning thickness is any value between 1.5 and 3 μm.

[0039] In an optional implementation manner, performing conductive processing on the second surface to form a second device structure includes:

[0040] Performing a second ion implantation on the second surface to form a conductive layer in the stripped epitaxial layer; the type of the second ions is different from the type of the first ions; and the upper edge of the conductive layer is flush with the second surface;

[0041] The conductive layer and the well region are subjected to an annealing process to form the second device structure.

[0042] In an optional implementation manner, activating the bonding interface to form the third device structure includes:

[0043] A secondary annealing process is performed on the device structure with the intermediate silicon carbide substrate removed to activate the bonding interface between the silicon substrate and the inverted second device structure to form the third device structure.

[0044] On the other hand, the present application also provides a bipolar power device, which is prepared by any method described in the embodiments of the present application.

[0045] A bipolar power device and a method for manufacturing the same in the present application have at least the following beneficial effects:

[0046] In the embodiment of the present application, a high-quality silicon carbide single crystal substrate is used to homogeneously grow an epitaxial layer, and the epitaxial layer is used to bond with a low-quality intermediate silicon carbide substrate, and a part of the device structure including the high-quality first silicon carbide substrate is peeled off through a peeling layer formed in the epitaxial layer, and then the peeled device structure is transferred to a silicon substrate with a double-sided injection layer through bonding, and a well region embedded with a doped sub-region is separately manufactured from an electrode layer to form a bipolar power device, thereby first transferring the epitaxial silicon carbide film to a low-cost intermediate silicon carbide substrate, and then transferring it to the silicon substrate through heterogeneous bonding, while overcoming the difficulty of preparing silicon-based silicon carbide materials, reducing the cost of silicon carbide single wafers, and further combining with a silicon substrate with a double-sided injection layer to overcome the difficulty of overall doping on the epitaxial silicon carbide film, and at the same time, the prepared bipolar power device contains a peeled silicon carbide epitaxial layer, giving full play to the excellent performance of the silicon carbide material itself, therefore, the present application provides a solution for low-cost preparation of high-voltage bipolar power devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions and advantages in the embodiments of the present application or the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0048] Figure 1 It is a flow chart of a method for preparing a bipolar power device provided in an embodiment of the present application;

[0049] Figure 2 It is a schematic structural diagram of a device in step S102 in a method for preparing a bipolar power device provided in an embodiment of the present application;

[0050] Figure 3 It is a schematic structural diagram of a device in step S103 of a method for preparing a bipolar power device provided in an embodiment of the present application;

[0051] Figure 4 It is a schematic structural diagram of a device in step S105 in a method for preparing a bipolar power device provided in an embodiment of the present application;

[0052] Figure 5 It is a schematic structural diagram of a device in step S106 in a method for preparing a bipolar power device provided in an embodiment of the present application;

[0053] Figure 6 It is a schematic structural diagram of a silicon substrate involved in step S107 in a method for preparing a bipolar power device provided in an embodiment of the present application;

[0054] Figure 7 It is a schematic structural diagram of a device in step S107 in a method for preparing a bipolar power device provided in an embodiment of the present application;

[0055] Figure 8 It is a schematic structural diagram of a device in step S108 in a method for preparing a bipolar power device provided in an embodiment of the present application;

[0056] Fig. 9 It is a schematic diagram of the structure of the device in step S109 in the method for preparing a bipolar power device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0057] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0058] The "one embodiment" or "embodiment" referred to below refers to a specific feature, structure or characteristic that may be included in at least one implementation of the present invention. In the description of the present invention, unless otherwise clearly specified and limited, the orientation or position relationship indicated by the terms "upper", "lower", "left", "right", "top", "bottom", etc. is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. Moreover, the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein.

[0059] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being located "on" or "above" another layer or another region, it may mean that it is directly located on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Moreover, if the component is turned over, the layer or a region will be located "below" or "beneath" another layer or another region.

[0060] In the related art, although relatively pure single crystal materials can be prepared by the PVT (Physical Vapor Transport) method, since the growth temperature of 4H-SiC prepared by the PVT method is greater than the melting point of silicon, it is impossible to grow single crystal silicon carbide thin films on silicon substrates by traditional thin film deposition heteroepitaxial methods. In addition, at the current 8-inch diameter expansion, problems such as defect control in the silicon carbide growth process and material loss caused by cutting, grinding and polishing have further highlighted the silicon carbide yield and cost issues, thus increasing the production cost of homoepitaxially generating single crystal silicon carbide thin films on large-sized silicon carbide substrates, hindering the large-scale use of silicon carbide in the semiconductor field. To this end, the embodiment of the present application provides a method for preparing bipolar power devices containing silicon carbide at low cost.

[0061] Figure 1 It is a flow chart of a method for preparing a bipolar power device provided in an embodiment of the present application. Figures 2 to 9 It is a schematic diagram of the device in each step of the preparation method of the bipolar power device of some preferred embodiments of the present application. The accompanying drawings are only schematic diagrams of multiple embodiments including common and possibly non-common parts, and the parts with differences or distinctions are presented in a textual description. In order to reduce the lengthy and unnecessary repeated description of the embodiments, based on the industrial characteristics and technical essence, the technicians familiar with the field should be able to correctly and reasonably understand and judge whether the individual technical features described below or any combination of them can be characterized in the same embodiment, or whether multiple technical features that are mutually exclusive in technical essence can only be characterized in different variations.

[0062] A method for preparing a bipolar power device provided in an embodiment of the present application includes the following steps.

[0063] Step S101, providing a silicon carbide single crystal substrate, and homoepitaxially growing an epitaxial layer on the silicon carbide single crystal substrate.

[0064] Among them, the silicon carbide single crystal substrate may refer to a high-quality silicon carbide substrate suitable for preparing bipolar power devices. Specifically, the silicon carbide single crystal substrate may be a single crystal substrate with a low defect content, and the size of the silicon carbide substrate may be greater than or equal to a preset size threshold, and illustratively, the preset size threshold may be 8 inches. Of course, according to actual needs, the preset size threshold may be a value less than 8 inches or greater than 8 inches.

[0065] In some embodiments, Figure 2As shown, an epitaxial layer 220 can be homoepitaxially grown on a silicon carbide single crystal substrate 210 by an epitaxial process. The epitaxial process refers to the process of growing a completely ordered single crystal layer on a substrate. Generally speaking, the epitaxial process is to grow a crystal layer with the same lattice orientation as the original substrate on a single crystal substrate, which is equivalent to extending the crystal of the single crystal substrate outward for a section. Here, the epitaxial layer 220 is made of the same material as the silicon carbide single crystal substrate 210 and has the same lattice orientation, that is, a single crystal silicon carbide epitaxial layer is obtained.

[0066] In some embodiments, the thickness of the epitaxial layer 220 may range from 11 μm to 21 μm, and may further range from 10 μm to 20 μm, such as 10.1 μm, 12.5 μm, 15.6 μm, 18 μm, and 20 μm.

[0067] In some embodiments, the epitaxial layer 220 has the same material properties as the silicon carbide single crystal substrate 210. For example, if the silicon carbide single crystal substrate 210 is an N-type silicon carbide substrate doped with a first dopant (e.g., nitrogen, phosphorus, or a combination thereof), the epitaxial layer 220 is the n-region of the device. The n-region can be obtained by doping the initial epitaxial layer obtained by epitaxy, and the doping elements of the epitaxial layer can include one or more of nitrogen and phosphorus, and the doping concentration range can be 1E12 to 1E15 / cm 3 For another example, if the silicon carbide single crystal substrate 210 is a P-type silicon carbide substrate, the epitaxial layer 220 is the p-region of the device. The p-region can be obtained by doping the epitaxial layer obtained by epitaxy, and the doping element of the epitaxial layer includes boron, and the doping concentration range can be 1E12 to 1E15 / cm 3 .

[0068] Step S102 , performing a first ion implantation on the exposed first surface of the epitaxial layer to form a lift-off layer in the epitaxial layer.

[0069] In some embodiments, continuing as Figure 2 As shown, the first surface a1 may be the exposed top surface of the epitaxial layer 220 . The first ion implantation is performed on the exposed first surface a1 of the epitaxial layer 220 by an ion implantation process to form a lift-off layer 222 in the epitaxial layer 220 .

[0070] In some embodiments, the implantation energy of the first ion may be 5 to 15 times the conventional ion implantation energy. As an example only, the implantation energy of the first ion ranges from 2 MeV to 10 MeV, such as 3 MeV, 4 MeV, 4.5 MeV, 5.8 MeV, 7 MeV, 8 MeV, 9 MeV, 9.6 MeV, etc. The implantation energy of the first ion used here is much higher than the conventional ion implantation energy. Thus, through high ion implantation energy, the implantation depth of the obtained peeling layer 222 in the epitaxial layer 220 is deeper, which facilitates subsequent peeling to obtain a thicker peeling epitaxial film, that is, a peeling silicon carbide film, so that the preparation of a bipolar power device containing the peeling silicon carbide film fully utilizes the good performance of single crystal silicon carbide.

[0071] In some embodiments, the implanted element of the first ions includes one or more of hydrogen ions and helium ions.

[0072] In some embodiments, the implantation dose of the first ion is in the range of 1E17 / cm 2 ~1E20 / cm 2 Any value in .

[0073] Step S103 , manufacturing a well region embedded with doped sub-regions between the first surface and the peeling layer to form a first device structure.

[0074] In some embodiments, Figure 3 As shown, a first initial well region 232a and a second initial well region 232b can be formed in the epitaxial layer by doping a second dopant between the first surface a1 and the stripping layer 222. The first initial well region 232a and the second initial well region 232b are arranged side by side and spaced apart, for example, the first initial well region 232a and the second initial well region 232b can be arranged at two corner regions of the epitaxial layer. Afterwards, the first dopant is doped in the first initial well region 232a and the second initial well region 232b respectively to form a first doped sub-region 234a and a second doped sub-region 234b, and the upper surface of the first doped sub-region 234a and the upper surface of the second doped sub-region 234b can be flush with the upper surface of the epitaxial layer 220 respectively. The first initial well region 232a and the corresponding first doped sub-region 234a, and the second initial well region 232b and the corresponding second doped sub-region 234b form the well region 230 embedded with doped sub-regions to form a first device structure.

[0075] The preparation process for forming the initial well region and the corresponding doped sub-regions here can be: first depositing a mask on the epitaxial layer, and then doping the exposed parts through the mask to generate the respective initial well regions and the corresponding doped sub-regions.

[0076] The first dopant and the second dopant have different conductivity types. For example, if the conductivity type of the first dopant is N-type, the conductivity type of the second dopant is P-type, that is, a well region with embedded doped sub-regions is formed, including a P-type first initial well region 232a and a P-type second initial well region 232b, and an N-type first doped sub-region 234a and an N-type second doped sub-region 234b covering a portion of each well region.

[0077] In addition, after the well region embedded with the doped sub-regions is prepared on the surface of the implanted epitaxial structure, the subsequent bonding step can be directly performed without performing a doping activation process.

[0078] Step S104, providing an intermediate silicon carbide substrate, and performing a bonding with the first device structure based on the first surface; the substrate quality of the silicon carbide single crystal substrate is higher than the substrate quality of the intermediate silicon carbide substrate.

[0079] In some embodiments, the substrate quality of the silicon carbide single crystal substrate 210 is higher than the substrate quality of the intermediate silicon carbide substrate 240. That is, the intermediate silicon carbide substrate 240 does not use high-quality single crystal silicon carbide, but uses low-quality silicon carbide. The measurement dimensions of the substrate quality include one or more of the number of substrate crystal forms, the type of substrate crystal forms, and the substrate defect density.

[0080] As an example only, the silicon carbide single crystal substrate 210 includes a high-quality single crystal silicon carbide substrate, such as 4H-SiC, etc. The intermediate silicon carbide substrate 240 may include one or more of a test-grade (Dummy-grade) single crystal silicon carbide substrate, a mixed crystal silicon carbide substrate, and a polycrystalline silicon carbide substrate. In addition, the defect density (e.g., micropipe density) content of the silicon carbide single crystal substrate 210 is lower than the defect density of the intermediate silicon carbide substrate 240.

[0081] In some embodiments, Figure 4 As shown, after providing the intermediate silicon carbide substrate 240, the intermediate silicon carbide substrate 240 can be bonded to the first surface a1 of the first device structure by a wafer bonding process to obtain a first bonding structure. The wafer bonding process includes but is not limited to one or more of direct bonding and hydrophilic bonding. Taking direct bonding as an example, the surface to be bonded is subjected to plasma activation treatment, and the two surfaces are directly bonded. The type of plasma activation includes but is not limited to nitrogen, oxygen or argon, and the bonding temperature can be 20-800°C.

[0082] Step S105 , peeling off part of the device structure including the silicon carbide single crystal substrate along the layer direction of the peeling layer and performing post-processing on the peeling surface to expose the second surface of the peeled epitaxial layer.

[0083] In some embodiments, continuing as Figure 4As shown, the first bonding structure can be peeled off along the layer direction of the peeling layer 222 by a peeling process, and part of the device structure including the silicon carbide single crystal substrate 210 can be peeled off, and the peeling surface can be post-processed to expose the second surface a2 in the peeled epitaxial layer 220a. The peeling process can include but is not limited to mechanical peeling or thermal peeling. Post-processing the peeling surface can improve the quality of the peeling surface and reduce the adverse effects of the peeling layer.

[0084] Optionally, the thickness of the stripped epitaxial layer 220a may range from 10 μm to 20 μm, such as 10 μm, 12 μm, 14.5 μm, 17 μm, and 19.8 μm, etc. The difference between the thickness of the silicon carbide single crystal substrate and the thickness of the stripped epitaxial layer 220a may be greater than or approximately equal to zero.

[0085] In some embodiments, post-processing the peeling surface to expose the second surface of the peeled epitaxial layer includes: thinning the peeling surface based on a preset thinning thickness; using the exposed peeling surface after the thinning process as the second surface of the peeled epitaxial layer; wherein the preset thinning thickness is any value between 1.5 and 3 μm.

[0086] Specifically, the stripping surface can be thinned by an etching thinning process according to a preset thinning thickness, and then the stripping surface after the thinning process is exposed, and the exposed stripping surface after the thinning process is used as the second surface of the stripped epitaxial layer. The preset thinning thickness can be 1.5μm, 1.8μm, 2μm, 2.3μm, 2.5μm, 2.7μm, or 3μm.

[0087] Step S106, performing conductive treatment on the second surface to form a second device structure.

[0088] The interface for bonding with the silicon substrate in the second device structure is conductive, and the conductive treatment can be achieved by ion implantation or other methods.

[0089] In some embodiments, performing a conductive treatment on the second surface to form a second device structure includes:

[0090] Performing a second ion implantation on the second surface to form a conductive layer in the stripped epitaxial layer; the type of the second ions is different from the type of the first ions; and the upper edge of the conductive layer is flush with the second surface;

[0091] The conductive layer and the well region are subjected to an annealing process to form a second device structure.

[0092] In the embodiments of the present application, Figure 5As shown, by performing a second ion implantation on the second surface a2, a conductive layer 224 is formed in the stripped epitaxial layer 220a, and the upper edge of the conductive layer 224 can be flush with the second surface. The type of the second ion is different from the type of the first ion. Unlike the first ion used for film stripping, the second ion can be an ion used to form a conductive layer, such as one or more N-type implanted ions such as nitrogen and phosphorus, and the implantation dose is 5E13-1E16 / cm 2 , the injection energy is 5keV~30keV.

[0093] Furthermore, after the second ion implantation, the conductive layer 224 and the well region 230 are subjected to an annealing treatment to activate all implanted doping regions to form a second device structure. In this way, there is no need to immediately perform an activation treatment after the well region with embedded doped sub-regions is prepared, but the conductive layer and the well region are activated together, thereby reducing the activation process and shortening the device preparation process. In addition, by reducing the number of activations, the defects or adverse effects caused by the activation can be reduced, which is beneficial to improving the recycling value of the silicon carbide single crystal substrate and the overall device performance.

[0094] In some embodiments, the processing conditions of the primary annealing process may include at least one of the following:

[0095] The annealing environment is vacuum, nitrogen atmosphere, or argon atmosphere (pressure is 0.2 to 0.5 atmospheres);

[0096] The annealing temperature is 1500-1800°C, the annealing time is 0.5-5 hours, and the annealing time is inversely proportional to the annealing temperature;

[0097] A carbon film is applied for protection before annealing. The thickness of the carbon film is 100 to 1000 nanometers. The thickness of the carbon film is directly proportional to the annealing temperature and inversely proportional to the annealing pressure.

[0098] Step S107 , obtaining a silicon substrate with double-sided implantation layers, and performing secondary bonding with the inverted second device structure based on the second surface.

[0099] In some embodiments, obtaining a silicon substrate having a double-sided implantation layer includes: providing an initial silicon substrate; and performing ion implantation treatment on the top surface and the back surface of the initial silicon substrate to obtain a silicon substrate having a double-sided implantation layer.

[0100] The conductivity type of the initial silicon substrate may be the same as the conductivity type of the silicon carbide single crystal substrate 210. For example, the initial silicon substrate may be an N-type low-resistance silicon wafer. Optionally, the resistance of the initial silicon substrate is less than or equal to 10 ohms, for example, the resistance of the initial silicon substrate is 0.01 to 10 ohms.

[0101] The conductivity types of the ions implanted in the double-sided implantation layers are opposite. Exemplarily, the double-sided implantation layers may include a first implantation layer and a second implantation layer. In the first implantation layer and the second implantation layer, one of them is implanted with P-type implantation ions (e.g., boron), and the other is implanted with N-type implantation ions (e.g., phosphorus) of opposite conductivity type to the P-type.

[0102] In some embodiments, the above-mentioned ion implantation treatment is performed on the top surface and the back surface of the initial silicon substrate to obtain a silicon substrate with a double-sided implantation layer, including:

[0103] Performing ion implantation of a first conductivity type on the top surface of the initial silicon substrate to form a first implantation layer;

[0104] Performing ion implantation of a second conductivity type on the back side of the initial silicon substrate to form a second implantation layer;

[0105] A double-sided implantation layer is formed based on the second implantation layer and the first implantation layer, thereby obtaining a silicon substrate having a double-sided implantation layer.

[0106] The ion implantation energy of the first conductive type and the ion implantation energy of the second conductive type are both lower than the ion implantation energy of the first ion implantation. In the aforementioned step S102, the ion implantation energy of the first ion is relatively large, and the ion implantation energy of the first ion is at the level of mega-electron volts, for example, 2MeV to 10MeV. Here, the ion implantation energy of the initial silicon substrate is at the level of kilo-electron volts, both of which are lower than the ion implantation energy of the first ion.

[0107] In the case where the second conductivity type is different from the conductivity type of the silicon carbide single crystal substrate, the ion implantation energy of the second conductivity type is higher than the ion implantation energy of the first conductivity type.

[0108] In some embodiments, the first conductivity type is an N-type conductivity type, and the second conductivity type is a P-type conductivity type; and during the secondary bonding process, the first injection layer is close to the second device structure, and the second injection layer is far away from the second device structure. Here, the purpose of injecting ions of the first conductivity type (e.g., phosphorus ions) into the bonding surface bonded to the second device structure is to increase the doping concentration near the surface to reduce the bonding interface resistance of the SiC-Si bonding structure. In addition, the purpose of injecting ions of the second conductivity type (e.g., boron ions) into the back side is to form a P-type region on the back side to meet the preparation requirements of the IGBT device structure.

[0109] In some embodiments, when the first conductivity type is N-type and the second conductivity type is P-type, the ion implantation energy of the first conductivity type is 5keV to 30keV, for example, 5keV, 8keV, 10keV, 12keV, 18keV, 20keV, 24keV, 28keV and 30keV, and the corresponding ion implantation dose is 1E15 to 1E17 / cm 2 Furthermore, the ion implantation energy of the second conductivity type is 50keV to 200keV, for example, 50keV, 80keV, 100keV, 120keV, 140keV, 160keV, 180keV and 200keV, and the corresponding ion implantation dose is 1E16 to 1E18 / cm 2 .

[0110] The number of times of the ion implantation of the first conductivity type and / or the ion implantation of the second conductivity type may be one or more times. When the number of implantations is multiple times, the energy of each ion implantation may be different, so that the uniformity of doping in the silicon substrate can be improved by using multiple implantations with different energies, thereby improving the performance of the device.

[0111] In a specific embodiment, Figure 6 As shown, after obtaining an initial N-type low-resistance silicon substrate 250, ions of the first conductive type (e.g., phosphorus ions) are implanted on the top surface of the initial silicon substrate 250 through an ion implantation process to form a first implantation layer (N+ region) 252; and ions of the second conductive type (e.g., boron ions) are implanted on the back surface of the initial silicon substrate to form a second implantation layer (P+ region) 252, thereby obtaining a silicon substrate 250a comprising a first implantation layer and a second implantation layer.

[0112] like Figure 7 As shown, after obtaining the silicon substrate 250a with double-sided injection layers, the silicon substrate can be bonded to the inverted second device structure for a second time through a wafer bonding process, and the exposed surface of the first injection layer 252 of the silicon substrate is used as the bonding interface on the silicon substrate side, that is, during the secondary bonding process, the first injection layer 252 is close to the second device structure, and the second injection layer 254 is far away from the second device structure. The wafer bonding process includes but is not limited to one or more of direct bonding and hydrophilic bonding. Taking direct bonding as an example, the surface to be bonded is subjected to plasma activation treatment, and the two surfaces are directly bonded. The type of plasma activation includes but is not limited to nitrogen, oxygen or argon, and the bonding temperature can be 20-800°C.

[0113] Step S108, removing the middle silicon carbide substrate and activating the bonding interface to form a third device structure.

[0114] like Figure 8As shown, after the secondary bonding, the intermediate silicon carbide substrate 240 can be removed by, for example, a thinning process (e.g., mechanical grinding, etc.), leaving the epitaxial layer 220a, the conductive layer 224, and the silicon substrate 250. Next, the bonding interface between the silicon substrate and the second device structure is activated by an activation process to form a third device structure.

[0115] In some embodiments, activating the bonding interface to form the third device structure includes: performing a secondary annealing process on the device structure with the intermediate silicon carbide substrate 240 removed to activate the bonding interface between the silicon substrate and the inverted second device structure to form the third device structure.

[0116] In some embodiments, the processing conditions of the secondary annealing process may include at least one of the following:

[0117] The annealing environment is vacuum, nitrogen atmosphere, or argon atmosphere (pressure is 0.2 to 0.5 atmospheres);

[0118] The annealing temperature is 1300-1370°C, and the annealing time is 3-5 hours. The annealing time is inversely proportional to the annealing temperature.

[0119] A carbon film is applied for protection before annealing. The thickness of the carbon film is 100 to 500 nanometers. The thickness of the carbon film is directly proportional to the annealing temperature and inversely proportional to the annealing pressure.

[0120] Step S109: preparing an electrode layer on the third device structure to form a bipolar power device.

[0121] The electrode layer includes a gate oxide layer and a metal layer. After the third device structure is formed, a gate oxide layer and a metal layer can be prepared on the third device structure to form a bipolar power device.

[0122] In some embodiments, Fig. 9 As shown, the gate oxide layer 260 may include a gate electrode 264 and an interlayer dielectric layer 262 . The interlayer dielectric layer 262 is disposed on the top surface of the third device structure, and the gate electrode 264 is disposed inside the interlayer dielectric layer 262 .

[0123] The metal layer 280 includes a first metal layer 282 disposed on the back of the third device structure and used to form a drain, and a second metal layer 284 disposed on the top surface of the third device structure and used to form a source. The first metal layer 282 is disposed on the back of the silicon substrate 250a in the third device structure. The middle portion of the second metal layer 284 covers the gate oxide, and the two side portions of the second metal layer 284 cover the top surface of the third device structure and are flush with the side surfaces of the third device structure. Specifically, a second metal layer 284 is deposited on the upper surface of the third device structure and the upper surface of the gate oxide layer 260, and a source is formed by an annealing process. Among them, the material of the deposited metal includes but is not limited to Al, AlCu (aluminum-copper alloy), AlSiCu (aluminum-silicon-copper alloy), and the thickness of the second metal layer can be 1 to 10 μm.

[0124] It should be noted that the bipolar power device formed here may refer to an insulated gate bipolar transistor IGBT.

[0125] In the above-mentioned embodiment, a high-quality silicon carbide single crystal substrate is used to homogeneously grow an epitaxial layer, and the epitaxial layer is used to bond with a low-quality intermediate silicon carbide substrate, and a part of the device structure including the high-quality first silicon carbide substrate is peeled off through a peeling layer formed in the epitaxial layer, and then the peeled device structure is transferred to a silicon substrate having a double-sided injection layer through bonding, and a well region embedded with a doped sub-region is separately manufactured from an electrode layer to form a bipolar power device, thereby first transferring the epitaxial silicon carbide film to a low-cost intermediate silicon carbide substrate, and then transferring it to the silicon substrate through heterogeneous bonding, while overcoming the difficulty of preparing silicon-based silicon carbide materials, reducing the cost of silicon carbide single wafers, and further combining with a silicon substrate having a double-sided injection layer to overcome the difficulty of overall doping on the epitaxial silicon carbide film, and at the same time, the prepared bipolar power device contains a peeled silicon carbide epitaxial layer, giving full play to the excellent performance of the silicon carbide material itself, therefore, the present application provides a solution for low-cost preparation of high-voltage bipolar power devices.

[0126] In addition, at the current 8-inch diameter expansion, the problems of defect control in the silicon carbide growth process and material loss caused by cutting, grinding and polishing have further highlighted the silicon carbide yield and cost issues, thus increasing the production cost of homoepitaxially generating single-crystal silicon carbide films on large-sized silicon carbide substrates, hindering the large-scale use of silicon carbide in the semiconductor field. Using the device preparation method provided by the present application, the prepared bipolar power device does not contain a high-quality first silicon carbide substrate, and only a high-quality silicon carbide single crystal substrate is used to homoepitaxially grow a silicon carbide epitaxial layer. By transferring the epitaxial silicon carbide film to a low-cost intermediate silicon carbide substrate, the high-quality silicon carbide single crystal substrate can be recycled and reused, reducing the dependence on high-quality silicon carbide materials and reducing device costs.

[0127] In some embodiments, the above method further includes: recycling the peeled silicon carbide single crystal substrate.

[0128] In some embodiments, the recycling step may include: firstly subjecting the peeled silicon carbide single crystal substrate to thermal oxidation treatment, then using hydrofluoric acid to remove the oxide layer, and finally polishing the remaining surface of the silicon carbide single crystal substrate after the hydrofluoric acid treatment, so as to obtain a recycled silicon carbide single crystal substrate. The recycled silicon carbide single crystal substrate can continue to be used in the preparation of bipolar power devices, so as to realize the recycling of silicon carbide single crystal substrates. This recycling method is different from the conventional grinding and polishing process. It can maximize the number of times the substrate is used while ensuring the wafer morphology of the substrate, thereby reducing the production cost of the prepared bipolar power device while taking into account the performance of silicon carbide.

[0129] In a specific embodiment, the recovery process may specifically include: firstly thermally oxidizing the peeled silicon carbide single crystal substrate, wet oxidizing it in a 1300°C pure oxygen environment for 2 to 5 hours; then using hydrofluoric acid wet etching to remove the oxide layer, and finally fine polishing the remaining surface of the silicon carbide single crystal substrate after the hydrofluoric acid treatment, and the film removal thickness does not exceed 500nm, so as to obtain a recycled silicon carbide single crystal substrate.

[0130] Since the ion implantation energy is large and the stripping layer is deep, it is difficult to solve the problem with a simple chemical mechanical polishing process. The stripping layer after injection is more easily oxidized due to defects, so a high-temperature thermal oxidation treatment is proposed, especially a thermal oxidation temperature higher than the silicon oxidation temperature, such as a thermal oxidation temperature of 1300°C, which is higher than the silicon oxidation temperature to improve efficiency. After the stripping layer is completely oxidized, the intact lattice below is better preserved due to the dual effects of the single crystal and the top oxide layer protection. Through hydrofluoric acid wet etching and a small amount of removal, the surface stripping layer can be completely removed while ensuring the wafer morphology. Finally, only a small amount of polishing removal is required to retain the high-quality silicon carbide substrate to the maximum extent, ensure the wafer morphology of the substrate, and maximize the number of times the substrate is used.

[0131] It should be noted that the silicon carbide single crystal substrate used in the above steps may be a silicon carbide substrate obtained through the above recycling process.

[0132] An embodiment of the present application also provides a bipolar power device, and the bipolar power device is prepared by any of the above-mentioned methods for preparing a bipolar power device.

[0133] In some embodiments, taking the bipolar power device as an insulated gate bipolar transistor IGBT as an example, the following steps are continued: Fig. 9As shown, the bipolar power device includes a silicon substrate 250a having a double-sided implantation layer, a stripped epitaxial layer 220a disposed on the silicon substrate 250a, a gate oxide layer 260 and a metal layer 280. The silicon substrate 250a and the stripped epitaxial layer 220a are made of different materials.

[0134] A conductive layer 226 is provided in a portion of the stripped epitaxial layer 220a close to the silicon substrate 250a, and an activated well region embedded with doped sub-regions is provided in the stripped epitaxial layer 220a. The well region embedded with doped sub-regions includes a first initial well region and a second initial well region arranged side by side and at intervals, and a first doped sub-region and a second doped sub-region of opposite conductivity types respectively arranged in the first initial well region and the second initial well region, the first initial well region and the second initial well region can be arranged at two corner regions of the epitaxial layer, and the upper surfaces of the first doped sub-region and the second doped sub-region can be respectively flush with the upper surface of the stripped epitaxial layer.

[0135] In some embodiments, the gate oxide layer 260 may include a gate 264 and an interlayer dielectric layer 262 . The interlayer dielectric layer 262 is disposed on the top surface of the third device structure, and the gate 264 is disposed inside the interlayer dielectric layer 262 .

[0136] The metal layer 280 includes a first metal layer 282 disposed on the back of the third device structure and used to form a drain, and a second metal layer 284 disposed on the top surface of the third device structure and used to form a source. The first metal layer 282 is disposed on the back of the silicon substrate in the third device structure. The middle portion of the second metal layer 284 covers the gate oxide, and the two side portions of the second metal layer 284 cover the top surface of the third device structure and are flush with the side surfaces of the third device structure. Specifically, a second metal layer 284 is deposited on the upper surface of the third device structure and the upper surface of the gate oxide layer, and a source is formed by an annealing process. The material of the deposited metal includes but is not limited to Al, AlCu (aluminum-copper alloy), and AlSiCu (aluminum-silicon-copper alloy), and the thickness of the formed second metal layer can be 1 to 10 μm.

[0137] In some embodiments, the silicon carbide single crystal substrate used in the preparation process of the above-mentioned bipolar power device may be a silicon carbide substrate obtained after a stripping and recycling process.

[0138] In some embodiments, the recycling step may include: firstly subjecting the peeled silicon carbide single crystal substrate to thermal oxidation treatment, then removing the oxide layer with hydrofluoric acid, and finally polishing the remaining surface of the silicon carbide single crystal substrate after the hydrofluoric acid treatment, so as to obtain a recycled silicon carbide single crystal substrate. The recycled silicon carbide single crystal substrate can continue to be used in the preparation of bipolar power devices, so as to realize the recycling of the silicon carbide single crystal substrate. This recycling method is different from the conventional grinding and polishing process, and can maximize the number of times the substrate is used while ensuring the wafer morphology of the substrate.

[0139] In a specific embodiment, the recycling process may specifically include: firstly subjecting the peeled silicon carbide single crystal substrate to thermal oxidation treatment, wet oxidation in a 1300°C pure oxygen environment for 2 to 5 hours; then using hydrofluoric acid wet etching to remove the oxide layer, and finally fine polishing the remaining surface of the silicon carbide single crystal substrate after hydrofluoric acid treatment, with the film removal thickness not exceeding 500nm, to obtain the recycled silicon carbide single crystal substrate. This recycling method is different from the conventional grinding and polishing process, and can maximize the number of times the substrate is used while ensuring the wafer morphology of the substrate, thereby greatly reducing the production cost of the prepared bipolar power device while taking into account the performance of silicon carbide.

[0140] It should be noted that the specific details and beneficial effects of the above-mentioned device embodiment can be found in the above-mentioned method embodiment, which will not be repeated here.

[0141] The above description has fully disclosed the specific implementation methods of the present application. It should be pointed out that any changes made by technicians familiar with the field to the specific implementation methods of the present application do not deviate from the scope of the claims of the present application. Accordingly, the scope of the claims of the present application is not limited to the above specific implementation methods.

Claims

1. A method for preparing a bipolar power device, characterized in that: The following steps are involved: Providing a silicon carbide single crystal substrate, and homoepitaxially growing an epitaxial layer on the silicon carbide single crystal substrate; Performing a first ion implantation on the exposed first surface of the epitaxial layer to form a stripping layer in the epitaxial layer; the implantation energy of the first ions in the epitaxial layer is 5 to 15 times the conventional ion implantation energy, and the distance between the stripping layer and the exposed first surface of the epitaxial layer is greater than the distance between the stripping layer and the lower edge of the epitaxial layer; A well region embedded with doped sub-regions is formed between the first surface and the stripping layer to form a first device structure without an electrode layer; in a process between the step of forming the first device structure and the step of performing a subsequent conductive treatment, the well region embedded with doped sub-regions does not need to be annealed for doping activation; Providing an intermediate silicon carbide substrate, and performing a primary bonding with the first device structure based on the first surface; The substrate quality of the silicon carbide single crystal substrate is higher than the substrate quality of the intermediate silicon carbide substrate; Along the layer direction of the peeling layer, a portion of the device structure including the silicon carbide single crystal substrate is peeled off, and a peeling surface of the peeled device structure is post-processed to expose the second surface of the peeled epitaxial layer; the peeled device structure does not include the silicon carbide single crystal substrate; Conducting a conductive treatment on the second surface to form a second device structure; the second device structure does not include the silicon carbide single crystal substrate; performing an annealing treatment during the formation of the second device structure, the annealing treatment at least used to activate the dopant in the well region embedded with the doped sub-region, the annealing treatment being performed after the step of stripping off the silicon carbide single crystal substrate; Obtaining a silicon substrate having a double-sided implantation layer, and performing secondary bonding with the inverted second device structure based on the second surface; The ions respectively implanted in the double-sided implantation layer include a first conductivity type and a second conductivity type having opposite conductivity types; when the second conductivity type is different from the conductivity type of the silicon carbide single crystal substrate, the ion implantation energy of the second conductivity type is higher than the ion implantation energy of the first conductivity type close to the second device structure; removing the intermediate silicon carbide substrate and activating the bonding interface to form a third device structure; preparing an electrode layer on the third device structure to form a bipolar power device; Wherein, after forming the second device structure, the method further comprises: Recycling the peeled silicon carbide single crystal substrate to obtain a recycled silicon carbide single crystal substrate; the recycled silicon carbide single crystal substrate is used to prepare the bipolar power device; The recycling step includes: sequentially performing thermal oxidation treatment, hydrofluoric acid treatment and polishing treatment on the peeled silicon carbide single crystal substrate, wherein the thickness of the film removed after polishing does not exceed 500nm, thereby obtaining the recycled silicon carbide single crystal substrate; wherein the conditions for the thermal oxidation treatment include: wet oxidation in a pure oxygen environment at 1300°C for 2 to 5 hours.

2. The method according to claim 1, characterized in that: The step of obtaining a silicon substrate having a double-sided implantation layer comprises: providing an initial silicon substrate; The top surface and the back surface of the initial silicon substrate are respectively subjected to ion implantation treatment to obtain the silicon substrate with double-sided implantation layers.

3. The method according to claim 2, characterized in that The step of performing ion implantation on the top surface and the back surface of the initial silicon substrate to obtain the silicon substrate with double-sided implantation layers comprises: Performing ion implantation of a first conductivity type on the top surface of the initial silicon substrate to form a first implantation layer; Performing ion implantation of a second conductivity type on the back side of the initial silicon substrate to form a second implantation layer; The double-sided injection layer is formed based on the second injection layer and the first injection layer, thereby obtaining the silicon substrate with the double-sided injection layer; The ion implantation energy of the first conductive type and the ion implantation energy of the second conductive type are both lower than the ion implantation energy of the first ion implantation.

4. The method according to claim 3, characterized in that The first conductivity type is an N-type conductivity type, and the second conductivity type is a P-type conductivity type; And in the secondary bonding process, the first injection layer is close to the second device structure, and the second injection layer is far away from the second device structure.

5. The method according to claim 4, characterized in that The ion implantation energy of the first conductive type is 5keV to 30keV, and the implantation dose is 1E15 to 1E17 / cm 2 ; The ion implantation energy of the second conductivity type is 50keV to 200keV, and the implantation dose is 1E16 to 1E18 / cm 2 .

6. The method according to any one of claims 1 to 5, characterized in that: The implantation parameters of the first ion include at least one of the following: The implanted element of the first ion includes one or more of hydrogen ions and helium ions; The implantation dose of the first ion is in the range of 1E17 / cm 2 ~1E20 / cm 2 ; The implantation energy of the first ions ranges from 2 MeV to 10 MeV.

7. The method according to any one of claims 1 to 5, characterized in that: The doping elements of the epitaxial layer include one or more of nitrogen and phosphorus, and the doping concentration range is 1E12-1E15 / cm 3 ; The measurement dimensions of the substrate quality include one or more of the substrate crystal type quantity, substrate crystal type, and substrate defect density.

8. The method according to any one of claims 1 to 5, characterized in that: The post-processing of the peeled surface to expose the second surface of the peeled epitaxial layer comprises: Based on a preset thinning thickness, the peeling surface is thinned; Using the exposed peeled surface after the thinning process as the second surface in the peeled epitaxial layer; The preset thinning thickness is any value between 1.5 and 3 μm.

9. The method according to any one of claims 1 to 5, characterized in that: The performing conductive processing on the second surface to form a second device structure comprises: Performing a second ion implantation on the second surface to form a conductive layer in the stripped epitaxial layer; the type of the second ions is different from the type of the first ions; and the upper edge of the conductive layer is flush with the second surface; The conductive layer and the well region are subjected to an annealing process to form the second device structure.

10. The method according to any one of claims 1 to 5, characterized in that: The activating the bonding interface to form the third device structure comprises: A secondary annealing process is performed on the device structure with the intermediate silicon carbide substrate removed to activate the bonding interface between the silicon substrate and the inverted second device structure to form the third device structure.

11. A bipolar power device, characterized in that: The bipolar power device is prepared by the method described in any one of claims 1-10.

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