Copper connection on glass panels for glass modules

Abstract

Copper-attached glass modules on glass panels are provided. An apparatus includes one or more dies, an interposer formed of a first material, the interposer coupled to the one or more silicon dies, the interposer including an interconnect layer formed on a side of the interposer, wherein the interconnect layer includes a plurality of copper interconnects, and a substrate including a top layer, a glass core, and a bottom layer, wherein the interconnect layer of the interposer is copper bonded with the top layer of the substrate.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 319,092, filed March 11, 2022, entitled “COPPER CONNECTED GLASS MODULES ON A GLASS BOARD,” the entire contents of which are incorporated herein by reference.

[0003] COPYRIGHT NOTICE

[0004] A portion of the disclosure of this patent document contains material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure as it appears in the Patent and Trademark Office, Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever. TECHNICAL FIELD

[0005] The present disclosure relates generally to methods, systems, and apparatuses for semiconductor packages including interposers and glass substrates. BACKGROUND

[0006] Complex systems for artificial intelligence training and other high performance computing are increasingly built from arrays of compute nodes, each implemented in a system-in-a-package module that typically contains one or more processor dies, a corresponding high bandwidth memory (HBM) module, and in some cases an input / output (I / O) die that drives a co-packaged optical device or a co-packaged copper output. As the systems scale, additional compute capability, memory capacity, and compute-to-memory bandwidth as well as off-module I / O bandwidth similarly increase, beyond the capabilities of conventional system-in-a-package technology.

[0007] Accordingly, methods, systems, and apparatuses for copper connected glass modules on a glass board are provided. SUMMARY

[0008] In one aspect, the present disclosure relates to an apparatus comprising: one or more dies; an interposer formed of a first material, the interposer coupled to the one or more dies, the interposer including an interconnect layer formed on a side of the interposer, wherein the interconnect layer includes a plurality of copper interconnects; and a substrate including a top layer, a glass core, and a bottom layer, wherein the interconnect layer of the interposer is copper bonded with the top layer of the substrate.

[0009] In another aspect, the disclosure relates to a semiconductor device comprising: a plurality of semiconductor modules, each semiconductor module comprising: one or more dies; an interposer formed of a first material, the interposer coupled to the one or more dies, the interposer comprising a first interconnect layer formed on a side of the interposer, wherein the first interconnect layer includes a plurality of copper interconnects; and a substrate comprising a first top layer, a first glass core, and a first bottom layer, wherein the first interconnect layer of the interposer is copper bonded with the top layer of the substrate; a circuit board coupled to the one or more semiconductor modules, the circuit board comprising a second top layer, a second bottom layer, and a second glass core, wherein the first bottom layer of the substrate is copper bonded with the second top layer of the circuit board.

[0010] In a further aspect, the disclosure relates to a method comprising: forming a first interconnect layer on a first side of an interposer, wherein the first interconnect layer includes a first plurality of copper interconnects, wherein the first interconnect layer is configured to couple the interposer to a substrate, and wherein the interposer is formed of a first material; bonding the first interconnect layer to a first top layer of the substrate via a copper bonding process, the substrate comprising the first top layer, a first glass core, and a first bottom layer; forming a second interconnect layer on the first bottom layer of the substrate, wherein the second interconnect layer includes a second plurality of copper interconnects, wherein the second interconnect layer is configured to couple the substrate to a circuit board; and bonding the second interconnect layer to a second top layer of the circuit board via the copper bonding process, the circuit board comprising the second top layer and a second glass core. BRIEF DESCRIPTION OF DRAWINGS

[0011] Further understanding of the nature and advantages of particular embodiments can be realized by reference to the remaining portions of the specification and the attached drawings, wherein like reference numerals are used throughout. In some instances, sub-labels are associated with an element number to indicate one of multiple similar elements. When reference is made to a structure or property that can relate to more than one element, the reference is intended to relate to all such elements collectively.

[0012] Figure 1 is a schematic cross-sectional view of a semiconductor module with a glass substrate according to various embodiments;

[0013] Figure 2 is a schematic top view of an array of semiconductor modules on a glass plate according to various embodiments;

[0014] Figure 3 is a schematic cross-sectional view of an array of copper-connected semiconductor modules on a glass plate according to various embodiments;

[0015] Figure 4 is a schematic top view of an array of copper-connected semiconductor modules on a glass plate according to various embodiments; and

[0016] Figure 5 is a flowchart of a method of fabricating a copper bonded semiconductor module array according to various embodiments. DETAILED DESCRIPTION

[0017] Various embodiments set forth glass modules and copper bonded arrays of glass modules, as well as methods of fabricating glass modules and copper bonded arrays of glass modules.

[0018] In some embodiments, an apparatus is provided. The apparatus includes one or more dies; an interposer formed of a first material, the interposer coupled to the one or more silicon dies, the interposer including an interconnect layer formed on a side of the interposer, wherein the interconnect layer includes a plurality of copper interconnects; and a substrate including a top layer, a glass core, and a bottom layer, wherein the interconnect layer of the interposer is copper bonded with the top layer of the substrate.

[0019] In some embodiments, a semiconductor device is provided. The semiconductor device includes a plurality of semiconductor modules and a circuit board. Each semiconductor module includes one or more dies; an interposer formed of a first material, the interposer coupled to the one or more dies; and a substrate. The interposer includes a first interconnect layer formed on a side of the interposer, wherein the first interconnect layer includes a plurality of copper interconnects. The substrate includes a first top layer, a first glass core, and a first bottom layer, wherein the first interconnect layer of the interposer is copper bonded with the top layer of the substrate. The circuit board is coupled to the one or more semiconductor modules, the circuit board including a second top layer, a second bottom layer, and a second glass core, wherein the first bottom layer of the substrate is copper bonded with the second top layer of the circuit board.

[0020] In further embodiments, a method of fabricating a copper bonded glass module is provided. The method includes forming a first interconnect layer on a first side of an interposer, wherein the first interconnect layer includes a first plurality of copper interconnects, wherein the first interconnect layer is configured to couple the interposer to a substrate, and wherein the interposer is formed of a first material; and bonding the first interconnect layer to a first top layer of the substrate via a copper bonding process, the substrate including the first top layer, a first glass core, and a first bottom layer. The method continues by forming a second interconnect layer on the first bottom layer of the substrate, wherein the second interconnect layer includes a second plurality of copper interconnects, wherein the second interconnect layer is configured to couple the substrate to a circuit board; and bonding the second interconnect layer to a second top layer of the circuit board via the copper bonding process, the circuit board including the second top layer and a second glass core.

[0021] In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments described. It is apparent, however, to one skilled in the art that embodiments can be practiced without some or all of these details. Several embodiments are described herein, and although various features are attributed to different embodiments, it can be appreciated that features of one embodiment can be incorporated into another embodiment. However, for the sake of brevity, not every feature of an implementation is always described in detail. It is to be understood that the terminology specifically used herein is for the purpose of describing particular embodiments and the scope of the application should not be limited accordingly.

[0022] Similarly, when an element is referred to as being "connected" or "coupled" to another element, it should be understood in an optional sense that the element can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, it should be understood in a mandatory sense that no

[0023] Similarly, when an element is referred to as being "connected" or "coupled" to another element, it should be understood in an optional sense that the element can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, it should be understood in a mandatory sense that no

[0024] Also, when an element is referred to as being "a layer", it should be understood that the layer can be a single layer or include a plurality of layers. When a layer is described as coupled or connected to another layer, it should be understood that the coupled or connected layer can include intervening elements present between the coupled or connected layers. In contrast, when a layer is referred to as being "directly" connected or coupled to another layer, it should be understood that no intervening elements are present between the layers. However, the presence of a directly coupled or connected layer does not preclude the presence of other connections in which intervening elements can be present.

[0025] Furthermore, the described methods and processes can be described in specific orders, sequences, or flowcharts. However, it should be understood that the intermediate processes can be performed in different orders, omitted, added, and / or combined with other processes, unless the context clearly dictates otherwise.

[0026] Unless otherwise indicated, all numbers expressing quantities, dimensions, and so forth used herein are to be understood as approximations based on the terminology used to the precision of the measurement. In this application, the use of "about" means that variations of ±20 percent, preferably ± 10 percent, and more preferably ± 5 percent are encompassed by the term. Unless otherwise indicated, the use of the terms "at least one" and "one or more" will be understood to include single as well as multiple references. Also, the use of "either," "or" will be understood to include both "either," as well as "or," unless otherwise indicated.

[0027] Conventional semiconductor packages for arrayed module systems rely on solder joints to attach processor dies and associated HBMs to packages, both with and without interposers. Conventional assemblies utilize packaging materials (e.g., substrates and / or circuit boards) formed from organic resins and polymers that have a significant coefficient of thermal expansion (CTE) mismatch with silicon. Solder provides some compliance, but scaling of the system is limited by the thermal expansion mismatch. In addition, due to the low electromigration resistance of ordinary solder, a large number of connections are used to meet the current / electrical current requirements of a given system, which increases cost and package size. Specifically, the package substrates and boards are complex, typically having many wiring layers and thick dielectric layers, due to the need to route a large number of high-speed signals through the package and out through a printed circuit board (PCB).

[0028] By utilizing glass modules to create an array of glass modules on a glass board, CTE matched materials can be used for the active circuitry, interposer, and package core as well as the board. Thus, more conductive joints with higher current density capacity can be used to connect the top layers of the circuit to the bottom layers, such as through mixed copper bonding, to the glass core module substrate from the interposer, and to the glass board from the glass core module substrate, such as through direct copper bonding. The increased current density of the joints allows for the size of the modules to be reduced, which further shortens the transmission length on the board, which further facilitates inter-module communication via local interconnects, such as through bridging dies between modules.

[0029] Furthermore, because of the CTE match, a partitioned-overlapping interposer (as described below) can have a large surface area, allowing zero-offset connections to multiple HBM stacks, which in turn allows "active routing" (also described below) in the HBM buffer die to shorten the HBM-to-logic channel for wider, higher bandwidth density HBM-to-logic connections. Specifically, in a conventional interposer, the interface circuitry on the HBM (e.g., driver-receiver circuitry that communicates with the die) cannot be directly opposite the corresponding interface circuitry on the compute die. The HBM is offset so that some portion of the interconnect between the two interfaces extends at an angle. Such an offset is typically utilized because the number and size of HMBs typically exceeds what can be supported by the perimeter of the die. Thus, the HMBs are placed with an offset, resulting in increased interconnect length.

[0030] By utilizing a CTE-matched and partitioned-overlapping interposer, the die perimeter can be effectively expanded so that all HBM can be accommodated without offset. An offset requires a minimum distance between the interface circuitry on the HBM and the interface circuitry on the die to allow for the diagonal routing (typically limited to 45 degrees). By eliminating all offsets, the interface circuitry on the HBM can be moved from the typical location of about the center of the HBM to directly facing the edge of the die—allowing "active routing" on the HBM base die—with zero offset. Specifically, with active routing, the signals of the HBM can be routed from the DRAM interface located centrally below the HBM stack to the interface circuitry (or in this case, the interposer) at the base die edge facing the compute die using on-die interconnects with active repeaters as needed. With the interfaces on the interposer and the interfaces on the HBM base die aligned at facing edges, the channel length between the interfaces is minimized, allowing the interfaces to be more efficient (e.g., higher speed and density, lower power).

[0031] Furthermore, because the high-speed I / O off-module is achieved through a physically compliant connection (e.g., fiber array or passive copper cable), the through-glass via (TGV) in the glass module core and glass plate can be optimized for power delivery. Specifically, by using the back surface of the glass plate for voltage down conversion, power delivery to the plate can be achieved at high voltage through a flexible cable, with high current carried over only a short vertical distance.

[0032] Figure 1is a schematic illustration of a cross-sectional view of a semiconductor module 100 according to various embodiments. The semiconductor module 100 includes a glass substrate 105, one or more HBM dies 110a, 110b, an interposer 115, which can include one or more interposer partitions 115a-c, one or more compute dies 120a, 120b, a fill die 125, and a silicon carrier die 130. It should be noted that various components of the semiconductor module 100 are schematically illustrated in Figure 1

[0033] In various embodiments, the glass substrate 105 can be a substrate of a semiconductor device that includes an upper layer 105a, a core 105b, and a bottom layer 105c. In some examples, the glass substrate 105 can include a core 105b having a CTE that matches the CTE of silicon. In some examples, the core 105b can be a glass configured to have a CTE that matches the CTE of silicon. In some examples, the glass can be configured to match the CTE of the interposer 115 (e.g., the interposer partitions 115a-c of the interposer 115) and / or the one or more compute dies 120a, 120b. A die (e.g., the one or more compute dies 120a, 120b, the fill die 125, and the silicon carrier die 130) includes a piece of semiconductor material (e.g., silicon or other semiconductor) on which a circuit or set of circuits (e.g., an IC) is fabricated. An interposer (e.g., the interposer 115) includes electrical interfaces formed of silicon or organic material that couple the die to other components (including other dies) and / or a substrate (e.g., a package substrate). The interposer can include interconnects such as through-hole vias, conductive lines, and conductive pillars. A substrate (e.g., a package substrate) such as the glass substrate 105 includes a planar structure (formed of silicon, glass, or other suitable material) on which dies and other components (e.g., passive elements) can be mounted (e.g., via an interposer).

[0034] In various examples, the interposer 115 can be formed of a material (e.g., silicon and / or an organic compound) on which the copper interconnect layers 135 can be formed. Thus, the CTE of the interposer 115 can refer to the CTE of the material forming the interposer 115, rather than the CTE of the material of the copper interconnect layers 135 (e.g., copper). For example, in some embodiments, the interposer 115 is formed of silicon. In further examples, the interposer 115 is formed of an organic compound. Thus, in some examples, the CTE of the core 105b can match the CTE of silicon, or in other examples, the CTE of the organic material forming the interposer 115.

[0035] ​In various examples, the CTE of the core 105b of the glass substrate 105 can be adjusted using various techniques, such as controlling the formation (e.g., crystallization) process of the glass, as well as through material selection for forming the glass. Further, it should be appreciated that the material for the core 105b of the glass substrate 105 is not limited to any one type of glass (which includes glass-ceramic) material, and any suitable glass material having a CTE as described can be utilized.

[0036] In some examples, the interposer 115 can include one or more interposer partitions 115a-c. Thus, the interposer 115 can be a layer of the semiconductor module 100 that includes an interposer. As is known by those skilled in the art, an interposer includes electrical and / or physical interfaces through which connections can be facilitated from the one or more compute dies 120a, 120b, as well as, for example, the glass substrate 105. In some examples, the interposer 115 (e.g., interposer) can include one or more interconnects to physically and / or electrically couple the one or more compute dies 120a, 120b to one or more wiring layers of the glass substrate 105. The one or more interconnects of the interposer 115 include, for example, through-silicon vias (TSVs) and / or TGVs, micro bumps, copper pads, and / or copper pillars (CuPs). Thus, in some embodiments, the interconnects of the interposer 115 can be referred to as an “interconnect layer,” such as a copper interconnect layer 135, which can further include a plurality of copper interconnects, as described above.

[0037] Further, as used herein, a layer can itself include one or more layers. Thus, the copper interconnect layer 135 includes one or more layers of the interposer 115 that include respective interconnects (e.g., copper lines or traces, microstrips, copper pads, copper pillars, and through-hole vias, such as TGVs). Thus, in some embodiments, the copper interconnect layer can include one or more redistribution layer (RDL) layers, wiring layers, and / or interconnects through which the interposer 115 can be bonded (e.g., copper bonded) to the glass substrate 105.

[0038] In further embodiments, the interposer 115 can be partitioned into one or more interposer partitions 115a-c that correspond to different dies of the semiconductor module 100. For example, in some embodiments, the interposer can be partitioned into a set of dies that overlap with the top dies (e.g., one or more compute dies 120a, 120b, filler dies 125, and / or carrier dies 130) as one or more interposer partitions. Thus, the interposer die size can be configured such that no stitching is needed between the interposer partitions 115a-c. For example, in some examples, the interposer partitions 115a-c can exceed the maximum field size of a stepper used to pattern the interposer features without shifting the exposure to the pattern interconnect lines, thereby “stitching” the pattern together across the reticle field boundaries.

[0039] In some examples, communication between different interposer partitions 115a-c can be implemented via passive bridge dies, as shown in Figure 2 Accordingly, in some examples, one or more interposer partitions 115a-c can be configured to communicate vertically with one or more compute dies 120a, 120b in an overlap region. Thus, in some embodiments, a given interposer partition of one or more interposer partitions 115a-c can be at least partially overlapped by at least one of a top die (e.g., one or more compute dies 120a, 120b, a fill die 125, and / or a carrier die 130). In some further examples, multiple top dies can overlap with individual ones of one or more interposer partitions 115a-c. In yet further examples, individual ones of one or more interposer partitions 115a-c can be completely overlapped by a top die.

[0040] In yet further examples, because the CTE is matched between the substrate 105 and the interposer 115, a single, monolithic interposer (not shown) can be utilized that overlaps the one or more compute dies 120a, 120b. In some further examples, the interposer 115 can be coupled to the substrate 105 via copper bonding. For example, in some embodiments, each of the interposers (e.g., one or more interposer partitions 115a-c and / or a single interposer) of the interposer 115 can be copper bonded (e.g., coupled by copper bonding) to the top layer 105a of the substrate 105. In various examples, the copper bonding includes bonding by a copper bonding process. For example, the copper bonding process can include, but is not limited to, hybrid copper bonding (HCB) and / or direct copper bonding (DCB). Thus, in some examples, the interposer 115 can include a copper interconnect layer 135 that can be copper bonded to the top layer 105a of the glass substrate 105. Thus, in some examples, the glass substrate 105 can include a respective copper routing layer 105a on the top layer of the glass substrate. The copper routing layer of the top layer 105a can include various interconnects, such as copper wires, copper traces, microstrip lines, copper pads, and through via vias (e.g., TGVs), among other suitable interconnects. Thus, in some examples, the copper routing layer of the glass substrate 105 can be configured to provide electrical and / or physical connections with other dies coupled on the glass substrate 105, and / or vertical connections (e.g., through TGVs) with the bottom layer 105c of the glass substrate 105 to further couple to other semiconductor packages 100 or circuit boards (e.g., PCBs) or other substrates. In yet further examples, the bottom layer 105c itself can include a copper routing layer, similar to the routing layer of the top layer 105a. The copper routing layer of the bottom layer 105c can include interconnects, such as micro bumps, wires, pads, copper pillars, TGVs, etc., configured to allow the substrate 105 to be coupled to, for example, a circuit board or other substrate. In some examples, the copper routing layer of the substrate 105 includes one or more layers of RDL.

[0041] The semiconductor module 100 can further include HBMs 110a, 110b that can be coupled to the substrate 105, for example, via HBM PHY dies (e.g., physical layer interface dies), I / O dies, and / or through the interposer 115 (e.g., via one or more interposer partitions 115a-c), and further coupled to the one or more compute dies 120a, 120b. A filler die 125 can be provided to fill the gap between the logic dies 120a, 120b and the respective HBMs 110a, 110b. In some examples, a silicon carrier die 130 can be provided that overlaps the one or more logic dies 120a, 120b, and the silicon carrier die 130 is configured to provide additional rigidity to the semiconductor module 100.

[0042] Figure 2is a schematic illustration of a top view of a semiconductor module 200 according to various embodiments. The semiconductor module 200 includes a glass substrate 205, one or more HBM dies 210, an interposer 215, which can include one or more interposer partitions (e.g., interposer partitions 115a-c of Figure 1 FIG. 1), one or more compute dies 220a-d, a fill die 225, a silicon carrier die 230, a bridge die 235, and an I / O die 240. It should be noted that various components of the semiconductor module 200 are schematically illustrated in Figure 2 FIG. 1, and modifications to the various components and other arrangements in the semiconductor module 200 can be made according to various embodiments.

[0043] As previously described with respect to Figure 1 FIG. 1, the semiconductor module 200 can include several dies coupled to the substrate 205 via the interposer 215. The interposer 215 can include one or more interposer partitions, which can be further coupled to the substrate 205 via copper bonding (e.g., HCB and / or DCB). In the top view, one or more compute dies 220a-d are shown, along with the bridge die 235 and the I / O die 240. Thus, Figure 1 it can be a cross-section taken along the line l-l, such that a cross-sectional view of the HBM 210, the fill die 225, the compute dies 220a, 220b, the interposer 215, and the substrate 205 are shown. As previously described, any area of the interposer and / or interposer partitions of the interposer 215 that is not covered by an active and / or passive top die can be covered by a respective fill die 225.

[0044] In various embodiments, because the CTE of the substrate 205 matches the CTE of the interposer of the interposer 215, a larger interposer die size can be utilized. Specifically, the larger interposer (e.g., of the interposer 215) allows for a larger compute area and a larger perimeter that the interposer can utilize to couple to the HBM 210 and the I / O die 240, enabling off-module and off-board communication through co-packaged optics and / or co-packaged copper cabling. Thus, the I / O die 240 includes a dedicated die configured to handle off-die (also referred to as “off-chip”) communication (e.g., communication to or from a given die / IC). This includes die-to-die communication on-board (e.g., between one or more compute dies 220a-d), and further includes off-board communication (e.g., from a die of the semiconductor module 200 to a board off and / or another component that is part of a different module). Thus, in some instances, the I / O die 240 can include one or more communication circuits configured to facilitate off-die communication, respectively. Facilitating off-die communication can include managing, processing, routing, and / or carrying various data signals, for example, between on-board dies and / or off-board dies.

[0045] In various examples, the bridge die 235 (also interchangeably referred to as a "bridge die") is a die configured to act as a silicon bridge between two or more interposer partitions of the interposer 215 in this example. Thus, the bridge die 235 can include various interconnects (e.g., conductive lines, through-hole vias, and / or pads) that electrically couple at least two interposer partitions, allowing data signals to be carried between the at least two interposer partitions coupled via the bridge die 235.

[0046] In some further embodiments, the HBMs 210 can be located off-module and can be coupled to the semiconductor module 200, e.g., via optically connected co-packaging. In some embodiments, zero- offset connections to many HBMs 210 can be possible, which in turn can allow active delivery in the HBM die to shorten the HBM-to-logic channel for wider, higher bandwidth density HBM-to-logic connections.

[0047] Figure 3 and 4 Examples of such semiconductor module arrays are illustrated.

[0048] Figure 3 is a schematic cross-sectional view of a copper-connected semiconductor module array 300 on a glass board in accordance with various embodiments. The array 300 includes one or more semiconductor modules 305a-305n, a copper interconnect layer 310, a circuit board 315, and a plurality of through-glass vias (TGVs) 320. Note that the arrangement of the array 300 is schematically illustrated in Figure 3 and modifications can be made to the arrangement of the array 300 and the semiconductor modules 305a-305n in accordance with various embodiments.

[0049] In various embodiments, the array 300 can include one or more semiconductor modules 305a-305n as described with respect to Figure 1 and 2 semiconductor substrate having a glass core via copper bonding. As with the semiconductor substrate of the one or more semiconductor modules 305a-305n, in various examples, the circuit board 315 can include a top layer 315a, a board core 315b, and a bottom layer 315c. The circuit board 315 can be further configured to have a CTE that matches that of silicon. Thus, in some examples, the circuit board 315 can be a glass board, and the board core 315b can be a glass core. In some examples, the glass can be an engineered glass configured to have a CTE that matches that of the CTE of the one or more interposers of the one or more semiconductor modules 305a-305n, and / or the CTE of the one or more compute dies of the one or more semiconductor modules 305a-305n.

[0050] As known to those skilled in the art, the CTE of a material is a property that varies with temperature. While materials can be created with a particular CTE value and adjusted, the CTE of a material is not exact because manufacturing tolerances are not exact and introduce CTE variations. Thus, in various examples, matching CTEs can include CTEs within a CTE range of a given material. For example, in some embodiments, a CTE can be considered to be "matched" when within a CTE range of a given material. For example, the CTE of pure silicon (Si) is between 2.6 and 3.3 parts per million per degree Celsius (e.g., 2.6-3.3 ppm / °C). Thus, if a material has a CTE within the range of 2.6-3.3 ppm / °C, the material can be considered to have a CTE that matches Si. Similarly, if a material is within a CTE range of a target material, the material can be considered to have the CTE of the target material. For example, if a material has a CTE within the range of 2.6-3.3 ppm / °C, the material can be considered to have the CTE of Si. In other examples, CTEs can be considered to be matched when within a threshold range of each other. In some examples, CTEs can be considered to be matched if within 10% of the CTE of a material with a higher CTE at the same temperature. For example, if a first material has a CTE of 3 ppm / °C at a given temperature, a second material can be considered to have a CTE that matches the first material if the CTE of the second material is within the range of 2.7-3.3 ppm / °C at the given temperature. Thus, as used herein, the terms "match," "matching," "matched," and other like terms are not limited to exact matches of exact CTE values, and include materials that are considered by those skilled in the art to have a "matched CTE" and to have a corresponding CTE value that is as close as possible under current (and / or later developed) material engineering process conditions, as used in the field of material engineering design.

[0051] In various examples, off-board I / O signals can be passed in through I / O physical compliant connections (e.g., flexible optical fiber and / or copper cabling) to the common package. Thus, in some examples, routing on the circuit board 315 can be implemented via a single copper routing layer on the front (e.g., top layer 315a) and back (e.g., bottom layer 315c) layers.

[0052] In further examples, the board core 315b of the circuit board 315 and the substrate core of the one or more semiconductor modules (e.g., 310a, 310b) can be made of the same material. For example, the board core 315b and the substrate core of the one or more semiconductor modules can be made of silicon (Si). In some examples, the board core 315b and the substrate core of the one or more semiconductor modules can be made of a different material. For example, the board core 315b can be made of silicon (Si) and the substrate core of the one or more semiconductor modules can be made of gallium arsenide (GaAs). Figure 1In the case where both the substrate core 105b) of the semiconductor module 305a to 305n and the substrate of the circuit board 315 are CTE-matched glass, one or more semiconductor modules 305a to 305n, and specifically the substrate of the respective semiconductor modules 305a to 305n, can be coupled to the circuit board 315 via copper bonding (e.g., HCB and / or DCB). In some examples, the copper bonding can include, but is not limited to, thermal compression copper bonding and / or nanoparticle copper bonding. In some further examples, soldering (e.g., ball grid array (BGA), etc.) can be used alone, or in combination with copper bonding. Thus, in various embodiments, the array 300 can include copper interconnect layers 310a to 310n that copper bond between the bottom layer of the semiconductor substrate and the top layer of the circuit board 315.

[0053] In various embodiments, the circuit board 315 can further include one or more TGVs 320. Since the off-module high-speed I / O can be through physically compliant connections (e.g., fiber and / or copper cables), the TGVs 320 through both the glass core of the semiconductor substrate and the circuit board 315 can be optimized for power delivery. This is in contrast to some conventional packages where the through-hole vias are designed based on the electrical characteristics of the I / O signals and the signal quality considered.

[0054] Figure 4 is a schematic top view of a copper-connected semiconductor module array 400 on a glass board, in accordance with various embodiments. The array 400 can include a circuit board 405, one or more semiconductor modules 410a to 410n, and a bridge die 415. It should be noted that the components of the array 400 are schematically illustrated in Figure 4 and the arrangement of the semiconductor modules 410a to 410n and other components can be modified, in accordance with various embodiments.

[0055] In some embodiments, one or more semiconductor modules 410a to 410n can be arranged in two rows (or columns, depending on the orientation). Thus, Figure 3 may be a cross-section taken along the line m-m, such that a cross-sectional view of a single row of semiconductor modules 410a to 410n is shown. In various embodiments, the interior-facing edges of each row of respective semiconductor modules 410a to 410n can be configured to transmit serialized electrical outputs. Specifically, in some examples, serializer-deserializer (SerDes) I / O dies can be arranged along at least one interior-facing edge of each respective semiconductor module. Similarly, optically or passively copper I / O dies that are co-packaged can be arranged along at least one exterior-facing edge of each respective semiconductor module. In yet further embodiments, internal electrical connections between the modules can be routed across an interconnect bridge die 415, which can be placed across the rows between the semiconductor modules.

[0056] Figure 5is a flowchart of a method 500 of fabricating an array of copper- connected semiconductor modules according to various embodiments. The method 500 can begin at block 505 by forming an interconnect layer on a bottom layer of a mediating layer of a semiconductor module. As previously described, in various embodiments, the mediating layer can be coupled to a glass substrate. The glass substrate can be configured to have a CTE that matches that of silicon, and in such cases, a CTE that matches that of the mediating layer. Thus, the mediating layer can include an interconnect layer through which the mediating layer can be coupled to the glass substrate via copper bonding. Thus, in some examples, the interconnect layer can be a copper interconnect layer in which copper interconnects (e.g., copper wires, traces, microstrips, pads, and / or TGVs having copper metallization layers) can be formed on the bottom layer of the mediating layer. In various embodiments, forming the copper interconnect layer can include plating copper and / or depositing a copper film to form respective interconnects of the interconnect layer.

[0057] The method 500 can continue at block 510 by copper bonding the interconnect layer of the mediating layer to the glass substrate. In some examples, the copper bonded interconnect layer can be copper bonded to a top layer of the glass substrate. Thus, in some examples, the glass substrate can include a respective copper interconnect layer on a top layer of the glass substrate. In yet further embodiments, the top layer of the glass substrate can include a copper wiring layer. In various examples, the copper bonding can include, but is not limited to, HCB, DCB, or both. In some examples, the connection between the mediating layer and the glass substrate can further include a solder connection, alone or in combination with the copper bonding connection. In some examples, the glass core of the substrate can be formed to have a CTE that matches that of silicon. As previously described, in some examples, the glass core can be engineered to have the CTE of silicon. The substrate can include one or more glass layers. In yet further examples, the top layer of the substrate can be a top surface of the glass core on which respective copper wiring layers and / or other copper interconnects can be formed (e.g., via copper plating or copper film deposition processes). Thus, in some further examples, the method can include forming a respective interconnect layer (e.g., a copper wiring layer) on a top layer (and / or top surface) of the glass substrate. In some examples, the interconnect layer can include one or more layers of RDL.

[0058] Method 500 continues at block 515 by forming an interconnect layer on the bottom layer of the glass substrate. In various embodiments, as with the interposer, the glass substrate can be further coupled to a glass circuit board. The glass circuit board can similarly be matched to the silicon CTE. In some examples, the CTE of the glass circuit board can be matched to the CTE of the interposer of the semiconductor package and / or the CTE of the one or more compute dies. As previously described, various techniques including those known to those of skill in the art can be used to adjust the CTE of the glass substrate, interposer, and / or glass circuit board, such as controlling the formation process of the glass (e.g., crystallization), and through material selection for forming the glass. In yet further examples, matching the CTE of the glass substrate, glass circuit board, and / or interposer can include selecting a glass substrate, glass circuit board, and / or interposer formed from a material having the same CTE.

[0059] Accordingly, the glass substrate can be further configured to include an interconnect layer through which the glass substrate can similarly be copper bonded to a glass circuit board (or other glass substrate) in this case. Accordingly, in some examples, the interconnect layer can be a copper interconnect layer (as opposed to a conventional solder BGA), which can be formed on the bottom layer of the glass substrate. As previously described, in some examples, the interconnect layer can include copper interconnects formed on the bottom surface (e.g., via copper plating or copper film deposition processes). The copper interconnects at the bottom layer of the glass substrate can include, but are not limited to, copper pillars (e.g., micro-bumps), TGVs, copper pads, copper lines, and / or traces. In some examples, the interconnect layer can be referred to as a copper wiring layer. In further examples, the interconnect layer includes one or more layers of RDL.

[0060] At block 520, method 500 can continue by copper bonding the glass substrate to a glass circuit board. As previously described, in various examples, the copper bonding can include, but is not limited to, HCB, DCB, or both. In some examples, the connection between the glass substrate and the glass circuit board can further include a solder connection, either alone or in combination with the copper bonding connection.

[0061] The method 500 continues at block 525 by arranging two or more semiconductor modules in an array of two or more rows on a glass circuit board. As previously described, an array of semiconductor modules having glass semiconductor substrates can be formed on a glass circuit board. Thus, in some examples, each of the semiconductor modules can be copper bonded to the glass circuit board. At block 530, the method further includes positioning serial electrical output I / O dies along an interior-facing edge of the respective semiconductor modules. In various embodiments, the interior-facing edge of each row of respective semiconductor modules can be configured for serialized electrical output. For example, respective SerDes I / O dies can be arranged along at least one interior-facing edge of each respective semiconductor module. In yet further embodiments, internal electrical connections between the modules can be routed across interconnect bridge dies, which can be placed between semiconductor modules across rows, between interior-facing edges of respective pairs of semiconductor modules. The method 500 further includes, at block 535, positioning off-board communication I / O dies along at least one exterior-facing edge of the semiconductor modules. As previously described, collectively packaged optical or passive copper I / O dies can be arranged along at least one exterior-facing edge of each respective semiconductor module for off-board communication, which can be conducted through physically compliant connection media (e.g., optical and / or copper cabling).

[0062] The techniques and processes described above with respect to various embodiments can be used to manufacture semiconductor modules 100, 200 and / or semiconductor module arrays 300, 400 and / or components thereof, as described herein.

[0063] While some features and aspects have been described with respect to embodiments, those skilled in the art will recognize that many modifications are possible. For example, the methods and processes described herein can be implemented using hardware components, custom integrated circuits (ICs), programmable logic, and / or any combination thereof. Further, while for ease of description, various methods and processes described herein can be described with respect to particular structural and / or functional components, the methods provided by various embodiments are not limited to any particular structural and / or functional architecture, but can be implemented in any suitable hardware configuration. Similarly, according to several embodiments, while some functionality is attributed to one or more system components, this functionality can be distributed among various other system components unless the context dictates otherwise.

[0064] Furthermore, although the processes described herein are described in a particular order for ease of description and illustration, unless otherwise specified, the various processes can be reordered, added, and / or omitted in accordance with various embodiments. Moreover, processes described with respect to one method or process can be incorporated into other described methods or processes; likewise, system components described according to a particular structural architecture and / or with respect to one system can be organized in alternative structural architectures and / or incorporated into other described systems. Therefore, although various embodiments are described with or without certain features for ease of description and illustration, the various components and / or features described herein with respect to a particular embodiment can be substituted, added, and / or subtracted in other described embodiments, unless otherwise specified. Thus, although several embodiments have been described above, it will be appreciated that the invention is intended to cover all modifications and equivalents within the scope of the following claims.

Claims

1. An apparatus comprising: one or more dies; an interposer formed of a first material, the interposer coupled to the one or more dies, the interposer including an interconnect layer formed on a side of the interposer, wherein the interconnect layer includes a plurality of copper interconnects; and a substrate including a top layer, a glass core, and a bottom layer, wherein the interconnect layer of the interposer is copper bonded with the top layer of the substrate, wherein the interposer includes a plurality of interposer partitions spaced apart from one another, each interposer partition at least partially overlapped by at least one of the one or more dies, and wherein the glass core and the first material of the interposer each have a matching coefficient of thermal expansion.

2. The apparatus of claim 1, wherein the glass core has a coefficient of thermal expansion of silicon.

3. The apparatus of claim 1, wherein the top layer of the substrate includes a copper wiring layer.

4. The apparatus of claim 1, wherein the bottom layer of the substrate includes a copper wiring layer.

5. The apparatus of claim 1, further comprising: one or more bridge dies, wherein each bridge die of the one or more bridge dies is coupled to at least two interposer partitions.

6. The apparatus of claim 1, wherein the one or more dies include: one or more first I / O dies configured to facilitate on-board communications; and one or more second I / O dies coupled to at least one of a co-packaged optical device or a copper cable, the at least one of a co-packaged optical device or a copper cable configured for off-board communications.

7. A semiconductor device comprising: a plurality of semiconductor modules, each semiconductor module respectively comprising: one or more dies; an interposer formed of a first material, the interposer coupled to the one or more dies, the interposer including a first interconnect layer formed on a side of the interposer, wherein the first interconnect layer includes a plurality of copper interconnects; and a substrate including a first top layer, a first glass core, and a first bottom layer, wherein the first interconnect layer of the interposer is copper bonded with the top layer of the substrate; a circuit board coupled to the one or more semiconductor modules, the circuit board including a second top layer, a second bottom layer, and a second glass core, wherein the first bottom layer of the substrate is copper bonded with the second top layer of the circuit board, wherein each of the respective first glass core, the first material of the interposer, and second glass core have a matching coefficient of thermal expansion.

8. The semiconductor device of claim 7, wherein the coefficient of thermal expansion of the second glass core has a coefficient of thermal expansion of silicon.

9. The semiconductor device of claim 7, wherein the plurality of semiconductor modules are arranged in two rows of semiconductor modules.

10. The semiconductor device of claim 9, wherein the one or more dies include: one or more first I / O dies configured to facilitate on-board communications and positioned at at least one inward-facing edge of the respective rows of the respective semiconductor modules; and one or more second I / O dies coupled to at least one of a co-packaged optical device or a copper cable, the at least one of a co-packaged optical device or a copper cable configured for off-board communications. one or more second I / O dies coupled to at least one of a co-packaged optical device or copper cable, the at least one of a co-packaged optical device or copper cable configured for off-board communication, the one or more second I / O dies positioned at at least one externally-facing edge of the respective row of the respective semiconductor module.

11. The semiconductor device of claim 7, wherein each of the respective interposers comprises one or more interposer partitions, each interposer partition at least partially overlapped by at least one of the one or more dies.

12. A method comprising: forming a first interconnect layer on a first side of an interposer, wherein the first interconnect layer includes a first plurality of copper interconnects, wherein the first interconnect layer is configured to couple the interposer to a substrate, and wherein the interposer is formed of a first material; bonding the first interconnect layer to a first top layer of the substrate via a copper bonding process, the substrate comprising the first top layer, a first glass core, and a first bottom layer; forming a second interconnect layer on the first bottom layer of the substrate, wherein the second interconnect layer includes a second plurality of copper interconnects, wherein the second interconnect layer is configured to couple the substrate to a circuit board; bonding the second interconnect layer to a second top layer of the circuit board via the copper bonding process, the circuit board comprising the second top layer and a second glass core; and forming the first glass core and the second glass core to have a coefficient of thermal expansion equal to a coefficient of thermal expansion of the first material of the interposer.

13. The method of claim 12, wherein the interposer comprises one or more interposer partitions, wherein copper bonding the first interconnect layer to the first top layer of the substrate comprises copper bonding each of the one or more interposer partitions to the substrate.

14. The method of claim 12, further comprising: arranging a plurality of semiconductor modules on the circuit board into an array of two or more rows of semiconductor modules, wherein each semiconductor module comprises a respective substrate having a respective second interconnect layer, wherein each semiconductor module is copper bonded to the circuit board via a respective second interconnect layer.

15. The method of claim 14, wherein each semiconductor module respectively comprises one or more dies coupled to a respective interposer, wherein each of the respective one or more dies includes one or more I / O dies configured to facilitate on-board communication, wherein arranging the plurality of semiconductor modules further comprises positioning the one or more I / O dies configured to manage on-board communication at at least one internally-facing edge of the respective row of the respective semiconductor module.

16. The method of claim 14, wherein each semiconductor module respectively comprises one or more dies coupled to a respective interposer, wherein each of the respective one or more dies includes one or more I / O dies coupled to at least one of a common packaged optical device or copper cable configured for off-board communication, wherein arranging the plurality of semiconductor modules further comprises positioning the one or more I / O dies coupled to the at least one of a common packaged optical device or copper cable at at least one externally facing edge of the respective row of the respective semiconductor modules.

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