Display substrate and display device

Abstract

A display substrate has a first display area and a second display area. The second display area at least partially surrounds the first display area. The display substrate includes a first light emitting device group disposed in the first display area, a first pixel circuit group disposed in the second display area, a lead group, and a plurality of second pixel circuits disposed in the second display area. The first light emitting device group includes N first light emitting devices. The first pixel circuit group includes N first pixel circuits. The lead group includes N leads; an i-th first light emitting device is electrically connected to an i-th first pixel circuit through an i-th lead, and lengths of the 1st to Nth leads gradually increase. N is an integer, i = 1 to N, and N ≥ 2. At least one row of second pixel circuits or at least one column of second pixel circuits is disposed between the 1st first light emitting device and the 1st first pixel circuit. The N leads extend from the first display area to the second display area through the at least one row of second pixel circuits or the at least one column of second pixel circuits.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Technology

[0002] With the continuous development of science and technology, users have an increasingly higher demand for screen ratio in display devices.

[0003] In related technical fields, the concept of a full-screen display has emerged, which means that optical components such as image acquisition devices in display devices are placed below the display screen. Summary of the Invention

[0004] On one hand, a display substrate is provided. The display substrate has a first display area and a second display area. The second display area at least partially surrounds the first display area. The display substrate includes: a first light-emitting device group disposed in the first display area, a first pixel circuit group disposed in the second display area, a lead group, and a plurality of second pixel circuits disposed in the second display area. The first light-emitting device group includes N first light-emitting devices; along a first direction and pointing from the second display area to the first display area, the N first light-emitting devices are respectively the 1st to the Nth first light-emitting devices. The first pixel circuit group includes N first pixel circuits; the 1st to the Nth first pixel circuits are arranged sequentially in a direction away from the first display area; the set direction is the direction in which the N first pixel circuits are arranged. The lead group includes N leads arranged in parallel; the i-th first light-emitting device is electrically connected to the i-th first pixel circuit through the i-th lead, and the lengths of the 1st to the Nth leads gradually increase; N≥2, and N is an integer, i=1~N. The plurality of second pixel circuits are arranged in multiple columns along the first direction and in multiple rows along the second direction; the first direction and the second direction intersect. Among them, at least one row of second pixel circuits or at least one column of second pixel circuits are provided between the first first light-emitting device and the first first pixel circuit; the N leads extend from the first display area, through the at least one row of second pixel circuits or the at least one column of second pixel circuits, to the second display area.

[0005] In some embodiments, the first light-emitting device group and the first pixel circuit group electrically connected to the first light-emitting device group are arranged in the same row along the first direction. At least one column of second pixel circuits is arranged between the first first light-emitting device and the first first pixel circuit. The N leads extend from the first display area, along the first direction, through the at least one column of second pixel circuits, to the second display area.

[0006] In some embodiments, the display substrate includes: a plurality of second light-emitting devices disposed in the second display area, at least one second light-emitting device being electrically connected to at least one second pixel circuit, and the orthographic projections of the at least one second light-emitting device and the at least one second pixel circuit on the plane of the display substrate at least partially overlapping. The display substrate includes a plurality of pixel units, each pixel unit including three sub-pixels arranged along the first direction, each sub-pixel including an electrically connected second light-emitting device and a second pixel circuit. Wherein, X second pixel circuits belonging to at least one pixel unit are spaced apart between the first first light-emitting device and the first first pixel circuit, where X is a multiple of 3.

[0007] In some embodiments, the display substrate includes: a plurality of second light-emitting devices disposed in the second display area, at least one of the second light-emitting devices being electrically connected to at least one second pixel circuit, and the orthographic projections of the at least one second light-emitting device and the at least one second pixel circuit on the plane of the display substrate at least partially overlapping. The display substrate further includes a plurality of pixel units, each pixel unit including a plurality of sub-pixels, each sub-pixel including an electrically connected second light-emitting device and a second pixel circuit; the plurality of pixel units are arranged in a pentile arrangement. Wherein, Y second pixel circuits belonging to at least one pixel unit are spaced apart between the first first light-emitting device and the first first pixel circuit, where Y is a multiple of 2.

[0008] In some embodiments, the sequence formed by the length values ​​of the N leads in the first direction is an arithmetic sequence.

[0009] In some embodiments, the sequence of resistance values ​​of the N leads is an arithmetic sequence.

[0010] In some embodiments, each lead forms a parasitic capacitance with the second pixel circuit and / or the first pixel circuit it passes through; the sequence of parasitic capacitance values ​​formed by the N leads is an arithmetic sequence.

[0011] In some embodiments, the display substrate includes multiple rows of first light-emitting devices located in the first display area, each row of first light-emitting devices being divided into two groups of first light-emitting devices located on both sides of a reference line; the reference line is a straight line extending along a second direction and passing through the first display area, the second direction being perpendicular to the first direction. Two first pixel circuit groups electrically connected to the two groups of first light-emitting devices are respectively located on opposite sides of the first display area in the first direction. Two lead groups electrically connected to the two groups of first light-emitting devices are respectively located on both sides of the reference line.

[0012] In some embodiments, the two lead groups electrically connected to the two first light-emitting device groups are arranged symmetrically about the reference line.

[0013] In some embodiments, the first display area has a center, and the reference line is a straight line passing through the center.

[0014] In some embodiments, the first light-emitting device group and the first pixel circuit group electrically connected to the first light-emitting device group are arranged in the same row along the first direction. The display substrate further includes: a group of adapter holes; the group of adapter holes includes N adapter holes, which are arranged sequentially along the first direction and correspond to the N first light-emitting devices respectively. Along the second direction, the i-th lead electrically connected to the i-th first light-emitting device is closer to the group of adapter holes than the (i+1)-th lead electrically connected to the (i+1)-th first light-emitting device; the second direction is perpendicular to the first direction.

[0015] In some embodiments, the first light-emitting device group and the first pixel circuit group electrically connected to the first light-emitting device group are arranged in the same row along the first direction. The display substrate further includes: a group of adapter holes; the group of adapter holes includes N adapter holes, the N adapter holes are arranged sequentially along the first direction and correspond to the N first light-emitting devices respectively. The i-th lead electrically connected to the i-th first light-emitting device and the i+1-th lead electrically connected to the (i+1)-th first light-emitting device are respectively located on opposite sides of the group of adapter holes in the second direction; the second direction is perpendicular to the first direction.

[0016] In some embodiments, the display substrate includes: a substrate; a pixel circuit layer disposed on the substrate, wherein the first pixel circuit group and the plurality of second pixel circuits are located on the pixel circuit layer; a light-emitting device layer disposed on the side of the pixel circuit layer away from the substrate, wherein the first light-emitting device group is located on the light-emitting device layer; and a plurality of lead layers disposed between the pixel circuit layer and the light-emitting device layer, wherein the material of the plurality of lead layers includes a light-transmitting conductive material. N leads of the lead group are respectively located in the plurality of lead layers.

[0017] In some embodiments, the number of the plurality of lead layers is two. Of the N leads, the first to the Nth leads are alternately located in the two lead layers.

[0018] In some embodiments, the length ratio of the Nth lead to the first lead is α, where α ≤ 25.

[0019] In some embodiments, the length ratio α satisfies α≤15.

[0020] In some embodiments, the number of rows or columns of the second pixel circuits disposed between the first first light-emitting device and the first first pixel circuit is β, where β≤30.

[0021] In some embodiments, the ratio of the number of rows or columns of pixel circuits spaced apart between the Nth first light-emitting device and the Nth first pixel circuit to the number of rows or columns of second pixel circuits spaced apart between the 1st first light-emitting device and the 1st first pixel circuit is γ, where 5≤γ≤50.

[0022] In some embodiments, the second display area includes a regular area and a compressed area; the first pixel circuit group is located in the compressed area, a portion of the plurality of second pixel circuits are located in the regular area, and another portion of the second pixel circuits are located in the compressed area, and in the compressed area, at least one second pixel circuit is disposed between two adjacent first pixel circuits along the first direction. The width of the column area where the first pixel circuit or the second pixel circuit located in the compressed area is located is smaller than the width of the column area where the second pixel circuit located in the regular area is located.

[0023] On the other hand, a display device is provided. The display device includes: a display substrate as described in any of the above embodiments; and an optical element disposed on the non-light-emitting side of the display substrate, the optical element being located in a first display area of ​​the display substrate. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are merely drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. Furthermore, the drawings described below can be considered as schematic diagrams and are not intended to limit the actual dimensions, etc., of the products involved in the embodiments of this disclosure.

[0025] Figure 1 This is a structural diagram of a display substrate according to some embodiments of the present disclosure;

[0026] Figure 2 This is a structural diagram of another display substrate according to some embodiments of the present disclosure;

[0027] Figure 3 This is a partial enlarged view of a display substrate according to some embodiments of the present disclosure;

[0028] Figure 4 for Figure 3 The image shows a cross-sectional view of the display substrate along the EE' direction;

[0029] Figure 5 This is a partial enlarged view of another display substrate according to some embodiments of the present disclosure;

[0030] Figure 6 for Figure 5 The image shows a cross-sectional view of the display substrate along the FF' direction;

[0031] Figure 7 This is a circuit diagram of a sub-pixel according to some embodiments of the present disclosure;

[0032] Figure 8 This is a structural diagram of a sub-pixel according to some embodiments of the present disclosure;

[0033] Figure 9 This is a partial enlarged view of yet another display substrate according to some embodiments of the present disclosure;

[0034] Figure 10 This is a partial enlarged view of yet another display substrate according to some embodiments of the present disclosure;

[0035] Figure 11 This is a partial enlarged view of yet another display substrate according to some embodiments of the present disclosure;

[0036] Figure 12 This is a partial enlarged view of yet another display substrate according to some embodiments of the present disclosure;

[0037] Figure 13 This is a partial enlarged view of yet another display substrate according to some embodiments of the present disclosure;

[0038] Figure 14 This is a partial enlarged view of yet another display substrate according to some embodiments of the present disclosure;

[0039] Figure 15 This is a partial enlarged view of yet another display substrate according to some embodiments of the present disclosure;

[0040] Figure 16 This is a partial enlarged view of yet another display substrate according to some embodiments of the present disclosure;

[0041] Figure 17 for Figure 16 The image shows a cross-sectional view of the display substrate along the GG' direction;

[0042] Figure 18 This is a structural diagram of a display device according to some embodiments of the present disclosure;

[0043] Figure 19 This is a structural diagram of another display device according to some embodiments of the present disclosure. Detailed Implementation

[0044] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0045] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0046] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0047] In describing some embodiments, the term "connection" and its derivative expressions may be used. For example, the term "connection" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0048] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0049] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0050] As used herein, depending on the context, the term “if” may optionally be interpreted as meaning “when”, “in the event of”, “in response to determination”, or “in response to detection”. Similarly, depending on the context, the phrase “if it is determined that…” or “if [the stated condition or event] is detected” may optionally be interpreted as meaning “in the event of determination that…”, “in response to determination that…”, “when [the stated condition or event] is detected”, or “in response to the detection of [the stated condition or event]”.

[0051] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0052] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0053] As used herein, “about” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0054] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0055] The transistors used in the circuits provided in the embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. In the embodiments of this disclosure, thin-film transistors are used as an example for illustration.

[0056] In some embodiments, the control electrode of each transistor used in each circuit is the gate of the transistor, the first electrode is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor. Since the source and drain of a transistor can be structurally symmetrical, they can be structurally indistinguishable; that is, the first and second electrodes of the transistor in the embodiments of this disclosure can be structurally indistinguishable. For example, in the case of a P-type transistor, the first electrode is the source and the second electrode is the drain; for example, in the case of an N-type transistor, the first electrode is the drain and the second electrode is the source.

[0057] In the circuits provided in the embodiments of this disclosure, "node" does not refer to an actual existing component, but rather to a junction point of related electrical connections in the circuit diagram. In other words, these nodes are equivalent to the junction points of related electrical connections in the circuit diagram.

[0058] The transistors included in the circuits provided in the embodiments of this disclosure can all be N-type transistors or all be P-type transistors. Alternatively, some of the transistors included in each circuit can be N-type transistors and others can be P-type transistors.

[0059] In this disclosure, "effective level" refers to a level that enables a transistor to conduct.

[0060] The circuits provided in the embodiments of this disclosure are described below using P-type transistors (where the effective level is low) as an example. It should be noted that the transistors in the circuits mentioned below use the same conduction type, which simplifies the process flow, reduces process difficulty, and improves the yield of products (e.g., display substrate 100, display device 1000).

[0061] Some embodiments of this disclosure provide a display substrate 100, such as Figure 1 As shown, the display substrate 100 has a first display area A1 and a second display area A2, with the second display area A2 at least partially surrounding the first display area A1. For example, the area of ​​the second display area A2 is larger than the area of ​​the first display area A1.

[0062] Here, the number of first display areas A1 can be at least one, and the number of second display areas A2 can be, for example, one. Below, as... Figure 1 As shown, taking one first display area A1 as an example, the structure of the display substrate 100 is illustrated.

[0063] For example, the second display area A2 may surround the first display area A1. In this case, the shape of the first display area A1 may be, for example, a circle, an ellipse, or a rectangle.

[0064] For example, the second display area A2 may surround a portion of the first display area A1, that is, a portion of the boundary of the second display area A2 overlaps with a portion of the boundary of the first display area A1. In this case, the shape of the first display area A1 may be, for example, a rectangle, a rounded rectangle, a teardrop shape, or a semicircle.

[0065] In some examples, such as Figure 2 As shown, the above-mentioned display substrate 100 may include: substrate 1.

[0066] The types of substrate 1 mentioned above include various types, and can be selected and set according to actual needs.

[0067] For example, the substrate 1 described above can be a rigid substrate. This rigid substrate can be a glass substrate or a PMMA (Polymethyl methacrylate) substrate, etc.

[0068] For example, the substrate 1 described above can be a flexible substrate. This flexible substrate can be a PET (Polyethylene terephthalate) substrate, a PEN (Polyethylenenaphthalate dimethyl methacrylate) substrate, or a PI (Polyimide) substrate, etc. In this case, the display substrate 100 can, for example, realize a flexible display.

[0069] In some examples, such as Figures 2-6 As shown, the display substrate 100 may further include a pixel circuit layer 2 disposed on the substrate 1.

[0070] For example, such as Figure 3 , Figure 5 and Figure 8 As shown, the pixel circuit layer 2 included in the display substrate 100 may include: a semiconductor layer, a first gate conductive layer, a second gate conductive layer, and a source / drain conductive layer sequentially stacked along a direction perpendicular to and away from the substrate 1. Furthermore, a first gate insulating layer may be disposed between the semiconductor layer and the first gate conductive layer, a second gate insulating layer may be disposed between the first gate conductive layer and the second gate conductive layer, and an interlayer insulating layer may be disposed between the second gate conductive layer and the source / drain conductive layer.

[0071] For example, such as Figure 3 , Figure 5 and Figure 8As shown, the pixel circuit layer 2 included in the display substrate 100 may further include a transition layer disposed on the side of the source / drain conductive layer away from the substrate 1. The material of the transition layer may be the same as the material of the source / drain conductive layer. A planarization layer may be disposed between the source / drain conductive layer and the transition layer.

[0072] For example, the pixel circuit layer 2 described above may include a plurality of first pixel circuits 21 and a plurality of second pixel circuits 22.

[0073] The structures of the first pixel circuit 21 and the second pixel circuit 22 described above include various types, which can be selected and set according to actual needs. For example, the structure of the first pixel circuit 21 or the second pixel circuit 22 may include structures such as "2T1C", "6T1C", "7T1C", "6T2C" or "7T2C". Here, "T" represents a transistor, and the number before "T" indicates the number of transistors; "C" represents a storage capacitor, and the number before "C" indicates the number of storage capacitors.

[0074] For example, such as Figure 7 As shown, the structures of the first pixel circuit 21 and the second pixel circuit 22 can, for example, be the same. For instance, both can be 7T1C structures. Figure 7 This is the equivalent circuit diagram of the second pixel circuit 22. Figure 8 for Figure 3 or Figure 5 The structure diagram of the second pixel circuit 22 in the image is shown below. Figure 7 and Figure 8 The structure of pixel circuit layer 2 and second pixel circuit 22 is schematically illustrated. Of course, the equivalent circuit diagram of first pixel circuit 21 can be compared with... Figure 7 The equivalent circuit shown is the same, and the structural diagram of the first pixel circuit 21 can be the same as that shown. Figure 8 The structure shown is the same.

[0075] For example, such as Figure 7 As shown, the second pixel circuit 22 includes: a switching transistor T1, a driving transistor T2, a compensation transistor T3, a first light-emitting control transistor T4, a second light-emitting control transistor T5, a first reset transistor T6, a second reset transistor T7, and a storage capacitor Cst.

[0076] Specifically, when the reset signal transmitted on the reset signal line RST is at an active level, the first reset transistor T6 and the second reset transistor T7 can be turned on under the control of the reset signal, receiving the initial signal transmitted from the initial signal line Vinit. The first reset transistor T6 can transmit the initial signal to one end of the storage capacitor Cst to reset it; the second reset transistor T7 can transmit the initial signal to its second terminal to reset it. Here, the drive transistor T2 can be turned on under the control of the initial signal.

[0077] When the scan signal transmitted on the scan signal line Gate is at an active level, switching transistor T1 and compensation transistor T3 can be turned on under the control of the scan signal. The data signal transmitted on the data signal line Data can be transmitted sequentially through switching transistor T1, driving transistor T2, and compensation transistor T3 to the control electrode of driving transistor T2, charging the control electrode of driving transistor T2 until driving transistor T2 is turned off. At this time, the threshold voltage compensation of driving transistor T2 is completed.

[0078] When the enable signal level transmitted by the enable signal line EM is valid, the first light-emitting control transistor T4 and the second light-emitting control transistor T5 can be turned on under the control of the enable signal to receive the first voltage signal from the first voltage signal line ELVDD. The driving transistor T2 can generate a driving signal according to the data signal and the first voltage signal, and transmit the driving signal difference to the second terminal of the second reset transistor T7.

[0079] For example, such as Figure 8 As shown, in the semiconductor layer, the portion covered by the first gate conductive layer constitutes the active layer of each transistor; the portion not covered by the first gate conductive layer is doped to form a conductor. The portion of the first gate conductive layer covering the semiconductor layer constitutes the control electrode of each transistor, including, for example: the control electrode T11 of the switching transistor T1, the control electrode T21 of the driving transistor T2, the control electrode T31 of the compensation transistor T3, the control electrode T41 of the first light-emitting control transistor T4, the control electrode T51 of the second light-emitting control transistor T5, the control electrode T61 of the first reset transistor T6, and the control electrode T71 of the second reset transistor T7.

[0080] For example, the first plate Cst1 of the storage capacitor Cst, the scan signal line Gate for transmitting the scan signal, the reset signal line RST for transmitting the reset signal, and the enable signal line EM for transmitting the enable signal can be located in the first gate conductive layer. The second plate Cst2 of the storage capacitor Cst and the initial signal line Vinit for transmitting the initial signal can be located in the second gate conductive layer. The data signal line Data for transmitting the data signal and the first voltage signal line ELVDD for transmitting the first voltage signal can be located in the source-drain conductive layer. The transition layer may also include a transition portion 61 for transition and a shielding block 62 for shielding.

[0081] It is understood that conductors in the semiconductor layer can constitute the first and second terminals of each transistor. In order to clearly identify the first or second terminal of the transistor, this disclosure uses the portion of the source / drain conductive layer connected to the conductor as the first or second terminal of the transistor.

[0082] like Figure 8 As shown, the first electrode T12 of the switching transistor T1 can be integrated with the data signal line Data, and is connected to the active layer located in the semiconductor layer through a first via H1 that sequentially penetrates the interlayer gate insulating layer, the second gate insulating layer, and the first insulating layer. The control electrode T11 of the switching transistor T1 can be integrated with the scan signal line Gate.

[0083] The second electrode of the switching transistor T1 and the second electrode of the first light-emitting control transistor T4 can be located in a conductor in the semiconductor layer and are integrally structured. The first electrode T42 of the first light-emitting control transistor T4 can be integrally structured with the first voltage signal line ELVDD and connected to the active layer located in the semiconductor layer through a fifth via H5 that sequentially penetrates the interlayer gate insulating layer, the second gate insulating layer, and the first insulating layer.

[0084] The first electrode of the driving transistor T2 can also be in a conductor within the semiconductor layer and is integrally formed with the second electrode of the switching transistor T1. The second electrode of the driving transistor T2 and the first electrode of the compensation transistor T3 can also be in a conductor within the semiconductor layer and are integrally formed. The control electrode T21 of the driving transistor T2 and the first plate Cst1 of the storage capacitor Cst can be integrally formed and connected to the second electrode T63 of the first reset transistor T6 via a third via H3 that sequentially penetrates the interlayer gate insulating layer, the second gate insulating layer, and the first insulating layer.

[0085] The second plate Cst2 of the storage capacitor Cst can be connected to the first voltage signal line ELVDD through the fourth via H4 that penetrates the interlayer insulation layer.

[0086] The second terminal T33 of the compensation transistor T3 can be integrated with the second terminal T63 of the first reset transistor T6. The control terminal T31 of the compensation transistor T3 can be integrated with the scan signal line Gate. The compensation transistor T3 is a dual-gate transistor.

[0087] The control electrode T61 of the first reset transistor T6 can be integrated with the reset signal line RST. The first electrode T62 of the first reset transistor T6 can be connected to the initial signal line Vinit through the seventh via H7 that penetrates the second gate insulating layer.

[0088] The control electrode T71 of the second reset transistor T7 can be integrated with the reset signal line RST. The first electrode T72 of the second reset transistor T7 can be connected to the initial signal line Vinit through the eighth via H8 penetrating the second gate insulating layer. The second electrode T73 of the second reset transistor T7 is integrated with the second electrode T53 of the second light-emitting control transistor T5. Within the same second pixel circuit 22, the control electrodes of the first reset transistor T6 and the second reset transistor T7 are connected to different reset signal lines RST, and the first electrodes of the first reset transistor T6 and the second reset transistor T7 are connected to different initial signal lines Vinit.

[0089] The first electrode of the second light-emitting control transistor T5 can be located in a conductor within the semiconductor layer, while the second electrode of the driving transistor T2 is an integral structure. The control electrode T51 of the second light-emitting control transistor T5 is connected to the enable signal line EM and is also an integral structure.

[0090] Optionally, such as Figures 9-11 As shown, the aforementioned plurality of second pixel circuits 22 can be arranged in multiple columns along the first direction X and in multiple rows along the second direction Y. Each column of second pixel circuits may include multiple second pixel circuits 22, which are arranged sequentially along the second direction Y. Each row of second pixel circuits may include multiple second pixel circuits 22, which are arranged sequentially along the first direction X.

[0091] For example, the first direction X intersects with the second direction Y.

[0092] Here, the angle between the first direction X and the second direction Y can be selected and set according to actual needs. For example, the angle between the first direction X and the second direction Y can be 85°, 88°, or 90°, etc.

[0093] It should be noted that in some examples of this disclosure, the first pixel circuit 21 and the second pixel circuit can both cover the above-mentioned signal lines. For ease of description, this disclosure describes the first pixel circuit 21, the second pixel circuit 22, and the signal lines separately.

[0094] In some examples, such as Figure 2 , Figure 4 and Figure 6 As shown, the above-mentioned display substrate 100 may further include: a light-emitting device layer 3 disposed on the side of the pixel circuit layer 2 away from the substrate 1.

[0095] For example, the light-emitting device layer 3 described above may include a plurality of first light-emitting devices 31 and a plurality of second light-emitting devices 32. The structures of the first light-emitting devices 31 and the second light-emitting devices 32 may, for example, be the same. Figure 15 As shown, the first light-emitting device 21 includes an anode, a light-emitting layer, and a cathode stacked sequentially. Correspondingly, the second light-emitting device 32 may also include an anode, a light-emitting layer, and a cathode stacked sequentially.

[0096] For example, at least one first pixel circuit 21 can be electrically connected to at least one first light-emitting device 31. For instance, the first pixel circuit 21 and the first light-emitting device 31 can be electrically connected in a one-to-one correspondence, or one first pixel circuit 21 can be electrically connected to multiple first light-emitting devices 31, or multiple first pixel circuits 21 can be electrically connected to one first light-emitting device 31. Each first pixel circuit 21 can provide a driving signal to the corresponding first light-emitting device 31 to drive the corresponding first light-emitting device 31 to emit light. Figure 7 As shown, this disclosure uses the electrical connection of a first pixel circuit 21 and a first light-emitting device 31 as an example for illustration.

[0097] For example, at least one second pixel circuit 22 can be electrically connected to at least one second light-emitting device 32. For instance, the second pixel circuit 22 and the second light-emitting device 32 can be electrically connected in a one-to-one correspondence, or one second pixel circuit 22 can be electrically connected to multiple second light-emitting devices 32, or multiple second pixel circuits 22 can be electrically connected to one second light-emitting device 32. Each second pixel circuit 22 can provide a driving signal to the corresponding second light-emitting device 32 to drive the corresponding second light-emitting device 32 to emit light. Figure 7 As shown, this disclosure uses the electrical connection of a second pixel circuit 22 and a second light-emitting device 32 as an example for illustration.

[0098] For example, the orthographic projections of at least one second light-emitting device 32 and at least one second pixel circuit 22 onto the plane of the display substrate 100 at least partially overlap. That is, the orthographic projections of the electrically connected second light-emitting device 32 and second pixel circuit 22 onto the plane of the display substrate 100 may partially or completely overlap.

[0099] The light emitted by the plurality of first light-emitting devices 31 and the plurality of second light-emitting devices 32 works together to enable the display substrate 100 to display images. The sum of the areas of the first display area A1 and the second display area A2 is close to the area of ​​the display substrate 100, which helps to increase the area ratio of the displayable region in the display substrate 100, thereby increasing the screen-to-body ratio and enabling the display substrate 100 to achieve full-screen display.

[0100] In some examples, such as Figure 10 and Figure 11 As shown, the plurality of first pixel circuits 21 and the plurality of second pixel circuits 22 in the pixel circuit layer 2 can all be located in the second display area A2. The plurality of first light-emitting devices 31 in the light-emitting device layer 3 can all be located in the first display area A1, and the plurality of second light-emitting devices 32 can all be located in the second display area A2. The transmittance of the portion of the display substrate 100 located in the first display area A1 is greater than the transmittance of the portion of the display substrate 100 located in the second display area A2.

[0101] Here, the first pixel circuit 21, the second pixel circuit 22, and the signal lines in pixel circuit layer 2 need to transmit electrical signals reliably. Therefore, a portion of the first pixel circuit 21, a portion of the second pixel circuit 22, and the signal lines are formed using a metallic material. It is understood that metallic materials can block light.

[0102] In some examples of this disclosure, the first pixel circuit 21 that provides a driving signal to the first light-emitting device 31 is placed after the second display area A2, which reduces the structure in the first display area A1 that can block light. External light can then pass through the gap between any two adjacent first light-emitting devices 31 from one side (e.g., the light-emitting side) of the portion of the display substrate 100 located in the first display area A1, and exit from the other side (e.g., the non-light-emitting side) of the portion of the display substrate 100 located in the first display area A1, so that the portion of the display substrate 100 located in the first display area A1 has a higher transmittance.

[0103] In this way, when the display substrate 100 is applied to the display device 1000, and an optical element 200 is provided on the non-light-emitting side of the display substrate 100 and in the first display area A1, external light can pass through the portion of the display substrate 100 located in the first display area A1 and be incident on the optical element 200, collected by the optical element 200, and enable the optical element 200 to work normally.

[0104] For example, the distribution density of the plurality of first light-emitting devices 31 is the same as the distribution density of the plurality of second light-emitting devices 32. This not only enables the display substrate 100 to achieve full-screen display, but also helps to ensure that the display substrate 100 has good image display quality.

[0105] For example, the distribution density of the plurality of first light-emitting devices 31 is less than the distribution density of the plurality of second light-emitting devices 32. This increases the spacing between any two adjacent first light-emitting devices 31, reduces the obstruction of external light by the first light-emitting devices 31, and increases the area of ​​the light-transmitting portion of the display substrate 100 located in the first display area A1, thereby further increasing the amount of external light that can pass through the portion of the display substrate 100 located in the first display area A1. After the display substrate 100 is applied to the display device 1000, it is beneficial to increase the amount of external light collected by the optical element 200 and improve the working performance of the optical element 200.

[0106] In some examples, such as Figures 9-11 As shown, the display substrate 100 may further include multiple leads 41.

[0107] For example, such as Figures 9-11 As shown, one end of each lead 41 can be electrically connected to the first pixel circuit 21, and the other end can be electrically connected to the first light-emitting device 31. In this way, the lead 41 can be used to realize the electrical connection between the first pixel circuit 21 and the first light-emitting device 31, and the first pixel circuit 21 can transmit driving signals to the corresponding first light-emitting device 31 through the lead 41.

[0108] It is understandable that, as the lead 41 extends from the first pixel circuit 21 to the first light-emitting device 31, it may cross the first pixel circuit 21 and / or the second pixel circuit 22, and form parasitic capacitance with them.

[0109] The presence of the parasitic capacitance mentioned above can easily affect the accuracy of the driving signal received by the first light-emitting device 31, and thus easily affect the light emission accuracy of the first light-emitting device 31, affecting the display effect of the part of the display substrate located in the first display area.

[0110] In one implementation, to reduce the impact of parasitic capacitance on the leads, the lead paths are adjusted to make the parasitic capacitance of different leads more consistent. However, this results in significant differences in the lengths of different leads, lacking a regular pattern, and requires specific design of their paths based on the parasitic capacitance of each lead, which can easily increase the design and fabrication difficulty of the display substrate.

[0111] Based on this, in some examples, such as Figures 9-11As shown, the plurality of first light-emitting devices 31 located in the first display area A1 can be divided into a plurality of first light-emitting device groups 31a. Each first light-emitting device group 31a may include N first light-emitting devices 31. Correspondingly, the plurality of first pixel circuits 21 located in the second display area A2 can be divided into a plurality of first pixel circuit groups 21a. Each first pixel circuit group 21a may include N first pixel circuits 21. The aforementioned plurality of leads 41 can be divided into a plurality of lead groups 41a. Each lead group 41a may include N leads 41. Where N ≥ 2, and N is an integer.

[0112] For example, the number of first light-emitting devices 31 included in different first light-emitting device groups 31a may be equal or unequal. The number of first pixel circuits 21 included in different first pixel circuit groups 21a may be equal or unequal. The number of leads 41 included in different lead groups 41a may be equal or unequal.

[0113] Among them, the number of first light-emitting devices 31, the number of first pixel circuits 21, and the number of leads 41 in the first light-emitting device group 31a, the first pixel circuit group 21a, and the lead group 41a that are electrically connected are the same.

[0114] For example, in the electrically connected first light-emitting device group 31a, first pixel circuit group 21a, and lead group 41a, the first light-emitting device group 31a includes 20 first light-emitting devices 31, the first pixel circuit group 21a includes 20 first pixel circuits 21, and the lead group 41a includes 20 leads 41. Each first light-emitting device 31 is electrically connected to a corresponding first pixel circuit 21 via a lead 41.

[0115] For example, along the first direction X and pointing from the second display area A2 to the first display area A1, the N first light-emitting devices 31 in the first light-emitting device group 31a are respectively the 1st to the Nth first light-emitting devices.

[0116] It is understandable that, based on the positional relationship between the first display area A1 and the second display area A2, the second display area A2 will surround the first display area A1 on opposite sides along the first direction X. For example, as... Figure 1 As shown, in this disclosure, the portions of the second display area A2 located on opposite sides of the first display area A1 along the first direction X are respectively referred to as the first sub-area A21a and the second sub-area A22a. Here, the phrase "along the first direction X and pointing from the second display area A2 to the first display area A1" refers to pointing from the first sub-area A21a to the first display area A1 along the first direction X, and / or pointing from the second sub-area A22a to the first display area A1 along the first direction X.

[0117] For example, in the above-mentioned "along the first direction X and from the second display area A2 to the first display area A1", it means that along the first direction X and from the first sub-area A21a to the first display area A1, among the N first light-emitting devices 31 in the first light-emitting device group 31a, the first first light-emitting device is closest to the first sub-area A21a, that is, closest to the boundary of the first display area A1. The second, third, fourth, ... N-1th and Nth first light-emitting devices are successively moved away from the first sub-area A21a.

[0118] For example, in the above-mentioned "along the first direction X and from the second display area A2 to the first display area A1", it means that along the first direction X and from the second sub-area A22a to the first display area A1, among the N first light-emitting devices 31 in the first light-emitting device group 31a, the first first light-emitting device is closest to the second sub-area A22a, that is, closest to the boundary of the first display area A1. The second, third, fourth, ... N-1th and Nth first light-emitting devices are successively moved away from the second sub-area A22a.

[0119] For example, in the above-mentioned "along the first direction X and from the second display area A2 to the first display area A1", it refers to the case where, along the first direction X and from the first sub-area A21a to the first display area A1, and along the first direction X and from the second sub-area A22a to the first display area A1, in a portion of the above-mentioned multiple first light-emitting device groups 31a, the first first light-emitting device is closest to the first sub-area A21a, and the remaining first light-emitting devices are successively moved away from the first sub-area A21a, and there is a certain distance between the Nth first light-emitting device and the second sub-area A22a; in another portion of the first light-emitting device groups 31a, the first first light-emitting device is closest to the second sub-area A22a, and the remaining first light-emitting devices are successively moved away from the second sub-area A22a, and there is a certain distance between the Nth first light-emitting device and the first sub-area A21a.

[0120] For example, the N first pixel circuits 21 in the first pixel circuit group 21a are respectively the 1st to the Nth first pixel circuits. The 1st to the Nth first pixel circuits are arranged sequentially along the direction away from the first display area A1.

[0121] That is, in the first pixel circuit group 21a, the first pixel circuit 21 closest to the first light-emitting device group 31a is the first first pixel circuit. The second, third, fourth... N-1th and Nth first pixel circuits are successively moved away from the first light-emitting device group 31a.

[0122] The arrangement direction of the first to Nth first pixel circuits can be varied and can be selected and set according to actual needs.

[0123] For example, the arrangement direction of the first to Nth first pixel circuits can be the first direction X. That is, the arrangement direction of the plurality of first pixel circuits 21 in the first pixel circuit group 21a is the same as the arrangement direction of the plurality of first light-emitting devices 31 in the first light-emitting device group 31a.

[0124] For example, the arrangement direction of the first to Nth pixel circuits can have an angle with the first direction X. The size of this angle can be selected and set according to actual needs. Optionally, the angle can be 45° or 90°.

[0125] For example, such as Figures 9-11 As shown, the N leads 41 included in the lead group 41a are arranged in parallel. The extension directions of these N leads 41 are, for example, parallel or substantially parallel.

[0126] For example, the i-th first light-emitting device is electrically connected to the i-th first pixel circuit through the i-th lead. Where i = 1 to N. That is, the 1st first light-emitting device can be electrically connected to the 1st first pixel circuit through the 1st lead, the 2nd first light-emitting device can be electrically connected to the 2nd first pixel circuit through the 2nd lead, and so on. The (N-1)th first light-emitting device can be electrically connected to the (N-1)th first pixel circuit through the (N-1)th lead, and the Nth first light-emitting device can be electrically connected to the Nth first pixel circuit through the Nth lead.

[0127] For example, the lengths of the first to Nth leads gradually increase.

[0128] It is understandable that the first to Nth first pixel circuits in the first pixel circuit group 21a move away from the first light-emitting device group 31a in sequence along their arrangement direction. This means that the distance between the first, second, third...N-1, and Nth first pixel circuits and the first light-emitting device group 31a gradually increases. Correspondingly, the distance between the first first pixel circuit and the first first light-emitting device, the distance between the second first pixel circuit and the second first light-emitting device, the distance between the (N-1)th first pixel circuit and the (N-1)th first light-emitting device, and the distance between the Nth first pixel circuit and the Nth first light-emitting device gradually increase. Thus, the length of the first lead connecting the first pixel circuit and the first light-emitting device, the length of the second lead connecting the second pixel circuit and the second light-emitting device, ... the length of the N-1 lead connecting the (N-1)th pixel circuit and the (N-1)th light-emitting device, and the length of the Nth lead connecting the Nth pixel circuit and the Nth light-emitting device gradually increase.

[0129] For example, the portion of each lead 41 located between the corresponding first pixel circuit 21 and the corresponding first light-emitting device 31 is straight. In this case, the length of the lead 41 refers, for example, to the distance between the corresponding first pixel circuit 21 and the corresponding first light-emitting device 31. This not only facilitates the fabrication of the lead 41 but also avoids the formation of corners or sharp points in the lead 41, ensuring good transmission of the driving signal within the lead 41.

[0130] The above-described arrangement and connection method not only facilitates the planning of the routing path of the lead 41 and improves the regularity of the length difference between any two adjacent leads 41 in the lead group 41a, but also reduces the number of leads 41 required, simplifies the structure of the display substrate 100, and reduces the difficulty of fabricating the display substrate 100.

[0131] Furthermore, the first pixel circuit 21, the second pixel circuit 22, and the signal lines in pixel circuit layer 2 are arranged in a regular pattern. This improves the regularity of the difference in the number of first pixel circuits 21 and / or second pixel circuits 22 crossed by any two adjacent leads 41 in lead group 41a during the extension process of the lead 41, thereby facilitating the improvement of the uniformity of parasitic capacitance changes formed in any two adjacent leads 41 in lead group 41a.

[0132] Here, the present disclosure may employ external compensation, for example, to compensate for the parasitic capacitance formed by the lead 41, thereby improving the accuracy of the driving signal received by the first light-emitting device 31 and the light emitted, and ensuring the display effect of the portion of the display substrate located in the first display area. The aforementioned external compensation methods include, but are not limited to, external optical compensation (demura) methods.

[0133] This disclosure improves the uniformity of parasitic capacitance variation formed in any two adjacent leads 41 in lead group 41a, which is beneficial for optimizing the external optical compensation (demura) algorithm, improving the display uniformity of display substrate 100, and enhancing the image quality displayed by display substrate 100.

[0134] In some examples, such as Figures 9-11 As shown, at least one row or at least one column of second pixel circuits are spaced between the first first light-emitting device and the first first pixel circuit. N leads 41 in lead group 41a extend from the first display area A1, through the aforementioned at least one row or at least one column of second pixel circuits, to the second display area A2.

[0135] For example, one, three, four, or seven rows of second pixel circuits may be arranged between the first light-emitting device and the first pixel circuit. Alternatively, one, three, four, eight, ten, or two columns of second pixel circuits may be arranged between the first light-emitting device and the first pixel circuit.

[0136] For example, such as Figures 9-11 As shown, when at least one column of second pixel circuits is provided between the first first light-emitting device and the first first pixel circuit, the first lead in lead group 41a will extend from the first display area A1 across the at least one column of second pixel circuits to the second display area A2. The second, third, ... Nth leads will extend from the first display area A1 across the at least one column of second pixel circuits and then continue to extend across the at least one column of second pixel circuits to the second display area A2.

[0137] In one implementation, the first light-emitting device and the first pixel circuit are arranged adjacent to each other, and there is no second pixel circuit between them. In this case, the length of the shortest first lead in the lead group is, for example, L. For example, if the length difference between any two adjacent leads in the lead group is m, then the length of the longest Nth lead is L + m(N-1). The ratio between the length of the Nth lead and the length of the first lead is:

[0138]

[0139] In some examples of this disclosure, after at least one row or at least one column of second pixel circuits are spaced between the first first light-emitting device and the first first pixel circuit, the length of the first lead connecting the first first light-emitting device and the first first pixel circuit is, for example, L+p. For example, if the length difference between any two adjacent leads in the lead group is m, then the length of the longest Nth lead is L+p+m(N-1). The ratio between the length of the Nth lead and the length of the first lead is:

[0140] in, Less than Correspondingly, the ratio of the parasitic capacitance formed by the Nth lead to the parasitic capacitance formed by the 1st lead will be less than the ratio in the above implementation.

[0141] In other words, in this disclosure, after at least one row of second pixel circuits or at least one column of second pixel circuits are provided between the first first light-emitting device and the first first pixel circuit, the length of the first lead can be increased by a large factor, but the length of the Nth lead can only be increased by a small factor. This can effectively reduce the ratio between the length of the Nth lead and the length of the first lead, and effectively reduce the ratio between the parasitic capacitance formed by the Nth lead and the parasitic capacitance formed by the first lead.

[0142] It is understandable that the smaller the length ratio between the longest Nth lead and the shortest 1st lead, the smaller the difference between the parasitic capacitance formed by the Nth lead and the parasitic capacitance formed by the 1st lead. This results in a smaller difference between the loss of the driving signal on the Nth lead and the loss on the 1st lead. Thus, during image display on the display substrate 100, the difference in grayscale levels can be reduced, improving display quality. Furthermore, in the subsequent process of compensating for grayscale differences using an external optical compensation (demura) algorithm, the smaller the grayscale difference, the less workload the external optical compensation (demura) algorithm requires, which facilitates further optimization of the algorithm. Moreover, once the grayscale difference is reduced to a certain extent, it may not be necessary to use an external optical compensation (demura) algorithm to ensure good image quality on the display substrate 100.

[0143] Therefore, the display substrate 100 provided in some embodiments of this disclosure, by setting a first display area A1 and a second display area A2, and setting a first light-emitting device 31 in the first display area A1 and a first pixel circuit 21 that provides driving signals to the first light-emitting device 31 in the second display area A2, avoids the first pixel circuit 21 blocking the light incident on the first display area A1, thereby improving the transmittance of the portion of the display substrate 100 located in the first display area A1. After the display substrate 100 is applied to the display device 1000, external light can pass through the portion of the display substrate 100 located in the first display area A1 and enter the optical element 200 of the display device 100. This allows the optical element 200 to work normally and increases the proportion of the displayable area in the display substrate 100, enabling the display substrate 100 and the display device 1000 to achieve full-screen display.

[0144] Furthermore, by setting a lead 41 connecting the first light-emitting device 31 and the first pixel circuit 21, this disclosure arranges N leads 41 in the lead group in parallel, so that the lengths of the first to Nth leads gradually increase. At least one row or at least one column of second pixel circuits are spaced between the first first light-emitting device in the first light-emitting device group 31a and the first first pixel circuit in the first pixel circuit group 21a. This not only facilitates the planning of the lead 41's path but also improves the regularity of the length difference between any two adjacent leads 41 in the lead group 41a, and enhances the consistency of the length difference between any two adjacent leads 41 in the lead group 41a. The uniformity of the parasitic capacitance formed in line 41 can also be improved by using at least one row or at least one column of second pixel circuits spaced between the first first light-emitting device and the first first pixel circuit. This can greatly increase the length of the first lead, thereby reducing the ratio between the length of the Nth lead and the length of the first lead, reducing the ratio between the parasitic capacitance formed by the Nth lead and the parasitic capacitance formed by the first lead, reducing the difference in grayscale displayed by the display substrate 100, optimizing the external optical compensation (demura) algorithm, or even eliminating the need for the external optical compensation (demura) algorithm.

[0145] In some embodiments, among the N leads 41 included in the lead group 41a, the length ratio of the Nth lead to the first lead is α, where α ≤ 25.

[0146] In some examples, α = 25, α ≤ 24, α ≤ 22, α ≤ 20, or α ≤ 18, etc.

[0147] By setting the length ratio of the Nth lead to the 1st lead to less than or equal to 25, the length ratio of the longest Nth lead to the shortest 1st lead can be effectively reduced. This reduces the difference between the parasitic capacitance formed by the Nth lead and the parasitic capacitance formed by the 1st lead, thereby reducing the grayscale difference of the image displayed on the display substrate 100. Furthermore, in the subsequent process of compensating for grayscale differences using an external optical compensation (demura) algorithm, the workload of the external optical compensation (demura) algorithm can be reduced, thus optimizing the algorithm.

[0148] For example, the above length ratio α satisfies that α≤15.

[0149] By setting the length ratio of the Nth lead to the 1st lead to less than or equal to 15, the length ratio of the longest Nth lead to the shortest 1st lead can be further reduced, thereby reducing the difference between the parasitic capacitance formed by the Nth lead and the parasitic capacitance formed by the 1st lead. This further reduces the grayscale difference of the image displayed on the display substrate 100. Moreover, in the subsequent process of compensating for grayscale differences using an external optical compensation (demura) algorithm, the workload of the external optical compensation (demura) algorithm can be further reduced, and the algorithm can be further optimized.

[0150] For example, the length ratio α can range from 5 to 10, 10 to 15, 15 to 20, or 7 to 13, etc.

[0151] For example, the length ratio α can take values ​​of 5, 6, 7.5, 9.1, 10, 12, 14, or 15, etc.

[0152] In some embodiments, the number of rows or columns of the second pixel circuits disposed between the first first light-emitting device and the first first pixel circuit is β, where β≤30.

[0153] In some examples, such as Figures 9-11 As shown, N first pixel circuits in the first pixel circuit group 21a are arranged sequentially along the first direction X. At this time, at least one column of second pixel circuits is arranged between the first first light-emitting device and the first first pixel circuit. The number of columns of the spaced-apart second pixel circuits 22 is β, where β ≤ 30.

[0154] For example, the above β satisfies β=30, β≤28, β≤25, β≤21, β≤20 or β≤15, etc.

[0155] By adopting the above configuration, it can be ensured that the length of the Nth lead increases by a small factor, thereby ensuring that the length ratio of the Nth lead to the 1st lead is small, ensuring a good improvement effect on the grayscale difference of the image displayed on the display substrate 100 and a good optimization effect on the external compensation (demura) algorithm.

[0156] In some embodiments, the ratio of the number of rows or columns of pixel circuits spaced apart between the Nth first light-emitting device and the Nth first pixel circuit to the number of rows or columns of second pixel circuits spaced apart between the 1st first light-emitting device and the 1st first pixel circuit is γ, where 5≤γ≤50.

[0157] It is understandable that, apart from the first first light-emitting device and the first first pixel circuit, a first pixel circuit 21 and a second pixel circuit 22 are disposed between the i-th first light-emitting device and the i-th first pixel circuit. That is to say, the pixel circuits disposed between the N-th first light-emitting device and the N-th first pixel circuit include the first pixel circuit and the second pixel circuit.

[0158] Furthermore, since the shape of the first display area A1 is variable, the number of first light-emitting devices 31 included in different first light-emitting device groups 31a can be different. For example, as Figure 1 As shown, along the second direction Y, the number of first light-emitting devices 31 included in the first light-emitting device group 31a that is closer to the upper or lower boundary of the first display area A1 is less, and the number of first light-emitting devices 31 included in the first light-emitting device group 31a that is closer to the middle boundary of the first display area A1 is more.

[0159] In the smaller number of first light-emitting device groups 31a, the ratio γ of the number of rows or columns of pixel circuits spaced between the Nth first light-emitting device and the Nth first pixel circuit to the number of rows or columns of second pixel circuits spaced between the 1st first light-emitting device and the 1st first pixel circuit can be relatively small. In the larger number of first light-emitting device groups 31a, the ratio γ of the number of rows or columns of pixel circuits spaced between the Nth first light-emitting device and the Nth first pixel circuit to the number of rows or columns of second pixel circuits spaced between the 1st first light-emitting device and the 1st first pixel circuit can be relatively large.

[0160] By adopting the above configuration, the length of the Nth lead will not be too large, and the ratio of the length of the Nth lead to the length of the 1st lead will be small. This ensures a good improvement effect on the grayscale difference of the image displayed on the display substrate 100 and a good optimization effect on the external compensation (demura) algorithm.

[0161] In some embodiments, the sequence of length values ​​of the N leads 41 in the lead group 41a is an arithmetic sequence. That is, the length difference between any two adjacent leads 41 is equal. Alternatively, the sequence of length values ​​of the N leads 41 in the first direction X in the lead group 41a is an arithmetic sequence. That is, the length difference between any two adjacent leads 41 is equal.

[0162] It is understandable that when there is an angle between the extension direction of the lead 41 and the first direction X, the length value of the lead 41 in the first direction X is the component of the actual length value of the lead 41 in the first direction X.

[0163] For example, the length of the first lead is L, and the length difference between any two adjacent leads 41 in lead group 41a is m. In this case, the sequence of lengths of the aforementioned N leads 41 is: L, L+m, L+2m, L+3m…L+m(N-2), L+m(N-1). The length of the lead 41 in the first direction X can be referred to the explanation here, and will not be repeated here.

[0164] By setting the sequence of length values ​​of the aforementioned N leads 41, or their length values ​​in the first direction X, as an arithmetic sequence, it can be ensured that the length values ​​of the N leads 41 vary uniformly. This facilitates the optimization of the external optical compensation (demura) algorithm and improves the display quality of the display substrate 100. Furthermore, this arrangement also improves the uniformity of the parasitic capacitance variation formed by the N leads 41, thereby facilitating further optimization of the external optical compensation (demura) algorithm and further enhancing the display quality of the display substrate 100.

[0165] In some embodiments, the resistance values ​​of the N leads 41 in the lead group 41a form an arithmetic sequence. That is, the resistance difference between any two adjacent leads 41 is equal.

[0166] For example, the resistance value of the first lead is R, and the resistance difference between any two adjacent leads 41 in lead group 41a is t. In this case, the sequence of resistance values ​​of the above N leads 41 is: R, R+t, R+2t, R+3t...R+t(N-2), R+t(N-1).

[0167] It is understandable that after the driving signal provided by the first pixel circuit 21 is transmitted to the lead 41, the presence of resistance in the lead 41 will cause a certain loss to the driving signal, reducing the accuracy of the driving signal received by the first light-emitting device 31.

[0168] By setting the sequence of resistance values ​​of the aforementioned N leads 41 as an arithmetic sequence, it can be ensured that the resistance values ​​of the N leads 41 vary uniformly. This helps to reduce the difficulty of compensating for the resistance of the leads 41 and improves the display quality of the display substrate 100.

[0169] In some embodiments, each lead 41 forms a parasitic capacitance with the second pixel circuit 22 and / or the first pixel circuit 21 it passes through. The sequence of parasitic capacitance values ​​formed by the above N leads 41 is an arithmetic sequence. That is, the difference in parasitic capacitance between any two adjacent leads 41 is equal.

[0170] For example, the parasitic capacitance value formed by the first lead is Cs, and the parasitic capacitance difference between any two adjacent leads 41 in lead group 41a is u. At this time, the sequence of resistance values ​​formed by the above N leads 41 is: Cs, Cs+u, Cs+2u, Cs+3u...Cs+u(N-2), Cs+u(N-1).

[0171] It is understandable that after the driving signal provided by the first pixel circuit 21 is transmitted to the lead 41, the presence of parasitic capacitance in the lead 41 will cause a large loss to the driving signal, greatly reducing the accuracy of the driving signal received by the first light-emitting device 31, and causing a time delay in the driving signal received by the first light-emitting device 31.

[0172] By setting the sequence of parasitic capacitance values ​​formed by the aforementioned N leads 41 as an arithmetic sequence, it can be ensured that the parasitic capacitance values ​​formed by the N leads 41 vary uniformly. This facilitates compensation for the parasitic capacitance values ​​and time delay, which is beneficial for optimizing the external optical compensation (demura) algorithm and improving the display quality of the display substrate 100.

[0173] It is understandable that the arrangement direction of the first to Nth first pixel circuits in the first pixel circuit group 21a can be configured in multiple ways.

[0174] In some examples, such as Figures 9-11 As shown, the above arrangement direction is the first direction X.

[0175] For example, the first light-emitting device group 31a and the first pixel circuit group 21a electrically connected to the first light-emitting device group 31a are arranged in the same row. That is, along the first direction X, the first light-emitting device group 31a and the first pixel circuit group 21a are located in the same row. Correspondingly, the N leads 41 in the lead group 41a can extend along the first direction X.

[0176] At this time, at least one column of second pixel circuits can be provided at intervals between the first light-emitting device and the first pixel circuit. Correspondingly, the aforementioned N leads 41 can extend from the first display area A1 along the first direction X through the at least one column of second pixel circuits to the second display area A2.

[0177] By setting the direction Z to the first direction X, and arranging the first light-emitting device group 31a and the first pixel circuit group 21a electrically connected to the first light-emitting device group 31a in the same row, it is convenient to route the signal lines (e.g., gate lines) in the pixel circuit layer 2, facilitate driving the first pixel circuit group 21a, and reduce the design and fabrication difficulty of the display substrate 100.

[0178] It is understandable that the first pixel circuit group 21a can be arranged in the same row as the second pixel circuit, which is beneficial for simultaneously driving the pixel circuit group 21a and the second pixel circuit in the same row. At least one second pixel circuit 22 can be arranged between any two adjacent first pixel circuits 21, which reduces the misalignment between the second pixel circuit 22 and the corresponding second light-emitting device 32. For example, the number of second pixel circuits 22 spaced apart between any two adjacent first pixel circuits 21 is the same. This helps improve the uniformity of the length variation of the N leads 41 in the lead group 41a and improves the uniformity of the parasitic capacitance variation formed by the N leads 41.

[0179] For example, such as Figure 9 As shown, the first pixel circuit group 21a may include 20 first pixel circuits 21, the first light-emitting device group 31a may include 20 first light-emitting devices 31, and the lead group 41a may include 20 leads 41. Six columns of second pixel circuits may be spaced apart between the first first light-emitting device and the first first pixel circuit. Two second pixel circuits 22 are spaced apart between any two adjacent first pixel circuits 21; that is, one first pixel circuit 21 is spaced apart between every two second pixel circuits 22.

[0180] For example, such as Figure 9 As shown, along the first direction X, the size of the area occupied by each second pixel circuit 22 or each first pixel circuit 21 is b, and the size of the area occupied by each first light-emitting device 31 is c, and 3b = 2c.

[0181] At this point, without any second pixel circuits spaced between the first first light-emitting device and the first first pixel circuit, the length of the first lead is the sum of the dimensions of the areas occupied by the first first pixel circuit and the first first light-emitting device, i.e., b + c = 2.5b. The difference in length between any two adjacent leads is the sum of the dimensions of the areas occupied by the two second pixel circuits, one first pixel circuit, and one first light-emitting device, i.e., 2b + b + c = 3b + c. The length of the Nth (i.e., the 20th) lead is (b + c) + 19(3b + c) = 88b. The ratio between the length of the 20th lead and the length of the first lead is 35.20.

[0182] When six columns of second pixel circuits are spaced between the first first light-emitting device and the first first pixel circuit, the length of the first lead is the sum of the dimensions of the area occupied by the first first pixel circuit, the first first light-emitting device, and the six second pixel circuits spaced between the first first pixel circuit and the first first light-emitting device, i.e., b + c + 6b = 7b + c. Since 3b = 2c, 7b + c = 8.5b. The difference in length between any two adjacent leads is the sum of the dimensions of the areas occupied by the two second pixel circuits, the one first pixel circuit, and the one first light-emitting device, i.e., 2b + b + c = 3b + c. The length of the Nth (i.e., the 20th) lead is (7b + c) + 19(3b + c) = 94b. The ratio between the length of the 20th lead and the length of the first lead is 11.06 (rounded to two decimal places).

[0183] As can be seen from the above, after 6 columns of second pixel circuits are arranged between the first light-emitting device and the first pixel circuit, the length of the first lead increases by 6 bytes compared to when no second pixel circuits are arranged, which is a significant increase.

[0184] Meanwhile, the length of the Nth lead also increased by 6b, a relatively small increase. Consequently, the ratio between the length of the 20th lead and the length of the 1st lead is significantly reduced, which is beneficial for optimizing the external optical compensation (demura) algorithm.

[0185] Optionally, this disclosure may also provide a first pixel circuit 21 spaced between every four second pixel circuits 22, or a first pixel circuit 21 spaced between every six second pixel circuits 22, or a first pixel circuit 21 spaced between every seven second pixel circuits 22, which can reduce the ratio between the Nth lead and the 1st lead and optimize the external optical compensation (demura) algorithm.

[0186] In other examples, the angle between the above arrangement direction and the first direction X is 45°. In this case, the N leads 41 in the lead group 41a can extend, for example, in a direction perpendicular to the first direction X, and extend from the first display area A1, in a direction perpendicular to the first direction X, through at least one row or at least one column of the second pixel circuit, to the second display area A2.

[0187] In some other examples, the angle between the above-mentioned arrangement direction and the first direction X is 90°. In this case, the angle between the extension direction of the N leads 41 in the lead group 41a and the first direction X is, for example, 45°. These N leads 41 can extend from the first display area A1, along a direction at a 45° angle to the first direction X, through at least one row or at least one column of the second pixel circuit, to the second display area A2.

[0188] It is understandable that the number of rows or columns of the second pixel circuits that are spaced between the first light-emitting device and the first pixel circuit can be selected and set according to actual needs, so that the length ratio of the Nth lead 41 to the first lead 41 is less than or equal to a preset value.

[0189] Optionally, the number of rows or columns of the second pixel circuits spaced apart between the first light-emitting device and the first pixel circuit is related to the arrangement of the sub-pixels P in the display substrate 100. That is, different sub-pixels P have different arrangements, and the number of rows or columns of the second pixel circuits spaced apart between the first light-emitting device and the first pixel circuit can be different. This helps ensure the normal use of the external optical compensation algorithm (demura) and avoids causing algorithm confusion.

[0190] For example, the sub-pixel P may include a second pixel circuit 22 and a second light-emitting device 32 that are electrically connected. Of course, the sub-pixel P may also include a first pixel circuit 21 and a first light-emitting device 31 that are electrically connected.

[0191] The following example illustrates the arrangement of the first light-emitting device group 31a and the first pixel circuit group 21a electrically connected to the first light-emitting device group 31a in the same row, taking the above arrangement direction as the first direction X and the first light-emitting device group 31a in the same row as an example. According to different sub-pixel P arrangement methods, the number of columns of the second pixel circuits that are spaced apart between the first first light-emitting device and the first first pixel circuit will be illustrated.

[0192] In some examples, such as Figure 12 As shown, the display substrate 100 includes a plurality of pixel units, each pixel unit including three sub-pixels P arranged along a first direction X.

[0193] For example, the three sub-pixels P mentioned above include a red sub-pixel (R), a green sub-pixel (G), and a blue sub-pixel (B). The RGB sub-pixels are arranged periodically along the first direction X.

[0194] For example, X second pixel circuits 22 belonging to at least one pixel unit are provided between the first first light-emitting device and the first first pixel circuit, where X is a multiple of 3.

[0195] For example, between the first light-emitting device and the first pixel circuit, there may be 3, 6, 9 or 12 second pixel circuits, etc.

[0196] In other examples, such as Figure 13 As shown, the display substrate 100 includes multiple pixel units, and each pixel unit includes multiple sub-pixels P. The multiple pixel units are arranged in a pentile arrangement.

[0197] For example, a pentile arrangement can refer to adding a subpixel to the RGB array to achieve, for example, RGBG, RGBW, RGBY, etc., and some subpixels P in the pentile arrangement are "shared," thereby achieving a higher resolution visually than the actual resolution. Here, W represents a white subpixel, and Y represents a yellow subpixel. The number of subpixels P included in each pixel unit can be determined based on the sharing situation, and this disclosure does not limit this.

[0198] For example, Y second pixel circuits belonging to at least one pixel unit are disposed between the first first light-emitting device and the first first pixel circuit, where Y is a multiple of 2.

[0199] For example, two, four, six, or eight second pixel circuits may be provided between the first light-emitting device and the first pixel circuit.

[0200] In some embodiments, such as Figure 10 and Figure 11 As shown, the display substrate 100 has a straight line extending along the second direction Y and passing through the first display area A1, which can be called a reference line DD'. The second direction Y is, for example, perpendicular to the first direction X.

[0201] The positional relationships among the first pixel circuit group 21a, the first light-emitting device group 31a, the lead group 41a, and the reference line DD' included in the display substrate 100 can be varied and can be selected and set according to actual needs.

[0202] In some examples, the first pixel circuit group 21a, the first light-emitting device group 31a, and the lead group 41a may all be located on the same side of the reference line DD'.

[0203] In other examples, such as Figure 10 and Figure 11 As shown, the plurality of first light-emitting devices 31 located in the first display area A1 can be arranged in multiple rows along the second direction Y. Each row of first light-emitting devices 31 may include a plurality of first light-emitting devices 31 arranged sequentially along the first direction X. Each row of first light-emitting devices can be divided into two groups 31a of first light-emitting devices located on both sides of the reference line DD'.

[0204] Correspondingly, the two first pixel circuit groups 21a, which are electrically connected to the two first light-emitting device groups 31a located in the same row, can be located on opposite sides of the first display area A1 in the first direction X. At this time, the two first pixel circuit groups 21a are located on both sides of the reference line DD'.

[0205] Correspondingly, the two lead groups 41a electrically connected to the two first light-emitting device groups 31a located in the same row are located on both sides of the reference line DD'.

[0206] By arranging the first pixel circuit group 21a, the first light-emitting device group 31a, and the lead group 41a on both sides of the reference line DD', the number of first pixel circuits 21 included in the first pixel circuit group 21a, the number of first light-emitting devices 31 included in the first light-emitting device group 31a, and the number of leads 41 included in the lead group 41a can be reduced. This not only helps to reduce the complexity of the lead path 41, but also helps to reduce the pressure on the external optical compensation (demura) algorithm.

[0207] For example, such as Figure 10 and Figure 11 As shown, the two lead groups 41a that are electrically connected to the two first light-emitting device groups 31a are symmetrically arranged about the reference line DD'.

[0208] This not only further reduces the complexity of the routing path of lead 41, but also helps to make the length variation law of the two lead groups 41a and the parasitic capacitance variation law the same, thereby further reducing the pressure on the external optical compensation (demura) algorithm and optimizing the external optical compensation (demura) algorithm.

[0209] For example, such as Figure 10 and Figure 11 As shown, the first display area A1 has a center O, and the aforementioned reference line DD' is a straight line passing through the center O.

[0210] This ensures that the two first light-emitting device groups 31a located in the same row include the same number of first light-emitting devices 31, which in turn ensures that the two corresponding first pixel circuits 21a include the same number of first pixel circuits 21, and the two corresponding lead groups 41a include the same number of leads 41. This helps reduce the pressure on the external optical compensation (demura) algorithm.

[0211] It is understandable that the first light-emitting device 31 and the corresponding lead 41 are electrically connected through the adapter hole 5 (i.e., via) to avoid short circuits.

[0212] Based on this, in some examples, such as Figure 14 and Figure 15 As shown, the display substrate 100 further includes a set of adapter holes 5a. The set of adapter holes 5a includes N adapter holes 5, which are arranged sequentially along the first direction X and correspond to N first light-emitting devices 31 in the first light-emitting device group 31a.

[0213] For example, the N adapter holes 5 in the adapter hole group 5a are configured one-to-one with the N first light-emitting devices 31 in the first light-emitting device group 31a. Furthermore, the N adapter holes 5 in the adapter hole group 5a are configured one-to-one with the N leads 41 in the lead wire group 41a. In this way, each first light-emitting device 31 can be electrically connected to its corresponding lead wire 41 through the corresponding adapter hole 5.

[0214] Optionally, the orthographic shape of the adapter hole 5 on the substrate 1 can be selected and set according to actual needs. For example, the orthographic shape of the adapter hole 5 on the substrate 1 can be circular or square, etc.

[0215] Here, the positional relationship between the N leads 41 in the lead group 41a and the adapter hole group 5a can be varied. The following is an illustrative example of the first light-emitting device group 31a and the first pixel circuit group 21a electrically connected to the first light-emitting device group 31a being arranged in the same row along the first direction X.

[0216] For example, such as Figure 14 As shown, along the second direction Y, the i-th lead electrically connected to the i-th first light-emitting device is closer to the adapter hole group 5a than the i+1 lead electrically connected to the i+1-th first light-emitting device.

[0217] That is, the N leads 41 in the lead group 41a are located on the same side of the adapter hole group 5a, and along the second direction Y, the 1st, 2nd, 3rd...N-1th and Nth leads move away from the adapter hole group 5a in sequence.

[0218] For example, such as Figure 15 As shown, the i-th lead electrically connected to the i-th first light-emitting device and the i+1-th lead electrically connected to the i+1-th first light-emitting device are located on opposite sides of the adapter hole group 5a in the second direction Y.

[0219] That is, in the lead group 41a, the odd number of leads can be located on one side of the adapter hole group 5a in the second direction Y, and the even number of leads can be located on the other side of the adapter hole group 5a in the second direction Y.

[0220] In some embodiments, such as Figures 2-6 As shown, the display substrate 100 may further include a plurality of lead layers 4 disposed between the pixel circuit layer 2 and the light-emitting device layer 3. These plurality of lead layers 4 may be stacked sequentially along a direction perpendicular to the substrate 1. For example, the number of lead layers 4 may be two, three, or more.

[0221] It is understood that insulating layers can be spaced apart between the pixel circuit layer 2 and the aforementioned plurality of lead layers 4, insulating layers can be spaced apart between any two adjacent lead layers 4, and insulating layers can be spaced apart between the aforementioned plurality of lead layers 4 and the light-emitting device layer 3. Wherein, for example... Figure 4 As shown, the adapter hole group 5a can be located in the insulating layer between the plurality of lead layers 4 and the light-emitting device layer 3. Wherein, Figure 4 In the diagram, the anode is used to represent the light-emitting device layer 3.

[0222] In some examples, the N leads 41 of lead group 41a are located in the aforementioned multiple lead layers 4.

[0223] For example, each lead layer 4 may include at least one of N leads 41.

[0224] For example, such as Figure 4 , Figure 6 and Figure 17 As shown, each lead layer 4 may also include multiple connecting portions 42. The connecting portion 42 can replace the lead 41 that is electrically connected to it, so that the lead 41 can be electrically connected to the corresponding first light-emitting device 31 or first pixel circuit 21.

[0225] For example, such as Figure 3 and Figure 4 As shown, taking a lead layer 4 with three layers as an example, where, as Figure 4 As shown, along a direction perpendicular to and away from the substrate 1, the three lead layers 4 are respectively the first lead layer 4a, the second lead layer 4b, and the third lead layer 4c.

[0226] like Figure 4 As shown, each second pixel circuit 22 can be electrically connected to the corresponding second light-emitting device 32 through the connection part 42 located in the first lead layer 4a, the connection part 42 located in the second lead layer 4b, and the connection part 42 located in the third lead layer 4c in sequence. Figure 11 In the diagram, the anode of the second light-emitting device 32 represents the second light-emitting device 22, and the driving transistor T5 in the second pixel circuit 22 represents the second pixel circuit 22.

[0227] For example, part of the first pixel circuit 21 can be electrically connected to one end of the lead 41 located in the first lead layer 4a, and the other end of the lead 41 can be electrically connected to the corresponding first light-emitting device 31 through the connection part 42 located in the second lead layer 4b and the connection part 42 located in the third lead layer 4c in sequence.

[0228] For example, part of the first pixel circuit 21 can be electrically connected to one end of the lead 41 located in the second lead layer 4b through the connection part 42 located in the first lead layer 4a, and the other end of the lead 41 can be electrically connected to the corresponding first light-emitting device 31 through the connection part 42 located in the third lead layer 4c.

[0229] For example, part of the first pixel circuit 21 can be electrically connected to one end of the lead 41 located in the third lead layer 4c through the connection part 42 located in the first lead layer 4a and the connection part 42 located in the second lead layer 4b in sequence, and the other end of the lead 41 can be electrically connected to the corresponding first light-emitting device 31.

[0230] For example, such as Figure 5 and Figure 6 As shown, taking two lead layers as an example, where, as Figure 13 As shown, along a direction perpendicular to and away from the substrate 1, the two lead layers 4 are respectively the first lead layer 4a and the second lead layer 4b.

[0231] like Figure 6 As shown, each second pixel circuit 22 can be electrically connected to the corresponding second light-emitting device 32 through the connection portion 42 located in the first lead layer 4a and the connection portion 42 located in the second lead layer 4b in sequence. Figure 11 In the diagram, the anode of the second light-emitting device 32 represents the second light-emitting device 22, and the driving transistor T5 in the second pixel circuit 22 represents the second pixel circuit 22.

[0232] For example, part of the first pixel circuit 21 can be electrically connected to one end of the lead 41 located in the first lead layer 4a, and the other end of the lead 41 can be electrically connected to the corresponding first light-emitting device 31 through the connection part 42 located in the second lead layer 4b.

[0233] For example, part of the first pixel circuit 21 can be electrically connected to one end of the lead 41 located in the second lead layer 4b through the connection part 42 located in the first lead layer 4a, and the other end of the lead 41 can be electrically connected to the corresponding first light-emitting device 31.

[0234] In some examples, the material of the aforementioned multiple lead layers 4 includes a light-transmitting conductive material.

[0235] It is understandable that light-transmitting conductive materials have high transmittance. By using a light-transmitting conductive material to form the lead layer 4, the leads 41 located in the lead layer 4 can have high transmittance, avoiding blocking of light passing through the portion of the display substrate 100 located in the first display area A1, thereby ensuring that the portion of the display substrate 100 located in the first display area A1 has high transmittance.

[0236] For example, the aforementioned light-transmitting conductive material may include at least one of the following: indium tin oxide, indium zinc oxide, and indium gallium zinc oxide.

[0237] In some embodiments, such as Figures 3-6 As shown, the display substrate 100 further includes a transition layer 6 disposed between the pixel circuit layer 2 and the plurality of lead layers 4. The material of the transition layer 6 includes a metallic material.

[0238] For example, the material of the transition layer 6 can be the same as that of the source / drain conductive layer. This ensures that the transition layer 6 has good conductivity.

[0239] For example, the aforementioned metallic materials may include copper or aluminum.

[0240] In some examples, such as Figure 4 and Figure 6 As shown, the transition layer 6 is provided with a plurality of transition portions 61. These plurality of transition portions 61 are respectively provided corresponding to the plurality of first pixel circuits 21 and the plurality of second pixel circuits 22 included in the display substrate 100, for example, in a one-to-one correspondence. Each transition portion 61 can be connected to the second electrode of the second light-emitting control transistor T5 and the lead layer 4 located closest to the substrate 1.

[0241] By setting the transition layer 6, it is beneficial to increase the wiring space of the display substrate 100 and reduce the wiring difficulty.

[0242] Figure 16 In the diagram, the dashed line, resembling a broken line, represents the boundary between the first display area A1 and the second display area A2. The rightmost first light-emitting device 31 is the first light-emitting device, and the leftmost first pixel circuit 21 is the first first pixel circuit. The lead 41 connecting the first light-emitting device and the first first pixel circuit is the first lead. Figure 16 A first pixel circuit 21 is disposed within the area defined by the H-shaped solid line, and a second pixel circuit 22 is disposed within the area between two adjacent H-shaped solid lines. For details regarding the virtual pixel circuit, please refer to the description below; it will not be repeated here.

[0243] In some examples, such as Figure 17 As shown, the display substrate 100 includes two lead layers 4. Among the aforementioned N leads 41, the first to the Nth leads are alternately located in the two lead layers 4.

[0244] This allows for a larger spacing between any two adjacent leads 41 within the same lead layer 4, preventing short circuits between adjacent leads 41 and ensuring the accuracy of drive signal transmission.

[0245] It should be noted that there are multiple settings between the first pixel circuit 21 and the second pixel circuit 22 located in the second display area A2, which can be selected according to actual needs.

[0246] In some embodiments, such as Figure 10 As shown, the compression settings are configured in the second display area A2.

[0247] In some examples, such as Figure 10 As shown, the second display area A2 includes a regular area A21b and a compressed area A22b. A first pixel circuit group 21a is located in the compressed area A22b. A portion of the multiple second pixel circuits 22 are located in the regular area A21b, and another portion are located in the compressed area A22b. Furthermore, in the compressed area A22b, along the first direction X, at least one second pixel circuit 22 is disposed between two adjacent first pixel circuits 21. The width of the column region containing either the first pixel circuit 21 or the second pixel circuit 22 located in the compressed area A22b is smaller than the width of the column region containing the second pixel circuit 22 located in the regular area A21b.

[0248] For example, the width of the column region where the first pixel circuit 21 is located refers to the size of the area occupied by the pixel circuit column where the first pixel driving circuit 21 is located in the first direction X. The width of the column region where the second pixel circuit 22 is located refers to the size of the area occupied by the pixel circuit column where the second pixel driving circuit 22 is located in the first direction X.

[0249] The width of the column region where the first pixel circuit 21 or the second pixel circuit 22 is located in the compression region A22b is smaller than the width of the column region where the second pixel circuit 22 is located in the normal region A21b. This means that the width of the column region where the first pixel circuit 21 or the second pixel circuit 22 is located in the compression region A22b is compressed, while the width of the column region where the second pixel circuit 22 is located in the normal region A21b is not compressed.

[0250] By compressing the width of the column region where the first pixel circuit 21 or the second pixel circuit 22 is located in the compression region A22b, space can be freed up in the compression region A22b to accommodate the first pixel circuit 21.

[0251] In other embodiments, such as Figure 11 As shown, the second display area A2 is compressed as a whole. That is, in the first direction X, the width of the column area where the first pixel circuit 21 or the second pixel circuit 22 is located is compressed.

[0252] This allows for a greater placement space for the first pixel circuit 21, making it easier to place more first pixel circuits 21 in the second display area A2.

[0253] It should be noted that, Figure 9 , Figure 14 , Figure 15 and Figure 16 The virtual pixel circuit shown refers to an area occupied by a rectangular pattern where no pixel circuit is set, and the width of the rectangular pattern in the first direction X is the same as the width of the column area where the first pixel circuit 21 or the second pixel circuit 22 is located. This helps to improve the regularity of the arrangement of the second pixel circuit 22 and the regularity of the length variation of the lead 41.

[0254] Some embodiments of this disclosure provide a display device 1000. For example... Figure 18 and Figure 19 As shown, the display device 1000 includes: a display substrate 100 as described in any of the above embodiments, and an optical element 200 disposed on the non-light-emitting side of the display substrate 100. The optical element 200 is located in the first display area A1 of the display substrate 100.

[0255] In some examples, the optical element 200 described above may include a photosensitive device. For example, the photosensitive device may include an image acquisition device (e.g., a camera) or an infrared receiver.

[0256] Here, the number of optical elements 200 can be selected and set according to actual needs.

[0257] For example, after the optical element 200 is disposed in the first display area A1 and located on the non-light-emitting side of the display substrate 100, external light can pass through the portion of the display substrate 100 located in the first display area A1 and be incident on the optical element 200, so that the optical element 200 can work.

[0258] For example, when the optical element 200 is not working, the portion of the display substrate 100 located in the first display area A1 can be displayed, so that the display substrate 100 and the display device 1000 as a whole can display an image.

[0259] For example, when the optical element 200 (e.g., an image capture device) is working (e.g., a user taking a selfie), the first display area A1 can display a black screen, while the second display area A2 displays the selfie, clearly showing the location of the image capture device. Alternatively, both the first display area A1 and the second display area A2 can display the selfie without showing the location of the image capture device.

[0260] The beneficial effects that the display device 1000 provided in some embodiments of the present invention can achieve are the same as those that the display substrate 100 provided in some embodiments described above can achieve, and will not be repeated here.

[0261] In some examples, the display device 1000 may also include a frame, a circuit board disposed within the frame, a display driver IC (Integrated Circuit), and other electronic components.

[0262] In some embodiments, the display device 1000 described above can be any product or component with display and image acquisition functions, such as a mobile phone, tablet computer, laptop computer, personal computer, monitor, wearable device, etc.

[0263] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display substrate, characterized in that, The display substrate has a first display area and a second display area, wherein the second display area at least partially surrounds the first display area; the display substrate includes: A first light-emitting device group is disposed in the first display area, the first light-emitting device group includes N first light-emitting devices; along a first direction and pointing from the second display area to the first display area, the N first light-emitting devices are respectively the 1st to the Nth first light-emitting devices; A first pixel circuit group is provided in the second display area, and the first pixel circuit group includes N first pixel circuits; the first to Nth first pixel circuits are arranged sequentially in a direction away from the first display area; The lead group includes N leads arranged in parallel; the i-th first light-emitting device is electrically connected to the i-th first pixel circuit through the i-th lead, and the lengths of the 1st to Nth leads gradually increase; N > 2, and N is an integer, i = 1 to N; and, A plurality of second pixel circuits are disposed in the second display area, the plurality of second pixel circuits being arranged in multiple columns along the first direction and in multiple rows along the second direction; the first direction and the second direction intersect. Among them, at least one row of second pixel circuits or at least one column of second pixel circuits are provided between the first first light-emitting device and the first first pixel circuit; the N leads extend from the first display area, through the at least one row of second pixel circuits or the at least one column of second pixel circuits, to the second display area; The sequence formed by the lengths of the N leads in the first direction is an arithmetic sequence. Each lead forms a parasitic capacitance with the second pixel circuit and / or the first pixel circuit it passes through; the sequence of parasitic capacitance values ​​formed by the N leads is an arithmetic sequence.

2. The display substrate according to claim 1, characterized in that, The first light-emitting device group and the first pixel circuit group electrically connected to the first light-emitting device group are arranged in the same row along the first direction; At least one column of second pixel circuits is provided between the first first light-emitting device and the first first pixel circuit; The N leads extend from the first display area, along the first direction, through the at least one column of second pixel circuits, to the second display area.

3. The display substrate according to claim 2, characterized in that, The display substrate includes: a plurality of second light-emitting devices disposed in the second display area, at least one second light-emitting device being electrically connected to at least one second pixel circuit, and the orthographic projections of the at least one second light-emitting device and the at least one second pixel circuit on the plane of the display substrate at least partially overlap; The display substrate includes a plurality of pixel units, each pixel unit including three sub-pixels arranged along the first direction, and each sub-pixel including a second light-emitting device and a second pixel circuit electrically connected to each other. Among them, X second pixel circuits belonging to at least one pixel unit are arranged at intervals between the first first light-emitting device and the first first pixel circuit, where X is a multiple of 3.

4. The display substrate according to claim 2, characterized in that, The display substrate includes: a plurality of second light-emitting devices disposed in the second display area, at least one second light-emitting device being electrically connected to at least one second pixel circuit, and the orthographic projections of the at least one second light-emitting device and the at least one second pixel circuit on the plane of the display substrate at least partially overlap; The display substrate further includes multiple pixel units, each pixel unit includes multiple sub-pixels, and each sub-pixel includes a second light-emitting device and a second pixel circuit that are electrically connected; the multiple pixel units are arranged in a pentile arrangement. Among them, Y second pixel circuits belonging to at least one pixel unit are arranged at intervals between the first first light-emitting device and the first first pixel circuit, where Y is a multiple of 2.

5. The display substrate according to claim 1, characterized in that, The sequence formed by the resistance values ​​of the N leads is an arithmetic sequence.

6. The display substrate according to claim 1, characterized in that, The display substrate includes multiple rows of first light-emitting devices located in the first display area, and each row of first light-emitting devices is divided into two groups of first light-emitting devices located on both sides of a reference line; the reference line is a straight line extending along the second direction and passing through the first display area, and the second direction is perpendicular to the first direction; Two first pixel circuit groups electrically connected to the two first light-emitting device groups are respectively located on opposite sides of the first display area in the first direction; The two lead groups electrically connected to the two first light-emitting device groups are located on both sides of the reference line.

7. The display substrate according to claim 6, characterized in that, The two lead groups electrically connected to the two first light-emitting device groups are arranged symmetrically about the reference line.

8. The display substrate according to claim 6, characterized in that, The first display area has a center, and the reference line is a straight line passing through the center.

9. The display substrate according to claim 1, characterized in that, The first light-emitting device group and the first pixel circuit group electrically connected to the first light-emitting device group are arranged in the same row along the first direction; The display substrate further includes: a set of adapter holes; the set of adapter holes includes N adapter holes, the N adapter holes are arranged sequentially along the first direction, and each corresponds to one of the N first light-emitting devices; Along the second direction, the i-th lead electrically connected to the i-th first light-emitting device is closer to the adapter hole group than the i+1 lead electrically connected to the (i+1)-th first light-emitting device; the second direction is perpendicular to the first direction.

10. The display substrate according to claim 1, characterized in that, The first light-emitting device group and the first pixel circuit group electrically connected to the first light-emitting device group are arranged in the same row along the first direction; The display substrate further includes: a set of adapter holes; the set of adapter holes includes N adapter holes, the N adapter holes are arranged sequentially along the first direction, and each corresponds to one of the N first light-emitting devices; The i-th lead electrically connected to the i-th first light-emitting device and the i+1-th lead electrically connected to the (i+1)-th first light-emitting device are respectively located on opposite sides of the adapter hole group in the second direction; the second direction is perpendicular to the first direction.

11. The display substrate according to claim 1, characterized in that, The display substrate includes: Substrate; A pixel circuit layer is disposed on the substrate, wherein the first pixel circuit group and the plurality of second pixel circuits are located in the pixel circuit layer; A light-emitting device layer disposed on the side of the pixel circuit layer away from the substrate, wherein the first light-emitting device group is located in the light-emitting device layer; and... Multiple lead layers are disposed between the pixel circuit layer and the light-emitting device layer, wherein the material of the multiple lead layers includes a light-transmitting conductive material; The N leads of the lead group are located in the plurality of lead layers.

12. The display substrate according to claim 11, characterized in that, The number of the plurality of lead layers is two; Of the N leads, the first to the Nth leads are alternately located in two lead layers.

13. The display substrate according to claim 1, characterized in that, In the N leads, the length ratio of the Nth lead to the first lead is α, where α ≤ 25.

14. The display substrate according to claim 13, characterized in that, The length ratio α satisfies that α≤15.

15. The display substrate according to claim 1, characterized in that, The number of rows or columns of the second pixel circuit that is spaced between the first light-emitting device and the first pixel circuit is β, where β≤30.

16. The display substrate according to claim 1, characterized in that, The ratio of the number of rows or columns of pixel circuits spaced apart between the Nth first light-emitting device and the Nth first pixel circuit to the number of rows or columns of second pixel circuits spaced apart between the 1st first light-emitting device and the 1st first pixel circuit is γ, where 5≤γ≤50.

17. The display substrate according to any one of claims 1 to 16, characterized in that, The second display area includes a regular area and a compressed area; the first pixel circuit group is located in the compressed area, a portion of the multiple second pixel circuits are located in the regular area, and another portion of the second pixel circuits are located in the compressed area, and in the compressed area, at least one second pixel circuit is disposed between two adjacent first pixel circuits along the first direction; The width of the column region where the first pixel circuit or the second pixel circuit is located in the compressed region is smaller than the width of the column region where the second pixel circuit is located in the normal region.

18. A display device, characterized in that, The display device includes: The display substrate as claimed in any one of claims 1 to 17; and, An optical element disposed on the non-light-emitting side of the display substrate, the optical element being located in the first display area of ​​the display substrate.

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