Communication method and system based on multi-partition independent cache of FC device

Abstract

The application provides a communication method and system based on multi-partition independent cache of FC equipment, which comprises an FPGA arranged in the FC equipment and a DDR connected with the FPGA. The FPGA is used to realize data communication between the FC equipment and a target cache partition of a peer device. The data flow direction of the target cache partition to the peer device is a sending direction, and vice versa. In the data flow receiving direction, the FPGA receives an IU and stores the IU in a small queue mode by default, divides the IU according to the size of a dma_buffer, pushes the IU into a corresponding block in the DDR for storage, and reads out the IU when a condition is met; the FPGA switches to a large queue mode for storage when the condition is met, stores the IU in the same block used by the large queue in the DDR by splicing, and reads out the data stored in the block by using an aging timeout report. The communication method can fully improve the buffer use efficiency, dynamically adjust the number of DDR storage blocks, dynamically solve the multi-channel concurrency problem, and improve the overall system performance.

Description

Technical Field

[0001] This invention relates to the field of FC (Fibre Channel) network technology, and more specifically to a communication method and system based on multi-partition independent buffering of FC devices. Background Technology

[0002] Airborne data bus technology is used for interconnection between airborne equipment, subsystems, and modules. From a computer perspective, various avionics devices are equivalent to microcomputers, and bus communication technology is the channel and link connecting these microcomputers, enabling avionics equipment to form a fully functional network. FC (Fibre Channel) is a channel standard proposed by the American Industrial Standards Institute (ANSI) in 1988, designed to meet the growing demand for high-speed data channels within aerospace vehicles. FC serial transmission rates can reach 133 Mbps to 1.0625 Gbps, and it is currently the main implementation method for airborne avionics system communication networks, achieving high-speed airborne communication requirements.

[0003] FC (Fibre Channel) is a standards-based network architecture that offers the dual advantages of both channel and network capabilities. It allows the operation of mainstream channel standards and network protocols on a single physical interface. Its massive data throughput enables large-scale data transmission between different onboard systems and allows the use of the same equipment to establish any topology, meeting various connection requirements such as point-to-point communication networks, arbitration ring communication networks, and switched networks, thus achieving high-speed communication between node devices.

[0004] In an FC (Fibre Channel) communication topology, node devices are typically configured with one or more Fibre Channel ports (FC ports). Node devices can connect to the host via a PCIe interface to communicate and send / receive messages, such as sending service messages to the host, receiving configuration information from the host for the node devices (including FPGAs, DDR storage, optical signal processing, etc.), and connecting the host to the FC topology network via the FC port.

[0005] FPGA chips are key components in node devices for enabling node communication, and their performance directly affects whether the communicating parties can connect and communicate normally. In the increasingly complex application environments of modern airborne equipment, airborne communication topologies are becoming more complex, and the amount of data transmitted in the network is growing exponentially, especially given the dynamic and concurrent transmission characteristics. How to improve the overall performance of node devices in the FC network, maximize their role in the FC network, and improve data processing efficiency are key issues that current airborne avionics FC network communication systems need to address. Summary of the Invention

[0006] The first aspect of this invention is to propose a communication method based on multi-partition independent buffers in an FC device, comprising the following steps:

[0007] After the FPGA of the FC device is powered on, the register submodule of the RX_TOP module divides the DDR connected to the FPGA into blocks. Within the DDR, buffer areas are divided for large queues, small queues, and dynamic scheduling. The size of each block is the same as the dma_buffer size of the destination buffer partition, and the base address of each block is stored in the FPGA's FIFO queue. When data enters the DDR for storage, a base address is read out for use. After a block of data is read from the DDR, the base address is released back into the FIFO queue for subsequent cyclic use. The total size of the buffer areas used for large queues, small queues, and dynamic scheduling is less than or equal to the capacity of the DDR.

[0008] In the data flow transmission direction from the destination buffer partition to the peer device, the data is stored in the destination buffer partition according to four priorities pri0 to pri3. The data is stored in the dma_buffer of the destination buffer partition. When a partition sends data, the dma_buffer data of the corresponding priority of the corresponding partition is pushed to the DMA_TOP module of the FPGA. The DMA_TOP module parses the data into raw data and adds the corresponding descriptor, and pushes it to the TX_TOP module of the FPGA. The TX_TOP module assembles and packages the received data into a data frame that conforms to the FC frame protocol, and finally sends it to the peer device through the FC_MAC module of the FPGA.

[0009] In the data stream receiving direction from the peer device to the destination buffer partition, the data sent from the peer device flows in through the FPGA's FC_MAC module, is parsed into raw data by the FPGA's RX_TOP module, and then stored in the DDR connected to the FPGA according to either a large queue mode or a small queue mode. Furthermore, when the receiving direction meets the conditions for initiating DMA, the FPGA's RX_TOP module reads the data from the DDR and sends it to the FPGA's DMA_TOP module, and finally sends the data to the corresponding priority dma_buffer of the destination buffer partition via DMA.

[0010] In the data stream receiving direction, after the FPGA receives the IU, it buffers it in a small queue mode by default. The IU is then segmented according to the size of the dma_buffer and pushed into the corresponding block in the DDR for buffering. It is then read out when certain conditions are met.

[0011] Under predetermined conditions, the control switches to the large queue mode for caching. In DDR, IUs are cached in the same block used for large queue caching by splicing. If the memory of the block is still not full after a predetermined time period and no new IUs are received, an aging timeout report is made, and the data stored in the block is read out.

[0012] In an optional embodiment, when caching in large queue mode, IUs of different channels with the same priority under the same partition are concatenated into the same block of DDR using a splicing method.

[0013] In an optional embodiment, in unicast mode, if the received IU contains data from multiple frames, the default small queue mode is used for caching. The received IU is divided according to the size of dma_buffer and pushed to the blocks divided in DDR for caching. When the eop mark in the IU is detected, it is read out. If no new data is received in the block after a predetermined time period, a timeout mechanism is triggered, the contents of the block are read out and pushed to the DMA_TOP module for DMA. The read data is sent to the dma_buffer of the corresponding priority of the destination cache partition through DMA.

[0014] In an optional embodiment, in multicast mode, if the received IU contains data from multiple frames, the default small queue mode is used for caching. The IU is divided according to the size of dma_buffer and pushed to the corresponding block in DDR for caching. After reading the data from DDR, the DMA_TOP module completes the copying of one set of data into multiple sets and sends them to different destination cache partitions.

[0015] In an optional embodiment, if the received IU contains only one frame of data, the received IU is buffered by switching from the default small queue mode to the large queue mode.

[0016] In an optional embodiment, when all blocks in the buffer area used for small queues are occupied, when a new IU is received, the FPGA controls and adjusts the blocks in the dynamic scheduling buffer area for subsequent IUs to be cached and stored.

[0017] In an optional embodiment, when the FPGA partitions DDR into blocks, it sets an occupancy threshold for blocks in the buffer area used by the small queue. If the number of blocks used in the buffer area used by the small queue reaches the occupancy threshold, dynamic scheduling of blocks in the buffer area is enabled to replenish them for subsequent IUs to cache and store.

[0018] When the number of blocks used in the buffer area for small queues falls below the set release threshold, the newly added blocks will be released and recycled to the dynamic scheduling buffer area.

[0019] According to a second aspect of the present invention, a communication system based on a multi-partition independent buffer of an FC device is also proposed, comprising:

[0020] The FPGA is installed in the FC device, and the FPGA enables data communication and transmission between the FC device and the target cache partition.

[0021] DDR connected to the FPGA;

[0022] The FPGA configuration includes a DMA_TOP module, a TX_TOP module, an RX_TOP module, and an FC_MAC module. The DMA_TOP module is used for DMA direct memory access processing. The TX_TOP module is used to package the data sent by the DMA_TOP module into frames conforming to the FC protocol and send them to the peer device through the FC_MAC module. At the same time, the FC_MAC module receives the data sent by the peer device, parses it, and sends it to the RX_TOP module. The RX_TOP module controls the DDR to perform data buffer storage, and when a predetermined condition is met, it reads the data in the DDR and sends it to the DMA_TOP module. Then, the data is sent to the dma_buffer of the corresponding priority of the destination buffer partition via DMA.

[0023] In this FC device, after power-on, the FPGA divides the DDR into blocks in the register submodule of its internal RX_TOP module. The DDR is divided into buffer areas for large queues, small queues, and dynamic scheduling. The size of each block is the same as the dma_buffer size of the destination buffer partition, and the base address of each block is stored in the FPGA's FIFO queue. When data enters the DDR for storage, a base address is read out for use. After a block of data is read from the DDR, the base address is released back into the FIFO queue for subsequent cyclic use. The total size of the buffer areas used for large queues, small queues, and dynamic scheduling is less than or equal to the capacity of the DDR.

[0024] In the data flow transmission direction from the destination buffer partition to the peer device, the data is stored in the destination buffer partition according to four priorities pri0 to pri3. The data is stored in the dma_buffer of the destination buffer partition. When a partition sends data, the dma_buffer data of the corresponding priority of the corresponding partition is pushed to the DMA_TOP module of the FPGA. The DMA_TOP module parses the data into raw data and adds the corresponding descriptor, and pushes it to the TX_TOP module of the FPGA. The TX_TOP module assembles and packages the received data into a data frame that conforms to the FC frame protocol, and finally sends it to the peer device through the FC_MAC module of the FPGA.

[0025] In the data stream receiving direction from the peer device to the destination buffer partition, the data sent from the peer device flows in through the FPGA's FC_MAC module, is parsed into raw data by the FPGA's RX_TOP module, and then stored in the DDR connected to the FPGA according to either a large queue mode or a small queue mode. Furthermore, when the receiving direction meets the conditions for initiating DMA, the FPGA's RX_TOP module reads the data from the DDR and sends it to the FPGA's DMA_TOP module, and finally sends the data to the corresponding priority dma_buffer of the destination buffer partition via DMA.

[0026] In the data stream receiving direction, after the FPGA receives the IU, it buffers it in a small queue mode by default. The IU is then segmented according to the size of the dma_buffer and pushed into the corresponding block in the DDR for buffering. It is then read out when certain conditions are met.

[0027] Under predetermined conditions, the control switches to the large queue mode for caching. In DDR, IUs are cached in the same block used for large queue caching by splicing. If the memory of the block is still not full after a predetermined time period and no new IUs are received, an aging timeout report is made, and the data stored in the block is read out.

[0028] As an optional embodiment, the RX_TOP module is configured with a register submodule, a write control module, and a read control module. The write control module is divided into two submodules: a large queue write module and a small queue write module, which are used for write operations in large queue mode and small queue mode, respectively.

[0029] When the IU flows from the FC_MAC module into the RX_TOP module, the RX_TOP module first completes the frame parsing, parsing the IU into the raw data of the frame and the corresponding frame descriptor;

[0030] The write control module determines whether the data frame belongs to the large queue or the small queue based on the descriptor, and enters the large queue write module or the small queue write module accordingly. At the same time, it reads the allocated DDR block address from the memory submodule, writes the IU data into the DDR block, and writes the data frame descriptor into the register submodule for storage.

[0031] When the read control module detects that there is descriptor storage information in the register submodule, it starts reading the descriptor information, reads the contents of the DDR block according to the descriptor information, and sends the data to the next-level DMA_TOP module. After reading a block, the read control module releases the address of the DDR block back to the register submodule for subsequent cyclic use.

[0032] Specifically, after the FC_MAC module receives an IU, it defaults to using a small queue mode for caching. The IU is split and pushed into the corresponding block in DDR for caching according to the size of dma_buffer, and read out when conditions are met. Under predetermined conditions, it controls the switch to a large queue mode for caching. In DDR, IUs are cached in the same block used for large queue caching by concatenation. If the memory of the block is not full after a predetermined time period and no new IU is received, an aging timeout is reported, and the data stored in the block is read out. In the large queue mode, IUs from different channels with the same priority under the same partition are concatenated in the same block of DDR by concatenation.

[0033] As an optional implementation, if the received IU contains only one frame of data, the received IU is buffered by switching from the default small queue mode to the large queue mode.

[0034] Based on the above technical solutions of this invention, the proposed method for multi-partition big-small queue communication in FC devices utilizes a big-small queue data processing mode within the FPGA of the FC device, thereby enhancing the system's data processing capabilities. External DDR storage is employed to save internal FPGA resources, adapting to different transmission scenarios and improving system data processing efficiency. Furthermore, building upon multi-partition communication in FC devices, this invention segments data packets within the FPGA and selects a big-small queue mode, which on the one hand significantly improves buffer utilization efficiency, and on the other hand dynamically addresses multi-channel concurrency issues, thus enhancing overall system performance.

[0035] It should be understood that all combinations of the foregoing concepts and the additional concepts described in more detail below may be considered part of the inventive subject matter of this disclosure, provided that such concepts do not contradict each other. Furthermore, all combinations of the claimed subject matter are considered part of the inventive subject matter of this disclosure.

[0036] The foregoing and other aspects, embodiments, and features of the teachings of the present invention will be more fully understood from the following description in conjunction with the accompanying drawings. Other additional aspects of the invention, such as features and / or beneficial effects of exemplary embodiments, will become apparent from the following description or may be learned through practice of specific embodiments according to the teachings of the present invention. Attached Figure Description

[0037] The accompanying drawings are not intended to be drawn to scale. In the drawings, each identical or nearly identical component shown in the various figures may be denoted by the same reference numeral. For clarity, not every component is labeled in each figure. Embodiments of various aspects of the invention will now be described by way of example and with reference to the accompanying drawings.

[0038] Figure 1 This is a system block diagram of a communication system based on multi-partition independent caching of FC devices according to an embodiment of the present invention.

[0039] Figure 2 This is a schematic diagram of the small queue mode data storage method according to an embodiment of the present invention.

[0040] Figure 3 This is a schematic diagram of the large queue mode data storage method according to an embodiment of the present invention.

[0041] Figure 4 This is a flowchart of the small queue data writing process according to an embodiment of the present invention.

[0042] Figure 5 This is a flowchart of the large queue data writing process according to an embodiment of the present invention.

[0043] Figure 6 This is a flowchart of the data reading process according to an embodiment of the present invention. Detailed Implementation

[0044] To better understand the technical content of the present invention, specific embodiments are described below in conjunction with the accompanying drawings.

[0045] Various aspects of the invention are described in this disclosure with reference to the accompanying drawings, which illustrate numerous illustrative embodiments. The embodiments of this disclosure are not necessarily intended to encompass all aspects of the invention. It should be understood that the various concepts and embodiments described above, as well as those described in more detail below, can be implemented in any of many ways, because the concepts and embodiments disclosed herein are not limited to any particular implementation. Furthermore, some aspects of the invention disclosed may be used alone or in any suitable combination with other aspects of the invention disclosed.

[0046] Combination Figure 1 , 2The communication system based on multi-partition independent cache of an FC device, as shown in example 3, includes an FPGA (Field Programmable Gate Array) located within the FC device and a DDR (Double Data Rate Synchronous Dynamic Random Access Memory, a type of memory) connected to the FPGA. The FPGA located within the FC device enables data communication and transmission between the FC device and the target cache partition.

[0047] In embodiments of the present invention, FC devices particularly refer to FC switches.

[0048] like Figure 1 The direction of data flow from the destination cache partition to the other end is the sending direction, and the opposite direction is the receiving direction. We will use the sending and receiving of data flows to explain the relationship, connection and state changes between the modules.

[0049] Combination Figure 1 As shown, the FPGA configuration includes a DMA_TOP module, a TX_TOP module, an RX_TOP module, and an FC_MAC module. The DMA_TOP module is used for DMA direct memory access processing. The TX_TOP module is used to package the data sent by the DMA_TOP module into frames conforming to the FC protocol and send them to the peer device through the FC_MAC module. At the same time, the FC_MAC module receives the data sent by the peer device, parses it, and sends it to the RX_TOP module. The RX_TOP module controls the DDR to perform data buffer storage, and when a predetermined condition is met, it reads the data in the DDR and sends it to the DMA_TOP module. Finally, the data is sent to the dma_buffer of the corresponding priority in the destination buffer partition via DMA.

[0050] In the data flow transmission direction from the destination buffer partition to the peer device, data is stored within the destination buffer partition according to four priorities pri0 to pri3. The data is stored in the dma_buffer of the destination buffer partition. When a partition sends data, the dma_buffer data of the corresponding priority of the corresponding partition is pushed to the DMA_TOP module of the FPGA. The DMA_TOP module parses the data into raw data and adds the corresponding descriptor, and pushes it to the TX_TOP module of the FPGA. The TX_TOP module assembles and packages the received data into data frames that conform to the FC frame protocol, and finally sends them to the peer device through the FC_MAC module of the FPGA.

[0051] In the data flow receiving direction from the peer device to the destination buffer partition, the data sent from the peer device flows in through the FPGA's FC_MAC module, is parsed into raw data by the FPGA's RX_TOP module, and then stored in the DDR connected to the FPGA according to either a large queue mode or a small queue mode. Furthermore, when the receiving direction meets the conditions for initiating DMA, the FPGA's RX_TOP module reads the data from the DDR and sends it to the FPGA's DMA_TOP module, and finally sends the data to the corresponding priority dma_buffer of the destination buffer partition via DMA.

[0052] In the data stream receiving direction, after the FPGA receives the IU, it buffers it by default in a small queue mode. The IU is segmented according to the size of the dma_buffer and pushed into the corresponding block in the DDR for buffering, and then read out when conditions are met; and

[0053] Under predetermined conditions, the control switches to the large queue mode for caching. In DDR, IUs are cached in the same block used for large queue caching by splicing. If the memory of the block is still not full after a predetermined time period and no new IUs are received, an aging timeout report is made, and the data stored in the block is read out.

[0054] The communication method designed in this invention is multi-partition transmission and reception. Therefore, multiple buffer partitions will receive data in the receiving direction. Each buffer partition will allocate a fixed-size dma_buffer and push the corresponding dma buffer address to the FPGA. Thus, after the FPGA receives the IU (Information Unit) data information, it will divide the IU according to the size of the dma_buffer and then upload a complete IU in multiple parts. The destination buffer partition will receive multiple dma_buffers storing data and then concatenate them into a complete IU.

[0055] Combination Figure 1 The example shown has a register submodule, a write control module, and a read control module. The write control module is divided into two submodules: a large queue write module and a small queue write module, which are used for write operations in large queue mode and small queue mode, respectively.

[0056] When the IU flows from the FC_MAC module into the RX_TOP module, the RX_TOP module first completes the frame parsing, parsing the IU into the raw data of the frame and the corresponding frame descriptor.

[0057] The write control module determines whether the data frame belongs to the large queue or the small queue based on the descriptor, and enters the large queue write module or the small queue write module accordingly. At the same time, it reads the allocated DDR block address from the memory submodule, writes the IU data into the DDR block, and writes the data frame descriptor into the register submodule for storage.

[0058] When the read control module detects that there is descriptor storage information in the register submodule, it starts reading the descriptor information, reads the contents of the DDR block according to the descriptor information, and sends the data to the next-level DMA_TOP module. After reading a block, the read control module releases the address of the DDR block back to the register submodule for subsequent cyclic use.

[0059] In this module, after the FC_MAC module receives an IU, it defaults to using a small queue mode for caching. The IU is split and pushed into the corresponding block in DDR for caching according to the size of dma_buffer, and read out when conditions are met. Under predetermined conditions, it switches to a large queue mode for caching. In DDR, the IU is cached in the same block used for large queue caching by concatenation. If the block is not full after a predetermined time period and no new IU is received, an aging timeout is reported, and the data stored in the block is read out. In the large queue mode, IUs from different channels with the same priority under the same partition are concatenated into the same block in DDR by concatenation.

[0060] In an embodiment of the present invention, the received IU is judged based on the data received. If the received IU contains only one frame of data, the received IU is buffered by switching from the default small queue mode to the large queue mode.

[0061] In the large queue mode, when caching, IUs of different channels with the same priority under the same partition are concatenated into the same block of DDR using a splicing method.

[0062] As an optional embodiment, in unicast mode, if the received IU contains data from multiple frames, the default small queue mode is used for buffering. The received IU is divided according to the size of dma_buffer and pushed to the blocks divided in DDR for buffering. When the eop mark in the IU is detected, it is read out. If no new data is received in the block after a predetermined time period, a timeout mechanism is triggered, the contents of the block are read out and pushed to the DMA_TOP module for DMA. The read data is sent to the dma_buffer of the corresponding priority in the destination buffer partition through DMA.

[0063] As an optional embodiment, in multicast mode, if the received IU contains data from multiple frames, the default small queue mode is used for caching. The IU is divided according to the size of dma_buffer and pushed to the corresponding block in DDR for caching. After reading the data from DDR, the DMA_TOP module completes the copying of one set of data into multiple sets and sends them to different destination cache partitions.

[0064] As an optional implementation, if the received IU contains only one frame of data, the received IU is buffered by switching from the default small queue mode to the large queue mode.

[0065] Furthermore, once all blocks in the buffer used for small queues are occupied, when a new IU is received, the FPGA controls and adjusts the blocks in the dynamic scheduling buffer to be cached and stored for subsequent incoming IUs.

[0066] When the FPGA partitions DDR into blocks, it sets a threshold for the number of blocks in the buffer area used by the small queue. If the number of blocks in the buffer area used by the small queue reaches the threshold, it enables dynamic scheduling of blocks in the buffer area to replenish them for subsequent IUs to cache and store.

[0067] When the number of blocks used in the buffer area for small queues falls below the set release threshold, the newly added blocks will be released and recycled to the dynamic scheduling buffer area.

[0068] We will now provide further explanation with specific examples.

[0069] In an embodiment of the present invention, after the FPGA of the FC device is powered on, the DDR is divided into blocks in the register submodule of the RX_TOP module inside the FPGA. The DDR is divided into buffer areas for large queues, small queues and dynamic scheduling respectively. The size of each block is the same as the size of the dma_buffer of the destination buffer partition, and the base address of each block is stored in the FIFO queue of the FPGA. When data enters the DDR for storage, a base address is read out for use. After a block of data is read from the DDR, the base address is released back into the FIFO queue for subsequent cyclic use. The total size of the buffer area used for large queue buffer, small queue buffer and dynamic scheduling is less than or equal to the capacity of the DDR.

[0070] Combination Figure 1 , 2 As shown in the example in Figure 3, the DDR memory is first divided into three parts: the first part is used by the small queue, the second part is used by the large queue, and the third part is used for dynamic scheduling.

[0071] After the system powers on, the FPGA divides the DDR into three blocks in the register submodule of the RX_TOP module. The size of each block is the same as the size of the dma_buffer. During initialization, it is assumed that the FPGA will allocate A blocks (A1~An), B blocks (B1~Bn), and C blocks (C1~Cn) to the three parts, and their total capacity is less than or equal to the capacity of the DDR. The base address of each block is stored in the FPGA's FIFO. When data enters the DDR for storage, an address is read out for use. After reading a block of data from the DDR, the address is released back into the corresponding FIFO for subsequent cyclic use.

[0072] 1. Small queue storage method (default method)

[0073] 1.1 Unicast: In the embodiments of the present invention, the small queue storage method is proposed for the case where one IU contains multiple frames. The storage method of the small queue in DDR is as follows: Figure 2 As shown, the data writing process flowchart is as follows: Figure 4 As shown, when a unicast is initiated, that is, when the data of a channel is only sent to one partition, the IU is split and stored according to the size of the DDR block (i.e. the size of the dma_buffer).

[0074] For example, assuming the IU size occupies three blocks A1 to A3, normally, when the eop marker of the IU is detected, it indicates the end of an IU, and the read control module will proceed accordingly. Figure 6 The process reads data.

[0075] For example, if data in IU is stored in block A2, but half of the capacity of block A2 is occupied by the stored data, and subsequent data is stored for an extended period of time, thus triggering a timeout mechanism, then the data in A1 and A2 will be read out first for DMA reporting, and after receiving subsequent IU data, it will continue to be stored in A3 and A4.

[0076] If, under the default small queue storage mode, an IU sent from the peer device contains only one frame, then this one frame will occupy a block of part A for reporting, resulting in very low storage space utilization. Therefore, the controlled switch can be turned on to enable a large queue for caching.

[0077] 1.2 Multicast

[0078] When initiating a multicast, the data writing process in DDR is the same as that in unicast. However, after reading data from DDR, the DMA_TOP module will copy one set of data into multiple copies and then send them to different destination cache partitions.

[0079] 1.3 Multi-channel concurrency

[0080] Suppose that each block in A1 to An can store 32 frames. However, at this time, data from n channels is received concurrently, and each channel only receives one frame. Therefore, each block in A1 to An is occupied because each block can only store data from the same channel. If the (n+1)th channel arrives, the blocks in part A have been used up and have not been released back to available addresses. In this case, the blocks in part C (used for dynamic scheduling) need to be adjusted to supplement the blocks for subsequent use.

[0081] In an optional embodiment, the FPGA can supplement and release blocks in part A by setting thresholds. When dividing DDR into blocks, a threshold is set for the occupancy of blocks in the buffer area used by the small queue. If the number of blocks used in the buffer area used by the small queue reaches the occupancy threshold, blocks in the dynamic scheduling buffer area are supplemented for subsequent IUs to cache and store. And when the number of blocks used in the buffer area used by the small queue is lower than the set release threshold, the supplemented blocks are released and returned to the dynamic scheduling buffer area.

[0082] For example, when the number of blocks used in part A exceeds the occupancy threshold, blocks in part C are used to replenish blocks in part A. When the number of blocks used in part A falls below the release threshold, the blocks replenished in part C are released back into part C.

[0083] It should be understood that if no blocks are added to part A from part C, then block reclamation is not required even if the number of blocks used in part A is below the release threshold.

[0084] In some embodiments, when there are no available blocks in part C to supplement part A, and new received data frames require new blocks for storage, the user can configure the process, for example, clearing all (or some) blocks in the DDR to store the newly received data, or directly discarding all subsequent newly received data until there is space available for storage.

[0085] 2. Large queue mode (requires user activation)

[0086] In an embodiment of the present invention, the large queue mode is proposed for the case where an IU contains only one frame.

[0087] In the data stream receiving direction, after the FPGA receives an IU, it defaults to buffering in small queue mode. The IU is divided and pushed into the corresponding block in DDR for buffering according to the size of dma_buffer, and read out when the conditions are met. If the received IU contains only one frame of data, the default small queue mode is switched to large queue mode to buffer the received IU. In DDR, the IU is buffered in the same block used for large queue buffering by splicing. If the memory of the block is still not full after a predetermined time period and no new IU is received, an aging timeout is reported and the data stored in the block is read out.

[0088] 2.1 The write data processing flow in the large queue mode is as follows: Figure 5 As shown, different channels of IU with the same priority under the same partition are spliced ​​together in DDR in a DDR block. When the memory of the block is not full for a long time and no new data is received, an aging timeout is reported and the contents of the block are read out.

[0089] For example, when the large queue mode is started, since the received IUs are all single frames, if the small queue method is still used, it would be wasteful to store only one frame of data in a DDR block, resulting in low resource utilization. Therefore, in the embodiments of this invention, for a single priority data of a single destination partition, one IU (containing only one frame) of data is entered into the DDR and copied to the corresponding DDR block cache according to the destination partition and priority for storage. When the block is full of data, DMA is initiated to report the data. If a portion of the data is stored in the DDR block but no new data is received within a specified time, then after the specified time has elapsed, the data stored in the DDR block is directly read out and DMA is performed for reporting. The reading process is as follows: Figure 6 As shown.

[0090] 2.2 Under the large queue, for unicast, the data is directly placed into the block of the corresponding partition. For multicast, a copy of the data is placed into the blocks corresponding to the two partitions. In addition, if there are not enough DDR blocks, the handling method is the same as that of the small queue: the data is retrieved from part C to supplement the blocks, and the supplemented blocks are released when the conditions are met.

[0091] Therefore, the proposed multi-partition big-small queue communication method for FC devices utilizes a big-small queue data processing approach within the FPGA to enhance system data processing capabilities. It employs external DDR storage to conserve FPGA resources, adapts to different transmission scenarios, and improves system data processing efficiency. Furthermore, based on multi-partition communication in FC devices, by segmenting data packets within the FPGA and combining this with big-small queue storage for write operations, it significantly improves buffer utilization efficiency and dynamically adjusts the number of adaptive DDR storage blocks. This dynamically addresses multi-channel concurrency issues and data caching problems under concurrent channels, thereby improving overall system performance.

[0092] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A communication method based on multi-partition independent buffering of FC devices, characterized in that, Includes the following steps: After the FPGA of the FC device is powered on, the register submodule of the RX_TOP module divides the DDR connected to the FPGA into blocks. Within the DDR, buffer areas are divided for large queues, small queues, and dynamic scheduling. The size of each block is the same as the dma_buffer size of the destination buffer partition, and the base address of each block is stored in the FPGA's FIFO queue. When data enters the DDR for storage, a base address is read out for use. After a block of data is read from the DDR, the base address is released back into the FIFO queue for subsequent cyclic use. The total size of the buffer areas used for large queues, small queues, and dynamic scheduling is less than or equal to the capacity of the DDR. In the data flow transmission direction from the destination buffer partition to the peer device, the data is stored in the destination buffer partition according to four priorities pri0~pri3. The data is stored in the dma_buffer of the destination buffer partition. When a partition sends data, the dma_buffer data of the corresponding priority of the corresponding partition is pushed to the DMA_TOP module of the FPGA. The DMA_TOP module parses the data into raw data and adds the corresponding descriptor, and pushes it to the TX_TOP module of the FPGA. The TX_TOP module assembles and packages the received data into a data frame that conforms to the FC frame protocol, and finally sends it to the peer device through the FC_MAC module of the FPGA. In the data stream receiving direction from the peer device to the destination buffer partition, the data sent from the peer device flows in through the FPGA's FC_MAC module, is parsed into raw data by the FPGA's RX_TOP module, and then stored in the DDR connected to the FPGA according to the large queue mode or small queue mode. Furthermore, when the receiving direction meets the conditions for initiating DMA, the FPGA's RX_TOP module reads the data from the DDR and sends it to the FPGA's DMA_TOP module, and finally sends the data to the corresponding priority dma_buffer of the destination buffer partition through DMA. In the data stream receiving direction, after the FPGA receives the IU, it buffers it in a small queue mode by default. The IU is then segmented according to the size of the dma_buffer and pushed into the corresponding block in the DDR for buffering. It is then read out when certain conditions are met. Under predetermined conditions, the control switches to the large queue mode for caching. In DDR, IUs are cached in the same block used for large queue caching by splicing. If the memory of the block is still not full after a predetermined time period and no new IUs are received, an aging timeout report is made, and the data stored in the block is read out. When all blocks in the buffer area used for small queues are occupied, when a new IU is received, the FPGA controls and adjusts the blocks in the dynamic scheduling buffer area for subsequent IUs to cache and store. Furthermore, when the FPGA partitions DDR into blocks, it sets a threshold for the number of blocks in the buffer area used by the small queue. If the number of blocks used in the buffer area used by the small queue reaches the threshold, it enables dynamic scheduling of blocks in the buffer area to replenish them for subsequent IUs to cache and store. When the number of blocks used in the buffer area for small queues falls below the set release threshold, the newly added blocks will be released and recycled to the dynamic scheduling buffer area.

2. The communication method based on multi-partition independent buffering of FC devices according to claim 1, characterized in that, When caching in large queue mode, IUs of different channels with the same priority under the same partition are concatenated into the same block of DDR using a splicing method.

3. The communication method based on multi-partition independent buffering of FC devices according to claim 1, characterized in that, In unicast mode, if the received IU contains data from multiple frames, the default small queue mode is used for buffering. The received IU is divided according to the size of dma_buffer and pushed into the blocks allocated in DDR for buffering. When the eop mark in the IU is detected, it is read out. If no new data is received in the block after a predetermined time period, the timeout mechanism is triggered, the contents of the block are read out and pushed to the DMA_TOP module for DMA. The read data is sent to the dma_buffer of the corresponding priority in the destination buffer partition via DMA.

4. The communication method based on multi-partition independent buffering of FC devices according to claim 3, characterized in that, In multicast mode, if the received IU contains data from multiple frames, the default small queue mode is used for buffering. The IU is divided according to the size of dma_buffer and pushed to the corresponding block in DDR for buffering. After reading the data from DDR, the DMA_TOP module completes the copying of one set of data into multiple sets and sends them to different destination buffer partitions.

5. The communication method based on multi-partition independent buffering of FC devices according to any one of claims 1-4, characterized in that, If the received IU contains only one frame of data, the system switches from the default small queue mode to the large queue mode to buffer the received IU.

6. A communication system based on multi-partition independent buffering of FC devices, characterized in that, include: The FPGA is installed in the FC device, and the FPGA enables data communication and transmission between the FC device and the destination buffer partition. DDR connected to the FPGA; The FPGA configuration includes a DMA_TOP module, a TX_TOP module, an RX_TOP module, and an FC_MAC module. The DMA_TOP module is used for DMA direct memory access processing. The TX_TOP module is used to package the data sent by the DMA_TOP module into frames conforming to the FC protocol and send them to the peer device through the FC_MAC module. At the same time, the FC_MAC module receives the data sent by the peer device, parses it, and sends it to the RX_TOP module. The RX_TOP module controls the DDR to perform data buffer storage, and when a predetermined condition is met, it reads the data in the DDR and sends it to the DMA_TOP module. Then, the data is sent to the dma_buffer of the corresponding priority of the destination buffer partition via DMA. In this FC device, after power-on, the FPGA divides the DDR into blocks in the register submodule of its internal RX_TOP module. The DDR is divided into buffer areas for large queues, small queues, and dynamic scheduling. The size of each block is the same as the dma_buffer size of the destination buffer partition, and the base address of each block is stored in the FPGA's FIFO queue. When data enters the DDR for storage, a base address is read out for use. After a block of data is read from the DDR, the base address is released back into the FIFO queue for subsequent cyclic use. The total size of the buffer areas used for large queues, small queues, and dynamic scheduling is less than or equal to the capacity of the DDR. In the data flow transmission direction from the destination buffer partition to the peer device, the data is stored in the destination buffer partition according to four priorities pri0~pri3. The data is stored in the dma_buffer of the destination buffer partition. When a partition sends data, the dma_buffer data of the corresponding priority of the corresponding partition is pushed to the DMA_TOP module of the FPGA. The DMA_TOP module parses the data into raw data and adds the corresponding descriptor, and pushes it to the TX_TOP module of the FPGA. The TX_TOP module assembles and packages the received data into a data frame that conforms to the FC frame protocol, and finally sends it to the peer device through the FC_MAC module of the FPGA. In the data stream receiving direction from the peer device to the destination buffer partition, the data sent from the peer device flows in through the FPGA's FC_MAC module, is parsed into raw data by the FPGA's RX_TOP module, and then stored in the DDR connected to the FPGA according to the large queue mode or small queue mode. Furthermore, when the receiving direction meets the conditions for initiating DMA, the FPGA's RX_TOP module reads the data from the DDR and sends it to the FPGA's DMA_TOP module, and finally sends the data to the corresponding priority dma_buffer of the destination buffer partition through DMA. In the data stream receiving direction, after the FPGA receives the IU, it buffers it in a small queue mode by default. The IU is then segmented according to the size of the dma_buffer and pushed into the corresponding block in the DDR for buffering. It is then read out when certain conditions are met. Under predetermined conditions, the control switches to the large queue mode for caching. In DDR, IUs are cached in the same block used for large queue caching by splicing. If the memory of the block is still not full after a predetermined time period and no new IUs are received, an aging timeout report is made, and the data stored in the block is read out. When all blocks in the buffer area used for small queues are occupied, when a new IU is received, the FPGA controls and adjusts the blocks in the dynamic scheduling buffer area for subsequent IUs to cache and store. Furthermore, when the FPGA partitions DDR into blocks, it sets a threshold for the number of blocks in the buffer area used by the small queue. If the number of blocks used in the buffer area used by the small queue reaches the threshold, it enables dynamic scheduling of blocks in the buffer area to replenish them for subsequent IUs to cache and store. When the number of blocks used in the buffer area for small queues falls below the set release threshold, the newly added blocks will be released and recycled to the dynamic scheduling buffer area.

7. The communication system based on multi-partition independent buffering of FC devices according to claim 6, characterized in that, The RX_TOP module is configured with a register submodule, a write control module, and a read control module. The write control module is divided into two submodules: a large queue write module and a small queue write module, which are used for write operations in large queue mode and small queue mode, respectively. When the IU flows from the FC_MAC module into the RX_TOP module, the RX_TOP module first completes the frame parsing, parsing the IU into the raw data of the frame and the corresponding frame descriptor; The write control module determines whether the data frame belongs to the large queue or the small queue based on the descriptor, and enters the large queue write module or the small queue write module accordingly. At the same time, it reads the allocated DDR block address from the register submodule, writes the IU data into the DDR block, and writes the data frame descriptor into the register submodule for storage. When the read control module detects that there is descriptor storage information in the register submodule, it starts reading the descriptor information, reads the contents of the DDR block according to the descriptor information, and sends the data to the next-level DMA_TOP module. After reading a block, the read control module releases the address of the DDR block back to the register submodule for subsequent cyclic use. Specifically, after the FC_MAC module receives an IU, it defaults to using a small queue mode for caching. The IU is split and pushed into the corresponding block in the DDR for caching according to the size of the dma_buffer, and read out when certain conditions are met. Under predetermined conditions, it switches to a large queue mode for caching, where IUs are concatenated in the DDR and cached in the same block used for large queue caching. If, after a predetermined time period, the block's memory is still not full and no new IUs are received, an aging timeout is reported, and the data stored in the block is read out. In large queue mode, IUs from different channels with the same priority under the same partition are concatenated in the same DDR block.

8. The communication system based on multi-partition independent buffering of FC devices according to claim 7, characterized in that, If the received IU contains only one frame of data, the system switches from the default small queue mode to the large queue mode to buffer the received IU.

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