A free window selection method applied to array readout circuit

Abstract

The application discloses a free window selection method applied to an array readout circuit, and a window selection circuit structure comprises a configuration module, an execution module and a transmission module. In the array configuration stage, the configuration module supports user-defined window size and position, the execution module activates the pixels in the window according to the configuration information, and forms a dedicated data transmission path; in the array quantization stage, the execution module selects a time-to-digital converter to quantize the photon time of flight; in the array transmission stage, the transmission module adaptively adjusts the transmission duration according to the window size, and sequentially outputs the quantized data from the dedicated data transmission path. The window selection circuit can provide various spatial resolution and frame frequency selection under the premise of ensuring consistent array time resolution, improve the application flexibility of the array, reduce the system power consumption, and has good portability.

Description

Technical Field

[0001] This invention belongs to the field of lidar imaging technology and is applied to large-scale readout circuit systems that directly measure flight time and need to face complex environments. In particular, it relates to a free window selection method for array readout circuits. Background Technology

[0002] In traditional Readout Integrated Circuits (ROICs), performance metrics are mutually restrictive. Improving spatial resolution requires addressing issues such as crosstalk, hot pixels, data volume, and pixel size. Furthermore, existing ROICs often sacrifice performance in other areas when addressing one aspect of these problems. While a balance can be achieved through combining various technologies, compatibility issues between different technologies increase design complexity. For example, combining multi-echo and macropixel technologies requires simultaneously recording the temporal and spatial information of echo photons, but macropixels increase the difficulty of recording spatial information. Therefore, combining the advantages of multiple technologies within a limited pixel size, enabling ROICs to operate effectively in more complex environments, has become the biggest challenge. Window selection technology, as an effective measure to address these challenges, allows for high-resolution, full-window, wide-field-of-view readout while also enabling high-speed data rate readout within a narrow field of view.

[0003] Existing window selection technologies mainly fall into two categories. One type is used in ROICs based on transimpedance amplifiers, employing Gray code decoders. This offers high flexibility in window selection, but the decoding readout method limits imaging speed. The other type is used in ROICs based on Time-to-Digital Converters (TDCs). This method tracks the position of individual light spots through photon counting, activating the TDC only for pixels exceeding a counting threshold, thus achieving window selection. This approach is highly intelligent, but the maximum window size is limited by a preset light spot diameter, and the accuracy of photon counting directly affects tracking performance. Therefore, existing window selection technologies cannot simultaneously achieve high-speed readout and high-degree-of-freedom window selection. Summary of the Invention

[0004] The purpose of this invention is to provide a free window selection method for array readout circuits. While ensuring the consistency of the time resolution of the TDC array, it can provide a variety of spatial resolution and frame rate selection, improve the application flexibility of ROIC, and is of great significance for expanding the scale of ROIC. This solves the technical problem of the limitations of complex environment on the pixel size, performance and power consumption of ROIC.

[0005] To solve the above-mentioned technical problems, the specific technical solution of the present invention is as follows:

[0006] A free-viewpoint selection method applied to an array readout circuit, the circuit comprising a transmission module, a configuration module, and an execution module; wherein:

[0007] The reset signal, flag bit, configuration data, and configuration clock required by the configuration module are all input by the user through programming. Since the programming information is set to be input at the top left corner of the ROIC readout circuit, when the ROIC is considered a Cartesian coordinate system, the origin will be placed at the bottom right corner of the ROIC. Furthermore, the overall timing follows a configuration-then-ROIC operation sequence. The configuration module consists of a D flip-flop and a 2-to-1 multiplexer connected in parallel, serving as the horizontal axis (X) and vertical axis (Y) of the coordinate system. When the outputs of the i-th configuration module on the horizontal axis and the j-th configuration module on the vertical axis are both high, it represents a high level on the horizontal axis (X). i , vertical axis Y j Both are valid, and the pixel unit in the j-th row and i-th column of the corresponding ROIC is enabled. The enabled pixel unit is called the pixel within the window; conversely, if the horizontal axis X i , vertical axis Y j When only one is valid, or all are invalid, the pixel unit in the j-th row and i-th column of the corresponding ROIC is disabled. The disabled pixel is called the pixel outside the window. Therefore, the window size, position, and number represent the size, position, and number of enabled pixels. Different configuration data and configuration clocks are processed by the configuration module to form diverse windows. The minimum window size can be configured as 1×1.

[0008] The execution module, as part of each pixel unit, works in conjunction with the configuration module to control the pixel unit. Each pixel unit consists of a single-photon avalanche diode (SPAD), a quenching circuit, a time-to-digital converter (TDC), and the execution module. The execution module comprises two AND gates, a 2-to-1 multiplexer, and a multiplexer. The output and reset signal of the configuration module serve as the inputs to the AND gates in the execution module, and the outputs of the AND gates serve as the inputs to the quenching circuit. The configuration module controls the inputs and outputs of the 2-to-1 multiplexer and the multiplexer to be directly connected in series to form transmission path one, or to connect the inputs and outputs of the 2-to-1 multiplexer and the multiplexer in series with the inputs and outputs of the TDC to form transmission path two. When the execution module detects that a pixel is marked within a window, the SPAD, quenching circuit, and TDC within the pixel operate normally, and transmission path two is used for the transmission of input and output data between adjacent pixel units. When a pixel is detected to be marked outside the window, the quenching circuit's function of detecting avalanche current is disabled, and transmission path one is used instead of transmission path two.

[0009] The transmission module is a peripheral circuit within the ROIC. It consists of a modulo-64 counter, a multiplexer, a timing adjustment module, an OR tree, RC allocation logic, and a row invalidation check. Configuration data and a configuration clock serve as inputs to the modulo-64 counter and the OR tree. The modulo-64 counter controls the multiplexer to select different positions for the timing adjustment module. The outputs of the timing adjustment module and the OR tree are connected to the inputs of the RC allocation logic. The output of the OR tree also controls the row invalidation check for processing special configuration data. The transmission module uses a parallel transmission readout method, dividing the ROIC into two auxiliary ROICs (left and right), each further divided into several sub-ROICs. The transmission module controls the transmission timing of the two auxiliary ROICs, with the sub-ROICs under each auxiliary ROIC using the same transmission timing. By extracting valid information from the horizontal and vertical axes, the transmission module determines the length, width, and position of the largest window in each auxiliary ROIC, thereby controlling the pixel data transmission time and number of transmissions required for each row in the auxiliary ROIC, and sequentially allocating the data to the valid rows in the sub-ROICs. This achieves adaptive transmission time based on changes in the user-programmed window information.

[0010] Furthermore, when extracting valid information on the horizontal axis, the transmission module will use a configuration clock to drive the OR tree counter in the transmission module to generate a sampling clock: the number of sampling clocks corresponds to the maximum number of rows N in the sub-ROIC, the period of the sampling clock is N times the configuration clock, and the sampling start points of different sampling clocks are sequentially spaced one configuration clock period apart; the configuration data is sampled using N sampling clocks, and then N D flip-flops are driven respectively. When a D flip-flop is triggered, it means that the corresponding row of the sub-ROIC is valid; thus, the maximum width of the window is determined, that is, the number of valid horizontal axis values ​​in the sub-ROIC.

[0011] Furthermore, the RC allocation logic in the transmission module will arrange the transmission clock path corresponding to the valid row of the sub-ROIC based on the number of valid rows in the sub-ROIC, and generate the RC configuration number as the programming value of the RC counter in the time adjustment module of the transmission module, which is used to realize the number of transmissions required by the auxiliary ROIC.

[0012] Furthermore, when the transmission module extracts valid information on the vertical axis, the programmable row pixel counter in the time adjustment module of the transmission module will be time-division multiplexed: during the configuration phase, the configuration clock and configuration data based on the user-programmed input are processed by an AND gate as the driving clock for the programmable row pixel counter, and the final counting result is used as the programmed value of the programmable row pixel counter; during the transmission phase, the maximum count value of the programmable row pixel counter is the programmed value, and each full count represents the transmission time required to generate a row of pixels in the window; thus, the maximum length of the window is determined, i.e., the number of valid vertical axis pixels.

[0013] The free window selection method for array readout circuits of the present invention has the following advantages:

[0014] 1. The free-viewpoint selection method for array readout circuits proposed in this invention is implemented through the cooperation of a configuration module, an execution module, and a transmission module. It does not affect the temporal resolution of the TDC array. The configuration and execution modules can provide diverse spatial resolutions, while the transmission module can adaptively adjust the transmission time according to different spatial resolutions. Therefore, a smaller window will result in a higher frame rate and faster imaging speed.

[0015] 2. The free window selection method for array readout circuits proposed in this invention has good portability because, in terms of circuit implementation, the configuration module and transmission module are both peripheral circuits of ROIC, and the execution module consists of only two AND gates, one 2-to-1 selector and a multiplexer, occupying a very small portion of the pixel area.

[0016] 3. The free window selection method proposed in this invention for array readout circuits, when extracting effective information of the horizontal and vertical axes, achieves lower area consumption and better power consumption utilization compared to traditional methods by using a strategy based on sampling configuration data and configuration clock.

[0017] 4. The free window selection method for array readout circuits proposed in this invention, compared with the decoding windowing method, allows the configuration module and execution module to allow users to program multiple windows simultaneously, providing greater freedom in the number of windows. Furthermore, in terms of circuit timing, the configuration stage and the transmission stage are separated, and the transmission stage is not limited by decoding readout. In addition, the transmission module supports parallel transmission readout mode, enabling the array readout circuit to have a faster transmission speed.

[0018] 5. The free window selection method for array readout circuits proposed in this invention, compared with the windowing method for photon counting, not only improves the freedom of window selection in the configuration module and execution module, but also realizes the window information of adaptive transmission time in the transmission module in terms of data transmission, which can intelligently control the imaging speed.

[0019] 6. The free window selection method proposed in this invention for array readout circuits gives ROICs greater flexibility. For example, this technology allows users to program, in conjunction with configuration and execution modules, to specify only the operation of pixels in alternate rows and columns, or pixels at specific locations, while disabling the remaining pixels. This not only supports subsampling and suppresses crosstalk between adjacent pixels, but also supports hot pixel detection to disable pixels. Furthermore, it can be used for spot localization, processing data for regions of interest. In addition, when ported to ROICs that integrate photon counting and photon timing functions, this method can provide high spatial resolution 2D image data and high temporal resolution, low spatial resolution 3D graphics data, providing technical support for subsequent algorithms to achieve 2D-3D fusion.

[0020] 7. The window selection method proposed in this invention is applied to an array readout circuit with a time-to-digital converter as the main body. Unlike the prior art, this invention supports the simultaneous configuration of multiple windows of different sizes in window selection, with the minimum window size allowed to be configured as 1×1. In data reading, a parallel reading method of sub-readout circuits is adopted, and the reading duration adapts to the window size and number, allowing intelligent adjustment of frame rate. Attached Figure Description

[0021] Figure 1 A schematic diagram of a free window selection method applied to an array readout circuit provided by the present invention;

[0022] Figure 2 A schematic diagram for configuring timing and configuration modules;

[0023] Figure 3 This is a schematic diagram of the implementation of a pixel unit, including the execution module;

[0024] Figure 4 A schematic diagram of the transmission strategy executed by the transmission module;

[0025] Figure 5 This is a schematic diagram of the transmission module;

[0026] Figure 6 This is a schematic diagram of the OR tree in the transmission module;

[0027] Figure 7 This is a schematic diagram of the time adjustment module in the transmission module;

[0028] Figure 8 A schematic diagram of the RC allocation logic in the transmission module. Detailed Implementation

[0029] To better understand the purpose, structure, and function of this invention, the following detailed description, in conjunction with the accompanying drawings, provides a free window selection method for array readout circuits according to this invention.

[0030] like Figure 1 The diagram illustrates a free window selection method for array readout circuits provided by this invention. The configuration module is attached to the periphery of the readout circuit ROIC. Since configuration data, clock, flag bits, and reset signals can be programmed by the user and input from the upper left corner of the ROIC, the spatial resolution selection is diversified. The execution module is embedded in the pixel unit. The transmission module controls the output of the auxiliary ROICs on the left and right sides from both ends of the ROIC. Every four rows of pixels in the auxiliary ROIC constitute a sub-ROIC, sharing an output port. This output strategy can reduce the power consumption of the ROIC and improve the data output speed of the ROIC.

[0031] Figure 2 This diagram illustrates the timing and configuration module. Traditional ROICs primarily consist of a quantization phase and a transmission phase, forming ordinary frames. This invention differs from traditional ROICs by placing a configuration phase before the quantization phase, with the configuration phase and ordinary frames constituting the configuration frame. The window selection method requires the first frame of the array to be a configuration frame; otherwise, the entire array is disabled by default. The second frame and subsequent frames are ordinary frames by default, operating according to the configuration result of the most recent configuration frame. During the configuration phase, a reset signal (Reset) is input to reset the ROIC. While the FLAG bit is low, the configuration clock CLK_Data samples the column data (Row_Data) and column data (Column_Data) via the rising edge, ensuring that changes in the row and column data occur only when the configuration clock is low. Since the configuration module considers the lower right corner of the ROIC as the origin of the coordinate system, the first data sampled by the configuration clock is ultimately reflected at the lower right corner of the ROIC. The horizontal and vertical axes of the coordinate system are implemented by the configuration module using a combination of a D flip-flop and a 2-to-1 multiplexer, connected in series. When the FLAG signal is low, the output Control_i signal of the 2-to-1 selector is grounded, thus avoiding the impact on ROIC during the configuration process. Until the configuration is completed, the FLAG signal is high, and the Control_i signal is assigned a value by the corresponding D flip-flop.

[0032] Figure 3The diagram shows a pixel unit in ROIC. The pixel unit originally contains a single-photon avalanche device (SPAD), an quenching circuit (AQC), and an event-driven quantization (TDC). The remaining two AND gates, a 2-to-1 selector, and a multiplexer together form the execution module. The execution module uses the AND operation of the row and column signals Control_Row and Control_Column as control signals. When a pixel is considered an out-of-window pixel, the event-driven quantization TDC is short-circuited, and the output of the previous pixel is directly connected to the output of the current pixel, forming a new data transmission path. In addition, the reset signal of the quenching circuit AQC is also shielded, keeping the potentials of the SPAD anode and cathode close and preventing the generation of avalanche current signals. When a pixel is considered an in-window pixel, the pixel maintains normal operation, i.e., the SPAD and ROIC are interconnected through indium pillars. The reset signal enters the AQC, biasing the SPAD in reverse bias. Once a photon signal is detected, an avalanche current is generated, triggering the AQC to quench the SPAD and generate a pulse signal STOP, which is transmitted to the TDC as the quantization start point of the TDC. When the quantization stage ends, the TDC also stops working until the transmission stage arrives. At this time, the TDC will serve as the data transmission path, outputting the current pixel data and the previous pixel data in sequence.

[0033] Figure 4 This diagram illustrates the transmission strategy executed by the transmission module. Each sub-ROIC consists of 4×8 pixels. Sub-ROICs 1-3 are output from the left, and sub-ROICs 4-6 are output from the right. The diagram shows four user-programmed windows with sizes of 3×3, 3×4, 2×3, and 2×4. Theoretically, sub-ROIC3 requires 3 pixels and 3 transmissions, sub-ROIC6 requires 4 pixels and 3 transmissions, sub-ROIC2 requires 3 pixels and 2 transmissions, and sub-ROIC5 requires 4 pixels and 2 transmissions. Since the duration of each ROIC transmission phase depends on the longest transmission duration within a sub-ROIC, the left sub-ROICs require a total of 3 pixels and 3 transmissions, and the right sub-ROICs require a total of 4 pixels and 3 transmissions. Therefore, the transmission strategy executed by the transmission module divides the ROIC into left and right parts, then further subdivides it into several sub-ROICs. Within each part, the union of the sub-ROIC windows is taken as the M pixels and N transmissions required for all sub-ROICs in that part.

[0034] Figure 5This is a schematic diagram of the transmission module. Taking a 128×128 ROIC as an example, a modulo-64 counter counts the falling edge of the configuration clock, sending the first 64 columns of valid information to the right-hand time adjustment module and the last 64 columns of valid information to the left-hand time adjustment module. The OR tree processes the configuration clock and row configuration data into subarray row valid information, and the RC allocation logic generates RC configuration numbers to program the number of transmissions of the time adjustment module. After receiving the RC configuration numbers and column valid information, the time adjustment module generates BIT, WORD, and FRAM signals for the left and right arrays, respectively, and four outputs to the RC allocation logic. The RC allocation logic then allocates the RC allocation clocks of the left and right parts according to the input situation. The row invalidity judgment is used to prevent the entire array from being disabled when there are columns that are valid but rows that are invalid. However, the generated RC configuration number allows the time adjustment module to continue to work, so the input clock needs to be masked in this case.

[0035] Figure 6 This is a schematic diagram of the OR tree in the transmission module. To obtain the union of window widths in all sub-ROICs, the traditional method is to output rows A through D of each sub-ROIC separately through an OR array. However, this consumes a large number of OR cells and power. Therefore, the proposed OR tree uses a configuration clock to drive a narrow pulse generator to produce A through D sampling clocks. The sampling clock frequency is four times that of the configuration clock. The sampling clocks and configuration data are ANDed to drive D flip-flops. Once the output of the D flip-flop goes high, it indicates that at least one sub-ROIC row is valid.

[0036] Figure 7 This is a schematic diagram of the time adjustment module in the transmission module. The readout clock LCK is processed through four parts to generate the synchronization BIT, WORD, FRAM signals, and RC clock. The clock gating section ensures that the time adjustment module only operates during the transmission phase; the gated clock drives the word generation counter to generate the transmission time T required for a single pixel; then the word drives the row pixel counter, and the column valid information L is programmed as the upper limit of the row pixel counter's count, so when the maximum value is reached, the generated transmission time is L×T; then the column drives the RC counter, which also uses the programmed number of RC counts Q as the upper limit of the count, selects the output channel corresponding to the RC count value, and generates the synchronization BIT, WORD, FRAM signals, and RC clock.

[0037] Figure 8 This diagram illustrates the RC allocation logic in the transmission module. Subarray valid information is generated by RC configuration numbers to form the number of RCs Q, which is then used to generate S1 to S10 via switch control. RC1 to S4 are the RC clocks. The RC clocks are allocated to the ARC to DRC channels by the switch control, and then transmitted to the corresponding rows of the subarray, i.e., the sub-ROIC.

[0038] Compared with traditional solutions, the free window selection method for array readout circuits of the present invention has the following advantages: (1) It mainly improves the peripheral circuits of the ROIC, resulting in low power consumption and strong portability. (2) It supports multiple options for spatial resolution selection, thus allowing for greater freedom in the number of windows. (3) The transmission phase adapts to changes in window information, enabling intelligent adjustment of imaging speed.

[0039] It is understood that the present invention has been described through some embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the invention. Furthermore, under the teachings of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of the present invention.

Claims

1. A free-viewpoint selection method applied to an array readout circuit, characterized in that, The circuit includes a transmission module, a configuration module, and an execution module; wherein: The reset signal, flag bit, configuration data, and configuration clock required by the configuration module are all input by the user through programming. Since the programming information is set to be input at the upper left corner of the ROIC readout circuit, when the ROIC is considered a Cartesian coordinate system, the origin will be placed at the lower right corner of the ROIC. Furthermore, the overall timing follows a configuration-then-ROIC operation sequence. The configuration module consists of a D flip-flop and a 2-to-1 multiplexer connected in parallel, serving as the horizontal axis (X) and vertical axis (Y) of the coordinate system. When the outputs of the i-th configuration module on the horizontal axis and the j-th configuration module on the vertical axis are both high, it represents a high level on the horizontal axis (X). i , vertical axis Y j Both are valid, and the pixel unit in the j-th row and i-th column of the corresponding ROIC is enabled. The enabled pixel unit is called the pixel within the window; conversely, if the horizontal axis X i , vertical axis Y j When only one is valid, or all are invalid, the pixel unit in the j-th row and i-th column of the corresponding ROIC is disabled. The disabled pixel is called the pixel outside the window. Therefore, the window size, position, and number represent the size, position, and number of enabled pixels. Different configuration data and configuration clocks are processed by the configuration module to form diverse windows. The minimum window size can be configured as 1×1. The execution module, as part of each pixel unit, works in conjunction with the configuration module to control the pixel unit. Each pixel unit consists of a single-photon avalanche diode (SPAD), a quenching circuit, a time-to-digital converter (TDC), and the execution module. The execution module comprises two AND gates, a 2-to-1 multiplexer, and a multiplexer. The output and reset signal of the configuration module serve as the inputs to the AND gates in the execution module, and the outputs of the AND gates serve as the inputs to the quenching circuit. The configuration module controls the inputs and outputs of the 2-to-1 multiplexer and the multiplexer to be directly connected in series to form transmission path one, or to connect the inputs and outputs of the 2-to-1 multiplexer and the multiplexer in series with the inputs and outputs of the TDC to form transmission path two. When the execution module detects that a pixel is marked within a window, the SPAD, quenching circuit, and TDC within the pixel operate normally, and transmission path two is used for the transmission of input and output data between adjacent pixel units. When a pixel is detected to be marked outside the window, the quenching circuit's function of detecting avalanche current is disabled, and transmission path one is used instead of transmission path two. The transmission module is a peripheral circuit within the ROIC. It consists of a modulo-64 counter, a multiplexer, a timing adjustment module, an OR tree, RC allocation logic, and a row invalidation check. Configuration data and a configuration clock serve as inputs to the modulo-64 counter and the OR tree. The modulo-64 counter controls the multiplexer to select different positions for the timing adjustment module. The outputs of the timing adjustment module and the OR tree are connected to the inputs of the RC allocation logic. The output of the OR tree also controls the row invalidation check for processing special configuration data. The transmission module uses a parallel transmission readout method, dividing the ROIC into two auxiliary ROICs (left and right), each further divided into several sub-ROICs. The transmission module controls the transmission timing of the two auxiliary ROICs, with the sub-ROICs under each auxiliary ROIC using the same transmission timing. By extracting valid information from the horizontal and vertical axes, the transmission module determines the length, width, and position of the largest window in each auxiliary ROIC, thereby controlling the pixel data transmission time and number of transmissions required for each row in the auxiliary ROIC, and sequentially allocating the data to the valid rows in the sub-ROICs. This achieves adaptive transmission time based on changes in the user-programmed window information.

2. The free window selection method applied to an array readout circuit according to claim 1, characterized in that, When extracting valid information on the horizontal axis, the transmission module will use a configuration clock to drive the OR tree counter in the transmission module to generate a sampling clock: the number of sampling clocks corresponds to the maximum number of rows N in the sub-ROIC, the period of the sampling clock is N times the configuration clock, and the sampling start points of different sampling clocks are sequentially spaced one configuration clock period apart; the configuration data is sampled using N sampling clocks, and then N D flip-flops are driven respectively. When a D flip-flop is triggered, it means that the corresponding row of the sub-ROIC is valid; thus, the maximum width of the window is determined, that is, the number of valid horizontal axis data in the sub-ROIC.

3. The free window selection method applied to an array readout circuit according to claim 2, characterized in that, The RC allocation logic in the transmission module will arrange the transmission clock path corresponding to the valid row of the sub-ROIC according to the number of valid rows in the sub-ROIC, and generate the RC configuration number as the programming value of the RC counter in the time adjustment module of the transmission module, which is used to realize the number of transmissions required by the auxiliary ROIC.

4. The free window selection method applied to an array readout circuit according to claim 3, characterized in that, When the transmission module extracts valid information on the vertical axis, the programmable row pixel counter in the time adjustment module of the transmission module is time-division multiplexed: during the configuration phase, based on the configuration clock and configuration data input by the user, it is processed by an AND gate as the driving clock of the programmable row pixel counter, and the final counting result is used as the programmed value of the programmable row pixel counter; during the transmission phase, the maximum count value of the programmable row pixel counter is the programmed value, and each time it is full, it represents the transmission time required to generate a row of pixels in the window; thus, the maximum length of the window is determined, that is, the number of valid vertical axes.

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