Bias generation circuit and storage circuit

Abstract

Embodiments of the present disclosure relate to the field of semiconductor technology and provide a bias generation circuit and a storage circuit. The bias generation circuit includes: a first load circuit coupled between an operating voltage and an adjustment node; a bias circuit receiving the operating voltage and outputting a bias voltage based on the operating voltage; a voltage regulator circuit coupled to an output terminal of the bias circuit and receiving a reference voltage for adjusting a voltage at the adjustment node based on the bias voltage and the reference voltage; and a second load circuit having one terminal coupled to the output terminal of the bias circuit and the other terminal coupled to the adjustment node. The embodiments of the present disclosure at least facilitate preventing the bias voltage from being affected by the operating voltage, thereby maintaining the bias voltage within a stable numerical range.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a bias generation circuit and a storage circuit. Background Art

[0002] In semiconductor devices, a power converter or operating power supply can be used to convert an operating voltage into a desired voltage to power one or more electronic devices. The operating power supply can be used to generate an auxiliary bias power supply for powering various circuits within the operating power supply itself. For example, a bias generation circuit can be used to convert the operating voltage into a bias voltage.

[0003] Then, the bias voltage generated by the bias generating circuit is easily changed due to changes in other voltages in the circuit, so that the bias voltage cannot be within a stable value range, which is not conducive to the stable working state of other circuits that receive the bias voltage to work. Summary of the Invention

[0004] The embodiments of the present disclosure provide a bias generation circuit and a storage circuit, which are at least conducive to keeping the bias voltage within a stable value range.

[0005] According to some embodiments of the present disclosure, on one hand, an embodiment of the present disclosure provides a bias generation circuit, including: a first load circuit, the first load circuit being coupled between an operating voltage and an adjustment node; a bias circuit, receiving the operating voltage and outputting a bias voltage according to the operating voltage; a voltage stabilizing circuit, the voltage stabilizing circuit being coupled to the output end of the bias circuit and receiving a reference voltage, for adjusting the voltage of the adjustment node according to the bias voltage and the reference voltage; and a second load circuit, one end of the second load circuit being coupled to the output end of the bias circuit, and the other end being coupled to the adjustment node.

[0006] In some embodiments, the voltage stabilization circuit includes: an operational amplifier, a first input terminal of the operational amplifier receiving the reference voltage, and a second input terminal of the operational amplifier coupled to the adjustment node; a drive circuit, the drive circuit coupled to the output terminal of the operational amplifier and receiving the bias voltage, and used to adjust the voltage of the adjustment node according to the output of the operational amplifier and the bias voltage; and a feedback circuit, the feedback circuit coupled between the adjustment node and the ground terminal.

[0007] In some embodiments, the feedback circuit includes a first resistor coupled between the adjustment node and the ground.

[0008] In some embodiments, the driving circuit includes a first NMOS transistor, a control end of the first NMOS transistor is coupled to the output end of the operational amplifier, a first end of the first NMOS transistor is coupled to the output end of the bias circuit, and a second end of the first NMOS transistor is coupled to the adjustment node.

[0009] In some embodiments, the first load circuit includes a second resistor coupled between the operating voltage and the adjustment node.

[0010] In some embodiments, the first load circuit includes: a first MOS transistor, a first end of the first MOS transistor coupled to the operating voltage, a second end of the first MOS transistor coupled to the adjustment node, and the first MOS transistor responding to a first control voltage signal to conduct the first end of the first MOS transistor and the second end of the first MOS transistor.

[0011] In some embodiments, the first load circuit includes: a second resistor, one end of the second resistor is coupled to the operating voltage; a first MOS transistor, a first end of the first MOS transistor is coupled to the other end of the second resistor, a second end of the first MOS transistor is coupled to the adjustment node, and the first MOS transistor responds to a first control voltage signal to conduct the first end and the second end of the first MOS transistor.

[0012] In some embodiments, the second load circuit includes: a second MOS transistor, wherein the control end of the second MOS transistor is coupled to the first end of the first MOS transistor, the first end of the second MOS transistor is coupled to the output end of the bias circuit, and the second end of the second MOS transistor is coupled to the adjustment node.

[0013] In some embodiments, the second load circuit includes: a third resistor, one end of the third resistor is coupled to the output end of the bias circuit; a second MOS transistor, a control end of the second MOS transistor is coupled to the first end of the first MOS transistor, a first end of the second MOS transistor is coupled to the other end of the third resistor, and a second end of the second MOS transistor is coupled to the adjustment node.

[0014] In some embodiments, the first MOS transistor is of either N-type or P-type, and the second MOS transistor is of the other of N-type or P-type.

[0015] In some embodiments, the second load circuit includes a third resistor coupled between an output terminal of the bias circuit and the adjustment node.

[0016] In some embodiments, the bias circuit includes: a third MOS transistor, a control end of the third MOS transistor coupled to the output end of the bias circuit, a first end of the third MOS transistor coupled to the operating voltage, and a second end of the third MOS transistor coupled to the output end of the bias circuit.

[0017] In some embodiments, the bias circuit further includes: a fourth MOS transistor, a first end of the fourth MOS transistor coupled to the second end of the third MOS transistor, a second end of the fourth MOS transistor coupled to the output end of the bias circuit, and a control end of the fourth MOS transistor conducting between the first end and the second end of the fourth MOS transistor in response to a second control voltage signal.

[0018] In some embodiments, the bias generating circuit further includes: a switching circuit configured to be turned on in response to an enable signal so that the first load circuit is coupled to the operating voltage via the switching circuit, and the bias circuit receives the operating voltage via the switching circuit.

[0019] In some embodiments, the switch circuit includes a sixth MOS transistor.

[0020] According to some embodiments of the present disclosure, another aspect of the present disclosure provides a storage circuit, comprising: a bias generating circuit as described in any one of the foregoing items; and an input buffer circuit coupled to an output end of the bias circuit.

[0021] The technical solution provided by the embodiments of the present disclosure has the following advantages:

[0022] In the bias generation circuit, a voltage regulator circuit is coupled to the output terminal of the bias circuit and an adjustment node, while a second load circuit also has one end coupled to the output terminal of the bias circuit and the adjustment node. Therefore, the voltage regulator circuit and the second load circuit can jointly regulate the voltage at the adjustment node. Thus, when the operating voltage is stable, the voltage regulator circuit can control the voltage at the adjustment node to a fixed voltage value, thereby stabilizing the current flowing through the bias circuit and outputting a stable bias voltage. Furthermore, when the operating voltage is excessive, the second load circuit can increase the current in the bias circuit compared to a bias generation circuit without a second load circuit. This helps prevent the bias voltage output by the bias circuit from becoming excessively large or small due to fluctuations in the operating voltage, thereby ensuring that the bias circuit outputs a bias voltage within a stable range of values, thereby maintaining stable operation of other circuits that receive the bias voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians who lack the skills, other drawings can be obtained based on these drawings without paying creative labor.

[0024] Figure 1 is a circuit schematic diagram of a bias generating circuit;

[0025] Figures 2 to 10 Nine circuit schematic diagrams of a bias generation circuit provided in an embodiment of the present disclosure;

[0026] Figure 11 A circuit diagram of a storage circuit provided in yet another embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] As known from the background art, the value of the bias voltage generated by the current bias generating circuit is unstable.

[0028] Figure 1 This is a circuit diagram of a bias generation circuit, refer to Figure 1 The bias generation circuit includes: a load circuit 10, which is coupled between an operating voltage VDD and a connection node 11; a bias circuit 12, which receives the operating voltage VDD and outputs a bias voltage Vbias according to the operating voltage VDD; and a voltage regulator circuit 13, which is coupled to the output end of the bias circuit 12 and receives a reference voltage Vref, and is used to adjust the bias voltage Vbias according to the reference voltage Vref and the voltage of the connection node 11.

[0029] If the operating voltage VDD increases, the value of the current I2 flowing through the load circuit 10 increases, causing the voltage at the connection node 11 to increase. The difference between the reference voltage Vref and the voltage at the connection node 11 increases. Based on the increase in the difference between the reference voltage Vref and the voltage at the connection node 11, the voltage outputted by the operational amplifier 14 in the voltage regulator circuit 13 decreases. Consequently, the voltage received by the control terminal of the NMOS transistor 15 coupled to the output terminal of the operational amplifier in the voltage regulator circuit 13 decreases, reducing the conduction level of the NMOS transistor 15 or causing it to turn off. This causes the current I1 in the bias circuit 12 to decrease or become zero, causing the voltage at the control terminal of the PMOS transistor 16 to approach the voltage at the terminal of the PMOS transistor 16 coupled to the operating voltage, i.e., causing the bias voltage Vbias to approach the operating voltage VDD.

[0030] Analysis has revealed that in current bias generation circuits, the bias voltage Vbias output by the bias circuit 12 increases with the operating voltage VDD. This makes it difficult to maintain a stable value for the bias voltage Vbias output by the bias circuit 12. Furthermore, other circuits that receive the bias voltage Vbias for operation may become inoperable due to the increased bias voltage Vbias. Therefore, there is an urgent need to design a bias generation circuit that can generate a stable bias voltage.

[0031] The present disclosure provides a bias generation circuit in which not only is a voltage stabilization circuit coupled to the output terminal of the bias circuit and an adjustment node, but one end of a second load circuit is also coupled to the output terminal of the bias circuit and the adjustment node. Therefore, the voltage stabilization circuit and the second load circuit can jointly regulate the current through the bias circuit, thereby causing the bias circuit to output a bias voltage within a stable numerical range. When the operating voltage is stable, the voltage stabilization circuit can control the voltage at the adjustment node to a fixed voltage value, thereby stabilizing the current through the bias circuit and outputting a stable bias voltage. When the operating voltage is excessive, the second load circuit can increase the current in the bias circuit compared to a bias generation circuit without a second load circuit. These two aspects help prevent the bias voltage output by the bias circuit from becoming excessively large or small with fluctuations in the operating voltage, thereby facilitating the bias circuit to output a bias voltage within a stable numerical range, thereby maintaining stable operating conditions for other circuits that receive the bias voltage for operation.

[0032] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure more clear, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the embodiments of the present disclosure to help readers better understand the embodiments of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.

[0033] An embodiment of the present disclosure provides a bias generation circuit. The bias generation circuit provided by an embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. Figures 2 to 10 Nine circuit schematic diagrams of a bias generation circuit provided in an embodiment of the present disclosure.

[0034] refer to Figure 2 The bias generation circuit includes: a first load circuit 100, which is coupled between an operating voltage VDD and an adjustment node 101; a bias circuit 102, which receives the operating voltage VDD and outputs a bias voltage Vbias according to the operating voltage VDD; a voltage regulator circuit 103, which is coupled to the output end of the bias circuit 102 and receives a reference voltage Vref, and is used to adjust the voltage of the adjustment node 101 according to the bias voltage Vbias and the reference voltage Vref; and a second load circuit 104, which has one end coupled to the output end of the bias circuit 102 and the other end coupled to the adjustment node 101.

[0035] In this manner, on the one hand, the voltage regulator circuit 103 is coupled to the output terminal of the bias circuit 102, and the voltage regulator circuit 103 can provide a conductive path between the output terminal of the bias circuit 102 and the adjustment node 101. On the other hand, one end of the second load circuit 104 is coupled to the output terminal of the bias circuit 102, and the other end is coupled to the adjustment node 101. Therefore, the second load circuit 104 can provide another conductive path between the output terminal of the bias circuit 102 and the adjustment node 101.

[0036] In this way, the current in the bias circuit 102 is affected by both the voltage regulator circuit 103 and the second load circuit 104 . Compared to currently common bias generation circuits, in which the output end of the bias circuit 102 is coupled to the adjustment node only via a voltage regulator circuit, and the current in the bias circuit is affected only by the voltage regulator circuit, in the bias generation circuit provided in one embodiment of the present disclosure, the output end of the bias circuit 102 can be coupled to the adjustment node 101 via both the voltage regulator circuit 103 and the second load circuit 104. Therefore, when the operating voltage VDD fluctuates, reducing the voltage regulator circuit 103's ability to regulate the voltage at the adjustment node 101 and the current flowing through the bias circuit 102, the second load circuit 104 can assist the voltage regulator circuit 103 in regulating the current flowing through the bias circuit 102. This helps maintain the current flowing through the bias circuit 102 within a stable value range, allowing the bias circuit 102 to output a bias voltage Vbias within a stable value range based on the stable current in the bias circuit 102, thereby facilitating stable operation of other circuits that receive the bias voltage Vbias.

[0037] The bias generating circuit provided by an embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0038] Regarding the specific situation where the first load circuit 100 is coupled between the working voltage VDD and the adjustment node 101 , two embodiments are described in detail below.

[0039] In some embodiments, reference Figure 2 The coupling of the first load circuit 100 to the operating voltage VDD means that the first load circuit 100 is directly electrically connected to the operating voltage VDD without any other circuit or electronic device being indirectly electrically connected therebetween.

[0040] In other embodiments, reference Figure 3 The bias generating circuit may further include: a switch circuit 105, configured to be turned on in response to an enable signal EnN, so that the first load circuit 100 is coupled to the operating voltage VDD via the switch circuit 105, and the bias circuit 102 receives the operating voltage VDD via the switch circuit 105.

[0041] In some embodiments, the switch circuit 105 may include a sixth MOS transistor. Figure 3In the example, the switch circuit 105 includes only one sixth MOS transistor. In actual applications, the switch circuit 105 can also be a circuit composed of multiple sixth MOS transistors connected in series, or a circuit composed of other single electronic devices or a combination of multiple electronic devices that can be turned on based on an enable signal. The embodiment of the present disclosure does not limit the composition of the switch circuit 105, as long as it is capable of being turned on in response to the enable signal EnN. It should be noted that in one example, the sixth MOS transistor can be a PMOS transistor; in another example, the sixth MOS transistor can be an NMOS transistor.

[0042] In some embodiments, reference Figure 4 The voltage stabilization circuit 103 may include: an operational amplifier 113, wherein a first input terminal of the operational amplifier 113 receives a reference voltage Vref, and a second input terminal of the operational amplifier 113 is coupled to the adjustment node 101; a driving circuit 123, wherein the driving circuit 123 is coupled to the output terminal of the operational amplifier 113 and receives a bias voltage Vbias, and is configured to adjust the voltage of the adjustment node 101 according to the output of the operational amplifier 113 and the bias voltage Vbias; and a feedback circuit 133, wherein the feedback circuit 133 is coupled between the adjustment node 101 and the ground.

[0043] It should be noted that the coupling of the second input terminal of the operational amplifier 113 to the adjustment node 101 means that the second input terminal of the operational amplifier 113 and the adjustment node 101 can be directly electrically connected; the coupling of the drive circuit 123 to the output terminal of the operational amplifier 113 means that the drive circuit 123 and the output terminal of the operational amplifier 113 can be directly electrically connected; and the coupling of the feedback circuit 133 between the adjustment node 101 and the ground terminal means that the feedback circuit 133 and the adjustment node 101 and the ground terminal can all be directly electrically connected.

[0044] The configuration of the voltage stabilizing circuit 103 will be described in detail below.

[0045] In some embodiments, reference Figure 4 The driving circuit 123 may include a first NMOS transistor, a control terminal of the first NMOS transistor coupled to the output terminal of the operational amplifier 113, a first terminal of the first NMOS transistor coupled to the output terminal of the bias circuit 102, and a second terminal of the first NMOS transistor coupled to the adjustment node 101.

[0046] As the operating voltage VDD increases, the current I2 flowing through the first load circuit 100 increases, causing the voltage at the adjustment node 101 to increase. In the initial stage of the increase in the operating voltage VDD, the voltage regulator circuit 103 outputs a relatively low output voltage based on the reference voltage Vref and the increased voltage at the adjustment node 101. The first NMOS transistor receives this relatively low output voltage, causing the first NMOS transistor to have a very low degree of conduction or even be turned off. This prevents the first NMOS transistor from effectively reducing the voltage at the adjustment node 101, and thus prevents the current flowing through the bias circuit 102 from being regulated. In this case, the second load circuit 104 regulates the current flowing through the bias circuit 102, ensuring that the current I1 in the bias circuit 102 is primarily influenced by the current I3 in the second load circuit 104. This maintains the current I1 flowing through the bias circuit 102 within a stable value range, allowing the bias circuit 102 to output a bias voltage Vbias within a stable value range based on the stable current I1 in the bias circuit 102.

[0047] In some embodiments, reference Figure 4 The feedback circuit 133 may include a first resistor coupled between the adjustment node 101 and the ground. In other embodiments, the feedback circuit may be a plurality of first resistors connected in series, or may be at least one other electronic device such as a MOS transistor.

[0048] The structure of the first load circuit is described in detail below through three embodiments.

[0049] In some embodiments, reference Figure 4 The first load circuit 100 may include: a second resistor 110 , and the second resistor 110 is coupled between the operating voltage VDD and the adjustment node 101 .

[0050] It should be noted that the coupling of the second resistor 110 to the operating voltage VDD may be achieved by electrically connecting the second resistor 110 to the adjustment node 101 via the switch circuit 105. In other embodiments, the coupling of the second resistor 110 to the operating voltage VDD may be achieved by directly electrically connecting the second resistor 110 to the operating voltage VDD. The second resistor 110 may be directly electrically connected to the adjustment node 101. Figure 4 In the example, the first load circuit 100 includes a second resistor 110. In actual applications, the first load circuit 100 may include at least two second resistors 110 connected in series.

[0051] In other embodiments, reference Figure 5The first load circuit 100 may include a first MOS transistor 120, wherein a first terminal of the first MOS transistor 120 is coupled to an operating voltage VDD, a second terminal of the first MOS transistor 120 is coupled to an adjustment node 101, and the first MOS transistor 120 is responsive to a first control voltage signal 10a to conduct electricity between the first terminal of the first MOS transistor 120 and the second terminal of the first MOS transistor 120. The first MOS transistor may be a PMOS transistor or an NMOS transistor.

[0052] It should be noted that the coupling of the first terminal of the first MOS transistor 120 to the operating voltage VDD may be achieved by electrically connecting the first terminal of the first MOS transistor 120 to the adjustment node 101 via the switch circuit 105. In other embodiments, the coupling of the first terminal of the first MOS transistor 120 to the operating voltage VDD may be achieved by directly electrically connecting the first terminal of the first MOS transistor 120 to the operating voltage VDD. The second terminal of the first MOS transistor 120 may be directly electrically connected to the adjustment node 101. Figure 5 In the example, the first load circuit 100 includes a first MOS transistor 120. In actual applications, the first load circuit 100 may include at least two first MOS transistors 120 connected in series.

[0053] In some other embodiments, reference Figure 6 The first load circuit 100 may include: a second resistor 110, one end of the second resistor 110 is coupled to the operating voltage VDD; a first MOS transistor 120, a first end of the first MOS transistor 120 is coupled to the other end of the second resistor 110, and a second end of the first MOS transistor 120 is coupled to the adjustment node 101. The first MOS transistor 120 responds to the first control voltage signal 10a to conduct the first and second ends of the first MOS transistor 120.

[0054] It should be noted that coupling one end of the second resistor 110 to the operating voltage VDD may be achieved by electrically connecting one end of the second resistor 110 to the adjustment node 101 via the switch circuit 105. In other embodiments, coupling the second resistor to the operating voltage VDD may be achieved by directly electrically connecting the second resistor to the operating voltage VDD. The first end of the first MOS transistor 120 may be directly electrically connected to the other end of the second resistor 110, and the second end of the first MOS transistor 120 may be directly electrically connected to the adjustment node 101. Figure 6 In the example, the first load circuit 100 includes a second resistor 110 and a first MOS transistor 120. In actual applications, there is no restriction on the number of the second resistors 110 and the number of the first MOS transistors 120. The number of the second resistors 110 and the number of the first MOS transistors 120 can be reasonably set according to the specific requirements of the bias generation circuit.

[0055] When the operating voltage VDD remains unchanged and the voltage regulator circuit 103 stably controls the voltage at the adjustment node 101, the current flowing through the feedback circuit 133 remains unchanged. Since the current flowing through the feedback circuit 133 is the sum of the current I1 flowing through the bias circuit 102, the current I2 flowing through the first load circuit 100, and the current I3 flowing through the second load circuit 104, compared to a bias generation circuit without the first load circuit 100, the first load circuit 100 in this case acts as a shunt, facilitating the reduction of the current I1 flowing through the bias circuit 102. This allows the bias circuit 102 to output a higher bias voltage Vbias based on the smaller current I1. Therefore, adding the first load circuit 100 to the bias generation circuit facilitates the bias circuit 102 to output a higher bias voltage Vbias while the operating voltage VDD remains unchanged.

[0056] In the embodiment of the present disclosure, as the operating voltage VDD increases, the voltage of the adjustment node 101 increases, and the output voltage of the voltage stabilizing circuit 103 based on the reference voltage Vref and the voltage of the adjustment node 101 is small, so that the driving circuit 123 in the voltage stabilizing circuit 103 is almost in a shut-off state, which reduces the ability of the voltage stabilizing circuit 103 to regulate the voltage of the adjustment node 101, thereby failing to adjust the current I1 flowing through the bias circuit 102, so that the current I1 in the bias circuit 102 is mainly affected by the current I3 in the second load circuit 104, which makes the current I1 in the bias circuit 102 The current I1 is larger than the current in the bias circuit in the currently commonly used bias generation circuit, which helps to prevent the bias voltage Vbias output by the bias circuit 102 from being too large and helps to keep the bias voltage Vbias within a stable numerical range. On the other hand, when the bias voltage Vbias is required to be at a certain specified value, the current I3 in the second load circuit 104 can be controlled by adjusting the overall resistance value of the second load circuit 104, so as to adjust the current I1 in the bias circuit 102 and thus control the bias voltage Vbias.

[0057] The structure of the second load circuit 104 is described in detail below through three embodiments.

[0058] In some embodiments, reference Figure 7 The second load circuit 104 may include a third resistor 114 coupled between the output terminal of the bias circuit 102 and the adjustment node 101. The resistance of the third resistor 114 may be 15 kΩ to 25 kΩ.

[0059] It should be noted that the coupling between the third resistor 114 and the output terminal of the bias circuit 102 and the adjustment node 101 can be direct electrical connections. Figure 7In the example, the second load circuit 104 includes a third resistor 114. In practical applications, depending on the specific requirements of the bias generation circuit, the second load circuit 104 may include at least two third resistors 114 connected in series. For example, the resistance value of the second load circuit 104 may be set based on the magnitude of the bias voltage Vbias output by the bias circuit 102. This helps further ensure that the bias voltage Vbias output by the bias circuit 102 is within a stable value range, facilitating stable operation of other circuits that receive the bias voltage. The overall resistance value of the second load circuit 104 may be 15 kΩ to 25 kΩ. This prevents the resistance value of the second load circuit 104 from being too small, thereby preventing the current I3 in the second load circuit 104 from being too large, and thus preventing the bias voltage Vbias output by the bias circuit 102 based on the current I1 in the bias circuit 102 from being too small.

[0060] In other embodiments, reference Figure 8 Under the premise that the first load circuit 100 includes the second resistor 110 and the first MOS transistor 120, the second load circuit 104 may include a second MOS transistor 124, wherein the control terminal of the second MOS transistor 124 is coupled to the first terminal of the first MOS transistor 120, the first terminal of the second MOS transistor 124 is coupled to the output terminal of the bias circuit 102, and the second terminal of the second MOS transistor 124 is coupled to the adjustment node 101. In this way, the second MOS transistor 124 is designed in the second load circuit 104 to control the current I3 in the second load circuit 104. This not only helps to control the bias voltage Vbias within a stable value range, but also helps to save circuit and layout space, thereby improving the integration density of the bias generation circuit.

[0061] One end of the second resistor 110 is coupled to the operating voltage VDD; the first MOS transistor 120 has a first end coupled to the other end of the second resistor 110, and a second end coupled to the adjustment node 101. The first MOS transistor 120 responds to the first control voltage signal 10a to conduct the first and second ends of the first MOS transistor 120.

[0062] It should be noted that the control end of the second MOS transistor 124 can be directly electrically connected to the first end of the first MOS transistor 120, the first end of the second MOS transistor 124 can be directly electrically connected to the output end of the bias circuit 102, and the second end of the second MOS transistor 124 can be directly electrically connected to the adjustment node 101.

[0063] The first MOS transistor 120 may be of N-type or P-type, and the second MOS transistor may be of the other of N-type or P-type.

[0064] In one example, the first MOS transistor 120 may be a PMOS transistor, and the second MOS transistor 124 may be an NMOS transistor. Thus, when the operating voltage VDD increases and the voltage of the adjustment node 101 increases accordingly, the voltage received by the control terminal of the second MOS transistor 124 also increases, which helps to increase the conduction degree of the second MOS transistor 124, thereby increasing the current I3 in the second load circuit 104, thereby increasing the current I1 in the bias circuit 102, thereby helping the bias circuit 102 output a smaller bias voltage Vbias based on the larger current I1, that is, helping to reduce the bias voltage Vbias output by the bias circuit 102, thereby preventing the bias voltage Vbias from increasing significantly with the increase of the operating voltage VDD, and ensuring that the bias voltage Vbias is within a stable value range.

[0065] In some other embodiments, reference Figure 9 On the premise that the first load circuit 100 includes the second resistor 110 and the first MOS transistor 120, the second load circuit 104 may include: a third resistor 114, where one end of the third resistor 114 is coupled to the output end of the bias circuit 102; and a second MOS transistor 124, where a control end of the second MOS transistor 124 is coupled to the first end of the first MOS transistor 120, a first end of the second MOS transistor 124 is coupled to the other end of the third resistor 114, and a second end of the second MOS transistor 124 is coupled to the adjustment node 101.

[0066] To prevent the resistance value of the second load circuit 104 from being too small, the second load circuit 104 is provided with a third resistor 114 in addition to the second MOS transistor 124. The third resistor 114 and the second MOS transistor 124 are jointly controlled to ensure that the overall resistance value of the second load circuit 104 is within an appropriate range, thereby stabilizing the current I3 in the second load circuit 104 within an appropriate value range, preventing the current I3 in the second load circuit 104 from being too large or too small, and preventing the current I1 in the bias circuit 102 from being too large or too small. This helps to stabilize the bias voltage Vbias output by the bias circuit 102 based on the current I1 in the bias circuit 102 within an appropriate value range. Furthermore, compared to resistors, the second MOS transistor 124 is smaller in size. Therefore, by combining the third resistor 114 and the second MOS transistor 124 to maintain the overall resistance of the second load circuit 104 within an appropriate range, the need for a third resistor 114 with a very large resistance value can be avoided. This helps prevent the third resistor 114 from occupying excessive circuit and layout space, thereby saving circuit and layout space while ensuring that the overall resistance of the second load circuit 104 is within an appropriate range. The resistance of the third resistor 114 can be 5 kΩ to 7 kΩ.

[0067] One end of the second resistor 110 is coupled to the operating voltage VDD; the first MOS transistor 120 has a first end coupled to the other end of the second resistor 110, and a second end coupled to the adjustment node 101. The first MOS transistor 120 responds to the first control voltage signal 10a to conduct the first and second ends of the first MOS transistor 120.

[0068] It should be noted that one end of the third resistor 114 can be directly electrically connected to the output end of the bias circuit 102, the control end of the second MOS transistor 124 can be directly electrically connected to the first end of the first MOS transistor 120, the first end of the second MOS transistor 124 can be directly electrically connected to the other end of the third resistor 114, and the second end of the second MOS transistor 124 can be directly electrically connected to the adjustment node 101.

[0069] The first MOS transistor 120 may be of an N-type or a P-type, and the second MOS transistor 124 may be of the other of an N-type or a P-type.

[0070] In one example, the first MOS transistor 120 may be a PMOS transistor, and the second MOS transistor 124 may be an NMOS transistor. Thus, when the operating voltage VDD increases and the voltage of the adjustment node 101 increases accordingly, the voltage received by the control terminal of the second MOS transistor 124 also increases, which helps to increase the conduction degree of the second MOS transistor 124, thereby increasing the current I3 in the second load circuit 104, thereby increasing the current I1 in the bias circuit 102, and thus helping to reduce the bias voltage Vbias output by the output terminal of the bias circuit 102, thereby preventing the bias voltage Vbias from increasing with the increase of the operating voltage VDD, and ensuring that the bias voltage Vbias is within a stable value range.

[0071] In some embodiments, the bias circuit 102 may include: a third MOS transistor 112, wherein the control terminal of the third MOS transistor 112 is directly coupled to the output terminal of the bias circuit 102, the first terminal of the third MOS transistor 112 is coupled to the operating voltage VDD, and the second terminal of the third MOS transistor 112 is coupled to the output terminal of the bias circuit 102.

[0072] In some embodiments, the third MOS transistor 112 may be a PMOS transistor. As the operating voltage VDD increases, the voltage regulator circuit 103's ability to regulate the voltage at the adjustment node 101 decreases, making it unable to regulate the current I1 flowing through the bias circuit 102. In this case, the second load circuit 104 may regulate the current I1 flowing through the bias circuit 102, so that the current I1 in the bias circuit 102 is primarily affected by the current I3 in the second load circuit 104. This maintains the current I1 flowing through the bias circuit 102 within a stable value range and makes the current I1 in the bias circuit 102 larger than the current in the bias circuit in a commonly used bias generation circuit. Based on the larger current I1, the third MOS transistor 112 can reduce the voltage at the control terminal of the third MOS transistor 112, thereby preventing the voltage at the control terminal of the third MOS transistor 112 from increasing with the operating voltage VDD, thereby maintaining the bias voltage Vbias within a stable value range. In other embodiments, the third MOS transistor 112 may also be an NMOS transistor.

[0073] The principle that the third MOS transistor 112 can reduce the voltage at the control terminal of the third MOS transistor 112 based on the larger current I1 is as follows:

[0074]

[0075] Wherein, I1 is the current flowing through the third MOS transistor 112, W is the width of the channel region in the third MOS transistor 112, L is the length of the channel region in the third MOS transistor 112, μ n is the carrier mobility, C ox is the thickness of the gate dielectric layer in the third MOS transistor 112, V GS is the voltage difference between the control terminal of the third MOS transistor 112 and the first terminal of the third MOS transistor 112, V TH is the threshold voltage of the third MOS transistor 112. As the current I1 in the bias circuit 102 increases, that is, the current I1 flowing through the third MOS transistor 112 increases, then (V GS -V TH ) 2 When the third MOS tube 112 is a PMOS tube, V GS For negative values, (V GS -V TH ) 2 Increase, then you need V GS Decreases. Since V GS is the voltage difference between the control terminal of the third MOS transistor 112 and the first terminal of the third MOS transistor 112. The voltage V S When it is unchanged, V GS To reduce, the voltage V at the control terminal of the third MOS tube 112 is requiredG Decreases, because the voltage V G That is, the bias voltage Vbias output by the bias circuit 102. Therefore, when the current I1 flowing through the third MOS transistor 112 increases, the bias voltage Vbias output by the bias circuit 102 can be reduced by adding the second load circuit 104, so as to prevent the bias voltage Vbias from increasing with the increase of the operating voltage VDD, so that the bias voltage Vbias is within a stable value range.

[0076] In some embodiments, continue to refer to Figures 7 to 9 In addition to the bias circuit 102 including the third MOS transistor 112, the bias circuit 102 may further include a fourth MOS transistor 122. A first end of the fourth MOS transistor 122 is coupled to the second end of the third MOS transistor 112, a second end of the fourth MOS transistor 122 is directly coupled to the output end of the bias circuit 102, and a control end of the fourth MOS transistor 122 conducts electricity between the first and second ends of the fourth MOS transistor 122 in response to the second control voltage signal 10b.

[0077] It should be noted that the first end of the fourth MOS transistor 122 may be directly electrically connected to the second end of the third MOS transistor 112. The fourth MOS transistor 122 may be an NMOS transistor or a PMOS transistor.

[0078] The following Figure 7 The bias generating circuit provided in is taken as an example to explain in detail the principle that the bias voltage Vbias output by the bias circuit 102 does not change with the change of the operating voltage VDD.

[0079] When the working voltage VDD increases, the value of the current I2 flowing through the first load circuit 100 increases, so that the voltage of the adjustment node 101 increases. In the early stage of the increase of the working voltage VDD, the difference between the voltage of the adjustment node 101 and the reference voltage Vref is large, so that the operational amplifier 113 in the voltage stabilizing circuit 103 outputs a small output voltage. The first NMOS transistor in the driving circuit 123 receives the small output voltage, so that the conduction degree of the first NMOS transistor is very low or the first NMOS transistor is turned off, so that the current driving the first NMOS transistor is reduced. If the current I1 in the bias circuit 102 is almost zero, the current I1 in the bias circuit 102 is mainly affected by the current I3 in the second load circuit 104, so that the current I1 flowing through the bias circuit 102 is larger than that in the bias generating circuit without the second load circuit. Therefore, the third MOS transistor 112 in the bias circuit 102 controls the voltage at the control end of the third MOS transistor 112 to decrease based on the larger current I1, so as to prevent the bias voltage Vbias from increasing with the increase of the operating voltage VDD, so that the bias circuit 102 outputs the bias voltage Vbias within a stable value range.

[0080] When the operating voltage VDD is stable, the voltage stabilizing circuit 103 can control the voltage of the adjustment node 101 to a fixed voltage value, so that the current passing through the bias circuit 102 is stable, thereby outputting a stable bias voltage.

[0081] In some embodiments, the first control voltage signal 10 a , the second control voltage signal 10 b , and the reference voltage Vref may be the same.

[0082] In summary, compared to currently common bias generation circuits, the voltage regulator circuit 103 can, on the one hand, provide a conductive path between the output terminal of the bias circuit 102 and the adjustment node 101. Furthermore, the second load circuit 104 can provide another conductive path between the output terminal of the bias circuit 102 and the adjustment node 101. Consequently, as the operating voltage VDD increases, the potential of the adjustment node 101 also increases. As the voltage regulator circuit 103's ability to regulate the voltage at the adjustment node 101 decreases, the voltage regulator circuit 103's ability to regulate the current flowing through the bias circuit 102 also decreases. In this case, the second load circuit 104 can assist the voltage regulator circuit 103 in regulating the current flowing through the bias circuit 102, thereby facilitating the maintenance of a stable current flowing through the bias circuit 102 within a stable value range. This allows the bias circuit 102 to output a bias voltage Vbias within a stable value range based on the stable current I1, thereby facilitating stable operation of other circuits that receive the bias voltage Vbias.

[0083] Another embodiment of the present disclosure further provides a storage circuit, comprising any bias generation circuit provided in the aforementioned embodiments. The storage circuit provided in another embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. Figure 11 A circuit diagram of a storage circuit provided in yet another embodiment of the present disclosure.

[0084] refer to Figure 11 The storage circuit includes: a bias generation circuit 106 as provided in any of the above embodiments; and an input buffer circuit 107, which is coupled to the output terminal of the bias circuit 102. It should be noted that the bias generation circuit 106 is the same as in the above embodiments and is not described here in detail. Figure 11 In the figure, only one circuit schematic diagram of the bias generating circuit 106 is used as an example for the convenience of illustration.

[0085] In some embodiments, input buffer circuit 107 includes a seventh MOS transistor 117. A control terminal of seventh MOS transistor 117 is coupled to the output terminal of bias circuit 102 in bias generation circuit 106. That is, the control terminal of seventh MOS transistor 117 receives bias voltage Vbias. The control terminal of seventh MOS transistor 117 and the output terminal of bias circuit 102 can be directly electrically connected.

[0086] Among them, the third MOS transistor 112 in the bias circuit 102 and the seventh MOS transistor 117 in the input buffer circuit 107 form a current mirror structure.

[0087] In one example, both the third MOS transistor 112 and the seventh MOS transistor 117 are PMOS transistors. Since the third MOS transistor 112 serves as the input transistor, the control terminal and the second terminal of the third MOS transistor 112 are shorted, VDS1 = VGS1 < VGS1 - VT1, and the third MOS transistor 112 always operates in the saturation region. Moreover, since the control terminal and the second terminal of the third MOS transistor 112 are shorted, the input resistance of the third MOS transistor 112 is also relatively low. Among them, VDS1 is the voltage between the second terminal and the first terminal of the third MOS transistor 112, VGS1 is the voltage between the control terminal and the first terminal of the third MOS transistor 112, and VT1 is the threshold voltage of the third MOS transistor 112.

[0088] Since the seventh MOS transistor 117 operates in the saturation region, then VDS2 < VGS2 - VT2. Also, since VGS1 = VGS2, then VDS2 < VGS1 - VT2. And since VGS1 = VDS1, then VDS2 < VDS1 - VT2. Since both VDS2 and VDS1 are negative values, the absolute value of VDS2 is greater than the absolute value of VDS1. Among them, VDS2 is the voltage between the second terminal and the first terminal of the seventh MOS transistor 117, VGS2 is the voltage between the control terminal and the first terminal of the seventh MOS transistor 117, and VT2 is the threshold voltage of the seventh MOS transistor 117.

[0089] According to the current mirror formula:

[0090] where, I out is the current value output by the seventh MOS transistor 117, I ref is the current value provided by the third MOS transistor 112 to the seventh MOS transistor 117, W1 is the width of the channel of the third MOS transistor 112, L1 is the length of the channel of the third MOS transistor 112, V DS1 is the voltage between the second terminal and the first terminal of the third MOS transistor 112, W2 is the width of the channel of the seventh MOS transistor 117, L2 is the length of the channel of the seventh MOS transistor 117, V DS2 is the voltage between the second terminal and the first terminal of the seventh MOS transistor 117, and λ is the current mirror coefficient.

[0091] To make the result of the current mirror more accurate, it is necessary In order to reduce the influence of VDS1, it is necessary to increase W2, that is, increase the width of the channel of the seventh MOS transistor 117, to ensure that I out with I ref proportion.

[0092] In the embodiment of the present disclosure, after adding the fourth MOS tube 122, ideally, I ref If the bias voltage Vbias remains unchanged, the bias voltage Vbias remains substantially unchanged. Without the fourth MOS transistor 122, VDS1 = Vbias - VS1. With the fourth MOS transistor 122, VDS1 = VS3 - VS1, where VS1 is the voltage at the control terminal of the third MOS transistor 112 and VS3 is the voltage at the control terminal of the fourth MOS transistor 122. Since VS3 is greater than the bias voltage Vbias, and both the third MOS transistor 112 and the seventh MOS transistor 117 are PMOS transistors, VDS1 is a negative value. Therefore, the absolute value of VDS1 after the fourth MOS transistor 122 is added is smaller than the absolute value of VDS1 without the fourth MOS transistor 122. Furthermore, for the PMOS transistor, λ is a negative value, so after the fourth MOS transistor 122 is added, 1+λV DS1 Less than 1+λV when the fourth MOS tube 122 is not added DS1 It can be seen that after adding the fourth MOS transistor 122, it is not necessary to increase the width of the channel of the seventh MOS transistor 117, and the fourth MOS transistor 122 can be provided to ensure I out with I ref proportion.

[0093] In summary, if the storage circuit includes any bias generating circuit 106 provided in the aforementioned embodiments, the bias voltage Vbias outputted by the output terminal of the bias circuit 102 and received by the input buffer circuit 107 is a stable value, which is conducive to keeping the input buffer circuit 107 in a stable working state.

[0094] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and that in actual applications, various changes may be made to the embodiments in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the scope of protection of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A bias generating circuit, characterized in that: include: a first load circuit coupled between an operating voltage and an adjustment node; a bias circuit, receiving the operating voltage and outputting a bias voltage according to the operating voltage; a voltage stabilizing circuit, coupled to an output terminal of the bias circuit and receiving a reference voltage, and configured to adjust a voltage of the adjustment node according to the bias voltage and the reference voltage; A second load circuit has one end coupled to the output end of the bias circuit and the other end coupled to the adjustment node.

2. The bias generating circuit according to claim 1, wherein: The voltage stabilizing circuit comprises: an operational amplifier, wherein a first input terminal of the operational amplifier receives the reference voltage, and a second input terminal of the operational amplifier is coupled to the adjustment node; a driving circuit coupled to the output terminal of the operational amplifier and receiving the bias voltage, and configured to adjust the voltage of the adjustment node according to the output of the operational amplifier and the bias voltage; A feedback circuit is coupled between the adjustment node and a ground terminal.

3. The bias generating circuit according to claim 2, wherein: The feedback circuit includes a first resistor coupled between the adjustment node and the ground.

4. The bias generating circuit according to claim 2, wherein: The driving circuit includes a first NMOS transistor, a control end of the first NMOS transistor is coupled to the output end of the operational amplifier, a first end of the first NMOS transistor is coupled to the output end of the bias circuit, and a second end of the first NMOS transistor is coupled to the adjustment node.

5. The bias generating circuit according to claim 1, wherein: The first load circuit includes a second resistor coupled between the operating voltage and the adjustment node.

6. The bias generating circuit according to claim 1, wherein: The first load circuit includes: a first MOS transistor, a first end of the first MOS transistor is coupled to the operating voltage, a second end of the first MOS transistor is coupled to the adjustment node, and the first MOS transistor responds to a first control voltage signal to conduct the first end of the first MOS transistor and the second end of the first MOS transistor.

7. The bias generating circuit according to claim 1, wherein: The first load circuit includes: a second resistor, one end of the second resistor being coupled to the operating voltage; a first MOS transistor, wherein a first end of the first MOS transistor is coupled to the other end of the second resistor, a second end of the first MOS transistor is coupled to the adjustment node, and the first MOS transistor is responsive to a first control voltage signal to conduct the first end and the second end of the first MOS transistor.

8. The bias generating circuit according to claim 7, wherein: The second load circuit includes: a second MOS transistor, a control end of the second MOS transistor coupled to the first end of the first MOS transistor, a first end of the second MOS transistor coupled to the output end of the bias circuit, and a second end of the second MOS transistor coupled to the adjustment node.

9. The bias generating circuit according to claim 7, wherein: The second load circuit includes: a third resistor, one end of the third resistor being coupled to the output end of the bias circuit; A second MOS transistor, wherein the control end of the second MOS transistor is coupled to the first end of the first MOS transistor, the first end of the second MOS transistor is coupled to the other end of the third resistor, and the second end of the second MOS transistor is coupled to the adjustment node.

10. The bias generating circuit according to claim 8 or 9, wherein: The first MOS transistor is of either N-type or P-type, and the second MOS transistor is of the other of N-type or P-type.

11. The bias generating circuit according to claim 1, wherein: The second load circuit includes a third resistor coupled between an output terminal of the bias circuit and the adjustment node.

12. The bias generating circuit according to claim 1, wherein: The bias circuit includes: a third MOS transistor, a control end of the third MOS transistor is coupled to the output end of the bias circuit, a first end of the third MOS transistor is coupled to the operating voltage, and a second end of the third MOS transistor is coupled to the output end of the bias circuit.

13. The bias generating circuit according to claim 12, wherein: The bias circuit further includes: a fourth MOS transistor, a first end of the fourth MOS transistor coupled to the second end of the third MOS transistor, a second end of the fourth MOS transistor coupled to the output end of the bias circuit, and a control end of the fourth MOS transistor conducting between the first end and the second end of the fourth MOS transistor in response to a second control voltage signal.

14. The bias generating circuit according to claim 1, wherein: Also includes: The switch circuit is configured to be turned on in response to an enable signal, so that the first load circuit is coupled to the operating voltage via the switch circuit, and the bias circuit receives the operating voltage via the switch circuit.

15. The bias generating circuit according to claim 14, wherein: The switch circuit includes a sixth MOS transistor.

16. A storage circuit, characterized in that: include: The bias generating circuit according to any one of claims 1 to 15; An input buffer circuit is coupled to the output terminal of the bias circuit.

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