Wafer-level multi-gpu simulation method and device based on gem5 framework and storage medium

Abstract

This invention discloses a multi-GPU simulation method based on the Gem5 framework for wafer-level systems. The method includes: building a Gem5 system simulation environment, downloading source files, compiling, and running them; creating multiple GPU components and connecting the L2 caches of each GPU to a Directory, which then points to the memory segments belonging to each GPU; modifying the ROCk driver to create multiple software queues for one or more programs and assigning them to multiple GPUs, creating a doorbell region for each GPU; and using the built Gem5 system to simulate and test the multi-GPU wafer-level system and verify its performance. This invention achieves communication, interaction, and scheduling between multiple GPUs, thereby reducing the design time of the wafer-level system and lowering the system verification cost. This invention also discloses a GPU simulation device and storage medium based on Gem5.

Description

Technical Field

[0001] This invention relates to the field of wafer-level GPU design simulation technology, and more specifically, to a wafer-level multi-GPU simulation method, apparatus, and storage medium based on the Gem5 framework. Background Technology

[0002] GPUs, with their powerful parallel computing capabilities, have enabled varying degrees of performance improvements in most applications. Since GPUs were first used in general-purpose computing, researchers have developed a series of GPU architecture simulators to support the exploration of GPU architectures, enabling the parallelization of different applications on multi-GPU platforms and achieving better results.

[0003] Early GPU emulators, such as GPGPU-Sim and Multi2-Sim, were developed for single GPU platforms and did not support multi-GPU expansion. The later Gem5 emulator was a configurable architecture simulator integrating multiple instruction sets and GPU models. It hybridized the M5 and GEMS emulators. The M5 emulator, developed by the University of Michigan, primarily focuses on simulating GPU models and instruction sets. The GEMS emulator, developed by the University of Wisconsin, offers flexible simulation of memory tiers and supports various cache coherence and on-chip interconnect models.

[0004] With technological advancements and driven by market demand for parallel computing applications such as AI and data centers, GPUs have evolved into multi-threaded, multi-core, and highly parallel processors. The powerful computing capabilities of GPUs, characterized by high parallelism, have made high-performance computing a trend of the times. This architecture, which has disrupted traditional multi-core systems, brings advantages such as high performance and low power consumption, but also presents new challenges to chip design, hardware architecture, and a range of resource management strategies.

[0005] In wafer-level system design, there are numerous prefabricated components, each of which can be a separate GPU. However, while the aforementioned simulators offer rich configuration options, they can only simulate one GPU at a time during the design process, and can only modify the internal configuration options of that single GPU. Therefore, in the wafer-level system design process, using existing simulators can only achieve component-by-component simulation, which increases the design time and verification cost of wafer-level systems.

[0006] Therefore, how to reduce the design time and verification cost of wafer-level systems is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0007] The purpose of this invention is to provide a GPU simulation method, device, and storage medium based on Gem5, which solves the above-mentioned technical problems by enabling the simulation of multiple GPUs during wafer-level system design.

[0008] To achieve the above objectives, the present invention adopts the following technical solution:

[0009] A GPU simulation method based on Gem5 for wafer-level systems is characterized by the following steps:

[0010] S1: Set up a Gem5 system simulation environment, including downloading source files, compiling, and running;

[0011] S2: Create multiple GPU components in the Gem5 system and connect the L2 caches of the multiple GPUs to the Directory, and then the Directory points them to different memory segments belonging to each GPU.

[0012] S3: Modify the Radeon Open Compute kernel (ROCk) driver to create multiple software queues for one or more programs and assign them to multiple GPUs, creating a doorbell region for each GPU;

[0013] S4: The Gem5 system was built to simulate and test the wafer-level system with multiple GPUs and verify the system performance.

[0014] Specifically, step S2 includes:

[0015] Step S21: During the GPU component creation process, N GPU components are created repeatedly in a loop from 0 to N, where N is the number of GPUs;

[0016] Step S22: Create a Shader, Compute Units, HSAPacketProcessor, GPUDispatcher, and GPUCommandProcessor for each GPU component;

[0017] Step S23: Reconstruct the topology by connecting each GPU as a Node to the Directory, simulating the PCIe interaction mode;

[0018] Step S24: Within the Directory, add a section where each Node points to a different memory segment.

[0019] Step S25: In the GPU's Viper system, add a cache for each GPU component by repeatedly adding it in a loop from 0 to N;

[0020] Step S26: In the GPU's TLB configuration, set up a TLB hierarchy for each GPU component.

[0021] Specifically, step S3 includes:

[0022] Step S31: When the user space code calls the system's ioctl function, it requests ROCk to create a queue. ROCk obtains the GPU ID through the parameter of ioctl() and assigns the kernel to the corresponding GPU.

[0023] Step S32: Create a hash table for ROCk to maintain the mapping between queues and GPUs, so that ROCk records the GPU corresponding to each queue;

[0024] Step S33: Create a doorbell region for each GPU;

[0025] Step S34: Add the offset parameter to the input parameters of the mmap() function;

[0026] Step S35: Add calculation logic to the mmap() function to calculate the memory mapping address of the GPU in physical memory using the starting address, length, and offset value.

[0027] A multi-GPU simulation device based on the Gem5 framework for wafer-level systems is characterized by comprising the following modules:

[0028] The environment setup module is used to set up a Gem5 system simulation environment, including downloading source files, compiling, and running.

[0029] The GPU component creation module is used to create multiple GPU components and connect the L2 caches of multiple GPUs to the Directory, which then points them to different memory segments belonging to each GPU.

[0030] The ROCk driver modification module is used to modify the Radeon Open Compute kernel (ROCk) driver, creating multiple software queues for one or more programs and assigning them to multiple GPUs, creating a doorbell region for each GPU;

[0031] The test and verification module is used to perform simulation tests and verify the system performance of the multi-GPU wafer-level system using the built Gem5 system.

[0032] Specifically, the GPU component creation module includes:

[0033] The loop creation module is used to repeatedly create N GPU components from 0 to N during the GPU component creation process, where N is the number of GPUs.

[0034] The component configuration module is used to create Shaders, Compute Units, HSAPacketProcessor, GPUDispatcher, and GPUCommandProcessor for each GPU component.

[0035] The topology building module is used to rebuild the topology, connecting each GPU as a Node to the Directory, simulating the PCIe interaction mode.

[0036] The memory mapping module is used to add a point within the Directory where each Node points to a different memory segment.

[0037] The cache configuration module is used to add a cache to each GPU component in the Viper system of the GPU by repeatedly adding a cache from 0 to N in a loop;

[0038] The TLB configuration module is used to set up a separate TLB hierarchy for each GPU component in the GPU's TLB configuration.

[0039] Specifically, the ROCk driver modification module includes:

[0040] The queue creation module is used to request ROCk to create a queue when user space code calls the system's ioctl function. ROCk obtains the GPU ID through the parameter of ioctl() and allocates the kernel to the corresponding GPU.

[0041] The hash table creation module is used to create a hash table for ROCk to maintain the mapping between queues and GPUs, so that ROCk records the GPU corresponding to each queue;

[0042] The doorbell region configuration module is used to create a doorbell region for each GPU;

[0043] The offset configuration module is used to add the offset parameter to the input parameters of the mmap() function;

[0044] The logic calculation module is used to add calculation logic to the mmap() function, which calculates the memory mapping address of the GPU in physical memory using the starting address, length, and offset value.

[0045] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the above-described method for GPU simulation based on Gem5.

[0046] Compared with existing technologies, this invention provides a multi-GPU simulation method, device, and storage medium based on the Gem5 framework. When designing wafer-level systems, it provides a simulator capable of simulating multiple GPUs and a ROCk driver capable of supporting the operation of multiple GPUs. It can easily create simulation systems with multiple GPUs, realize communication, interaction, and scheduling between multiple GPUs, and test and verify the system performance, thereby reducing the design time of wafer-level systems and lowering the system verification cost. Attached Figure Description

[0047] Figure 1 Background technology: Schematic diagram of GPU simulation topology for Gem5

[0048] Figure 2 This is a schematic diagram of the GPU simulation topology based on Gem5 disclosed in this invention.

[0049] Figure 3 This is a schematic diagram of the GPU simulation method based on Gem5 disclosed in this invention.

[0050] Figure 4 This is a schematic diagram of the software queue process from program to GPU disclosed in this invention.

[0051] Figure 5 This is a schematic diagram of the GPU memory address structure for mmap query disclosed in this invention. Implementation

[0052] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0053] Figure 1The diagram illustrates the GPU simulation topology of Gem5. In Gem5's GPU architecture, the L2 cache of the GPU module is connected to the directory and then pointed to memory. Regarding GPU simulation, Gem5 supports simulating AMD GCN architecture GPUs. It achieves simulation of AMD GPU functions by supporting the GCN3 instruction set. In terms of drivers, GCN3 uses the Radeon Open Compute platform (ROCm). The ROCm platform provides BLAS (basic linear algebra subroutine) and MIOpen (Machine Intelligence Library). For example, upper-layer applications can call BLAS and MIOpen, which in turn call the common API interface HIP. Of course, upper-layer applications can also directly call the API interface HIP or OpenCL without using the libraries. Below the API interface lies the driver part, which can be summarized into three layers: ROC Runtime, ROC Thunk, and ROCkernel Driver (ROCk), calling downwards sequentially. The ROCk driver resides below the operating system and is responsible for interacting with the GPU hardware. Figure 1 As shown, AMD's GPU architecture consists of multiple CUs. All CUs share the SQC (AMD's instruction L1 cache), each CU has its own TCP (data L1 cache), and CUs share the same memory TCC (unified L2 cache).

[0054] like Figure 3 As shown, a GPU simulation method based on Gem5 for wafer-level systems is characterized by the following steps:

[0055] S1: Set up a Gem5 system simulation environment, including downloading source files, compiling, and running;

[0056] S2: Create multiple GPU components in the Gem5 system and connect the L2 caches of the multiple GPUs to the Directory, and then the Directory points them to different memory segments belonging to each GPU.

[0057] S3: Modify the ROCk driver to create multiple software queues for one or more programs and assign them to multiple GPUs, creating a doorbell region for each GPU;

[0058] S4: The Gem5 system was built to simulate and test the wafer-level system with multiple GPUs and verify the system performance.

[0059] Figure 2 The diagram below illustrates the GPU simulation topology based on Gem5 according to the present invention. The present invention creates multiple GPUComponent components, connects the L2 caches of multiple GPUs to the Directory, and the Directory then points to the memory segment to which each GPU belongs. In Gem5, although there is only one Memory, by pointing to different memory segments through the Directory, it is possible to achieve the effect that each GPU has its own memory.

[0060] Specifically, step S2 includes:

[0061] Step S21: During the GPU component creation process, N GPU components are created repeatedly in a loop from 0 to N, where N is the number of GPUs;

[0062] Step S22: Create a Shader, Compute Units, HSAPacketProcessor, GPUDispatcher, and GPUCommandProcessor for each GPU component;

[0063] Step S23: Reconstruct the topology by connecting each GPU as a Node to the Directory, simulating the PCIe interaction mode;

[0064] Step S24: Within the Directory, add a section where each Node points to a different memory segment.

[0065] Step S25: In the GPU's Viper system, add a cache for each GPU component by repeatedly adding it in a loop from 0 to N;

[0066] Step S26: In the GPU's TLB configuration, set up a TLB hierarchy for each GPU component.

[0067] Specifically, step S3 includes:

[0068] Step S31: When the user space code calls the system's ioctl function, it requests ROCk to create a queue. ROCk obtains the GPU ID through the parameter of ioctl() and assigns the kernel to the corresponding GPU.

[0069] Step S32: Create a hash table for ROCk to maintain the mapping between queues and GPUs, so that ROCk records the GPU corresponding to each queue;

[0070] Step S33: Create a doorbell region for each GPU;

[0071] Step S34: Add the offset parameter to the input parameters of the mmap() function;

[0072] Step S35: Add calculation logic to the mmap() function to calculate the memory mapping address of the GPU in physical memory using the starting address, length, and offset value.

[0073] In gem5, gem5 emulates the Linux ROCk kernel-space driver. Each program generates one or more software queues and allocates them to a GPU. The emulator's driver creates and manages these software queues. Figure 4 As shown, this invention creates multiple software queues for one or more programs and allocates them to multiple GPUs by modifying the ROCk driver.

[0074] The software notifies the GPU to activate it by writing data to a fixed memory location and then writing a value to the "doorbell region" field in memory. The software uses the mmap() function to write data to virtual memory and then transfers it to the doorbell region in physical memory.

[0075] Since the wafer-level system of this invention contains multiple GPUs, a doorbell region needs to be created for each GPU. However, the existing mmap() function cannot distinguish the doorbell regions of multiple GPUs. This invention adds an offset parameter to the input parameters of the mmap() function. mmap() distinguishes the GPU ID by the memory offset value, specifically as follows: Figure 5 The diagram shown illustrates the GPU memory address structure corresponding to the mmap query.

[0076] A multi-GPU simulation device based on the Gem5 framework for wafer-level systems is characterized by comprising the following modules:

[0077] The environment setup module is used to set up a Gem5 system simulation environment, including downloading source files, compiling, and running.

[0078] The GPU component creation module is used to create multiple GPU components and connect the L2 caches of multiple GPUs to the Directory, which then points them to different memory segments belonging to each GPU.

[0079] The ROCk driver modification module is used to modify the ROCk driver, create multiple software queues for one or more programs, and assign them to multiple GPUs, creating a doorbell region for each GPU.

[0080] The test and verification module is used to perform simulation tests and verify the system performance of the multi-GPU wafer-level system using the built Gem5 system.

[0081] Specifically, the GPU component creation module includes:

[0082] The loop creation module is used to repeatedly create N GPU components from 0 to N during the GPU component creation process, where N is the number of GPUs.

[0083] The component configuration module is used to create Shaders, Compute Units, HSAPacketProcessor, GPUDispatcher, and GPUCommandProcessor for each GPU component.

[0084] The topology building module is used to rebuild the topology, connecting each GPU as a Node to the Directory, simulating the PCIe interaction mode.

[0085] The memory mapping module is used to add a point within the Directory where each Node points to a different memory segment.

[0086] The cache configuration module is used to add a cache to each GPU component in the Viper system of the GPU by repeatedly adding a cache from 0 to N in a loop;

[0087] The TLB configuration module is used to set up a separate TLB hierarchy for each GPU component in the GPU's TLB configuration.

[0088] Specifically, the ROCk driver modification module includes:

[0089] The queue creation module is used to request ROCk to create a queue when user space code calls the system's ioctl function. ROCk obtains the GPU ID through the parameter of ioctl() and allocates the kernel to the corresponding GPU.

[0090] The hash table creation module is used to create a hash table for ROCk to maintain the mapping between queues and GPUs, so that ROCk records the GPU corresponding to each queue;

[0091] The doorbell region configuration module is used to create a doorbell region for each GPU;

[0092] The offset configuration module is used to add the offset parameter to the input parameters of the mmap() function;

[0093] The logic calculation module is used to add calculation logic to the mmap() function, which calculates the memory mapping address of the GPU in physical memory using the starting address, length, and offset value.

[0094] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the above-described method for GPU simulation based on Gem5.

[0095] This invention provides a method, apparatus, and storage medium for GPU simulation of Gem5. Based on Gem5, a wafer-level simulation system composed of multiple GPUs connected via PCIe is created. A ROCk driver capable of supporting the operation of multiple GPUs is configured, realizing communication, interaction, and scheduling between multiple GPUs, thereby reducing the design time of the wafer-level system and lowering the system verification cost.

[0096] Those skilled in the art will recognize that the units of the various examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware or a combination of computer software and electronic hardware.

[0097] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0098] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and other division methods may exist in actual implementation. Furthermore, the functional units in the various embodiments of this invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0099] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A method for multi-GPU simulation based on a Gem5 framework, for wafer-level systems, the method comprising: Includes the following steps: S1: Set up a Gem5 system simulation environment, including downloading source files, compiling, and running; S2: Create multiple GPU components in the Gem5 system and connect the L2 caches of the multiple GPUs to the Directory, and then the Directory points them to different memory segments belonging to each GPU. S3: Modify the ROCk (Radeon Open Compute kernel) driver to create multiple software queues for one or more programs and assign them to multiple GPUs, creating a doorbell region for each GPU; S4: The Gem5 system was built to simulate and test the wafer-level system with multiple GPUs and verify the system performance. Specifically, step S2 includes: S21: During the GPU component creation process, N GPU components are created repeatedly in a loop from 0 to N, where N is the number of GPUs; S22: Creates a Shader, Compute Units, HSAPacketProcessor, GPUDispatcher, and GPUCommandProcessor for each GPU component; Step S23: Reconstruct the topology by connecting each GPU as a Node to the Directory, simulating the PCIe interaction mode; Step S24: Inside the Directory, add each Node pointing to a different memory segment; Step S25: In the GPU's Viper system, add a cache for each GPU component by repeatedly adding it in a loop from 0 to N; Step S26: In the GPU's TLB configuration, set up a TLB hierarchy for each GPU component; Step S3 specifically includes: Step S31: When the user space code calls the system's ioctl function, it requests ROCk to create a queue. ROCk obtains the GPU ID through the parameter of ioctl() and assigns the kernel to the corresponding GPU. Step S32: Create a hash table for ROCk to maintain the mapping between queues and GPUs, so that ROCk records the GPU corresponding to each queue; Step S33: Create a doorbell region for each GPU; Step S34: Add the offset parameter to the input parameters of the mmap() function; Step S35: Add calculation logic to the mmap() function to calculate the memory mapping address of the GPU in physical memory using the starting address, length, and offset value.

2. A multi-GPU simulation device based on the Gem5 framework for wafer-level systems, characterized in that, The simulation device includes the following modules: The environment setup module is used to set up a Gem5 system simulation environment, including downloading source files, compiling, and running. The GPU component creation module is used to create multiple GPU components in the Gem5 system and connect the L2 caches of multiple GPUs to the Directory, which then points them to the memory segments belonging to each GPU. The ROCk driver modification module is used to modify the ROCk (Radeon Open Compute kernel) driver, creating multiple software queues for one or more programs and assigning them to multiple GPUs, creating a doorbell region for each GPU; The test and verification module is used to perform simulation tests and verify the system performance of the multi-GPU wafer-level system using the built Gem5 system; Specifically, the GPU component creation module includes: The loop creation module is used to repeatedly create N GPU components from 0 to N during the GPU component creation process, where N is the number of GPUs. The component configuration module is used to create Shaders, Compute Units, HSAPacketProcessor, GPUDispatcher, and GPUCommandProcessor for each GPU component. The topology building module is used to rebuild the topology, connecting each GPU as a Node to the Directory, simulating the PCIe interaction mode. The memory mapping module is used to add a point within the Directory where each Node points to a different memory segment. The cache configuration module is used to add a cache to each GPU component in the Viper system of the GPU by repeatedly adding a cache from 0 to N in a loop; The TLB configuration module is used to set up a separate TLB hierarchy for each GPU component in the GPU's TLB configuration. The ROCk driver modification module specifically includes: The queue creation module is used to request ROCk to create a queue when user space code calls the system's ioctl function. ROCk obtains the GPU ID through the parameter of ioctl() and allocates the kernel to the corresponding GPU. The hash table creation module is used to create a hash table for ROCk to maintain the mapping between queues and GPUs, so that ROCk records the GPU corresponding to each queue; The doorbell region configuration module is used to create a doorbell region for each GPU; The offset configuration module is used to add the offset parameter to the input parameters of the mmap() function; The logic calculation module is used to add calculation logic to the mmap() function, which calculates the memory mapping address of the GPU in physical memory using the starting address, length, and offset value.

3. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method of claim 1.

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