Forming 3c-sic based electronic devices and 3c-sic electronic devices

Abstract

This disclosure relates to the formation of 3C-SiC-based electronic devices and 3C-SiC electronic devices. The method for manufacturing the electronic device includes the following steps: forming at least one implantation region having a second conductivity opposite to the first conductivity at the front side of a 4H-SiC solid-state substrate; forming a 3C-SiC layer on the front side; and forming an ohmic contact region in the 3C-SiC layer that extends through the entire thickness of the 3C-SiC layer until reaching the implantation region. A silicon layer may be present on the 3C-SiC layer; in this case, the ohmic contact also extends through the silicon layer.

Description

Technical Field

[0001] This disclosure relates to electronic devices formed at least in part of 3C-SiC and methods for manufacturing 3C-SiC electronic devices. Background Technology

[0002] As is known, semiconductor materials with wide bandgap, particularly bandgap energy values ​​Eg greater than 1.1 eV, low on-state resistance (RON), high thermal conductivity, high operating frequency, and high charge carrier saturation velocity are ideal for manufacturing electronic components, such as diodes or transistors, especially for power applications. Silicon carbide (SiC) is a material with these properties designed for manufacturing electronic components. Silicon carbide exists in different crystal forms, also known as polytypes. The most common polytypes are cubic polytypes (polytype 3C-SiC), hexagonal polytypes (polytypes 4H-SiC and 6H-SiC), and rhombic polytypes (polytype 15R-SiC).

[0003] Compared to similar devices mounted on silicon substrates, electronic devices mounted on silicon carbide substrates offer numerous advantages, such as lower output resistance during conduction, lower leakage current, higher operating temperature, and higher operating frequency. In particular, SiC Schottky diodes have demonstrated superior switching performance, making SiC electronic devices especially advantageous for high-frequency applications. Current applications place demands on both the electrical performance and long-term reliability of these devices.

[0004] 4H-SiC is commonly used as a substrate due to its easier fabrication compared to other polytypes. However, the larger bandgap (3.2 eV) of 4H-SiC compared to the corresponding bandgap of 3C-SiC (2.3 eV) or silicon (1.12 eV) makes it less attractive for some electronic applications. For example, in the case of Schottky barrier diodes, the ability to control the Schottky barrier height (SBH) is important to reduce power consumption and minimize conduction losses. Therefore, the implementation of metal / 3C-SiC or metal / Si contacts results in a lower SBH value compared to metal / 4H-SiC contacts, enabling the fabrication of more efficient Schottky diodes.

[0005] Furthermore, the breakdown voltage of SiC is also greater than that of silicon. This is because the critical electric field of silicon carbide is approximately ten times that of silicon. Another advantage typically associated with fabricating devices on a 4H-SiC substrate (bulk) is the retention of the breakdown voltage, but materials with lower band gaps at the surface (e.g., silicon or 3C-SiC) result in a lower barrier height for materials such as Schottky contacts. In other words, it is desirable to retain the advantages of reverse bias and optimize the voltage drop under forward bias.

[0006] Figure 1A transverse cross-sectional view in a Cartesian (triaxial) reference frame with X, Y, and Z axes is shown for a junction barrier Schottky (JBS) device, or a similarly combined PN Schottky (MPS) diode, indicated by reference numeral 1. Figure 1 The devices described herein are not necessarily prior art, and reference will be made to JBS device 1 below without loss of generality.

[0007] JBS device 1 includes: an N-type doped 4H-SiC substrate 3 having a first dopant concentration (e.g., including 1.10). 19 and 1.10 22 atoms / cm 3 The resistivity includes, for example, between 2 mΩ·cm and 40 mΩ·cm, having a surface 3a opposite to surface 3b, and a thickness including between 50 μm and 350 μm, more particularly between 160 μm and 200 μm, for example equal to 180 μm; a drift layer (epipolar growth) 2, made of N-type 4H-SiC, having a second dopant concentration lower than the first dopant concentration (e.g., including 10... 14 and 10 16 atoms / cm 3 The drift layer 2 has a layer of P-type implantation region 9' and an ohmic contact region 9'"; a cathode metallization 7, such as Ti / NiV / Ag or Ti / NiV / Au, extending on the ohmic contact region 6; an anode metallization 8, such as Ti / AlSiCu or Ni / AlSiCu, extending on the top surface 2a of the drift layer 2; a passivation layer 19 on the anode metallization 8 to protect the anode metallization; a plurality of junction barrier (JB) elements 9 in the drift layer 2 facing the top surface 2a of the drift layer 2, and each junction barrier element 9 includes a corresponding P-type implantation region 9' and an ohmic contact 9'"; and an edge termination region or guard ring 10 (optional), particularly a P-type implantation region, surrounding (completely or partially, depending on design selection) the JB elements 9.

[0008] A Schottky diode 12 is formed at the interface between the drift layer 2 and the anode metallization 8. Specifically, the Schottky (semiconductor-metal) junction is formed from a portion of the drift layer 2 that is in direct electrical contact with a corresponding portion of the anode metallization 8.

[0009] The region of the JBS device 1, including the JB element 9 and the Schottky diode 12 (i.e., the region contained within the guard ring 10), is the active region 4 of the JBS device 1.

[0010] refer to Figure 2A and 2B , Figure 1 Manufacturing steps of JBS device 1 ( Figure 2AThe method provides a step for mask-implanting a dopant (e.g., boron or aluminum) having a second conductivity type (P) in the drift layer 2. Figure 2A Arrow 18 in the diagram indicates implantation. Mask 11 is used for implantation, specifically a hard mask of silicon oxide or TEOS. In an exemplary embodiment, the implantation step includes implantation of one or more dopants having a second conductivity type, with an implantation energy between 30 keV and 400 keV and a dose of 1.10. 12 atoms / cm 2 and 1.10 15 atoms / cm 2 between.

[0011] This forms the injection region 9' and the edge termination region 10. The injection region 9' and the edge termination region 10 have depths between 0.2 μm and 1 μm, as measured from the surface 2a.

[0012] Then, in Figure 2B In the middle, remove mask 11 and perform a thermal annealing step to activate it. Figure 2A The dopant material is injected during the process. Thermal annealing is performed in a furnace at temperatures above 1600°C (e.g., 1700–1900°C, and in some cases even higher).

[0013] refer to Figure 3A -3C, then perform additional steps to form an ohmic contact 9". Reference Figure 3A A deposition mask 13, forming silicon oxide or TEOS, is formed to cover the surface area of ​​the drift layer 2 except for the injection region 9' (and the surface area of ​​the edge terminal 10, if any). In other words, the mask 13 has a through opening 13a at the injection region 9' (and optionally at at least a portion of the edge terminal 10). Then, in Figure 3B In the middle, on the mask 13 and the through opening 13a ( Figure 3B Nickel deposition is performed within the metal layer 14). The deposited nickel reaches and contacts the injection region 9' and the edge termination region 10 through the through opening 13a.

[0014] refer to Figure 3C The subsequent high-temperature thermal annealing (between 700°C and 1200°C, with time intervals from 1 minute to 120 minutes) allows the formation of ohmic contacts 9" of nickel silicide through a chemical reaction between the nickel deposited at the through-opening 13a and the silicon carbide (4H-SiC) of the drift layer 2. In effect, the deposited nickel reacts where it contacts the surface material of the drift layer 2 to form Ni2Si (i.e., the ohmic contact). Subsequently, the removal of the metal extending over the mask 13 and the removal of the mask 13 are performed.

[0015] After forming the ohmic contact, the method continues to form (e.g., by deposition) an anode metallization 8, such as Ti / AlSiCu or Ni / AlSiCu, on the top surface 2a of the drift layer 2 in direct electrical contact with the ohmic contact 9". A passivation layer 19 is then formed on the anode metallization layer 8 to protect the anode metallization. Consequently, a corresponding Schottky diode 12 is formed at the interface between the drift layer 2 and the anode metallization 8, laterally to the implantation region 9'. Specifically, the Schottky (semiconductor-metal) junction is formed from the portion of the drift layer 2 in direct electrical contact with the corresponding portion of the anode metallization 8 between the JB elements 9. Summary of the Invention

[0016] The purpose of this disclosure is to provide electronic devices formed at least in part of 3C-SiC and methods for manufacturing 3C-SiC electronic devices, in order to overcome the shortcomings of the prior art.

[0017] According to this disclosure, a method for manufacturing an electronic device and an electronic device as defined in the appended claims are provided.

[0018] In one embodiment, a method for manufacturing an electronic device includes forming at least one injection region having a second conductivity opposite to the first conductivity on the front side of a 4H-SiC solid-state substrate having a first conductivity. The method includes forming a 3C-SiC layer on the front side and forming an ohmic contact region in the 3C-SiC layer extending through the entire thickness of the 3C-SiC layer until reaching the injection region.

[0019] In one embodiment, the electronic device includes a 4H-SiC solid-state body having a first conductivity. The electronic device includes at least one implantation region having a second conductivity, opposing the first conductivity, extending on the front side of the solid-state body. The electronic device includes a 3C-SiC layer on the front side and an ohmic contact region extending through the entire thickness of the 3C-SiC layer to the implantation region. Attached Figure Description

[0020] To better understand this disclosure, preferred embodiments thereof will now be described by way of non-limiting example only with reference to the accompanying drawings, in which:

[0021] - Figure 1 A cross-sectional view of a JBS or MPS device according to one embodiment is shown;

[0022] Figure 2A and 2B An example is shown. Figure 1 Cross-sectional view of the intermediate manufacturing steps of the device;

[0023] Figure 3A -3C illustrates an embodiment in Figure 2A and2B The steps following the formation Figure 1 A cross-sectional view of the steps of the ohmic contact of the device;

[0024] Figure 4 A cross-sectional view of a JBS or MPS device according to an embodiment is shown;

[0025] Figure 5A and 5B An example is shown. Figure 4 Cross-sectional view of the intermediate manufacturing steps of the device;

[0026] Figure 6A -6D illustrates another embodiment Figure 4 A cross-sectional view of an intermediate manufacturing step of the device, which is... Figure 6A - An alternative to the embodiment of -6B;

[0027] Figure 7 A cross-sectional view of a JBS or MPS device according to another embodiment is shown;

[0028] Figure 8A -8C illustrates an embodiment Figure 7 Cross-sectional view of the intermediate manufacturing steps of the device;

[0029] Figure 9 A cross-sectional view shows a JBS or MPS device according to one embodiment;

[0030] Figure 10A -10D illustrates an embodiment Figure 9 Cross-sectional views of intermediate manufacturing steps of the device; and

[0031] Figure 11 A cross-sectional view of a planar MOSFET device according to another embodiment is shown. Detailed Implementation

[0032] and Figure 1 Common elements of the JBS devices are identified by the same reference numerals and will not be described further.

[0033] Figure 4 by Figure 1 A cross-sectional view of a JBS device 50 according to one embodiment is shown in a Cartesian (triaxial) reference system of X, Y, and Z axes. Figure 4 The view may resemble that of an MPS device (diode) (the following will refer only to JBS devices without losing generality).

[0034] JBS device 50 includes: a substrate 3 of N-type 4H-SiC having a first dopant concentration; an epitaxial drift layer 2 of N-type 4H-SiC having a second dopant concentration; a cubic silicon carbide (3C-SiC) layer 52 on surface 2a; an anode metallization layer 8, such as Ti / AlSiCu or Ni / AlSiCu, extending on the 3C-SiC layer 52; a passivation layer 19 on the anode metallization layer 8; and a plurality of implantation regions 9' in the drift layer 2, facing the top surface 2a of the drift layer 2, in contact with the substrate 3. At the interface of the C-SiC layer 52; a plurality of ohmic contacts 54 extending through the 3C-SiC layer at the corresponding implantation region 9' and forming a corresponding JB element 59 with the latter; an edge termination region or guard ring 10 (optional), particularly a P-type implantation region, completely or partially surrounding the JB element 9; an ohmic contact region or layer 6 (e.g., nickel silicide) extending on the surface 3b of the substrate 3; and a cathode metallization 7, such as Ti / NiV / Ag or Ti / NiV / Au, extending on the ohmic contact region 6.

[0035] One or more Schottky diodes 57 extend laterally to the implantation region 9' at the interface between the 3C-SiC layer 52 and the anode metallization 8. In particular, one or more Schottky (semiconductor-metal) junctions are formed from portions of the 3C-SiC layer 52 that are in direct electrical contact with corresponding portions of the anode metallization 8.

[0036] The region of the JBS device 50, including the JB element 59 and the Schottky diode 57 (i.e., the region contained within the guard ring 10, if any) is the active region 4 of the JBS device 50.

[0037] Figure 5A and 5B exist Figure 2A The intermediate manufacturing steps of the JBS device 50 according to an embodiment of the present disclosure are shown in the transverse cross-sectional views of the X, Y, Z axes in the Cartesian (triaxial) reference system of -2B, 3A, -3C, and 4.

[0038] Specifically, in execution Figure 2A and 2B Following the steps (which will not be described further here), the step of forming (e.g., growing) a cubic silicon carbide (3C-SiC) layer 52 on the surface 2a of the drift layer 2 is performed, as follows: Figure 5A As shown.

[0039] The growth of 3C-SiC on 4H-SiC substrates / layers is known in itself. The method used for this purpose is called the vapor-liquid-solid (VLS) mechanism, as described, for example, by Soueidan M et al., “A Vapor–Liquid–Solid Mechanism for Growing 3C-SiC Single-Domain Layers on 6H-SiC(0001)”, Advanced Functional Materials, vol. 16, pages 975-979, 02 May 2006.

[0040] Another approach is called sublimation extension (SE), as described by Valdas Jokubavicius et al. in “Lateral Enlargement Growth Mechanism of 3C-SiC on Off-Oriented 4H-SiC Substrates”, Crystal Growth & Design 2014 14(12), 6514-6520.

[0041] Another method is known from "Growth, Defects and Doping of 3C-SiC on Hexagonal Polytypes" by Rositsa Yakimova et al., ECS Journal of Solid State Science and Technology, Vol. 6, No. 10, p. 741, November 2017.

[0042] Then, the method continues to execute. Figure 5B It has the step of forming ohmic contact 54, using a previously referenced... Figure 3A - The process described in 3C is applicable to Figure 5B In this embodiment, specifically, the mask 13 is formed on the 3C-SiC layer 52, and the through opening 13a extends to reach the 3C-SiC layer 52. Therefore, the metal layer 14 extends to reach the 3C-SiC layer 52.

[0043] The formation of the ohmic contact involves depositing nickel within the opening 13a. The deposited nickel thus reaches and contacts the 3C-SiC 52 layer. Subsequent high-temperature heat treatment (with intervals between 1 minute and 120 minutes between 700°C and 1200°C) allows the formation of a nickel silicide ohmic contact 54 through a chemical reaction between the nickel deposited at the opening 13a and the silicon carbide (3C-SiC).

[0044] Alternatively, an opening 13a extending into the drift layer 2 can be formed in the implantation region 9'. In this case, the formation of the ohmic contact involves depositing nickel within the opening 13a until it reaches the implantation region 9'.

[0045] exist Figure 5B Following the first step, the method performs the following steps: forming (e.g., by deposition) an anode metallization 8, such as Ti / AlSiCu or Ni / AlSiCu, in direct electrical contact with the ohmic contact 54 on the 3C-SiC layer 52. Then, a passivation layer 19 is formed on the anode metallization layer 8 to protect the anode metallization. Therefore, a corresponding Schottky diode 57 is formed at the interface between the 3C-SiC layer 52 and the anode metallization 8, laterally to the ohmic contact 57.

[0046] Figure 6A -6D illustrates another method for forming the 3C-SiC layer 52.

[0047] In this case, the step of forming a cubic silicon carbide (3C-SiC) layer 52 on the surface 2a of the drift layer 2 can be performed by melting and resolidifying (crystallizing) the 4H-SiC material of the drift layer 2, as described by Choi, I., Jeong, H., Shin, H. et al., “Laser-induced phase separation of silicon carbide”, Nature Communications 7, 13562 (2016).

[0048] like Figure 6A As shown, the process results in the formation of a stack 60, comprising: a 3C-SiC layer 52 on a drift layer 2 of 4H-SiC; a silicon layer 56 on the 3C-SiC layer 52; and a carbon-rich layer 58 (e.g., graphite or including graphite or including a graphite layer) on the silicon layer 56. In one embodiment, the thickness of the 3C-SiC layer 52 is 10–200 nm, the thickness of the silicon layer 56 is 5–100 nm, and the thickness of the carbon-rich layer is 5–100 nm. Because the process requires a phase change at the top surface 2a of a portion of the drift layer 2, the drift layer 2 has a reduced thickness after the formation of the stack 60. From an electrical or functional point of view, this melting and crystallization step does not damage the implantation region 9'.

[0049] The 3C-SiC layer 52 and silicon layer 56 have essentially the same doping as the drift layer 2 of 4H-SiC, because the melting and crystallization steps do not require changing the dosage of the dopants already present in the drift layer 2.

[0050] The melting of the 4H-SiC material in drift layer 2 is specifically performed via laser processing, with the following configuration and operating parameters:

[0051] The wavelength is between 240 and 700 nm, especially 308 nm;

[0052] The pulse duration ranges from 20 ns to 500 ns, especially 160 ns;

[0053] The pulse number is between 1 and 16, especially 4;

[0054] Energy density is between 1.6 and 4 J / cm³ 2 Between, especially 2.6 J / cm 2 (Consider the layer at the top surface 2a);

[0055] The temperature is between 1400℃ and 2600℃, especially 2200℃ (considering the layer at surface 2a).

[0056] The area of ​​the beam spot 102 at the front side 2a level includes, for example, 0.7 and 1.5 cm². 2 between.

[0057] Following the melting step, the crystallization of the molten portion is carried out at a temperature of 1600–2600 °C for 200–600 ns. This forms the aforementioned stack 60.

[0058] Then, Figure 6B The oxidation steps of the carbon-rich layer 58 and the underlying silicon layer 56 are performed to form the corresponding oxide layers. This step is performed by immersing the wafer in a furnace at 800°C for 60 minutes. This facilitates the oxidation of both the carbon-rich layer 58 and the silicon layer 56. The corresponding oxidation of the 3C-SiC layer 52 and the 4H-SiC material of the substrate 3 and the epitaxial layer 2 will not occur.

[0059] Then, Figure 6C Subsequent baths in a suitable wet etching solution, such as BOE (buffered oxide etchant), allow for [further etching]. Figure 6B The oxide layer is completely removed in the step, exposing the 3C-SiC layer 52. Since the etching chemical solution selectively removes the material of the oxidized layers 56 and 58, etching is performed until the oxidized layer is completely removed without removing the underlying 3C-SiC layer 52.

[0060] Then, based on the references already provided Figure 5B The content described (i.e., following) Figure 3A - The 3C process (appropriate modifications have been discussed), in Figure 6D In the middle, the ohmic contact 54 penetrates the 3C-SiC layer 52 at the injection region 9' (and may be located at the ring 10, if any).

[0061] By using a properly configured laser source, the surface portion of the drift layer 2 (thus forming the 3C-SiC layer 52 as described above) can be melted simultaneously, and the doped material in the implanted region 9' can be activated. The relevant laser configuration parameters are as follows:

[0062] - Equal to or greater than 2.4 J / cm 2 The energy density (considered at the top surface 2a level),

[0063] - The number of pulses is between 1 and 16, for example, equal to 4.

[0064] - The duration of each pulse is between 20 and 500 ns, for example, equal to 160 ns.

[0065] - The wavelength of the emitted radiation is between 240 and 700, for example, equal to 308 nm.

[0066] In this embodiment, the reference may be omitted. Figure 2B The step of activating the dopant in the furnace.

[0067] exist Figure 6D Following the first step, the method performs the following steps: forming (e.g., by deposition) an anode metallization 8, such as Ti / AlSiCu or Ni / AlSiCu, in direct electrical contact with the ohmic contact 54 on the 3C-SiC layer 52. Then, a passivation layer 19 is formed on the anode metallization layer 8 to protect the anode metallization. Therefore, a corresponding Schottky diode 57 is formed at the interface between the 3C-SiC layer 52 and the anode metallization 8, laterally to the ohmic contact 57.

[0068] Figure 7 exist Figure 1 and Figure 4 A lateral cross-sectional view of the X, Y, and Z axes in a Cartesian (triaxial) reference frame shows the JBS device 80 according to an embodiment of the present disclosure.

[0069] Figure 1 JBS device 1 or Figure 4 The components common to the JBS device 50 are identified by the same reference numerals and need not be described again.

[0070] JBS device 80 includes: a substrate 3 of N-type 4H-SiC having a first dopant concentration; an epitaxial drift layer 2 of N-type 4H-SiC having a second dopant concentration; a cubic silicon carbide (3C-SiC) layer 52 on surface 2a; a silicon layer 56 on the 3C-SiC layer 52; an anode metallization 8, such as Ti / AlSiCu or Ni / AlSiCu, extending on the silicon layer 56; a passivation layer 19 on the anode metallization 8; and a plurality of implantation regions 9' in the drift layer 2, facing the top surface 2a of the drift layer 2, in contact with the 3C-SiC layer 52. At the interface of SiC layer 52; a plurality of ohmic contacts 84 extending through 3C-SiC layer 52 and through silicon layer 56 at corresponding implantation regions 9', and forming corresponding JB elements 89 together with the implantation regions; edge termination regions or guard rings 10 (optional), particularly P-type implantation regions, which completely or partially surround JB elements 9; ohmic contact regions or layers 6 (e.g., nickel silicide) extending on surface 3b of substrate 3; cathode metallization 7, such as Ti / NiV / Ag or Ti / NiV / Au, extending on ohmic contact regions 6.

[0071] One or more Schottky diodes 87 extend laterally to the implantation region 9' at the interface between the silicon layer 56 and the anode metallization 8. In particular, one or more Schottky (semiconductor-metal) junctions are formed from portions of the silicon layer 56 that are in direct electrical contact with corresponding portions of the anode metallization 8.

[0072] The region of the JBS device 80, including the JB element 89 and the Schottky diode 87 (i.e., the region contained within the guard ring 10, if any) is the active region 4 of the JBS device 80.

[0073] Figure 8A -8C shows the intermediate manufacturing steps of the JBS device 80 according to an embodiment of the present disclosure in a transverse cross-sectional view of a Cartesian (triaxial) reference system with X, Y, and Z axes.

[0074] In this case, the steps of forming cubic silicon carbide (3C-SiC) layer 52 and silicon layer 56 occur through the melting and recrystallization (crystallization) of the 4H-SiC material of drift layer 2, as shown in the reference. Figure 5A - 6D has already been discussed.

[0075] like Figure 8A As shown (corresponding to) Figure 5A Initially, this process led to the formation of Figure 6A The same stack already described, namely, a 3C-SiC layer 52 on a drift layer 2 comprising 4H-SiC, a silicon layer 56 on the 3C-SiC layer 52, and a carbon-rich (e.g., graphite or including graphite or including graphite layers) layer 58 on the silicon layer 56.

[0076] Then, Figure 8BThe step involves selectively removing the carbon-rich layer 58 without removing the underlying silicon layer 56. This step is performed, for example, by a plasma etching process in an O2 environment. Other chemicals or methods for selectively removing graphite can be used.

[0077] Then, in Figure 8C In this configuration, the ohmic contact 84 is formed at the implantation region 9' (and possibly at the guard ring 10, if present) through the silicon layer 56 and the 3C-SiC layer 52. For this purpose, reference has been made... Figure 3A The process described in -3C has been modified as appropriate to suit the situation discussed herein. Specifically, in this case, mask 13 is formed on silicon layer 56, and through opening 13a extends to reach silicon layer 56. Therefore, metal layer 14 extends to reach silicon layer 56.

[0078] The formation of the ohmic contact involves depositing nickel within the opening 13a. Subsequent high-temperature heat treatment (within time intervals of 1 minute to 120 minutes between 700°C and 1200°C) allows the formation of a nickel silicide ohmic contact 84 through a chemical reaction between the nickel and silicon deposited in layer 52 at the opening 13a.

[0079] In another implementation, the opening 13a extends into the 3C-SiC52 layer or drift layer 2 at the implantation region 9'. The formation of the ohmic contact involves depositing nickel within these openings 13a.

[0080] By using a properly configured laser source, the surface portion of the drift layer 2 can be melted simultaneously (thus forming the 3C-SiC layer 52 and the silicon layer 56 as described above) and the dopant in the implanted region 9' can be activated. The relevant laser configuration parameters are as follows:

[0081] - Equal to or greater than 2.4 J / cm 2 The energy density (considered at the top surface 2a level),

[0082] - The number of pulses is between 1 and 16, for example, equal to 4.

[0083] - The duration of each pulse is between 20 and 500 ns, for example, equal to 160 ns.

[0084] - The wavelength of the emitted radiation is between 240 and 700, for example, equal to 308 nm.

[0085] In this embodiment, the reference may be omitted. Figure 2B The step of activating the dopant in the furnace.

[0086] exist Figure 8CFollowing the first step, the method performs the following steps: forming (e.g., by deposition) an anode metallization 8, such as Ti / AlSiCu or Ni / AlSiCu, on the silicon layer 56 in direct electrical contact with the ohmic contact 84. Then, a passivation layer 19 is formed on the anode metallization layer 8 to protect the anode metallization. Consequently, a corresponding Schottky diode 87 is formed at the interface between the silicon layer 56 and the anode metallization 8, laterally to the ohmic contact 84.

[0087] Figure 9 exist Figure 7 A side section view of a Cartesian (triaxial) X, Y, Z reference system shows an electronic device (particularly a JBS) 100 device according to another embodiment.

[0088] and Figure 7 The common elements of the JBS80 devices are indicated by the same reference numerals and need not be described in detail again.

[0089] JBS device 100 includes: a substrate 3 of N-type 4H-SiC with a first dopant concentration; a drift (epitaxy) layer 2 of N-type 4H-SiC with a second dopant concentration; a cubic silicon carbide (3C-SiC) layer 52 on surface 2a; a silicon layer 56 on the 3C-SiC layer 52; a carbon-rich layer 58 on the silicon layer 56; an anode metallization layer 8, such as Ti / AlSiCu or Ni / AlSiCu, extending on the carbon-rich layer 58; a passivation layer 19 on the anode metallization layer 8; and a plurality of implantation regions 9' in the drift layer 2 facing the top surface 2 of the drift layer 2. a. At the interface with the 3C-SiC layer 52; a plurality of ohmic contacts 104 extending through the 3C-SiC layer 52, the silicon layer 56 and the carbon-rich layer 58 at the corresponding implantation regions 9' and forming corresponding JB elements 89 with the implantation regions; an edge termination region or guard ring 10 (optional) completely or partially surrounding the JB element 9, particularly a P-type implantation region; an ohmic contact region or layer 6 (e.g., nickel silicide) extending on the surface 3b of the substrate 3; a cathode metallization 7, such as Ti / NiV / Ag or Ti / NiV / Au, extending on the ohmic contact region 6.

[0090] One or more Schottky diodes 87 extend laterally to the implantation region 9' at the interface between the carbon-rich layer 58 and the anode metallization 8. Specifically, one or more Schottky (semiconductor-metal) junctions are formed from portions of the carbon-rich layer 58 that are in direct electrical contact with corresponding portions of the anode metallization 8. Note that the 3C-SiC 52 and silicon 56 layers, as well as the carbon-rich layer 58, have doped (N-type) drift layers 2 that form them, and are therefore conductive.

[0091] The region of the JBS device 100, including the JB element 89 and the Schottky diode 87 (i.e., the region contained within the guard ring 10, when present) is the active region 4 of the JBS device 100.

[0092] A carbon-rich layer 58 exists between the metallization layer 8 and the silicon layer 56, which has the function of preventing metal ions or metal contaminants from diffusing from the metallization layer 8 to the silicon layer 56, and from the silicon layer to the 3C-SiC layer 52, and thus to the drift layer 2.

[0093] Figure 10A -10D shows the intermediate manufacturing steps of the JBS device 100 according to an embodiment in a Cartesian (triaxial) reference frame with X, Y, and Z axes.

[0094] In this case, through the melting and recrystallization (crystallization) of the 4H-SiC material in the drift layer 2, the formation steps of the cubic silicon carbide (3C-SiC) layer 52, the silicon layer 56, and the carbon-rich layer 58 occur, as described above. Figure 5A -6D and Figure 8A The subject of discussion.

[0095] like Figure 10A As shown (which corresponds to) Figure 5A and Figure 8A The process initially resulted in the formation of the previously described stack (“stack”), namely, a 3C-SiC layer 52 on a 4H-SiC drift layer 2, a silicon layer 56 on the 3C-SiC layer 52, and a carbon-rich layer 58 (e.g., graphite or including graphite or including a graphite layer) on the silicon layer 56.

[0096] Then, in Figure 10B In the implantation region 9' (and guard ring 10, if present), an ohmic contact 104 is formed across the carbon-rich layer 58, the silicon layer 56, and the 3C-SiC layer 52. (See reference...) Figure 3A - The process described in -3C is used for this purpose and has been modified appropriately to suit the situation discussed herein. Specifically, in this case, a mask 13 is formed on the carbon-rich layer 58, and a through opening 13a extends to expose the carbon-rich layer 58.

[0097] The formation of the ohmic contact involves the deposition of nickel within the through opening 13a. (Reference) Figure 10C The subsequent high-temperature heat treatment (with time intervals between 1 minute and 120 minutes between 700°C and 1200°C) allows the formation of nickel silicide ohmic contacts 104 through a chemical reaction between the deposited nickel and the silicon present in layer 58.

[0098] Optionally, the through-opening 13a extends through the carbon-rich layers 58 until they reach the silicon layer 56; or, the through-opening 13a extends through the carbon-rich layers 58 and the silicon layer 56 until they reach the 3C-SiC layer 52; or, the through-opening 13a extends through the carbon-rich layers 58, the silicon layer 56, and the 3C-SiC layer 52 until they reach the implantation region 9' in the drift layer 2. In all these possible embodiments, after a high-temperature heat treatment (within a time interval of 1 minute to 120 minutes between 700°C and 1200°C), the nickel deposited in the through-opening 13a forms an ohmic contact 104 of nickel silicide through a chemical reaction between the deposited nickel and the silicon present in layers 56, 52, 2 (depending on the respective embodiments).

[0099] By using a properly configured laser source, the surface portion of the drift layer 2 (for forming the 3C-SiC layer 52, silicon layer 56, and carbon-rich layer 58 as described above) can be melted simultaneously, and the dopant species in the implanted region 9' can be activated. The relevant laser configuration parameters are as follows:

[0100] - Energy density of 2.4 J / cm³ or greater 2 (Considering the layer at the top surface 2a),

[0101] - The number of pulses is between 1 and 16, for example, equal to 4.

[0102] - The duration of each pulse is between 20 and 500 ns, for example, equal to 160 ns.

[0103] - The wavelength of the emitted radiation is between 240 and 700 nm, for example, equal to 308 nm.

[0104] In this embodiment, the reference may be omitted. Figure 2B The furnace dopant activation steps are described.

[0105] exist Figure 10B Following the steps in the previous section, a step is performed to form (e.g., by deposition) an anode metallization layer 8, for example, made of Ti / AlSiCu or Ni / AlSiCu; the anode metallization layer 8 is formed on the carbon-rich layer 58 and in direct electrical contact with the ohmic contact 104. Then, a passivation layer 19 is formed on the anode metallization layer 8 to protect the anode metallization. Therefore, a corresponding Schottky diode 87 is formed laterally to the ohmic contact 104 at the interface between the carbon-rich layer 58 and the anode metallization layer 8. This produces... Figure 9 Device 100.

[0106] according to Figure 11 In another embodiment shown, the formation of a stack of 3C-SiC layer 52, silicon layer 56 and carbon-rich layer 58 can be used to fabricate the gate terminal of a transistor (e.g., a MOSFET).

[0107] After forming the stacked 3C-SiC 52, silicon 56, and carbon-rich layer 58, a step of removing the carbon-rich layer 58 is performed at least in selected regions where the gate terminals of the electronic device are to be formed. For example, the carbon-rich layer 58 is removed in the region between the two implantation regions 9', exposing the underlying silicon layer 56.

[0108] Then a step is performed to oxidize a portion of the thus exposed silicon layer 56, thereby forming silicon oxide (SiO2), i.e. Figure 11 Part 56′ is shown.

[0109] In an alternative embodiment, the carbon-rich layer 58 is completely removed, for example, by shaping the silicon layer 56 using a photolithography process, so that the silicon layer 56 remains only between the two implantation regions 9'. The silicon layer 56 between the two implantation regions 9' is then oxidized to form a portion 56'.

[0110] The 3C-SiC layer 52 can also be removed from the side of portion 56' and remain below portion 56'.

[0111] The oxide portion 56' of the silicon layer 56 functions as a gate oxide. In a top view on the XY plane, the oxide portion 56' extends between two implanted regions 9', optionally partially overlapping portions of the two implanted regions 9'.

[0112] Therefore, a metal layer with gate metallization 110 function is formed on the oxide portion 56'.

[0113] The source and drain regions of a MOSFET can be formed in a manner that is obvious to those skilled in the art by performing an N-type injection within the P-type injection region 9'.

[0114] During use, the 3C-SiC layer 52 below the oxide portion 56' can participate in the formation of the conductive channel.

[0115] Upon examination of the features of this disclosure provided in accordance with this specification, the advantages offered are apparent.

[0116] In particular, the advantages of 4H-SiC substrates and the reduced bandgap values ​​of 3C-SiC or silicon (in various embodiments) can be fully utilized for forming JB elements and Schottky contacts, as previously described.

[0117] Finally, it is clear that modifications and variations may be made to the content described and shown herein without departing from the scope of this disclosure as defined by the appended claims.

[0118] For example, refer to Figure 6A and 8AThe described molten 4H-SiC step can be performed without the implantation region 9'. Therefore, in this case, the epitaxial layer 2 does not accommodate the implantation region 9', which is formed as follows:

[0119] i) After the step of removing the silicon 56 and carbon 58 layers (i.e., for each embodiment, immediately following the step of removing the silicon 56 and carbon 58 layers). Figure 6C (after the steps); or

[0120] ii) After the step of removing the carbon-rich layer 58 (i.e., for each embodiment, immediately following the step of removing the carbon-rich layer 58) Figure 8B (After the steps).

[0121] Furthermore, this disclosure is not limited to the fabrication of 3C-SiC JBS devices, but extends to the formation of ohmic contacts in common electronic devices such as MOSFETs (especially vertical-channel MOSFETs), IGBTs, JFETs, DMOS, and integrated PN Schottky (MPS) diodes. Due to the different electron mobilities between 3C-SiC and 4H-SiC, forming the channel of a vertical MOSFET in a 3C-SiC layer (rather than in other SiC polytypes, such as 4H-SiC) offers considerable advantages in terms of the device's output resistance.

[0122] In one embodiment, a method for manufacturing an electronic device may be summarized as including the following steps: forming at least one injection region having a second conductivity (P) opposite to the first conductivity (N) on the front side of a 4H-SiC solid-state body having a first conductivity (N); forming a 3C-SiC layer on the front side; and forming an ohmic contact region in the 3C-SiC layer that extends through the entire thickness of the 3C-SiC layer until reaching the injection region.

[0123] Forming a 3C-SiC layer may include performing the steps of growing 3C-SiC using VLS technology or SE technology.

[0124] Forming a 3C-SiC layer may include heating at least a portion of the front side of a solid-state substrate with a laser beam to at least the melting temperature of the 4H-SiC material; and allowing cooling and crystallization of the molten portion of the solid-state substrate to form a stack comprising: the 3C-SiC layer in contact with the solid-state substrate, a silicon layer on the 3C-SiC layer, and a carbon-rich layer on the silicon layer.

[0125] The method may also include the steps of completely removing the carbon-rich layer and silicon layer to expose the 3C-SiC layer.

[0126] Complete removal of the carbon-rich layer and silicon layer may include performing steps of oxidizing the silicon oxide layer and the carbon-rich layer, as well as etching the silicon oxide layer and oxidizing the carbon-rich layer.

[0127] The method may also include a step of completely removing the carbon-rich layer to expose the silicon layer.

[0128] Complete removal of the carbon-rich layer may include performing selective etching to remove the carbon-rich layer that retains the silicon layer.

[0129] The method may also include the step of forming an ohmic contact region over the entire thickness of the silicon layer up to the implantation region.

[0130] The method may also include the step of forming a metal layer on the 3C-SiC layer and the ohmic contact region, thereby forming a Schottky diode between the metal layer and the 3C-SiC, while forming a junction barrier JB diode between the metal layer and the ohmic contact region.

[0131] The method may further include the following steps: forming a first electrical terminal shared by the JB diode and the Schottky diode at the metal layer; and forming a second electrical terminal shared by the JB diode and the Schottky diode on the rear side opposite to the front side of the solid.

[0132] The electronic device can be one of the following: a combined PiN Schottky MPS device; a junction barrier Schottky JBS device; a MOSFET; an IGBT; a JFET; or a DMOS.

[0133] The electronic device can be summarized as including a solid-state body of 4H-SiC having a first conductivity (N); at least one injection region having a second conductivity (P) opposite to the first conductivity (N); a 3C-SiC layer on the front side; and an ohmic contact region extending through the entire thickness of the 3C-SiC layer to the injection region.

[0134] The device may further include a silicon layer on top of a 3C-SiC layer, with the ohmic contact region extending through the entire thickness of the silicon layer until it reaches the implantation region.

[0135] The solid-state host may include a 4H-SiC substrate; and a 4H-SiC epitaxial layer on the substrate, wherein the epitaxial layer is a drift layer of the electronic device.

[0136] The first conductivity can be N-type, while the second conductivity is P-type.

[0137] The device may further include a metal layer on the 3C-SiC layer and on the ohmic contact region, thereby forming a Schottky diode between the metal layer and the 3C-SiC layer, and a junction barrier JB diode between the metal layer and the ohmic contact region.

[0138] The device may also include a first electrical terminal shared with the JB diode and the Schottky diode at a metal layer; and a second electrical terminal shared with the JB diode and the Schottky diode at a rear side opposite to the front side of the solid.

[0139] The electronic device can be one of the following: a combined PiN Schottky MPS device; a junction barrier Schottky JBS device; a MOSFET; an IGBT; a JFET; or a DMOS.

[0140] Based on the detailed description above, these and other changes can be made to the embodiments. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full scope of equivalents enjoyed by these claims. Therefore, the claims are not limited to this disclosure.

Claims

1. A method for manufacturing an electronic device, the method comprising: At least one injection region having a second conductivity opposite to the first conductivity is formed on the front side of the solid-state matrix of 4H-SiC having a first conductivity. At least a portion of the front side of the solid body is heated using a laser beam to at least reach the melting temperature of the 4H-SiC material; The molten portion of the solid body is cooled and crystallized to form a stack of superimposed layers, the stack of superimposed layers including a 3C-SiC layer in contact with the solid body, a silicon layer on the 3C-SiC layer, and a carbon-rich layer on the silicon layer; The ohmic contact area is formed to extend through the stack until it reaches the injection area; as well as A first electrical terminal of conductive material is formed above and in direct contact with the carbon-rich layer.

2. The method of claim 1, wherein forming the first electrical terminal comprises depositing a metallic material above and in direct contact with the carbon-rich layer and the ohmic contact region.

3. The method of claim 2, wherein forming the first electrical terminal includes simultaneously forming a Schottky diode between the first electrical terminal and the carbon-rich layer and a junction barrier diode between the first electrical terminal and the ohmic contact region.

4. The method of claim 3, wherein the first electrical terminal is shared by the junction barrier diode and the Schottky diode, and the method further comprises forming a second electrical terminal shared by the junction barrier diode and the Schottky diode at a rear side opposite to the front side of the solid body.

5. The method according to claim 1, further comprising the following step: Selective portions of the carbon-rich layer that extend laterally into the implantation region are removed, thereby exposing corresponding portions of the underlying silicon layer; Oxidation is performed on the exposed portion of the silicon layer to form an oxidized portion; as well as A metallization portion is formed above and in contact with the oxide portion of the silicon layer.

6. The method of claim 5, wherein the oxide portion and the metallization portion of the silicon layer form the gate terminal of the electronic device.

7. The method of claim 6, further comprising: An additional implantation region having the second conductivity is formed at the front side of the solid body, the additional implantation region extending at a certain distance from the implantation region, wherein the selectively removed portion of the carbon-rich layer extends between the implantation region and the additional implantation region, and wherein one of the implantation region and the additional implantation region accommodates the conductive power electrode region of the electronic device, and the other of the implantation region and the additional implantation region accommodates the conductive drain electrode region of the electronic device. as well as Prior to performing the oxidation step, the portion of the silicon layer except for the portion extending between the implantation region and the additional implantation region is removed.

8. An electronic device, comprising: The solid-state matrix of 4H-SiC exhibits primary electrical conductivity. At least one injection region extends at the front side of the solid body, the at least one injection region having a second conductivity opposite to the first conductivity; A 3C-SiC layer is placed on the front side; A silicon layer is placed on the 3C-SiC layer. A carbon-rich layer is placed on the silicon layer; The ohmic contact region extends through the entire thickness of the 3C-SiC layer, the silicon layer, and the carbon-rich layer until it reaches the implantation region; as well as The first electrical terminal of the conductive material is located above the carbon-rich layer and is in direct contact with the carbon-rich layer.

9. The device according to claim 8, wherein the solid-state substrate is 4H-SiC and the carbon-rich layer is graphite.

10. The device of claim 8, wherein the solid-state substrate is 4H-SiC and the carbon-rich layer comprises graphite.

11. The device of claim 8, wherein the solid-state substrate is 4H-SiC and the carbon-rich layer comprises one or more graphite layers.

12. The device of claim 8, wherein the solid-state substrate is 4H-SiC and the carbon-rich layer comprises graphene.

13. The device of claim 8, wherein the solid-state substrate is 4H-SiC and the carbon-rich layer comprises graphite and graphene.

14. The device according to any one of claims 9-13, wherein the first electrical terminal is formed into a Schottky diode using the carbon-rich layer and into a junction barrier diode using the ohmic contact region.

15. The device of claim 14, wherein the first electrical terminal is shared by the junction barrier diode and the Schottky diode, and the electronic device further includes a second electrical terminal shared by the junction barrier diode and the Schottky diode at a rear side opposite the front side of the solid-state body.

16. The device according to any one of claims 9-13, wherein the electronic device is one of: a combined PiN Schottky MPS device; a junction barrier Schottky JBS device; a MOSFET; an IGBT; a JFET; or a DMOS.

17. An electronic device, comprising: The solid-state matrix of 4H-SiC exhibits primary electrical conductivity. A first injection region extends at the front side of the solid body, the first injection region having a second conductivity opposite to the first conductivity, and the first injection region including a source terminal. The second injection region, having the second conductivity, extends at a certain distance from the first injection region on the front side of the solid body, and the second injection region includes a drain terminal. A 3C-SiC layer is placed on the front side; A silicon layer is placed on the 3C-SiC layer. An ohmic contact region that extends through the entire thickness of the silicon layer and the 3C-SiC layer until it reaches the first implantation region and the second implantation region; as well as A first electrical terminal of a conductive material, the first electrical terminal of the conductive material being above the silicon layer and in direct contact with the ohmic contact region.

18. The electronic device of claim 17, comprising one or more of the following: a combined PiN Schottky MPS device; a junction barrier Schottky JBS device; a MOSFET; an IGBT; a JFET; or a DMOS.

19. A method for manufacturing an electronic device, the method comprising: At least one injection region having a second conductivity opposite to the first conductivity is formed on the front side of the solid-state matrix of 4H-SiC having a first conductivity. A 3C-SiC layer is formed on the front side; An ohmic contact region is formed in the 3C-SiC layer, the ohmic contact region extending through the entire thickness of the 3C-SiC layer until reaching the implantation region, wherein forming the 3C-SiC layer includes: At least a portion of the front side of the solid-state body is heated by a laser beam to at least reach the melting temperature of the 4H-SiC material; and The molten portion of the solid substrate is cooled and crystallized to form a stack of layers, the stack comprising: a 3C-SiC layer in contact with the solid substrate, a silicon layer on the 3C-SiC layer, and a carbon-rich layer on the silicon layer. Removing the carbon-rich layer includes one of the following: Perform the step of oxidizing the carbon-rich layer, and the subsequent step of etching the oxidized carbon-rich layer, or Etching is performed to selectively remove the carbon-rich layer.

20. The method of claim 19, further comprising completely removing the silicon layer to expose the 3C-SiC layer.

21. The method of claim 19, wherein the carbon-rich layer is graphite.

22. The method of claim 19, wherein the carbon-rich layer comprises graphite.

23. The method of claim 19, wherein the carbon-rich layer comprises one or more graphite layers.

24. The method of claim 19, wherein the carbon-rich layer comprises graphene.

25. The method of claim 19, wherein the carbon-rich layer comprises graphite and graphene.

26. The method of claim 19, wherein the electronic device comprises a Schottky diode having a carbon-rich layer and a junction barrier diode having an ohmic contact region.

27. The method of claim 26, wherein the first terminal is shared by the junction barrier diode and the Schottky diode, and the electronic device further includes a second terminal shared by the junction barrier diode and the Schottky diode at a rear side opposite the front side of the solid-state body.

28. The method of claim 19, wherein the electronic device is one of: a combined PiN Schottky MPS device; a junction barrier Schottky JBS device; a MOSFET; an IGBT; a JFET; or a DMOS.

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