Quantum processor architecture with compiler support

Abstract

Techniques are provided regarding superconducting quantum processor architectures and / or VQE compiler optimizations. For example, one or more embodiments described herein can involve an apparatus comprising a superconducting quantum processor topology that employs an X-tree architecture to depict connections between superconducting qubits, where a total number of the connections can be less than a total number of the superconducting qubits.

Description

Background Technology

[0001] This disclosure relates to compiler support for variational quantum eigenfunction solver (“VQE”) algorithms capable of utilizing multilevel hierarchical tree architectures, and more specifically, to compiler optimizations capable of mapping VQE algorithms to quantum processors with multilevel hierarchical tree architectures (e.g., X-tree architectures). Summary of the Invention

[0002] The following overview is presented to provide a basic understanding of one or more embodiments of the invention. This overview is not intended to identify key or essential elements, or to depict any scope of a particular embodiment or any scope of the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that follows. In one or more embodiments described herein, systems, computer-implemented methods, apparatuses, and / or computer program products are described that can utilize domain knowledge and / or program semantics to guide quantum bit connectivity architectures and / or compiler optimizations for one or more VQE algorithms.

[0003] According to an embodiment, an apparatus is provided. The apparatus may include a superconducting quantum processor topology, which may employ an X-tree architecture to depict the connections between superconducting qubits. The total number of these connections may be less than the total number of superconducting qubits.

[0004] According to an embodiment, a system is provided. The system may include a memory storing computer-executable components. The system may also include a processor operatively coupled to the memory, the processor being capable of executing the computer-executable components stored in the memory. These computer-executable components may include a compiler component that maps a variational quantum eigenvalue solver algorithm to a superconducting quantum processor, the superconducting quantum processor including qubit connectivity characterized by a multi-level hierarchical tree architecture.

[0005] According to an embodiment, a computer-implemented method is provided. This computer-implemented method may include mapping a variational quantum eigenvalue solver algorithm to a superconducting quantum processor via a system operatively coupled to the processor, the superconducting quantum processor including qubit connectivity characterized by a multi-level hierarchical tree architecture. Attached Figure Description

[0006] Figure 1A-1B A diagram of an example, non-limiting X-tree architecture for a superconducting quantum processor according to one or more embodiments described herein is shown.

[0007] Figure 2 A graph illustrating an example, non-limiting plot of one or more embodiments described herein is shown, which may demonstrate the effectiveness of one or more X-tree architectures for superconducting quantum processors.

[0008] Figure 3 A block diagram of a non-limiting system is shown, illustrating examples of one or more quantum compiler optimizations tailored for a VQE algorithm, according to one or more embodiments described herein, which minimizes the mapping overhead on a sparse qubit-connected quantum processor.

[0009] Figure 4 A block diagram of an example, non-limiting system is shown, according to one or more embodiments described herein, which can map physical and / or logical qubits represented by one or more Pauli strings to a multi-level hierarchical tree characterizing the connectivity of the qubits.

[0010] Figure 5 A diagram illustrating an example, non-restrictive layout and mapping method that can be implemented by one or more quantum compilers according to one or more embodiments described herein.

[0011] Figure 6 A block diagram of an example, non-limiting system of synthesis and routing methods that can be employed to merge to the root according to one or more embodiments described herein, wherein the synthesis and routing of quantum circuits of the VQE algorithm can be performed in combination.

[0012] Figure 7 A diagram illustrates an example, non-restrictive synthesis and routing method for incorporating into a root, which can be adopted by one or more quantum compilers according to one or more embodiments described herein.

[0013] Figure 8 A non-limiting diagram illustrating examples of the effectiveness of one or more quantum compilers that can employ synthesis and routing methods merged into the root, according to one or more embodiments described herein.

[0014] Figure 9 A computer-implemented method according to one or more embodiments described herein is illustrated, which can help map the VQE algorithm onto one or more superconducting quantum processors with a sparse qubit interconnect architecture while reducing mapping overhead.

[0015] Figure 10 A computer-implemented method according to one or more embodiments described herein is illustrated, which can help map the VQE algorithm onto one or more superconducting quantum processors with a sparse qubit interconnect architecture while reducing mapping overhead.

[0016] Figure 11 A cloud computing environment according to one or more embodiments described herein is depicted.

[0017] Figure 12 An abstract model layer is described according to one or more embodiments described herein.

[0018] Figure 13 A block diagram illustrating an example, non-limiting operating environment that may facilitate one or more embodiments described herein. Detailed Implementation

[0019] The following detailed description is illustrative only and is not intended to limit the embodiments and / or their application or use. Furthermore, it is not intended to be construed as being limited by any express or implied information presented in the preceding Background or Summary of the Invention or Detailed Description sections.

[0020] One or more embodiments will now be described with reference to the accompanying drawings, wherein like reference numerals are used throughout to refer to like elements. In the following description, numerous specific details are set forth for purposes of explanation in order to provide a more thorough understanding of the one or more embodiments. However, it will be apparent that, in various cases, the one or more embodiments described may be practiced without these specific details.

[0021] As the number of hardware resources (e.g., qubits and / or qubit connections) employed in a superconducting quantum processor increases, its fabrication becomes more difficult. For example, for each connected qubit pair, there is a probability that frequency collisions (e.g., hardware defects) will occur. Moreover, increased qubit connectivity can lead to a higher chance of crosstalk in quantum gates. Therefore, quantum processors with dense qubit connections typically have lower yields and / or poorer performance.

[0022] In contrast, limiting the number of qubit connections can prevent some two-qubit gates in quantum programs from being directly executed, as they can only be implemented between two adjacent physical qubits. Traditional quantum compilers use qubit mapping and / or routing iterations to insert additional operations to address these two-qubit dependencies. However, existing quantum compilers are typically at the gate level and cannot utilize higher-level field knowledge, resulting in high mapping overhead.

[0023] Various embodiments of the present invention may relate to computer processing systems, computer-implemented methods, apparatuses, and / or computer program products that facilitate the efficient, effective, and autonomous (e.g., without direct human guidance) synthesis of quantum circuits (e.g., Pauli string-simulated quantum circuits) based on qubit connectivity mapping and / or underlying quantum hardware architectures using VQE algorithms. For example, one or more embodiments described herein can map one or more VQE algorithms to a sparsely connected superconducting quantum processor architecture with minimal mapping overhead.

[0024] The computer processing systems, computer-implemented methods, apparatuses, and / or computer program products employ hardware and / or software to solve problems that are inherently highly technical (e.g., quantum processor architectures and / or quantum compiler optimizations tailored for VQE algorithms), not abstract, and cannot be performed as a set of human mental behaviors. For example, an individual or groups of individuals cannot compile and map Pauli strings to one or more quantum processor architectures to execute one or more VQE algorithms according to the different embodiments described herein.

[0025] Furthermore, one or more embodiments described herein can constitute a technical improvement over conventional quantum compilers by mapping the Pauli strings used in the VQE algorithm to qubit connectivity characterized by a multi-level hierarchical tree architecture. Additionally, the different embodiments described herein can demonstrate technical improvements over conventional quantum compilers by adaptively synthesizing each quantum circuit according to the evolving logic-to-physical qubit mapping. For example, the different embodiments described herein can be combined to perform quantum circuit synthesis and routing to reduce mapping overhead.

[0026] Furthermore, one or more embodiments described herein can be practically applied by executing one or more VQE algorithms (e.g., for analyzing one or more chemical simulations) by taking into account high-level domain knowledge and / or program semantics. For example, the different embodiments described herein can enable the execution of complex VQE algorithms, such as quantum chemistry algorithms, on sparsely connected superconducting quantum processor architectures.

[0027] Figure 1A-1B A diagram illustrating an example, non-limiting tree structure is shown, which can exemplify an X-tree architecture 100 that can characterize the qubit connectivity of a superconducting quantum processor. According to one or more embodiments described herein, the X-tree architecture 100 can exemplify a type of multi-level hierarchical tree architecture that can be used to reduce the mapping overhead performed by one or more quantum compilers.

[0028] VQE algorithms can be executed by one or more quantum computing programs that use Pauli string simulation circuits. For example, a variable quantum chemistry simulation program can use one or more VQE algorithms to find the ground state energy of a chemical system (e.g., a molecule). In a variable quantum chemistry simulation program, the basic building blocks of a chemically inspired ansatz (start) can be Pauli string simulation quantum circuits, which can simulate the time evolution of Pauli strings using parameters.

[0029] The quantum gates (such as two-qubit gates, e.g., controlled-NOT (“CNOT”) gates) in each of the Pauli string simulated quantum circuits can be formed into a tree structure to depict qubit connectivity. This tree structure can be used to guide the design of physical qubit connectivity within a superconducting quantum processor. Furthermore, the quantum gates (e.g., CNOT gates) in each of the Pauli string simulated quantum circuits can be synthesized into the tree structure without affecting the functionality of the circuit. For example, the same Pauli string can be characterized by various corresponding qubit connectivity layouts. The different embodiments described herein can leverage the flexibility of Pauli string simulated quantum circuits to design one or more compiler optimizations tailored to the execution of VQE algorithms (e.g., to the execution of one or more variable quantum chemistry simulation programs).

[0030] Example X-tree architecture 100 can characterize the qubit connectivity of Pauli string simulation quantum circuits. For example... Figure 1A-1B As shown, the X-tree architecture 100 can represent a superconducting quantum processor topology with sparse qubit connections. As used herein, the term "sparse qubit connection" and / or its grammatical variations can refer to one or more superconducting quantum processor topologies where the total number of connections between superconducting qubits is less than the total number of superconducting qubits. For example, the X-tree architecture 100 can characterize a superconducting quantum processor with sparse qubit connections, at least because the X-tree architecture 100 uses one less qubit than the total number of qubits. For example, for "N" qubits, the X-tree architecture 100 uses "N-1" connections to connect all the qubits.

[0031] like Figure 1A-1B As shown, the X-tree architecture 100 can represent qubit connectivity as a tree structure without loops. The X-tree architecture 100 may include multiple nodes 102 (e.g., represented by circles) coupled together via multiple connections 104 (e.g., represented by lines). Each node 102 may represent a corresponding superconducting qubit, and each connection 104 may represent a qubit connection (e.g., via a two-qubit gate, such as a CNOT gate). Among the nodes 102, one or more leaf nodes may be nodes 102 that branch from the corresponding root node (e.g., via connection 104).

[0032] For example, Figure 1AA first example X-tree architecture 100a is depicted, comprising five nodes 102 to represent the connectivity between five superconducting qubits. For clarity, the nodes 102 are also numbered with corresponding labels (e.g., first node 102, second node 102, third node 102, fourth node 102, and / or fifth node 102). In the first example X-tree architecture 100a, the second node 102, third node 102, fourth node 102, and / or fifth node 102 can be leaf nodes with respect to the first node 102, which can therefore be the root node. For example, the second node 102, third node 102, fourth node 102, and / or fifth node 102 can branch from the first node 102. Thus, the first example X-tree architecture 100a can depict a first qubit (e.g., represented by a first node 102) connected via a first quantum gate (e.g., a CNOT gate) to a second qubit (e.g., represented by a second node 102); connected via a second quantum gate (e.g., a CNOT gate) to a third qubit (e.g., represented by a third node 102); connected via a third quantum gate (e.g., a CNOT gate) to a fourth qubit (e.g., represented by a fourth node 102); and / or connected via a fourth quantum gate (e.g., a CNOT gate) to a fifth qubit (e.g., represented by a fifth node 102). Figure 1A As shown, the first example X-tree architecture 100a can characterize qubit connectivity, where five qubits can be coupled via four qubit connections to facilitate a superconducting quantum processor with sparse qubit connections.

[0033] Additionally, the size of the X-tree architecture 100 can be increased by adding one or more additional nodes 102 to one or more leaf nodes. For example, Figure 1A The second example X-tree shown in the example X-tree architecture 100b includes eight nodes 102 to represent the connectivity between eight superconducting qubits. Specifically, the sixth node 102, the seventh node 102, and / or the eighth node 102 can be further connected to the fifth node 102. Accordingly, the fifth node 102 can be considered a leaf node with respect to the first node 102 (e.g., whereby the first node 102 can be a paired root node), and is a root node with respect to the sixth node 102, the seventh node 102, and / or the eighth node 102 (e.g., whereby the sixth node 102, the seventh node 102, and / or the eighth node 102 can be paired corresponding leaf nodes). Figure 1A As shown, the second example X-tree architecture 100b can characterize qubit connectivity, where eight qubits can be coupled through seven qubit connections to assist a superconducting quantum processor with sparse qubit connections.

[0034] Furthermore, by adding additional leaf nodes, the X-tree architecture 100 can continue to grow to characterize superconducting quantum processor topologies that include even more qubits. For example, Figure 1A The third example X-tree architecture 100c shown can represent 26 qubits coupled through a 25-qubit connection. For example... Figure 1A As illustrated, the X-tree architecture 100 is not limited to a specific number of qubits; rather, the X-tree architecture 100 can be scaled up to accommodate any desired number of qubits by adding leaf nodes to extend the branches of the X-tree architecture 100. In one or more embodiments, each node 102 may be coupled via four or fewer connections 104 (e.g., node 102 may serve as the root node of four or fewer leaf nodes).

[0035] like Figure 1B As shown, the X-tree architecture 100 can be further divided into multiple levels (e.g., extending from the central region of the X-tree architecture 100 to the peripheral region of the X-tree architecture 100). For example, Figure 1B The fourth example X-tree architecture 100d is depicted. The fourth example X-tree architecture 100d may include seventeen nodes 102 (e.g., representing 17 qubits) connected via sixteen connections 104 (e.g., representing 16 qubit connections). Furthermore, the fourth example X-tree architecture 100d may be divided into three levels: level 0, level 1, and / or level 2. For clarity, in Figure 1B The boundary of level 0 is depicted using dark gray shading. Figure 1B The boundary of level 1 was depicted using light gray shading, and... Figure 1B The boundaries of the two levels are depicted against a white background. The boundaries of each level allow the connection 104 between the root node and leaf node pairs to span between different levels. In various embodiments, the physical qubits represented in the X-tree architecture 100 can be located at different levels from the root node to the leaf node. Additionally, each node 102 located at the outermost level (e.g., the highest level) of the X-tree architecture 100 can be a leaf node.

[0036] For example, regarding the fourth example X-tree architecture 100d, the second node 102, the third node 102, the fourth node 102, and / or the fifth node 102 can be leaf nodes of the first node 102 (e.g., the root node). Furthermore, the first node 102 can be located at level 0; while the second node 102, the third node 102, the fourth node 102, and / or the fifth node 102 can be located at level 1. Therefore, the connection 104 between the second node 102, the third node 102, the fourth node 102, and / or the fifth node 102 (e.g., leaf nodes) and the first node 102 (e.g., the root node) can traverse between levels 0 and 1 (e.g., it can span between levels 0 and 1).

[0037] Similarly, the second node 102, the third node 102, the fourth node 102, and / or the fifth node 102 can be the root node with respect to node 102 located within level 2. For example, the second node 102 can be the root node with respect to node 15, node 16, and / or node 17. Figure 1B As shown, the second node 102 can be located within level 1; while the 15th node 102, the 16th node 102, and / or the 17th node 102 can be located within level 2. Therefore, the connection 104 between the 15th node 102, the 16th node 102, and / or the 17th node 102 (e.g., leaf nodes) and the second node 102 (e.g., the root node relative to the 15th node 102, the 16th node 102, and / or the 17th node 102) can traverse between level 1 and level 2 (e.g., can span between level 1 and level 2).

[0038] As the branches of the X-tree architecture 100 grow, the number of levels in the X-tree architecture 100 can increase. For example, in the case where an additional node 102 is added to the fourth example X-tree architecture 100d, the additional node 102 can be added as a leaf node and positioned within level 3 (not shown) in the X-tree architecture 100. Thus, the X-tree architecture 100 can be implemented as a multi-level hierarchical tree architecture.

[0039] Figure 2 A non-limiting graph 200 illustrating examples of one or more embodiments described herein is shown, illustrating the effectiveness of a superconducting quantum processor topology characterized by an X-tree architecture 100. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. Figure 200 compares a fourth example X-tree architecture 100d with a conventional grid architecture “Grid17Q” (e.g., a conventional seventeen-node grid, where each node is coupled via at least two connections). Graph 200 shows that the superconducting quantum processor characterized by the X-tree architecture 100 (e.g., a seventeen-qubit superconducting quantum processor characterized by a 17-node grid) can achieve approximately eight times higher yields compared to a superconducting quantum processor characterized by conventional two-dimensional grid connections (e.g., a seventeen-qubit superconducting quantum processor characterized by a 17-node grid connection). Thus, the X-tree architecture 100 can realize an efficient superconducting quantum processor architecture with sparse qubit connections and high yields.

[0040] Figure 3A block diagram of an example, non-limiting system 300 is shown, which can map one or more VQE algorithms to a multi-level hierarchical architecture of qubit connectivity (e.g., X-tree architecture 100) to generate one or more quantum circuits for executing quantum programs (e.g., variational quantum chemistry simulations). For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. Aspects of systems (e.g., system 300, etc.), apparatuses, or processes in the various embodiments of the invention may constitute one or more machine-executable components implemented within one or more machines (e.g., implemented in one or more computer-readable media associated with one or more machines). Such components, when executed by one or more machines (e.g., computers, computing devices, virtual machines, combinations thereof, and / or the like), cause the machines to perform the described operations.

[0041] like Figure 3 As shown, system 300 may include one or more servers 302, a network 304, an input device 306, and / or a quantum processor 308. Server 302 may include a compiler component 310. Compiler component 310 may further include a communication component 312 and / or a layout component 314. Furthermore, server 302 may include at least one memory 316 or otherwise associated with at least one memory 316. Server 302 may also include a system bus 318, which may be coupled to different components, such as, but not limited to, compiler component 310 and associated components, memory 316, and / or processor 320. Although in Figure 3 Server 302 is shown, but in other embodiments, multiple devices of various types can be used. Figure 3 The features shown are associated with or include Figure 3 The features shown are described above. Furthermore, server 302 can communicate with one or more cloud computing environments.

[0042] One or more networks 304 may include wired and wireless networks, including but not limited to cellular networks, wide area networks (WANs) (e.g., the Internet), or local area networks (LANs). For example, server 302 may communicate with one or more input devices 306 and / or quantum processor 308 using virtually any desired wired or wireless technology (and vice versa), such technologies including but not limited to: cellular, WAN, Wi-Fi, Wi-Max, WLAN, Bluetooth, combinations thereof, and / or the like. Furthermore, although compiler component 310 may be provided on one or more servers 302 in the illustrated embodiment, it should be understood that the architecture of system 300 is not limited thereto. For example, compiler component 310 or one or more components of compiler component 310 may be located at another computer device (e.g., another server device, client device, combinations thereof, and / or the like).

[0043] One or more input devices 306 may include one or more computerized devices, including but not limited to: personal computers, desktop computers, laptop computers, cellular phones (e.g., smartphones), computerized tablets (e.g., including processors), smartwatches, keyboards, touchscreens, mice, combinations thereof, and / or the like. One or more VQE algorithm inputs (e.g., Hamiltonians, quantum programs, quantum circuits, Pauli strings, combinations thereof, and / or the like) may be input into system 300 using one or more input devices 306, thereby sharing the data with server 302 (e.g., via a direct connection and / or via one or more networks 304). For example, one or more input devices 306 may send data to communication component 312 (e.g., via a direct connection and / or via one or more networks 304). Furthermore, one or more input devices 306 may include one or more displays capable of presenting one or more outputs generated by system 300 to a user. For example, one or more displays may include, but are not limited to: cathode ray tube displays (“CRT”), light-emitting diode displays (“LED”), electroluminescent displays (“ELD”), plasma display panels (“PDP”), liquid crystal displays (“LCD”), organic light-emitting diode displays (“OLED”), combinations thereof and / or the like.

[0044] In various embodiments, one or more input devices 306 and / or one or more networks 304 may be used to input one or more settings and / or commands into system 300. For example, in the various embodiments described herein, one or more input devices 306 may be used to operate and / or manipulate server 302 and / or associated components. Additionally, one or more input devices 306 may be used to display one or more outputs (e.g., displays, data, visualizations, etc.) generated by server 302 and / or associated components. Furthermore, in one or more embodiments, one or more input devices 306 may be included within and / or operatively coupled to a cloud computing environment.

[0045] For example, in different embodiments, one or more input devices 306 may be used to input one or more initial quantum Hamiltonians into system 300 for analysis via one or more VQE algorithms. For example, the initial quantum Hamiltonians may include the sum of Pauli matrices and / or may be obtained by applying one or more versions of Jordan-Wigner coding. The initial quantum Hamiltonians may characterize the interparticle interactions of a chemical system, which may be a set of separable or inseparable operators that can cause a wavefunction to evolve into a stationary eigenstate (e.g., where its eigenvalues ​​are energies). In one or more embodiments, system 300 may be initialized with atomic coordinates (e.g., internal or absolute) of one or more given molecule and / or atom types / basis sets, from which the initial quantum Hamiltonians can be derived.

[0046] In various embodiments, one or more quantum processors 308 may include quantum hardware devices that can leverage the laws of quantum mechanics (e.g., superposition and / or quantum entanglement) to facilitate computational processing (e.g., while simultaneously satisfying the DiVincenzo criterion). In one or more embodiments, one or more quantum processors 308 may include a quantum data plane, a control processor plane, a control and measurement plane, and / or qubit technology.

[0047] In one or more embodiments, a quantum data plane may include one or more quantum circuits comprising physical qubits, structures for positioning these qubits, and / or support circuitry. The support circuitry may, for example, facilitate the measurement of the states of the qubits and / or the performance of gate operations on the qubits (e.g., for gate-based systems). In some embodiments, the support circuitry may include a wiring network that enables multiple qubits to interact with each other. Furthermore, the wiring network may facilitate the transmission of control signals via direct electrical connections and / or electromagnetic radiation (e.g., optical, microwave, and / or low-frequency signals). For example, the support circuitry may include one or more superconducting resonators operatively coupled to one or more qubits. As described herein, the term "superconducting" can characterize a material exhibiting superconducting properties at or below a superconducting critical temperature, such as aluminum (e.g., a superconducting critical temperature of 1.2 Kelvin) or niobium (e.g., a superconducting critical temperature of 9.3 Kelvin). Furthermore, those skilled in the art will recognize that other superconducting materials (e.g., hydride superconductors, such as lithium hydride / magnesium hydride alloys) may be used in the different embodiments described herein.

[0048] In one or more embodiments, the control processor plane can identify and / or trigger a sequence of Hamiltonians for quantum gate operations and / or measurements, wherein the sequence executes a program (e.g., provided by a host processor (such as server 302) via compiler component 310) for implementing a quantum algorithm (e.g., a VQE algorithm). For example, the control processor plane can translate compiled code into commands for controlling and measuring the plane. In one or more embodiments, the control processor plane can further execute one or more quantum error correction algorithms.

[0049] In one or more embodiments, the control and measurement plane can convert digital signals (which can describe the quantum operations to be performed) generated by the control processor plane into analog control signals to perform these operations on one or more qubits in the quantum data plane. Furthermore, the control and measurement plane can convert one or more analog measurement outputs of the qubits in the data plane into classical binary data that can be shared with other components of the system 300.

[0050] Those skilled in the art will recognize that various qubit technologies can provide the basis for one or more qubits of one or more quantum processors 308. Two exemplary qubit technologies may include trapped ion qubits and / or superconducting qubits. For example, in the case where quantum processor 308 utilizes trapped ion qubits, the quantum data plane may include multiple ions acting as qubits and one or more wells used to hold the ions in a specific location. Furthermore, the control and measurement plane may include: a laser or microwave source that is directed to one or more ions to influence the quantum state of the ions; a laser used to cool and / or enable measurement of the ions; and / or one or more photon detectors used to measure the state of the ions. In another instance, superconducting qubits (e.g., superconducting quantum interference devices "SQUIDs") may be photolithographically defined electronic circuits that can be cooled to millikelvin temperatures to exhibit quantized energy levels (e.g., quantized states due to charge or magnetic flux). Superconducting qubits may be based on Josephson junctions, such as transmon qubits, etc. Furthermore, superconducting qubits are compatible with microwave-controlled electronics and can be used with gate-based technologies or integrated cryogenic control. Other exemplary qubit technologies may include, but are not limited to: photonic qubits, quantum dot qubits, gate-based neutral atom qubits, semiconductor qubits (e.g., optically or electrically gated), topological qubits, combinations thereof, and so on.

[0051] In one or more embodiments, the communication component 312 may receive one or more initial quantum Hamiltonians from one or more input devices 306 (e.g., via direct electrical connections and / or through one or more networks 304) and share data with different associated components of the compiler component 310. Additionally, the communication component 312 may facilitate data sharing between the compiler component 310 and one or more quantum processors 308, and / or vice versa (e.g., via direct electrical connections and / or through one or more networks 304).

[0052] In various embodiments, one or more quantum processors 308 may include one or more VQE components 322 (e.g., included within a control processor plane) capable of executing one or more VQE algorithms on the quantum processor 308. In one or more embodiments, one or more VQE components 322 and compiler component 310 may work in combination to execute an iterative VQE algorithm based on one or more initial quantum Hamiltonians. For example, one or more VQE components 322 and / or compiler component 310 may work in combination to perform one or more variable quantum chemistry simulations.

[0053] As used herein, the term “variable quantum eigenvalue solver (“VQE”) algorithm” and its syntactic variations may refer to one or more hybrid quantum-classical computing algorithms that can share computational work between classical computing hardware (e.g., via one or more servers 302 of compiler component 310) and quantum computing hardware (e.g., via one or more quantum processors 308 of VQE component 322) to reduce the long coherence time required by fully quantum phase estimation algorithms. The VQE algorithm can be initialized with one or more assumptions about the form of the target wavefunction. Based on these one or more assumptions, an ansatz with one or more tunable parameters can be constructed, and quantum circuits capable of generating the ansatz (e.g., Pauli string simulation quantum circuits) can be designed. Throughout the execution of the VQE algorithm, the ansatz parameters can be varied to minimize the expected value of the resulting Hamiltonian matrix. The classical computing hardware (e.g., via one or more servers 302 of compiler component 310) can pre-compute one or more terms of the Hamiltonian matrix and / or update the parameters during optimization of the quantum circuit. Quantum hardware (e.g., one or more quantum processors 308 via VQE component 322) can prepare quantum states (e.g., defined by a set of ansatz parameter values ​​for the current iteration) and / or perform measurements of different interaction terms in the Hamiltonian matrix. State preparation can be repeated over multiple iterations until each individual operator has been measured a sufficient number of times to derive sufficient statistics. Furthermore, the efficiency of the VQE algorithm can be improved by using the particle-hole mapping of the quantum Hamiltonian to generate improved starting points for the trajectory wavefunction. Further, methods to reduce the number of qubits required for electronic structure computation (e.g., qubit tapering) can eliminate redundant degrees of freedom in the Hamiltonian.

[0054] In various embodiments, compiler component 310 may map one or more VQE algorithms to one or more quantum processors 308, wherein the one or more quantum processors 308 may have qubit connectivity characterized by a multi-layered hierarchical tree architecture. Further, in various embodiments, the one or more quantum processors 308 may have sparse qubit connectivity. For example, the one or more quantum processors 308 may have a topology characterized by an X-tree architecture 100. For example, the one or more quantum processors 308 may have sparse qubit connectivity characterized by an X-tree architecture 100, which may be utilized by compiler component 310 to minimize mapping overhead while synthesizing and / or routing one or more quantum lines to perform VQE algorithms (e.g., to perform variational quantum chemistry simulations).

[0055] In one or more embodiments, layout component 314 may generate a hierarchical layout for both physical qubits of one or more quantum processors 308 and / or logical qubits included in one or more Pauli strings adopted by one or more VQE algorithms. For example, assuming one or more quantum processors 308 have a multi-level hierarchical tree architecture (e.g., X-tree architecture 100) regarding qubit connectivity, the hierarchical layout generated by layout component 314 may initially assign program qubits of one or more VQE algorithms to one or more hardware qubits included in one or more quantum processors 308 and / or characterized by the multi-level hierarchical tree architecture (e.g., X-tree architecture 100). In different embodiments, layout component 314 may analyze one or more Pauli strings adopted by one or more VQE algorithms to perform quantum programs (e.g., variational quantum chemistry simulations) and initially assign qubits described by the Pauli strings to nodes 102 of the multi-level hierarchical tree architecture. Thus, the hierarchical layout generated by the layout component 314 can initially map logical qubits (e.g., qubits described by Pauli strings used by the VQE algorithm) to physical qubits of one or more quantum processors 308 (e.g., nodes 102 of a multi-level hierarchical tree architecture, such as X-tree architecture 100).

[0056] Figure 4 A diagram illustrating a non-limiting system 300, including an example of a mapping component 402, according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. In various embodiments, the mapping component 402 may further assist the layout component 314 in determining the distribution of logical qubits across multiple levels of a multi-level hierarchical tree architecture (e.g., X-tree architecture 100).

[0057] For example, mapping component 402 can analyze Pauli strings of one or more VQE algorithms and determine the amount of connectivity associated with logical qubits during the execution of the quantum program. In different embodiments, the amount of connectivity can be characterized by the number of times a logical qubit appears in a Pauli string. For example, each Pauli string can describe a corresponding quantum computation performed by a VQE algorithm. Thus, the number of quantum computations involving a given logical qubit can be characterized by the number of times that given logical qubit appears in a Pauli string. Since a logical qubit involves more quantum computations, the connectivity of that logical qubit can be considered to increase. For example, as the number of occurrences increases, the amount of connectivity experienced by the associated logical qubit during the execution of the quantum program also increases. For example, the logical qubit with the maximum number of occurrences in a Pauli string can be determined to have the maximum connectivity within a multi-level hierarchical tree architecture (e.g., X-tree architecture 100).

[0058] In different embodiments, mapping component 402 can assign logical qubits to different levels of a multi-level hierarchical tree architecture (e.g., X-tree architecture 100) based on the amount of associated connectivity. For example, in cases where the hierarchy of the tree architecture increases with each iteration of the branches (e.g., as in... Figure 1B As illustrated in the fourth example X tree architecture 100d, logical qubits can be assigned to the levels of the tree architecture in order of connectivity; wherein logical qubits with the greatest connectivity can be assigned to the lowest level (e.g., closest to the center of the tree architecture), and logical qubits with the least connectivity can be assigned to the highest level (e.g., closest to the periphery of the tree architecture).

[0059] Figure 5 A diagram illustrating an example, non-limiting initial hierarchical layout 500 that may be generated by layout component 314 and / or mapping component 402 according to one or more embodiments described herein is shown. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. Quantum computations that can be performed according to the VQE algorithm can be defined via multiple Pauli strings.

[0060] like Figure 5 As shown, one or more exemplary Pauli strings 502 may include a set of Pauli operators (e.g., "X", "Y", "Z", and "I") associated with each logical qubit used by the VQE algorithm to perform quantum computation. For example, Figure 5 The exemplary Pauli string 502 depicted relates to six member groups (e.g., where the qubits are represented as “q0”, “q1”, “q2”, “q3”, “q4”, “q5”, and / or “q6”) of Pauli operators associated with six qubits. In the exemplary Pauli string 502, qubit q0 has the maximum number of occurrences (e.g., the maximum number of “X”, “Y”, and / or “Z” Pauli operator associations within this set of exemplary Pauli strings 502). In contrast, qubit q5 has the minimum number of occurrences (e.g., the minimum number of “X”, “Y”, and / or “Z” Pauli operator associations within this set of exemplary Pauli strings 502).

[0061] like Figure 5As shown, compiler component 310 (e.g., via layout component 314 and / or mapping component 402) can assign logical qubits to different levels of a tree architecture (e.g., X-tree architecture 100) based on qubit connectivity (e.g., determined based on the number of occurrences within a Pauli string). In different embodiments, mapping component 402 can determine how much quantum computing is performed on each logical qubit using the VQE algorithm based on the number of occurrences of the corresponding logical qubit in a Pauli string (e.g., the number of “X”, “Y”, and / or “Z” Pauli operators associated within that set of Pauli strings), and thereby determine the amount of connectivity associated with each logical qubit.

[0062] For example, the qubit associated with the maximum occurrence count in the exemplary Pauli string 502 (e.g., qubit q0) can be assigned by the mapping component 402 to the lowest level (e.g., level 0) of the tree structure (e.g., X-tree structure 100). Furthermore, the qubit associated with the minimum occurrence count in the exemplary Pauli string 502 (e.g., qubit q5) can be assigned by the mapping component 402 to the highest level (e.g., level 2) of the tree structure (e.g., X-tree structure 100). Further, the mapping component 402 can assign qubits associated with occurrence counts that are neither the maximum nor the minimum in the exemplary Pauli string 502 (e.g., qubit q1, qubit q2, qubit q3, and / or qubit q4) to one or more intermediate levels (e.g., level 1) of the tree structure (e.g., X-tree structure 100).

[0063] Furthermore, compiler component 310 (e.g., via layout component 314 and / or mapping component 402) can map qubits to nodes 102 of a tree architecture (e.g., X-tree architecture 100) based on hierarchical allocation. For clarity, the boundary of level 0 within the tree architecture of the exemplary hierarchical layout 500 is... Figure 5 Depicted in dark gray shading, the boundary of level 1 within the tree structure of the exemplary hierarchical layout 500 is... Figure 5 Depicted in light gray shading, and the boundary of level 2 within the tree structure of the exemplary hierarchical layout 500 is... Figure 5Depicted against a white background. In different embodiments, as the mapped qubit is positioned closer to the center of the multi-level hierarchical tree architecture (e.g., X-tree architecture 100), the number of qubit connections experienced by the mapped qubit during the entire execution of the VQE algorithm increases. For example, in this set of exemplary Pauli strings 502, qubit q0 is shown as involving the most quantum computations during the entire execution of the VQE algorithm (e.g., as evidence of the number of occurrences within the Pauli string), and can therefore be positioned within the most central level (e.g., level 0) of the multi-level hierarchical tree architecture (e.g., X-tree architecture 100). In contrast, in this set of exemplary Pauli strings 502, qubit q5 is shown as involving the least quantum computations during the entire execution of the VQE algorithm (e.g., as evidence of the number of occurrences within the Pauli string), and can therefore be positioned within a level (e.g., level 2) further away from the center of the multi-level hierarchical tree architecture (e.g., X-tree architecture 100).

[0064] Since qubits are mapped based on hierarchical allocation within a tree architecture (e.g., X-tree architecture 100), the qubit mapped to node 102, which is closest to the center of the multi-level hierarchical tree architecture, is likely to be the qubit that experiences the largest number of qubit connection types during the execution of the VQE algorithm. Conversely, the qubit mapped to node 102, which is furthest from the center of the multi-level hierarchical tree architecture, is likely to be the qubit that experiences the smallest number of qubit connection types during the execution of the VQE algorithm.

[0065] For each synthesis of the quantum circuits employed by the VQE algorithm, logical qubits can be routed to new physical qubit maps, which facilitate different qubit connectivity schemes depicted by the corresponding quantum circuits. As the number of routing operations used to establish the desired connectivity increases, the mapping overhead also increases. However, the initial hierarchical layout described herein can reduce the number of routing operations by mapping busy qubits (e.g., qubits involving significant quantum computation) to one or more central levels of the tree architecture (e.g., X-tree architecture 100), thereby bringing them closer to each other. In other words, qubits initially mapped to central levels in the tree architecture (e.g., level 0 in the fourth exemplary X-tree architecture 100d) can be routed to desired qubit connections (e.g., desired root-to-leaf pairs) with fewer operations than qubits initially mapped to peripheral levels in the tree architecture (e.g., level 2 in the fourth exemplary X-tree architecture 100d).

[0066] Figure 6A diagram illustrating an example, non-limiting system 300 according to one or more embodiments described herein, the system 300 further including a synthesis component 602 and / or a routing component 604. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. In different embodiments, the compiler component 310 (e.g., via the synthesis component 602 and / or routing component 604) may employ a synthesis and routing approach merged into a root to generate one or more quantum circuits (e.g., Pauli string simulation quantum circuits) to perform one or more VQE algorithms (e.g., performing variable quantum chemistry simulations).

[0067] For example, for each iteration of the VQE algorithm, compiler component 310 (e.g., via synthesis component 602 and / or routing component 604) can synthesize a corresponding quantum circuit (e.g., a Pauli string emulation quantum circuit) to express a corresponding Pauli string, and can route the current logic-to-physical qubit mapping used to enable the qubit connectivity of the synthesized quantum circuit. In one or more embodiments, synthesis component 602 can synthesize a quantum circuit expressing a Pauli string from multiple Pauli strings through a series of qubit connection selections. Further, synthesis component 602 can select each qubit connection (e.g., between logical qubits) based on the effect of previously selected qubit connections on the mapping of physical qubits to logical qubits. Additionally, routing component 604 can change the position of logical qubits on a multi-level hierarchical tree architecture based on the qubit connection selections performed by synthesis component 602. For example, routing component 604 can perform one or more routing operations that define the relocation of one or more logical qubits from one node 102 of the tree architecture to another node 102, thereby moving the logical qubits to one or more nodes 102 capable of establishing selected qubit connections (e.g., and thereby physically allocating qubits). In different embodiments, synthesizing quantum circuits and performing routing operations can be performed in combination. For example, the routing operation adopted by routing component 604 can change the logical-to-physical qubit mapping, so the next synthesis operation adopted by synthesis component 602 (e.g., defining qubit connections) can be selected based on the changed state of the qubit mapping.

[0068] Figure 7 A diagram illustrates an example, non-limiting merging-to-root merging and routing method 700, implementable by merging component 602 and / or routing component 604, according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. Figure 7The exemplary merging-to-root synthesis and routing method 700 described herein can exemplify the features of the synthesis component 602 and / or routing component 604 of the exemplary quantum circuit. In various embodiments, the merging-to-root synthesis and routing method (e.g., the exemplary merging-to-root synthesis and routing method 700) executed by compiler component 310 can be implemented using quantum processor 308 having qubit connectivity characterized by a multi-level hierarchical tree architecture (e.g., X-tree architecture 100). For example, layout component 314 and / or mapping component 402 can generate an initial hierarchical layout of logical-to-physical qubit mappings that initially map logical qubits that may undergo multiple different qubit connections during the execution of VQE algorithms in the central level of the tree architecture (e.g., the central level of exemplary level 0 and / or level 1 in the fourth exemplary X-tree architecture 100d); thereby, the merging-to-root synthesis and routing method 700 is facilitated by enabling different quantum circuit synthesis options to be implemented with minimal routing operations.

[0069] As described herein, the same Pauli string can be represented by multiple different Pauli string simulation quantum circuits, each quantum circuit describing a variant scheme of qubit connectivity that can be used to implement quantum computation for that Pauli string. Thus, for a given Pauli string, multiple quantum circuits can be used for synthesis. At least due to the location of high-flow logic qubits (e.g., qubits that may experience a large number of qubit connections throughout the VQE algorithm) within the central hierarchy of the tree architecture (e.g., X-tree architecture 100), multiple qubit connectivity options are available for selection by the synthesis component 602 to synthesize the quantum circuit. Thus, the synthesis component 602 can combine the routing operations employed by the routing component 604 to select qubit connections in order to adaptively synthesize a quantum circuit that expresses the given Pauli string with minimal mapping overhead.

[0070] Figure 7 The exemplary synthesis and routing method 700 for merging to the root shown depicts the synthesis of an exemplary Pauli string from an exemplary input Pauli string 704, simulating a quantum circuit 702 (e.g., described in quantum assembly (“QASM”) code). For example, the exemplary input Pauli string 704 may be considered to involve four logical qubits (e.g., in…). Figure 7 Quantum computing (represented by qubits q1, q2, q3, and q4). For example... Figure 7As shown, these logical qubits may have already been mapped to a multi-level hierarchical tree architecture (e.g., X-tree architecture 100) of a given quantum processor 308. For example, the current mapped position of the logical qubits could be a residual position from a previous iteration of the VQE algorithm. In another instance, according to one or more embodiments described herein, the current mapped position of these logical qubits could be a position established by an initial hierarchical layout. The synthesis component 602 and / or routing component 604 may operate in combination with each other to remap the logical qubits to node 102, realizing qubit connectivity described by a synthesized quantum circuit (e.g., exemplary Pauli string simulation quantum circuit 702) expressing a given Pauli string (e.g., exemplary input Pauli string 704).

[0071] like Figure 7 As shown, synthesis operations employed by synthesis component 602 are depicted with “S” arrows, and routing operations employed by routing component 604 are depicted with “R” arrows. For clarity, the synthesis and routing operations are depicted as illustrations of at least a portion of a multi-level hierarchical tree architecture (e.g., X-tree architecture 100). Additionally, the synthesis and routing operations are depicted as QASM code, which, when compiled, can describe synthesized quantum circuits (e.g., exemplary Pauli string simulation quantum circuit 702). In various embodiments, synthesis component 602 may employ one or more synthesis operations to define selected qubit connections. For example, the one or more synthesis operations may define one or more quantum logic gates between qubits, such as two-qubit gates (e.g., CNOT gates and / or the like). In various embodiments, routing component 604 may use the one or more routing operations to route logical qubits to alternative nodes 102 in the tree architecture. For example, a routing operation may route a given logical qubit from initial node 102 to another node 102 capable of establishing a qubit connection defined by one or more synthesis operations. For example, the one or more routing operations may define one or more quantum logic gates, such as swap (“SWAP”) gates and / or the like, to adjust the ground state of a qubit.

[0072] For example, in Figure 7In the exemplary synthesis and routing method 700 for incorporating the root, the input Pauli string 704 can be expressed via multiple different combinations of qubit connections. The synthesis component 602 can select a first qubit connection from a pool of qubit connections, which is included in a pool of quantum circuit variants capable of expressing a given Pauli string (e.g., input Pauli string 704). Furthermore, the synthesis component 602 can select the first qubit connection based on the number of routing operations required to implement the first qubit connection on an existing logic-to-physical qubit mapping. For example, regarding... Figure 7 The initial logic-to-physical qubit mapping shown includes a first qubit connection pool comprising qubit connections between qubits q2 and q3, and qubit connections between qubits q3 and q1. The synthesis component 602 can select the qubit q3 and q1 connections, at least because qubits q3 and q1 have already been mapped to the connected node 102, and therefore the synthesis operation (e.g., a CNOT gate) used by the synthesis component 602 to define this qubit connection does not need to enable associated routing operations (e.g., such as...). Figure 7 (As shown).

[0073] Additionally, the synthesis component 602 can select a second qubit connection from a second qubit connection pool, which is included in a quantum circuit variant with a first qubit connection and capable of expressing the given Pauli string (e.g., input Pauli string 704). Furthermore, the synthesis component 602 can select the second qubit connection based on the number of routing operations required to implement the second qubit connection on the state of the logic-to-physical qubit mapping after the establishment of the first qubit connection. This can be done without one or more routing operations (e.g., such as...). Figure 7 In the case of establishing the first qubit connection (as shown), the state of the logical-to-physical qubit mapping can remain unchanged. For example, in the case where the second qubit connection pool includes qubit connections between qubits q0 and q1 and between qubits q0 and q2, the synthesis component 602 can employ a synthesis operation (e.g., a CNOT gate) defining the connection between qubits q0 and q2, at least because fewer routing operations can be used to establish the connection between qubits q0 and q2 than for the connection between qubits q0 and q1. For example, qubit q2 can be routed to node 102 connected to the node connected to qubit q0 with a single routing operation, while qubit q1 requires at least two routing operations to be routed to node 102 connected to the node connected to qubit q0. Figure 7As shown, routing component 604 can use a single routing operation (e.g., a SWAP gate) to change the position of qubit q2 to the root node in the tree structure, which is connected to node 102 of qubit q0.

[0074] Furthermore, the synthesis component 602 can select a third qubit connection from a third qubit connection pool, which is included in a quantum circuit variant having first and second qubit connections and capable of expressing a given Pauli string (e.g., input Pauli string 704). Furthermore, the synthesis component 602 can select the third qubit connection based on the number of routing operations that will need to be adopted to implement the third qubit connection on the state of the logic-to-physical qubit mapping after the establishment of the second qubit connection. In the depicted example, the state of the logic-to-physical mapping is changed by the last routing operation adopted by the routing component 604 (e.g., the SWAP gate of qubit q2). For example, in the case where the third qubit connection pool includes a qubit connection between qubits q2 and q3 and a qubit connection between qubits q2 and q1, the synthesis component 602 can choose to define the synthesis operation (e.g., the CNOT gate) for the connection between qubits q2 and q1, at least because the connection between qubits q2 and q1 can be established with fewer routing operations than the connection between qubits q2 and q3. For example, qubit q1 or q2 can be routed to node 102 connected to another corresponding qubit via a single routing operation, while many routing operations will be necessary to establish a connection between qubits q2 and q3 without hindering the connection between the first and second qubits described above. Figure 7 As shown, routing component 604 can use a single routing operation (e.g., a SWAP gate) to route qubit q1 to the root node in the tree architecture, which is connected to node 102 of qubit q2.

[0075] Those skilled in the art will recognize that the exemplary synthesis and routing method 700 for merging to the root described herein illustrates different features of compiler component 310 (e.g., via synthesis component 602 and / or routing component 604), and the architecture of the synthesis and routing method for merging to the root practiced by compiler component 310 is not limited thereto. For example, embodiments including more than three qubit connection selections and / or more than four logical qubits are also contemplated. For example, the different features described herein may be scaled to meet one or more requirements of the VQE algorithm.

[0076] By adaptively selecting synthesis operations based on how the synthesis evolves through the initial mapping state and / or the mapping state, synthesis component 602 can synthesize quantum circuits expressing a given Pauli string with minimal routing operations (e.g., minimal mapping overhead). Furthermore, according to the various embodiments described herein, mapping high-volume logic qubits to a central level in a multi-level hierarchical tree architecture in the initial hierarchical layout can increase the number of qubit connection candidates that can be selected with minimal routing operations. Additionally, in various embodiments, a multi-level hierarchical tree architecture (such as X-tree architecture 100) can enable the generation of the initial hierarchical layout with respect to a quantum processor 308 having sparse qubit connections and therefore high yield.

[0077] Figure 8 A non-limiting table 800 is shown illustrating examples of the effectiveness of the synthesis and routing methods employed by compiler component 310 on X-tree architecture 100, according to one or more embodiments described herein, to demonstrate the efficiency of such methods. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. Table 800 may illustrate the effectiveness of different features of compiler component 310 described herein relative to mapping overhead (e.g., the number of routing operations). Column 802 depicts the mapping overhead generated by using compiler component 310 on a fourth example X-tree architecture 100d by running variable quantum chemical simulations on the depicted molecules (e.g., hydrogen (“H2”), lithium hydride (“LiH”), sodium hydride (“NaH”), hydrogen fluoride (“HF”), beryllium hydride (“BeH2”), water (“H2O”), borane (“BH3”), ammonia (“NH3”), and methane (“CH4”)). Column 804 describes the mapping overhead incurred by running the same variable quantum chemical simulation on the depicted molecule using a conventional VQE compiler (e.g., the sabre compiler) on the fourth example X-tree architecture 100d. Figure 8 As shown, compared with traditional compilers, compiler component 310 can execute the VQE algorithm while reducing mapping overhead by nearly 99%.

[0078] Figure 9 A flowchart of a non-limiting computer implementation of a method 900, illustrating an example of mapping one or more VQE algorithms to a sparse qubit-connected quantum processor 308 according to one or more embodiments described herein, is shown, wherein mapping overhead is reduced. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted.

[0079] At 902, the computer-implemented method 900 may include mapping one or more VQE algorithms (e.g., via layout component 314 and / or mapping component 402) to one or more superconducting quantum processors 308 via a system 300 operatively coupled to processor 320. The processor 308 may include qubit connectivity characterized by a multi-level hierarchical tree architecture (e.g., X-tree architecture 100). In various embodiments, the mapping at 902 may include generating a hierarchical layout (e.g., exemplary hierarchical layout 500) based on the amount of connectivity expected for each logical qubit. For example, logical qubits with high connectivity throughout the VQE algorithm (e.g., as demonstrated by excessive occurrences in Pauli strings) may be mapped to physical qubits located at a central level of the tree architecture (e.g., high-flow qubits may be mapped to the root node).

[0080] At 904, the computer-implemented method 900 may include synthesizing (e.g., via synthesis component 602 and / or routing component 604) a quantum circuit (e.g., a Pauli string-simulated quantum circuit) by system 300 through a series of qubit connection selections, the quantum circuit representing a Pauli string of the VQE algorithm, wherein each qubit connection selection may be based on the effect on the logic-to-physical qubit mapping resulting from previous qubit connection selections. For example, a first selected qubit connection may be enabled by one or more routing operations. As a result of the accompanying routing, establishing the first selected qubit connection may alter the current logic-to-physical qubit mapping (e.g., may alter the mapping initially established at 902 and / or established during previous iterations of the VQE algorithm). A second qubit connection of the quantum circuit may be synthesized based on the altered mapping selection within this series of selections; thus taking into account how previous routing operations may affect the routing operations associated with each possible qubit connection candidate. By adaptively selecting qubit connections based on the evolution of states from a logic-to-physical qubit mapping, a computer-implemented method 900 can synthesize quantum circuits representing a given Pauli string while minimizing mapping overhead (e.g., as in the case of...). Figure 7 The exemplary merging and routing method 700 depicted in the diagram is shown.

[0081] Figure 10 A flowchart illustrating a non-limiting computer implementation of a method 1000 that maps one or more VQE algorithms to a sparse qubit-connected quantum processor 308 according to one or more embodiments described herein, wherein mapping overhead is reduced. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted.

[0082] At 1002, the computer-implemented method 1000 may include mapping the physical qubits of a superconducting quantum processor 308 to the logical qubits included in a plurality of Pauli strings used in the VQE algorithm by a system 300 operatively connected to the processor 320 (e.g., via layout component 314 and / or mapping component 402). In various embodiments, the superconducting quantum processor 308 may have qubit connectivity characterized by a multi-level hierarchical tree architecture (such as the X-tree architecture 100 illustrated herein). In various embodiments, the mapping at 902 may include generating a hierarchical layout (e.g., exemplary hierarchical layout 500) based on the amount of connectivity expected for each logical qubit. For example, logical qubits with high connectivity throughout the VQE algorithm (e.g., as demonstrated by excessive occurrences in Pauli strings) may be mapped to physical qubits located at a central level of the tree architecture (e.g., high-flow qubits may be mapped to the root node).

[0083] Furthermore, the computer-implemented method 1000 can synthesize quantum circuits for each Pauli string (e.g., Pauli string-simulated quantum circuits), and these quantum circuits can be executable by a superconducting quantum processor 308 through routing of qubits via a logic-to-physical qubit mapping. Different quantum circuits, each with corresponding qubit connectivity, can express the same Pauli string. However, quantum circuit variants can be associated with the amount of corresponding routing operations to enable execution on the superconducting quantum processor 308. Selecting a quantum circuit variant that requires the least amount of routing to implement reduces the mapping overhead associated with the execution of the VQE algorithm. According to the various embodiments described herein, the computer-implemented method 1000 can synthesize the quantum circuit by synthesizing the quantum circuit through a series of qubit connectivity selections, thereby minimizing the mapping overhead, where each qubit connection is adaptively selected based on how the logic-to-physical qubit mapping evolves in response to previous selections (e.g., as in...). Figure 7 The exemplary merging and routing method 700 described in the text is illustrated in the text.

[0084] For example, at 1004, the computer-implemented method 1000 may include the selection of a first qubit connection in the synthesis of a quantum circuit by system 300 (e.g., via synthesis component 602). The first qubit connection may be a qubit connection that requires a minimal amount of routing operations compared to other qubit connection candidates included in a pool of qubit connection candidates that can express one or more variants of the quantum circuit. In one or more embodiments, the computer-implemented method 1000 may include the modification (e.g., via routing component 604) of the logic-to-physical qubit mapping by system 300 by routing the logic qubit to a target node in a multi-level hierarchical tree architecture to enable the first qubit connection. At 1008, the computer-implemented method 1000 may then include a second qubit connection in the synthesis of the quantum circuit selected by system 300 (e.g., via synthesis component 602). The second qubit connection can be a qubit connection that requires a minimal number of routing operations compared to other qubit connection candidates in the qubit connection pool, which is included in one or more quantum circuit variants that also include the first qubit connection and can express the Pauli string. Further, the computer-implemented method 1000 can repeat steps 1004 to 1008 until the synthesis of the quantum circuit expressing the given Pauli string is achieved.

[0085] It should be understood that while this disclosure includes a detailed description of cloud computing, the implementation of the teachings cited herein is not limited to cloud computing environments. Rather, embodiments of the invention can be implemented in conjunction with any other type of computing environment now known or developed hereafter.

[0086] Cloud computing is a service delivery model that enables convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services), which can be rapidly provisioned and released with minimal management effort or interaction with the service provider. This cloud model may include at least five features, at least three service models, and at least four deployment models.

[0087] The features are as follows:

[0088] On-demand self-service: Cloud consumers can unilaterally and automatically provide computing power, such as server time and network storage, as needed, without requiring human interaction with the service provider.

[0089] Extensive network access: Capabilities are available through networks and accessed via standard mechanisms that facilitate the use of heterogeneous thin client or thick client platforms (e.g., mobile phones, laptops, and PDAs).

[0090] Resource pooling: A provider's computing resources are pooled to serve multiple consumers using a multi-tenant model, where different physical and virtual resources are dynamically assigned and reassigned as needed. There is a sense of location independence because consumers typically do not have control or knowledge of the exact location of the resources provided, but may be able to specify the location at a higher level of abstraction (e.g., country, state, or data center).

[0091] Rapid flexibility: The ability to provide capacity quickly and flexibly, automatically scaling down and up rapidly in some situations to scale up rapidly. For consumers, the available supply capacity often appears unlimited and can be purchased in any quantity at any time.

[0092] Measuring services: Cloud systems automatically control and optimize resource usage by leveraging metering capabilities at a level of abstraction appropriate to the service type (e.g., storage, processing, bandwidth, and active user accounts). Resource usage can be monitored, controlled, and reported, providing transparency to both service providers and consumers.

[0093] The service model is as follows:

[0094] Software as a Service (SaaS): This provides consumers with the ability to use the provider's applications running on cloud infrastructure. Applications can be accessed from different client devices via thin client interfaces such as web browsers (e.g., web-based email). Consumers do not manage or control the underlying cloud infrastructure, including the network, servers, operating system, storage, or even individual application capabilities, with possible exceptions such as limited user-specific application configuration settings.

[0095] Platform as a Service (PaaS): This provides consumers with the ability to deploy applications created or acquired by the consumer using programming languages ​​and tools supported by the provider onto cloud infrastructure. Consumers do not manage or control the underlying cloud infrastructure, including networks, servers, operating systems, or storage, but they have control over the deployed applications and the configuration of any application hosting environment.

[0096] Infrastructure as a Service (IaaS): The capabilities offered to consumers are processing, storage, networking, and other basic computing resources that enable consumers to deploy and run arbitrary software, which may include operating systems and applications. Consumers do not manage or control the underlying cloud infrastructure, but rather have control over the operating system, storage, deployed applications, and potentially limited control over selected networking components (e.g., host firewalls).

[0097] The deployment model is as follows:

[0098] Private cloud: A cloud infrastructure that operates solely for an organization. It can be managed by the organization or a third party and can exist on-site or off-site.

[0099] Community cloud: A cloud infrastructure shared by several organizations and supporting a specific community with shared concerns (e.g., tasks, security requirements, policies, and compliance considerations). It can be managed by an organization or a third party and can exist on-site or off-site.

[0100] Public cloud: Makes cloud infrastructure available to the public or large industry groups and is owned by an organization that sells cloud services.

[0101] Hybrid cloud: A cloud infrastructure is a combination of two or more clouds (private, community, or public) that remain a single entity but are bound together by standardized or proprietary technologies that enable data and applications to be ported (e.g., cloud bursting for load balancing between clouds).

[0102] Cloud computing environments are service-oriented, focusing on statelessness, loose coupling, modularity, and semantic interoperability. At the heart of cloud computing is the infrastructure that includes a network of interconnected nodes.

[0103] See now Figure 11 This describes an illustrative cloud computing environment 1100. As shown, the cloud computing environment 1100 includes one or more cloud computing nodes 1102, and local computing devices used by cloud consumers (such as, for example, personal digital assistants (PDAs) or cellular phones 1104, desktop computers 1106, laptop computers 1108, and / or automotive computer systems 1110) can communicate with the cloud computing nodes 1102. The nodes 1102 can communicate with each other. They can be physically or virtually grouped (not shown) in one or more networks, such as private clouds, community clouds, public clouds, or hybrid clouds, or combinations thereof, as described above. This allows the cloud computing environment 1100 to provide infrastructure, platform, and / or software as services that cloud consumers do not need to maintain on their local computing devices. It should be understood that... Figure 11 The types of computing devices 1104-1110 shown are intended to be illustrative only, and computing node 1102 and cloud computing environment 1100 can communicate with any type of computerized device via any type of network and / or network-addressable connection (e.g., using a web browser).

[0104] See now Figure 12 This demonstrates the 1100 cloud computing environment ( Figure 11This provides a set of functional abstraction layers. For the sake of brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. It should be understood in advance that... Figure 12 The components, layers, and functions shown are intended to be illustrative only, and embodiments of the invention are not limited thereto. As described, the following layers and corresponding functions are provided.

[0105] The hardware and software layer 1202 includes hardware and software components. Examples of hardware components include: a mainframe 1204; a server 1206 based on a RISC (Reduced Instruction Set Computer) architecture; a server 1208; a blade server 1210; a storage device 1212; and a network and network components 1214. In some embodiments, the software components include network application server software 1216 and database software 1218.

[0106] The virtualization layer 1220 provides an abstraction layer from which the following examples of virtual entities can be provided: virtual server 1222; virtual storage 1224; virtual network 1226, including virtual private network; virtual application and operating system 1228; and virtual client 1230.

[0107] In one example, management layer 1232 can provide the functions described below. Resource provisioning 1234 provides dynamic procurement of computing resources and other resources used to perform tasks within the cloud computing environment. Metering and pricing 1236 provides cost tracking as resources are utilized within the cloud computing environment and bills or invoices for the consumption of these resources. In one example, these resources may include application software licenses. Security provides authentication for cloud consumers and tasks, as well as protection for data and other resources. User portal 1238 provides access to the cloud computing environment for consumers and system administrators. Service level management 1240 provides cloud resource allocation and management to ensure the required service level is met. Service level agreement (SLA) planning and fulfillment 1242 provides pre-scheduling and procurement of cloud resources, anticipating future requirements for those resources according to the SLA.

[0108] Workload layer 1244 provides examples of functionalities that can leverage a cloud computing environment. Examples of workloads and functionalities that can be provided from this layer include: mapping and navigation 1246; software development and lifecycle management 1248; virtual classroom education delivery 1250; data analytics and processing 1252; transaction processing 1254; and VQE algorithm processing 1256. Various embodiments of the invention can be found by referring to [reference needed]. Figure 11 and Figure 12 The described cloud computing environment maps the VQE algorithm onto one or more quantum processors 308 with a multi-level hierarchical tree architecture (e.g., an X-tree architecture).

[0109] This invention can be a system, method, and / or computer program product of any possible level of technical detail integration. A computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to execute aspects of the invention. A computer-readable storage medium may be a tangible means capable of retaining and storing instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer-readable storage media includes: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital universal disk (DVD), memory sticks, floppy disks, mechanical encoding devices such as punch cards, or protrusions in slots having instructions recorded thereon, and any suitable combination of the following:

[0110] As stated above, the computer-readable storage medium used herein should not be construed as a temporary signal itself, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., optical pulses through fiber optic cables), or electrical signals transmitted through wires.

[0111] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a suitable computing / processing device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network), or to an external computer or external storage device. The network may include copper cables, optical fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to a computer-readable storage medium within the suitable computing / processing device.

[0112] Computer-readable program instructions used to perform the operations of this invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​(such as Smalltalk, C++, etc.) and procedural programming languages ​​(such as the "C" programming language or similar programming languages). The computer-readable program instructions may be executed entirely on a user's computer, partially on a user's computer, as a standalone software package, partially on a user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network (including a local area network (LAN) or a wide area network (WAN)) or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs) may execute computer-readable program instructions by utilizing state information from the computer-readable program instructions to personalize the electronic circuitry in order to perform aspects of this invention.

[0113] The present invention will now be described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0114] These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / actions specified in one or more boxes of a flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that can instruct a computer, programmable data processing apparatus, and / or other device to operate in a particular manner, such that the computer-readable storage medium having the instructions stored therein includes an article of writing comprising instructions for implementing aspects of the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0115] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other device to produce computer-implemented processing, such that the instructions executed on the computer, other programmable apparatus, or other device perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0116] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. Each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than indicated in the figures. For example, depending on the functions involved, two consecutively shown blocks may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order. It will also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0117] To provide additional background for the various implementations described herein, Figure 13 The following discussion is intended to provide a general description of a suitable computing environment 1300 in which various embodiments of the embodiments described herein may be implemented. Although embodiments have been described above in the general context of computer-executable instructions that can run on one or more computers, those skilled in the art will recognize that embodiments may also be implemented in combination with other program modules and / or as a combination of hardware and software.

[0118] Typically, program modules include routines, programs, components, data structures, etc., that perform specific tasks or implement specific abstract data types. Furthermore, those skilled in the art will recognize that the methods of this invention can be practiced with other computer system configurations, including single-processor or multi-processor computer systems, minicomputers, mainframes, Internet of Things (“IoT”) devices, distributed computing systems, and personal computers, handheld computing devices, microprocessor-based or programmable consumer electronics, each of which can be operatively coupled to one or more associated devices.

[0119] The embodiments illustrated herein can also be implemented in a distributed computing environment, where certain tasks are performed by remote processing devices linked via a communication network. In a distributed computing environment, program modules can reside in both local and remote memory storage devices. For example, in one or more embodiments, a computer-executable component can be executed from memory that may include or comprise one or more distributed memory cells. As used herein, the terms "memory" and "memory cell" are interchangeable. Furthermore, one or more embodiments described herein enable the execution of code from a computer-executable component in a distributed manner, for example, by multiple processors working together or cooperating to execute code from one or more distributed memory cells. As used herein, the term "memory" can encompass a single memory or memory cell at one location or multiple memories or memory cells at one or more locations.

[0120] Computing devices typically include a variety of media, which may include computer-readable storage media, machine-readable storage media, and / or communication media, these two terms being used differently from each other herein. A computer-readable storage medium or a machine-readable storage medium can be any available storage medium accessible by a computer, and includes volatile and non-volatile media, removable and non-removable media. By way of example and not limitation, a computer-readable storage medium or a machine-readable storage medium can be implemented in combination with any method or technique used for storing information such as computer-readable or machine-readable instructions, program modules, structured data, or unstructured data.

[0121] Computer-readable storage media may include, but is not limited to: random access memory (“RAM”), read-only memory (“ROM”), electrically erasable programmable read-only memory (“EEPROM”), flash memory or other memory technologies, compact disc read-only memory (“CD-ROM”), digital universal disc (“DVD”), Blu-ray disc (“BD”) or other optical disc storage, magnetic tape cassettes, magnetic tape, disk storage or other magnetic storage devices, solid-state drives or other solid-state storage devices, or other tangible and / or non-transient media that can be used to store desired information. In this regard, the terms “tangible” or “non-transient” as used herein with respect to storage, memory, or computer-readable media shall be understood to exclude only the propagation of transient signals themselves as a modifier, and shall not waive the rights to all standard storage, memory, or computer-readable media that do not only propagate transient signals themselves.

[0122] A computer-readable storage medium can be accessed by one or more local or remote computing devices, for example via access requests, queries or other data retrieval protocols, for various operations with respect to the information stored in the medium.

[0123] Communication media typically embody computer-readable instructions, data structures, program modules, or other structured or unstructured data as data signals such as modulated data signals (e.g., carrier waves or other transmission mechanisms), and include any medium for delivering or transmitting information. The term "modulated data signal" refers to a signal whose characteristics are set or altered in a manner that encodes information in one or more signals. By way of example and not limitation, communication media include wired media, such as wired networks or direct-line connections, and wireless media, such as acoustic, RF, infrared, and other wireless media.

[0124] Refer again Figure 13 Example environment 1300 for implementing various embodiments of the aspects described herein includes a computer 1302, which includes a processing unit 1304, system memory 1306, and a system bus 1308. The system bus 1308 couples system components, including but not limited to system memory 1306, to the processing unit 1304. The processing unit 1304 can be any of various commercially available processors. Dual microprocessors and other multiprocessor architectures can also be used as the processing unit 1304.

[0125] System bus 1308 can be any of several types of bus structures capable of further interconnecting to a memory bus (with or without a memory controller), a peripheral bus, and a local bus using any of a variety of commercially available bus architectures. System memory 1306 includes ROM 1310 and RAM 1312. The basic input / output system (“BIOS”) can be stored in non-volatile memory such as ROM, erasable programmable read-only memory (“EPROM”), or EEPROM. The BIOS contains basic routines such as those that help transfer information between components within computer 1302 during startup. RAM 1312 may also include high-speed RAM, such as static RAM for caching data.

[0126] Computer 1302 further includes an internal hard disk drive (“HDD”) 1314 (e.g., EIDE, SATA), one or more external storage devices 1316 (e.g., floppy disk drive (“FDD”) 1316, memory stick or flash drive reader, memory card reader, etc.), and an optical disc drive 1320 (e.g., capable of reading from or writing to CD-ROMs, DVDs, BDs, etc.). While the internal HDD 1314 is illustrated as being located within computer 1302, it can also be configured for external use in a suitable chassis (not shown). Furthermore, although not shown in environment 1300, a solid-state drive (“SSD”) may be used to supplement or replace the HDD 1314. The HDD 1314, external storage device 1316, and optical disc drive 1320 can be connected to system bus 1308 via HDD interface 1324, external storage interface 1326, and optical drive interface 1328, respectively. The interface 1324 for the external driver implementation may include at least one or both of Universal Serial Bus (“USB”) and Institute of Electrical and Electronics Engineers (“IEEE”) 1394 interface technologies. Other external driver connectivity technologies are contemplated in the embodiments described herein.

[0127] The drive and its associated computer-readable storage medium provide non-volatile storage of data, data structures, computer-executable instructions, etc. For computer 1302, the drive and storage medium accommodate any data stored in a suitable digital format. Although the above description of computer-readable storage media refers to a corresponding type of storage device, those skilled in the art will understand that other types of computer-readable storage media (whether currently existing or developed in the future) may also be used in the example operating environment, and further, any such storage medium may contain computer-executable instructions for performing the methods described herein.

[0128] Multiple program modules may be stored in the drive and RAM 1312, including an operating system 1330, one or more application programs 1332, other program modules 1334, and program data 1336. All or part of the operating system, application programs, modules, and / or data may also be cached in RAM 1312. The systems and methods described herein can be implemented using different commercially available operating systems or combinations of operating systems.

[0129] Computer 1302 may optionally include emulation technology. For example, a hypervisor (not shown) or other intermediary may emulate the hardware environment used for operating system 1330, and the emulated hardware may optionally be compatible with... Figure 13The hardware shown is different. In this embodiment, the operating system 1330 may include one of a plurality of VMs (“VMs”) hosted on the computer 1302. Furthermore, the operating system 1330 may provide a runtime environment for the application 1332, such as the Java Runtime Environment or the .NET Framework. A runtime environment is a consistent execution environment that allows the application 1332 to run on any operating system that includes a runtime environment. Similarly, the operating system 1330 may support containers, and the application 1332 may be in the form of containers, which are lightweight, standalone, executable software packages that include, for example, code, runtime, system tools, system libraries, and settings for the application.

[0130] Furthermore, computer 1302 may enable security modules, such as a Trusted Processing Module (“TPM”). For example, with TPM, before loading the boot component, the boot component hashes the boot component in time and waits for the result to match a security value. This process can occur at any layer of the computer 1302’s code execution stack, for example, at the application execution level or at the operating system (“OS”) kernel level, thereby achieving security at any code execution level.

[0131] Users can input commands and information into computer 1302 through one or more wired / wireless input devices (e.g., keyboard 1338, touchscreen 1340, and pointing devices such as mouse 1342). Other input devices (not shown) may include microphones, infrared (“IR”) remote controls, radio frequency (“RF”) remote controls, or other remote controls, joysticks, virtual reality controllers and / or virtual reality headsets, game controllers, styluses, image input devices (e.g., cameras), gesture sensor input devices, visual motion sensor input devices, emotion or face detection devices, biometric input devices (e.g., fingerprint or iris scanners), etc. These and other input devices are typically connected to processing unit 1304 via input device interface 1344, which is coupled to system bus 1308, but may also be connected via other interfaces such as parallel ports, IEEE 1394 serial ports, game ports, USB ports, IR interfaces, etc. Interfaces, etc.

[0132] Monitor 1346 or other types of display devices can also be connected to system bus 1308 via an interface such as video adapter 1348. In addition to monitor 1346, computers typically include other peripheral output devices (not shown), such as speakers, printers, etc.

[0133] Computer 1302 can operate in a networked environment using logical connections via wired and / or wireless communications to one or more remote computers, such as remote computer 1350. Remote computer 1350 may be a workstation, server computer, router, personal computer, portable computer, microprocessor-based entertainment device, peer-to-peer device, or other public network node, and typically includes many or all of the elements described relative to computer 1302; however, for brevity, only memory / storage device 1352 is shown. The depicted logical connections include wired / wireless connections to a local area network (“LAN”) 1354 and / or a larger network (e.g., a wide area network (“WAN”) 1356). Such LAN and WAN networking environments are common in offices and corporations and facilitate enterprise-wide computer networks, such as intranets, all of which can connect to global communication networks, such as the Internet.

[0134] When used in a LAN networking environment, computer 1302 can connect to local network 1354 via a wired and / or wireless communication network interface or adapter 1358. Adapter 1358 can facilitate wired or wireless communication to LAN 1354, which may also include a wireless access point (“AP”) disposed thereon for communicating with adapter 1358 in wireless mode.

[0135] When used in a WAN networking environment, computer 1302 may include modem 1360 or may be connected to a communication server on WAN 1356 via other means (such as via the Internet) for establishing communication on WAN 1356. Modem 1360 (which may be internal or external and wired or wireless) may be connected to system bus 1308 via input device interface 1344. In a networking environment, program modules depicted relative to computer 1302 or portions thereof may be stored in remote memory / storage device 1352. It should be understood that the network connection shown is an example, and other means for establishing communication links between computers may be used.

[0136] When used in a LAN or WAN networking environment, computer 1302 can access cloud storage systems or other network-based storage systems as a supplement to or replacement of external storage device 1316 as described above. Typically, the connection between computer 1302 and the cloud storage system can be established, for example, via adapter 1358 or modem 1360 through LAN 1354 or WAN 1356 respectively. When computer 1302 is connected to the associated cloud storage system, external storage interface 1326 can manage the storage provided by the cloud storage system with the aid of adapter 1358 and / or modem 1360, just like other types of external storage. For example, external storage interface 1326 can be configured to provide access to cloud storage sources as if those sources were physically connected to computer 1302.

[0137] Computer 1302 may be operable to communicate with any wireless device or entity operably arranged in wireless communication, such as a printer, scanner, desktop and / or portable computer, portable data assistant, communications satellite, any device or location associated with a wirelessly detectable tag (e.g., self-service terminal, newsstand, store shelf, etc.), and telephone. This may include Wireless Fibre (“Wi-Fi”) and Wireless technology. Therefore, communication can be a predefined structure like a traditional network, or simply self-organizing communication between at least two devices.

[0138] The above description includes only examples of systems, computer program products, and computer-implemented methods. Of course, for the purposes of describing this disclosure, it is impossible to describe every conceivable combination of components, products, and / or computer-implemented methods; however, those skilled in the art will recognize that many further combinations and substitutions of this disclosure are possible. Furthermore, the terms “comprising,” “having,” “possessing,” etc., used in the detailed description, claims, appendices, and drawings are intended to be inclusive in a manner similar to the term “including,” as “including” is interpreted when used as a transitional word in a claim. Various embodiments have been described for illustrative purposes but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements to technologies found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A system for quantum computing, comprising: Memory, which stores computer-executable components; as well as A processor, operatively coupled to the memory and executing a computer-executable component stored in the memory, wherein the computer-executable component includes: A compiler component maps a variational quantum eigenvalue solver algorithm to a superconducting quantum processor, the superconducting quantum processor including qubit connectivity characterized by a multi-level hierarchical tree architecture. Wherein, the variational quantum eigenvalue solver algorithm defines the quantum computations that the superconducting quantum processor can execute, and wherein, the system further comprises: A layout component that generates an initial hierarchical layout that maps the physical qubits of the superconducting quantum processor to logical qubits included in a plurality of Pauli strings employed by the variable quantum eigenvalue solver algorithm; and A mapping component that determines how much of the quantum computing uses a first logical qubit from the logical qubit, and how much of the quantum computing uses a second logical qubit from the logical qubit. In this context, the first logical qubit is used in more of the quantum computing compared to the second logical qubit, and in the initial hierarchical layout, the first logical qubit is mapped to a more central level of the multi-level hierarchical tree architecture compared to the second logical qubit.

2. The system of claim 1, wherein the multi-level hierarchical tree architecture includes a root node connected to leaf nodes across different levels, wherein the root node is connected to a plurality of leaf nodes.

3. The system according to claim 1, wherein, The multi-level hierarchical tree architecture is an X-tree architecture.

4. The system according to any one of claims 1 to 3, further comprising: A synthesis component that synthesizes a quantum circuit by selecting a series of qubit connections, the quantum circuit representing a Pauli string from the plurality of Pauli strings, wherein the synthesis component selects qubit connections between the logical qubits based on the effect of previously selected qubit connections on the mapping between the physical qubits and the logical qubits; as well as A routing component that changes the position of a logical quantum bit on the multi-level hierarchical tree architecture based on the quantum bit connection.

5. The system according to claim 4, wherein, The synthesis of the quantum circuit and the alteration of the position of the logical qubits are performed in combination.

6. A method for computer implementation of quantum computing, comprising: A system operatively coupled to a processor maps a variable quantum eigenvalue solver algorithm to a superconducting quantum processor, which includes qubit connectivity characterized by a multi-level hierarchical tree architecture. as well as The system generates an initial hierarchical layout that maps the physical qubits of the superconducting quantum processor to logical qubits included in a plurality of Pauli strings employed by the variable quantum eigenvalue solver algorithm. Wherein, the variational quantum eigenvalue solver algorithm defines the quantum computations that the superconducting quantum processor can execute, and wherein, the method further includes: The system determines how much of the quantum computing uses the first logical qubit from the logical qubit, and how much of the quantum computing uses the second logical qubit from the logical qubit. In this context, the first logical qubit is used in more of the quantum computing compared to the second logical qubit, and in the initial hierarchical layout, the first logical qubit is mapped to a more central level of the multi-level hierarchical tree architecture compared to the second logical qubit.

7. The computer-implemented method of claim 6, wherein the multi-level hierarchical tree architecture includes a root node connected to leaf nodes across different levels, wherein the root node is connected to a plurality of leaf nodes.

8. The computer-implemented method according to claim 6, wherein, The multi-level hierarchical tree architecture is an X-tree architecture.

9. The computer-implemented method according to any one of claims 6 to 8, further comprising: The system synthesizes quantum circuits by selecting a series of qubit connections, the quantum circuits representing Pauli strings from the plurality of Pauli strings, wherein the selection from the series of qubit connection selections is based on the effect of previously selected qubit connections on the mapping between the physical qubits and the logical qubits; as well as The system changes the position of the logical qubits on the multi-level hierarchical tree architecture based on the selection.

10. The computer-implemented method according to claim 9, wherein, The synthesis of the quantum circuit and the execution of changing the position of the logical qubits are performed in combination with each other.

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