A large dynamic range high resolution multi-purpose time-to-digital converter circuit

Abstract

The application discloses a high-dynamic-measurement-range high-resolution multipurpose time-to-digital converter circuit, which comprises a control signal generation module, a first frequency synthesizer FS1, a fine time-to-digital converter module, a coarse time-to-digital converter module, a reference clock counter module and a data processing and calibration module. A high-stage interpolator in the reference clock counter module is used to expand the maximum measurement dynamic range, and the quantization unit is one reference clock period; a middle-stage interpolator in the coarse time-to-digital converter module is used to coarsely quantize a time which is less than one reference clock period and greater than the time length of a basic delay unit in the middle-stage interpolator; and a low-stage interpolator in the fine time-to-digital converter module is used to finely quantize a time which is less than the time length of the basic delay unit in the middle-stage interpolator, so that high measurement resolution is realized.

Description

Technical Field

[0001] This invention relates to the field of mixed-signal integrated circuits, and more specifically to a high-resolution, multi-purpose time-to-digital converter circuit with a large dynamic range. Background Technology

[0002] Optical signals play a crucial role in locations where distance measurement via physical contact and traditional methods is impossible. Time-of-flight (TOF) based time measurement technology is vital in fields such as high-energy physics, medical imaging, radio frequency signal phase difference detection, and traffic monitoring, requiring the use of time-to-digital converters (TDCs). High-precision TODCs are high-precision time measurement instruments with picosecond-level resolution, offering advantages such as high resolution, low power consumption, and low latency, making them widely applicable in these scenarios.

[0003] Traditional TDC (Transmission Controlled Digital) systems mostly employ analog methods, requiring analog-to-digital conversion. Analog circuits often have high power consumption, are sensitive to leakage current, and their performance degrades as the supply voltage decreases. These factors have a far smaller impact on digital circuits than on analog circuits. In laser ranging applications, measurement accuracy is reduced and the dynamic measurement range is insufficient due to the reflectivity of the object's surface and its orientation.

[0004] An existing three-stage high-precision time-to-digital converter structure is as follows: Figure 1 As shown, the Start signal is input to the initial phase adjustment circuit, enabling synchronization between the Start signal and the rising edge of the external input clock CLK. The linear feedback shift register performs high-segment quantization of the measured time using the Stop signal and the synchronized Start signal via the external input clock. The dual-loop delay phase-locked loop provides the delay unit time for the middle segment quantization using the tapped delay line method and the differential delay unit time for the low segment quantization using the differential delay method. The edge detection circuit detects the Stop signal and inputs it as the start time of the low segment quantization to the ring vernier-type time-to-digital converter (TDC). This module performs low-segment quantization on the residual data from the middle segment quantization. The three quantized data segments are sent to the decoding unit for decoding, and then the data readout unit sequentially concatenates the three quantized values ​​to output the time-to-digital converter result. This TDC architecture typically requires a high-frequency reference clock, making it difficult to achieve a large measurement range.

[0005] Another existing three-stage high-precision time-to-digital converter structure is as follows: Figure 2As shown, this structure uses the same high-segment quantization method as the structure described above, except that it employs a ring oscillating TDC for both the middle and low-segment quantization. A two-bit binary synchronous counter inputs the middle-segment quantized value into a direct decoding latch circuit, and a serial data output circuit outputs the three quantized values ​​sequentially. Because this structure uses a ring oscillating TDC for the low-segment quantization, it is difficult to achieve high measurement resolution. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention discloses a high-resolution, multi-purpose time-to-digital converter circuit with a large dynamic range to solve the problems mentioned above.

[0007] To achieve the above objectives, the present invention includes: a control signal generation module 1, a first frequency synthesizer FS12, a fine-time digital converter module 3, a coarse-time digital converter module 4, a reference clock counter module 5, and a data processing and calibration module 6.

[0008] The control signal generation module 1 is used to generate control signals required for the normal operation of the circuit. It has two input terminals and one output terminal. The first input terminal is connected to the start signal Start, and the second input terminal is connected to the stop signal Stop. The output terminal outputs the enable signal en1 and is simultaneously connected to the fine time digital converter module 3 and the coarse time digital converter module 4.

[0009] The first frequency synthesizer FS12 has one input and one output. The input is connected to an external input reference clock Ref_clk, and the output outputs a second control signal V. ctr2 And connect to fine time-to-digital converter module 3;

[0010] The fine-time-to-digital converter module 3 mainly performs low-level quantization for time-to-digital conversion. It has four input terminals and one output terminal. The first input terminal is connected to the enable signal en1 output by the control signal generation module 1, and the second input terminal is connected to the second control signal V output by the first frequency synthesizer FS12. ctr2 The third input terminal is connected to the first control signal V output by the coarse-time digital converter module 4. ctr1 The fourth input terminal is connected to the enable signal en2 output by the coarse time-to-digital converter module 4; the output terminal outputs the low-level quantization result D1 and is connected to the data processing calibration module 6.

[0011] The coarse time-to-digital converter module 4 mainly performs mid-stage quantization for time-to-digital conversion. It has three input terminals and three output terminals. The first input terminal is connected to the enable signal en1 output by the control signal generation module 1, the second input terminal is connected to the external input reference clock Ref_clk, and the third input terminal is connected to the disable signal disen2 output by the reference clock counter module 5. The first output terminal outputs the first control signal V.ctr1 It is connected to the fine time digital converter module 3. The second output terminal outputs the enable signal en2 and is connected to the fine time digital converter module 3 and the reference clock counter module 5. The third output terminal outputs the mid-segment quantization result D2 and is connected to the data processing calibration module 6.

[0012] The reference clock counter module 5 has two input terminals and two output terminals. The first input terminal is connected to the enable signal en2 output by the coarse time-to-digital converter module 4, and the second input terminal is connected to the external input reference clock Ref_clk. The first output terminal outputs the disable signal disen2 and is connected to the coarse time-to-digital converter module 4. The second output terminal outputs the high-level quantization result D3 and is connected to the data processing calibration module 6.

[0013] The data processing calibration module 6 is mainly used to complete the calibration and merging of the final measurement results, and finally output them in binary code form. It has three input terminals and one output terminal. The first input terminal is connected to the low-level quantization result D1 output by the fine time-to-digital converter module 3, the second input terminal is connected to the mid-level quantization result D2 output by the coarse time-to-digital converter module 4, and the third input terminal is connected to the high-level quantization result D3 of the reference clock counter module 5. The output terminal is used to output the binary code of the measurement results.

[0014] The aforementioned fine-time digital converter module 3 includes a low-segment interpolator and a low-segment data processor, wherein: the low-segment interpolator has four input terminals and one output terminal; the first input terminal is connected to the enable signal en1 output by the control signal generation module 1; the second input terminal is connected to the second control signal V output by the first frequency synthesizer FS12. ctr2 The third input terminal is connected to the first control signal V output by the coarse-time digital converter module 4. ctr1 The fourth input terminal is connected to the enable signal en2 output by the coarse time-to-digital converter module 4; the output terminal outputs an M-bit binary string DM to the low-segment data processor; the low-segment data processor is mainly used to preprocess the M-bit binary string DM output by the low-segment interpolator to realize the conversion of the quantization time of the low-segment interpolator. It has one input terminal and one output terminal. The input terminal is connected to the M-bit binary string DM output by the low-segment interpolator, and the output terminal outputs the low-segment quantization result D1 and connects to the data processing calibration module 6.

[0015] The aforementioned low-segment interpolator is a one- or two-dimensional vernier delay chain type TDC, which consists of a first delay chain, a second delay chain, and an M*M dimensional sampling D flip-flop array, where M>1; the first delay chain is composed of M voltage-controlled delay units 1, and the delay duration of a single delay unit is τ1, where τ1>0. This delay duration τ1 is related to the first control signal V. ctr1The voltage value is proportional to the enable signal en1, which enables the first delay chain; the second delay chain consists of M voltage-controlled delay units 2, each with a delay duration of τ2, where τ2 > 0. This delay duration τ2 is proportional to the second control signal V. ctr2 The voltage value is proportional to the enable signal en2, which enables the second delay chain. Since the delay τ1 of the delay unit in the first delay chain is greater than the delay τ2 of the delay unit in the second delay chain, the first delay chain is also called the slow delay chain, and the second delay chain is also called the fast delay chain. The M*M D flip-flop array is used to sample the relative position of the signal transmission in the two delay chains. Its output is an M^2 bit binary string, which is transmitted to the low-segment data processor.

[0016] The aforementioned coarse-time digital converter module 4 includes an intermediate interpolator, a first phase detector PD1, and an intermediate data processor. The intermediate interpolator is a ring oscillator-based TDC with two inputs and three outputs. The first input is connected to an external input reference clock Ref_clk, and the second input is connected to the enable signal en1 of the output of the control signal generation module 1. Its first output outputs a pulse signal Clk representing the output oscillation period of the ring oscillator in the intermediate interpolator, and is connected to the intermediate data processor. Its second output outputs an N-bit binary string representing the phase state of each delay unit on the ring oscillator in the intermediate interpolator, and is connected to the interrupt data processor and the first phase detector PD1. Its third output outputs a first control signal V. ctr1 It is connected to the fine-time digital converter module 3; the first phase detector PD1 has an input terminal and an output terminal. Its input terminal is connected to the N-bit binary string DN, which represents the phase transmission information on the ring oscillator in the mid-section interpolator, and is used to detect the output level jump of each tap of the ring oscillator in the mid-section interpolator; its output terminal outputs an enable signal en2 and is connected to the fine-time digital converter module 3, the reference clock counter module 5, and the mid-section data processor; the mid-section data processor is mainly used to process the quantization results of the mid-section interpolator-ring oscillator. To realize the conversion of the quantization time of the mid-section interpolator, it has four input terminals and one output terminal. The first input terminal is connected to the periodic signal Clk, which represents the integer part of the oscillation period of the ring oscillator output in the mid-section interpolator. The second input terminal is connected to the signal DN, which represents the phase transmission information on the ring oscillator in the mid-section interpolator, that is, the period fraction part that is less than one oscillation period. The third input terminal is connected to the enable signal en2. The fourth input terminal is connected to the disable signal disen2 output by the reference clock counter module 5. Its output terminal outputs the mid-section quantization result D2 and is connected to the data processing calibration module 6.

[0017] The aforementioned mid-section interpolator employs a voltage-controlled ring oscillator (VCO) structure based on a frequency synthesizer. Its output comprises two parts: a periodic signal representing an integer number of oscillation cycles and a fractional portion less than one oscillation cycle. The fractional portion represents the output phase information of the taps of each delay unit in the ring oscillator. The mid-section interpolator includes a frequency controller, N voltage-controlled delay units, and N D flip-flops. The N voltage-controlled delay units are connected end-to-end to form a ring oscillator. The Nth delay unit in this ring oscillator outputs a periodic signal Clk representing the integer portion of the mid-section interpolator's oscillation cycle. The frequency controller, combined with an external input reference clock Ref_clk and the ring oscillator output signal Clk, obtains a frequency control signal V. ctrl The output of the ring oscillator is controlled to be an integer multiple of the reference clock Ref_clk; N D flip-flops latch the outputs of N voltage-controlled delay units respectively, and the enable signal en1 is used to control the working timing of the N D flip-flops.

[0018] The aforementioned mid-section data processor specifically includes a mid-section counter, a status decoder, and a combination decoder functional module. When the enable signal en2 output by the first phase detector PD1 is high, the counter starts counting the signal Clk, which represents the integer part of the oscillation period of the ring oscillator in the mid-section interpolator. The status decoder decodes the phase state of each tap on the ring oscillator delay chain based on the input signal DN, which represents the phase transmission status information on the ring oscillator in the mid-section interpolator, to obtain a fractional part of the period that is less than one oscillation period. The combination decoder then combines and decodes the integer part remembered by the mid-section counter and the fractional part decoded by the decoder to obtain the mid-section bit quantization result D2.

[0019] The aforementioned reference clock counter module 5 includes a high-segment interpolator, a 2-to-1 control selector, and a second phase detector PD2. The high-segment interpolator consists of a reference clock counter with an enable control terminal, having two input terminals and one output terminal. Its first input terminal receives an external input reference clock Ref_clk, serving as the clock control terminal for the counter. The second input terminal is connected to the control signal ctrl output from the 2-to-1 control selector, which enables the reference clock counter to start counting or locks the reference clock to stop counting. Its output terminal outputs the high-segment bit quantization result D3 and connects to the data processing and calibration module 6. The 2-to-1 control selector has three input terminals and one output terminal, with its first input terminal connected to a high level. The second input terminal is connected to a low level, and the third input terminal is connected to the control signal Sel output by the second phase detector PD2; its output terminal outputs the control signal ctrl to the high-segment interpolator to control the start or stop of the reference clock counter in the high-segment interpolator; the second phase detector PD2 has two input terminals and two output terminals. The first input terminal is connected to the enable signal en2 output by the coarse time-to-digital converter module 4, and the second input terminal is connected to the external input reference clock Ref_clk to detect the phase of Ref_clk; its first output terminal outputs the control signal Sel and is connected to a 2-to-1 control selector, and its second output terminal outputs the disable signal disen2 and is connected to the coarse time-to-digital converter module 4 to end the mid-segment quantization process.

[0020] Compared with the prior art, the present invention has the following advantages:

[0021] 1. Unlike traditional three-segment TDCs, this invention does not have very high requirements for the external reference clock frequency. Through its internal frequency multiplier, the required internal high-frequency clock can be flexibly achieved and used as the reference clock for the delay-locked loop. This reduces costs, and the lower external reference clock frequency makes it easier to extend the maximum measurement range.

[0022] 2. Unlike traditional time-delay chain type TDC and clock counting type TDC, the TDC circuit in this invention includes a low-segment interpolator unit—a two-dimensional time-delay chain type time-to-digital converter, which can overcome the limitation of the minimum gate delay determined by the process on the TDC measurement resolution, thereby greatly improving the measurement resolution.

[0023] 3. Unlike traditional successive approximation TDC and vernier delay chain TDC, the TDC circuit in this invention includes a high-segment interpolator, which greatly expands its measurement time range, i.e., the dynamic measurement range, while maintaining a high degree of linearity.

[0024] 4. The three-segment TDC in this invention has the function of continuously receiving and processing multiple stop signals, thereby expanding the working range and application scenarios of the TDC.

[0025] 5. This invention can use high-segment interpolators, mid-segment interpolators, and low-segment interpolators simultaneously according to measurement needs; it can also select only high-segment and mid-segment interpolators as needed, sacrificing measurement resolution for a larger measurement dynamic range while reducing measurement dynamic power consumption; or it can select only mid-segment and low-segment interpolators according to measurement needs, sacrificing measurement dynamic range for high measurement resolution while improving the system's measurement conversion rate, thus having high flexibility in use. Attached Figure Description

[0026] Figure 1 Here is a block diagram of an existing three-segment TDC circuit.

[0027] Figure 2 For another existing three-segment TDC circuit block diagram

[0028] Figure 3 This is a functional block diagram of the TDC system of the present invention.

[0029] Figure 4 This is a structural block diagram of the TDC system of the present invention.

[0030] Figure 5 The measurement principle signal timing diagram of the TDC system of this invention.

[0031] Figure 6 This invention relates to a mid-section interpolator based on a ring oscillating TDC in the TDC system.

[0032] Figure 7 This invention relates to a low-segment interpolator in a TDC system based on a two-dimensional vernier delay chain TDC. Detailed Implementation

[0033] The specific embodiments of the present invention will be further described below with reference to the accompanying drawings.

[0034] Reference Figure 3 The present invention includes: a control signal generation module 1, a first frequency synthesizer FS12, a fine-time digital-to-digital converter module 3, a coarse-time digital-to-digital converter module 4, a reference clock counter module 5, and a data processing and calibration module 6; wherein: the control signal generation module 1 is used to generate control signals required for normal circuit operation, and has two input terminals and one output terminal. The first input terminal is connected to a start signal Start, and the second input terminal is connected to a stop signal Stop; the output terminal outputs an enable signal en1 and is simultaneously connected to the fine-time digital-to-digital converter module 3 and the coarse-time digital-to-digital converter module 4; the first frequency synthesizer FS12 has one input terminal and one output terminal. The input terminal is connected to an external input reference clock Ref_clk, and the output terminal outputs a second control signal V. ctr2It is connected to the fine-time digital converter module 3; the fine-time digital converter module 3 mainly performs low-level quantization of time-to-digital conversion, and has four input terminals and one output terminal. The first input terminal is connected to the enable signal en1 output by the control signal generation module 1, and the second input terminal is connected to the second control signal V output by the first frequency synthesizer FS1. ctr2 The third input terminal is connected to the first control signal V output by the coarse-time digital converter module 4. ctr1 The fourth input terminal is connected to the enable signal en2 output by the coarse time-to-digital converter module 4; the output terminal outputs the low-level quantization result D1 and is connected to the data processing calibration module 6; the coarse time-to-digital converter module 4 mainly completes the mid-level quantization of time-to-digital conversion, and has three input terminals and three output terminals. The first input terminal is connected to the enable signal en1 output by the control signal generation module 1, the second input terminal is connected to the external input reference clock Ref_clk, and the third input terminal is connected to the disable signal disen2 output by the reference clock counter module 5; the first output terminal outputs the first control signal V. ctr1 The system is connected to the fine-time digit converter module 3. The second output terminal outputs an enable signal en2 and connects to the fine-time digit converter module 3 and the reference clock counter module 5. The third output terminal outputs the mid-level quantization result D2 and connects to the data processing calibration module 6. The reference clock counter module 5 has two input terminals and two output terminals. The first input terminal connects to the enable signal en2 output by the coarse-time digit converter module 4, and the second input terminal connects to the external input reference clock Ref_clk. The first output terminal outputs a disable signal disen2 and connects to the coarse-time digit converter module 4. The second output terminal outputs the high-level quantization result D3 and connects to the data processing calibration module 6. The data processing calibration module 6 is mainly used to complete the calibration and merging of the final measurement results, and finally outputs them in binary code form. It has three input terminals and one output terminal. The first input terminal connects to the low-level quantization result D1 output by the fine-time digit converter module 3, the second input terminal connects to the mid-level quantization result D2 output by the coarse-time digit converter module 4, and the third input terminal connects to the high-level quantization result D3 of the reference clock counter module 5. The output terminal is used to output the binary code of the measurement results.

[0035] Reference Figure 4 The fine-time digital converter module 3 includes a low-segment interpolator and a low-segment data processor, wherein: the low-segment interpolator has four input terminals and one output terminal; the first input terminal is connected to the enable signal en1 output by the control signal generation module 1; the second input terminal is connected to the second control signal V output by the first frequency synthesizer FS12. ctr2 The third input terminal is connected to the first control signal V output by the coarse-time digital converter module 4. ctr1The fourth input terminal is connected to the enable signal en2 output by the coarse time-to-digital converter module 4; the output terminal outputs an M^2-bit binary string DM to the low-segment data processor; the low-segment data processor is mainly used to preprocess the M^2-bit binary string DM output by the low-segment interpolator to realize the conversion of the quantization time of the low-segment interpolator. It has one input terminal and one output terminal. The input terminal is connected to the M^2-bit binary string DM output by the low-segment interpolator, and the output terminal outputs the low-segment quantization result D1 and connects to the data processing calibration module 6.

[0036] The coarse time-to-digital converter module 4 includes a mid-stage interpolator, a first phase detector PD1, and a mid-stage data processor. The mid-stage interpolator is a voltage-controlled ring oscillator (TDC) based on a frequency synthesizer. It has two inputs and three outputs. The first input is connected to an external input reference clock Ref_clk, and the second input is connected to the enable signal en1 output by the control signal generation module 1. Its first output outputs a signal Clk representing the oscillation period of the ring oscillator in the mid-stage interpolator, and is connected to the mid-stage data processor. The second output outputs a signal DN representing the phase transmission state signal of the ring oscillator in the mid-stage interpolator for less than one oscillation period, and is connected to the mid-stage data processor and the first phase detector PD1. The third output outputs a first control signal V. ctr1 The first phase detector PD1 is connected to the fine-time digital converter module 3. Its input terminal is connected to the signal DN, representing the phase transmission state of the ring oscillator, output by the mid-section interpolator, used to detect level transitions in the ring oscillator tap output of the mid-section interpolator. Its output terminal outputs an enable signal en2 and is connected to the fine-time digital converter module 3, the reference clock counter module 5, and the mid-section data processor. The mid-section data processor is mainly used to process the quantization results of the mid-section interpolator—ring oscillator—to realize the conversion of the quantization time of the mid-section interpolator. It has four input terminals and one output terminal. The first input terminal is connected to the oscillation period signal Clk, representing the output of the mid-section interpolator. The second input terminal is connected to the fractional output signal DN, representing the portion of the ring oscillator output less than one oscillation period in the mid-section interpolator. The third input terminal is connected to the enable signal en2, and the fourth input terminal is connected to the disable signal disen2 output by the reference clock counter module 5. Its output terminal outputs the mid-section bit quantization result D2 and is connected to the data processing calibration module 6.

[0037] The reference clock counter module 5 includes a high-segment interpolator, a 2-to-1 control selector, and a second phase detector PD2. The high-segment interpolator consists of a reference clock counter with an enable control terminal, having two input terminals and one output terminal. Its first input terminal receives an external input reference clock Ref_clk, serving as the clock control terminal for the counter. The second input terminal is connected to the control signal ctrl output from the 2-to-1 control selector, which enables the reference clock counter to start counting or locks it to stop counting. Its output terminal outputs the high-segment bit quantization result D3 and connects to the data processing and calibration module 6. The 2-to-1 control selector has three input terminals and one output terminal; its first input terminal is connected to a high level. The second input terminal is connected to a low level, and the third input terminal is connected to the control signal Sel output by the second phase detector PD2; its output terminal outputs the control signal ctrl to the high-segment interpolator to control the start or stop of the reference clock counter in the high-segment interpolator; the second phase detector PD2 has two input terminals and two output terminals. The first input terminal is connected to the enable signal en2 output by the coarse time-to-digital converter module 4, and the second input terminal is connected to the external input reference clock Ref_clk to detect the phase of Ref_clk; its first output terminal outputs the control signal Sel and is connected to a 2-to-1 control selector, and its second output terminal outputs the disable signal disen2 and is connected to the coarse time-to-digital converter module 4 to end the mid-segment quantization process.

[0038] Reference Figure 6 The intermediate interpolator adopts a voltage-controlled ring oscillator (VCO) structure based on a frequency synthesizer. Its output includes two parts: a periodic signal representing the integer oscillation period and a fractional part less than one oscillation period. The fractional part represents the current output phase information of each delay unit tap in the ring oscillator. The intermediate interpolator includes a frequency controller, N voltage-controlled delay units, and N D flip-flops (N>1). The N voltage-controlled delay units are connected end-to-end to form a ring oscillator. The Nth delay unit in this ring oscillator outputs a periodic signal Clk representing the integer part of the ring oscillation period in the intermediate interpolator. The frequency controller combines the external input reference clock Ref_clk and the ring oscillator output signal Clk to obtain the frequency control signal V. ctrlThe output of the ring oscillator is controlled to be an integer multiple of the reference clock Ref_clk. N D flip-flops latch the outputs of N voltage-controlled delay units to obtain the signal DN representing the fractional part of the intermediate interpolator. The enable signal en1 controls the operating timing of the N D flip-flops. The intermediate data processor specifically includes an intermediate counter, a state decoder, and a combination decoder. When the first phase detector PD1 detects the first 1 in the signal DN representing the output level status information of each tap of the ring oscillator in the intermediate interpolator, the output enable signal en2 is high, and the counter starts counting the periodic square wave signal Clk representing the output of the intermediate interpolator. The state decoder decodes the phase status of each tap on the ring oscillator delay chain according to the fractional part of the ring oscillator signal DN, which is less than one oscillation period, to obtain the fractional part of less than one oscillation period. The combination decoder combines and decodes the integer part remembered by the counter and the fractional part decoded by the decoder to obtain the intermediate bit quantization result D2.

[0039] Reference Figure 7 The low-segment interpolator is a two-dimensional vernier delay chain type TDC, which consists of a first delay chain, a second delay chain, and an M*M dimensional sampling D flip-flop array, where M>1; the first delay chain is composed of M voltage-controlled delay units 1, and the delay duration of a single delay unit is τ1, where τ1>0. This delay duration τ1 is related to the first control signal V. ctr1 The voltage value is proportional to the enable signal en1, which enables the first delay chain; the second delay chain consists of M voltage-controlled delay units 2, each with a delay duration of τ2, where τ2 > 0. This delay duration τ2 is proportional to the second control signal V. ctr2 The voltage value is proportional to the enable signal en2, which enables the second delay chain. Since the delay τ1 of the delay unit in the first delay chain is greater than the delay τ2 of the delay unit in the second delay chain, the first delay chain is also called the slow delay chain, and the second delay chain is also called the fast delay chain. The M*M dimension sampling D flip-flop array is used to sample the relative position of the signal transmission in the two delay chains. Its output is an M^2 bit binary string, which is transmitted to the low-segment data processor.

[0040] Reference Figures 4-7 The working principle of this invention is as follows: the external input reference clock Ref_clk passes through the frequency controller in the intermediate interpolator to obtain the first control signal V. ctrl1 The second control signal V is obtained after passing through the first frequency synthesizer FS12. ctrl2 Among them, the first control signal V ctrl1 The second control signal V controls the oscillation frequency of the first delay chain in the low-segment interpolator. ctrl2The frequency of the second delay chain in the low-segment interpolator is controlled. When the Start signal arrives, the output en1 of the control signal generation module 1 goes high, and the first delay chain (slow chain) in the low-segment interpolator starts working. The N D flip-flops in the median interpolator are enabled. When the first phase detector PD1 detects the first 1 in the signal DN representing the phase transmission status information on the ring oscillator in the median interpolator, the output enable signal en2 goes high, and the second delay chain (fast chain) in the low-segment interpolator starts working. When the fast chain catches up with the slow chain, it means that the low-segment quantization is over. The quantization result is recorded by the low-segment data processor and sent to the data processing calibration unit 6. The measurement result of the low-segment interpolator is t1. At the same time, when the enable signal en2 goes high, the counter in the median data processor starts counting the periodic signal Clk, which represents the integer part of the oscillation period of the ring oscillator in the median interpolator. The state decoder then counts the periodic signal Clk, which represents the integer part of the oscillation period of the ring oscillator in the median interpolator. The fractional period signal DN, representing the initial phase state of the ring oscillator, is used to decode the phase states of each tap on the ring oscillator delay chain, yielding a fractional portion less than one oscillation cycle. The combination decoder then combines and decodes the integer portion remembered by the counter and the fractional portion decoded by the decoder to obtain the mid-segment quantization result D2. Simultaneously, when the enable signal en2 is high, the second phase detector PD2 starts working. After detecting the first rising edge of the external reference clock Ref_clk, the control signal Sel goes high, and the two-to-one control selector outputs a high level to the high-segment interpolator. Thus, the high-segment interpolator starts counting Ref_clk, and the disable signal disen2 output by the second phase detector PD2 becomes effective. Therefore, the mid-segment data processor stops receiving the output of the mid-segment interpolator, which means that the mid-segment interpolator quantization is complete, and its quantization result is t2.

[0041] When the Stop signal arrives, the control signal generation module 1 also generates an enable signal en1. The first delay chain (slow chain) in the low-segment interpolator starts working, and the N D flip-flops in the median interpolator are enabled. When the first phase detector PD1 detects the first 1 in the signal DN representing the phase transmission status information on the ring oscillator in the median interpolator, the output enable signal en2 goes high, and the second delay chain (fast chain) in the low-segment interpolator starts working. When the fast chain catches up with the slow chain, it means that the low-segment quantization is over. The quantization result is recorded by the low-segment data processor and sent to the data processing calibration unit 6. The measurement result of the low-segment interpolator is t4. At the same time, when the enable signal en2 goes high, the counter in the median data processor starts counting the period signal Clk, which represents the integer part of the oscillation period of the ring oscillator output in the median interpolator. The status decoder then counts the period signal Clk, which represents the integer part of the oscillation period of the ring oscillator output in the median interpolator. The fractional-period signal DN, representing the initial phase state of the oscillator, is used to decode the phase states of each tap in the ring oscillator delay chain, yielding a fractional portion less than one oscillation cycle. The combination decoder then combines and decodes the integer portion counted by the counter and the fractional portion decoded by the decoder to obtain the mid-segment quantization result D2. Simultaneously, when the enable signal en2 is high, the second phase detector PD2 starts operating. Upon detecting the first rising edge of the external reference clock Ref_clk, the control signal Sel goes low, and the 2-to-1 selector outputs a low level to the high-segment interpolator, causing the high-segment interpolator to stop operating and high-segment quantization to end, with the result being t3. Simultaneously, the disable signal disen2 output by the second phase detector PD2 becomes active, causing the mid-segment data processor to stop receiving the output of the mid-segment interpolator, signifying the end of mid-segment quantization, with the result being t5. Each quantization result is input to the data processing calibration module 6, which calibrates and merges the final measurement results and outputs them in binary code. Figure 5 The time quantization relationship between the low-segment interpolator, the middle-segment interpolator and the high-segment interpolator is shown. The corresponding measurement time and the measurement time relationship of each segment interpolator can be expressed as T = t1 + t2 + t3 - t4 - t5.

[0042] The above description is merely a specific example of the present invention and does not constitute any limitation on the present invention. Obviously, those skilled in the art, after understanding the content and principles of the present invention, may make various modifications and changes in form and details without departing from the principles and structure of the present invention. However, these modifications and changes based on the ideas of the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A large dynamic measurement range high resolution multi-purpose time-to-digital converter circuit, the circuit composition mainly comprising: a control signal generation module (1), a first frequency synthesizer FS1 (2), a fine time-to-digital converter module (3), a coarse time-to-digital converter module (4), a reference clock counter module (5), and a data processing calibration module (6); characterized in that: the control signal generation module (1) is used to generate control signals required for normal operation of the circuit, has two input terminals and an output terminal, the first input terminal is connected to a start signal Start, the second input terminal is connected to a stop signal Stop; the output terminal outputs an enable signal en1 and is connected to the fine time-to-digital converter module (3) and the coarse time-to-digital converter module (4) at the same time; The first frequency synthesizer FS1(2) has an input terminal connected to an external input reference clock Ref_clk and an output terminal outputting a second control signal V ctr2 and connected to the fine time-to-digital converter module (3); The fine time-to-digital converter module (3) comprises a low-stage interpolator and a low-stage data processor, the low-stage interpolator is a two-dimensional vernier delay chain type time-to-digital converter, and the fine time-to-digital converter module (3) mainly completes low-stage bit quantization of time-to-digital conversion, has four input ends and one output end, the first input end is connected with an enabling signal en1 output by the control signal generation module (1), the second input end is connected with a second control signal V ctr2 output by the first frequency synthesizer FS1 (2), the third input end is connected with a first control signal V ctr1 output by the coarse time-to-digital converter module (4), and the fourth input end is connected with an enabling signal en2 output by the coarse time-to-digital converter module (4); and the output end outputs a low-stage bit quantization result D1 and is connected to the data processing and calibration module (6). The coarse time-to-digital converter module (4) comprises a middle-stage interpolator, a first phase detector PD1 and a middle-stage data processor, wherein the middle-stage interpolator is a ring-oscillation time-to-digital converter based on a frequency synthesizer, the coarse time-to-digital converter module (4) mainly completes middle-stage bit quantization of time-to-digital conversion, has three input ends and three output ends, the first input end is connected with an enabling signal en1 output by the control signal generation module (1), the second input end is connected with an external input reference clock Ref_clk, and the third input end is connected with a disabling signal disen2 output by the reference clock counter module (5); the first output end outputs a first control signal V ctr1 and is connected to the fine time-to-digital converter module (3), the second output end outputs an enabling signal en2 and is connected to the fine time-to-digital converter module (3) and the reference clock counter module (5), and the third output end outputs a middle-stage bit quantization result D2 and is connected to the data processing calibration module (6); the reference clock counter module (5) comprises a high-stage interpolator, a two-way control selector, and a second phase detector PD2, wherein the high-stage interpolator is composed of a reference clock counter with an enable control terminal, the reference clock counter module (5) has two input terminals and two output terminals, the first input terminal is connected to an enable signal en2 output by the coarse time-to-digital converter module (4), the second input terminal is connected to an external input reference clock Ref_clk; the first output terminal outputs a disable signal disen2 and is connected to the coarse time-to-digital converter module (4), and the second output terminal outputs a high-stage bit quantization result D3 and is connected to the data processing calibration module (6); the data processing calibration module (6) is mainly used to complete calibration and merging of a final measurement result and finally outputs in the form of a binary code, has three input terminals and an output terminal, the first input terminal is connected to a low-stage bit quantization result D1 output by the fine time-to-digital converter module (3), the second input terminal is connected to a middle-stage bit quantization result D2 output by the coarse time-to-digital converter module (4), and the third input terminal is connected to the high-stage bit quantization result D3 of the reference clock counter module (5); the output terminal is used to output a binary code of the measurement result.

2. The large dynamic range high resolution multipurpose time-to-digital converter circuit of claim 1, wherein, The low-stage interpolator is provided with four input ends and an output end, the first input end is connected with the enable signal en1 outputted by the control signal generating module (1), the second input end is connected with the second control signal V ctr2 outputted by the first frequency synthesizer FS1 (2), the third input end is connected with the first control signal V ctr1 outputted by the coarse time digital converter module (4), the fourth input end is connected with the enable signal en2 outputted by the coarse time digital converter module (4), and the output end outputs the M-bit binary string DM to the low-stage data processor. the low-stage data processor is mainly used to pre-process an M-bit binary string DM output by the low-stage interpolator to realize conversion of a quantized time amount of the low-stage interpolator, has one input terminal and one output terminal, the input terminal is connected to the M-bit binary string DM output by the low-stage interpolator, and the output terminal outputs a low-stage bit quantization result D1 and is connected to the data processing calibration module (6).

3. The large dynamic range high resolution multipurpose time-to-digital converter circuit of claim 1, wherein, The middle section interpolator has two input terminals and three output terminals. The first input terminal is connected with an external input reference clock Ref_clk, and the second input terminal is connected with the enable signal en1 outputted by the control signal generating module (1). The first output terminal outputs a period oscillation signal Clk representing the ring oscillator in the middle section interpolator and is connected to the middle section data processor. The second output terminal outputs an N-bit binary string DN representing the phase state of each delay unit outputted by the ring oscillator in the middle section interpolator, which also represents the fractional part of less than one oscillation period and is connected to the interrupt data processor and the first phase detector PD1. The third output terminal outputs the first control signal V ctr1 and is connected to the fine time digital converter module (3). the first phase detector PD1 is provided with one input terminal and one output terminal, the input terminal is connected to an N-bit binary string DN representing a fractional part of an oscillation period of an annular oscillator in the middle-stage interpolator output by the middle-stage interpolator, and is used to detect a level jump of a tap output level of the annular oscillator in the middle-stage interpolator; the output terminal outputs an enable signal en2 and is connected to the fine time-to-digital converter module (3), the reference clock counter module (5), and the middle-stage data processor. The middle section data processor is mainly used for processing the quantization result of the middle section interpolator, i.e. the ring oscillator, to realize the conversion of the quantization time amount of the middle section interpolator. The middle section data processor is provided with four input ends and one output end. The first input end is connected with the output periodic oscillation signal Clk representing the ring oscillator in the middle section interpolator. The second input end is connected with the N-bit binary string DN representing the phase state of the output of each delay unit of the ring oscillator in the middle section interpolator. The third input end is connected with the enable signal en2. The fourth input end is connected with the disable signal disen2 output by the reference clock counter module (5). The output end outputs the middle section bit quantization result D2 and is connected to the data processing calibration module (6).

4. The large dynamic range high resolution multipurpose time-to-digital converter circuit of claim 1, wherein, The high section interpolator is provided with two input ends and one output end. The first input end receives the external input reference clock Ref_clk as the clock control end of the counter. The second input end is connected with the control signal ctrl output by the two-option control selector. The control signal can enable the reference clock counter to start counting or can lock the reference clock to stop counting. The output end outputs the high section bit quantization result D3 and is connected to the data processing calibration module (6). The two-option control selector is provided with three input ends and one output end. The first input end is connected with the high level. The second input end is connected with the low level. The third input end is connected with the control signal Sel output by the second phase detector PD2. The output end outputs the control signal ctrl to the high section interpolator for controlling the start or stop of the reference clock counter in the high section interpolator. The second phase detector PD2 is provided with two input ends and two output ends. The first input end is connected with the enable signal en2 output by the coarse time digital converter module (4). The second input end is connected with the external input reference clock Ref_clk for detecting the phase of Ref_clk. The first output end outputs the control signal Sel and is connected to the two-option control selector. The second output end outputs the disable signal disen2 and is connected to the coarse time digital converter module (4) for ending the middle section quantization process.

5. The large dynamic range high resolution multipurpose time-to-digital converter circuit of claim 2, wherein: The low-stage interpolator comprises a first delay chain, a second delay chain and a M*M-dimension sampling D flip-flop array, M>1; the first delay chain is composed of M voltage-controlled delay units 1, the delay time of a single delay unit is τ1, τ1>0, the delay time τ1 is proportional to the voltage value of a first control signal V ctr1 , and an enable signal en1 is used to enable the first delay chain; the second delay chain is composed of M voltage-controlled delay units 2, the delay time of a single delay unit is τ2, τ2>0, the delay time τ2 is proportional to the voltage value of a second control signal V ctr2 , and an enable signal en2 is used to enable the second delay chain; since the delay time τ1 of the delay unit in the first delay chain is greater than the delay time τ2 of the delay unit in the second delay chain, the first delay chain is called a slow delay chain, and the second delay chain is called a fast delay chain; the M*M-dimension sampling D flip-flop array is used to sample the relative positions of the signal transmission in the two delay chains, and the output is a M^2-bit binary string, which is transmitted to a low-stage data processor for preprocessing.

6. The large dynamic range high resolution multipurpose time-to-digital converter circuit of claim 3, wherein: The middle interpolator adopts a frequency synthesizer based on a ring oscillator structure to realize a coarse quantization time-to-digital converter, and the output of the frequency synthesizer includes two parts, one part is an output oscillation period of the ring oscillator, and the other part is a fractional part less than one oscillation period; the fractional part is represented by current output phase information of taps of each delay unit of the ring oscillator; the middle interpolator includes a frequency controller, N voltage-controlled delay units, and N D flip-flops, and N>1; the N voltage-controlled delay units are connected in a ring oscillator structure, and the Nth delay unit in the ring oscillator is used as an output terminal of the ring oscillator to output a signal Clk representing an integer part of an oscillation period of the middle interpolator; the frequency controller combines an external input reference clock Ref_clk and the output signal Clk of the ring oscillator to obtain a first control signal Vctrl1, so as to control the output of the ring oscillator to be an integer multiple of the reference clock Ref_clk, and also control the time length of each delay unit in a first delay chain in a low interpolator; the N D flip-flops latch the outputs of the N voltage-controlled delay units, and an enable signal en1 is used to control the working time of the N D flip-flops.

7. The large dynamic range high resolution multipurpose time-to-digital converter circuit of claim 3, wherein: The middle data processor specifically includes a middle counter, a state decoder, and a combination decoder functional module; when a first phase detector PD1 detects a first 1 in a signal DN representing a fractional part of the middle interpolator, an enable signal en2 is high, and at this time, the middle counter starts to count a signal Clk representing an integer part of the middle interpolator; the state decoder samples and decodes a phase state of a last tap in a delay chain of the ring oscillator according to the signal DN representing the fractional part of the output oscillation period of the middle interpolator, to obtain the fractional part less than one oscillation period; and the combination decoder recombines the integer part counted by the counter and the fractional part decoded by the decoder, to obtain a middle bit quantization result D2.

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