A pixel circuit, a driving method, a display panel and a display device

Abstract

Embodiments of the present application provide a pixel circuit, a driving method, a display panel and a display device, and relate to the technical field of display panels. The pixel circuit comprises a first light-emitting control module, a driving module and a pre-charging module. The working process of the pixel circuit comprises a data writing stage and a light-emitting stage. The control end of the pre-charging module is electrically connected with a pre-charging control signal line, the first end of the pre-charging module is electrically connected with a third node, and the second end of the pre-charging module is electrically connected with the first pole of a light-emitting element. In a first time period after the data writing stage and before the light-emitting stage, the first light-emitting control module and the driving module are turned on, and the pre-charging module is turned off. In a second time period after the first time period and before the light-emitting stage, the first light-emitting control module is turned off, and the pre-charging module is turned on. According to the embodiments of the present application, the uniformity of light emission and the display effect of the display panel can be effectively improved.

Description

Technical Field

[0001] This application belongs to the field of display panel technology, and particularly relates to a pixel circuit, driving method, display panel and display device. Background Technology

[0002] With the increasing prevalence of Organic Light Emitting Diodes (OLEDs) and the rapid development of display technology, coupled with the growing demands of consumers for display panels, the functions integrated into display panels are becoming increasingly diverse. Currently, display panels commonly use OLEDs as organic light-emitting elements; therefore, the proper functioning of OLEDs is crucial for various screen displays. However, the inventors of this application have discovered that, in the current display process, the uniformity of light emission and the overall display effect still need further improvement. Summary of the Invention

[0003] This application provides a pixel circuit, driving method, display panel, and display device, which can effectively improve the uniformity of light emission and display effect of the display panel.

[0004] In a first aspect, embodiments of this application provide a pixel circuit, the pixel circuit comprising:

[0005] The first light-emitting control module, driving module, and pre-charging module; the working process of the pixel circuit includes a data writing stage and a light-emitting stage;

[0006] The control terminal of the drive module is electrically connected to the first node, the first terminal of the drive module is electrically connected to the second node, and the second terminal of the drive module is electrically connected to the third node.

[0007] The control terminal of the first light-emitting control module is electrically connected to the first light-emitting control signal line, the first terminal of the first light-emitting control module is electrically connected to the first power supply voltage signal terminal, and the second terminal of the first light-emitting control module is electrically connected to the second node.

[0008] The control terminal of the pre-charge module is electrically connected to the pre-charge control signal line, the first terminal of the pre-charge module is electrically connected to the third node, and the second terminal of the pre-charge module is electrically connected to the first electrode of the light-emitting element.

[0009] In the first time period after the data writing stage and before the light emission stage, the first light emission control module and the driver module are turned on, and the pre-charging module is turned off.

[0010] In the second time period, which is after the first time period and before the light emission stage, the first light emission control module is turned off and the pre-charging module is turned on.

[0011] Based on the same inventive concept, in a second aspect, embodiments of this application provide a driving method applied to the pixel circuit of the aforementioned first aspect embodiment, the driving method comprising:

[0012] In the first time period after the data writing stage and before the light emission stage, the first light emission control module and the driving module are turned on, and the pre-charging module is turned off, so that the first power supply voltage signal provided by the first power supply voltage signal terminal is transmitted to the third node through the first light emission control module and the driving module.

[0013] In the second time period after the first time period and before the light emission stage, the first light emission control module is turned off and the pre-charging module is turned on, so that the first power supply voltage signal of the third node is transmitted to the first electrode of the light emission element through the pre-charging module.

[0014] Based on the same inventive concept, in a third aspect, embodiments of this application provide a display panel that includes the pixel circuit described in the first aspect of the embodiments.

[0015] Based on the same inventive concept, in a fourth aspect, embodiments of this application provide a display device, which includes a display panel as described in the aforementioned third aspect embodiment.

[0016] As described above, an embodiment of this application provides a pixel circuit, driving method, display panel, and display device. The pixel circuit includes a first light-emitting control module, a driving module, and a pre-charging module. During a first time period after the data writing phase, the first light-emitting control module and the driving module are turned on, transmitting the first power supply voltage provided by the first power supply voltage signal terminal to the third node to charge the third node. During a second time period after the first time period and before the light-emitting phase, the first light-emitting control module is turned off, and the pre-charging module is turned on, transmitting the pre-charged voltage signal at the third node to the anode of the light-emitting element, thereby pre-charging the anode of the light-emitting element in advance.

[0017] Compared to existing technologies, the pixel circuit, driving method, display panel, and display device of this application embodiment achieve pre-charging of the anode of the light-emitting element by setting the aforementioned first time period and second time period between the data writing stage and the light-emitting stage. In this way, different light-emitting elements can quickly respond and emit light when the formal light-emitting stage is activated, indirectly avoiding the problem of inconsistent charging times required by different light-emitting elements affecting the display effect during the light-emitting stage. This solution can help improve color shift phenomena and effectively improve the uniformity of light emission and display effect of the display panel. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of this application;

[0020] Figure 2 This is a timing diagram of a pixel circuit provided in an embodiment of this application;

[0021] Figure 3 This is a timing diagram of another pixel circuit provided in an embodiment of this application;

[0022] Figure 4 This is a schematic diagram of another pixel circuit structure provided in an embodiment of this application;

[0023] Figure 5 This is a timing diagram of another pixel circuit provided in an embodiment of this application;

[0024] Figure 6 This is a schematic diagram of another pixel circuit provided in an embodiment of this application;

[0025] Figure 7 This is a schematic diagram of another pixel circuit provided in an embodiment of this application;

[0026] Figure 8 This is a schematic diagram of another pixel circuit provided in an embodiment of this application;

[0027] Figure 9 This is a schematic diagram of another pixel circuit provided in an embodiment of this application;

[0028] Figure 10 This is a schematic diagram of another pixel circuit provided in an embodiment of this application;

[0029] Figure 11 This is a schematic diagram of another pixel circuit provided in an embodiment of this application;

[0030] Figure 12 This is a timing diagram of another pixel circuit provided in an embodiment of this application;

[0031] Figure 13 This is a schematic diagram of another pixel circuit provided in an embodiment of this application;

[0032] Figure 14 This is a timing diagram of another pixel circuit provided in an embodiment of this application;

[0033] Figure 15 This is a timing diagram of another pixel circuit provided in an embodiment of this application;

[0034] Figure 16 This is a timing diagram of another pixel circuit provided in an embodiment of this application;

[0035] Figure 17 This is a timing diagram of another pixel circuit provided in an embodiment of this application;

[0036] Figure 18 This is a timing diagram of another pixel circuit provided in an embodiment of this application;

[0037] Figure 19 This is a flowchart illustrating a driving method provided in an embodiment of this application;

[0038] Figure 20 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application.

[0039] Figure 21 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0040] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0041] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0042] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0043] It should be noted that the transistors in the embodiments of this application can be either N-type or P-type transistors. For N-type transistors, the enable level is high and the disable level is low. That is, when the gate of an N-type transistor is high, its first and second terminals are connected; when the gate of an N-type transistor is low, its first and second terminals are turned off. For P-type transistors, the enable level is low and the disable level is high. That is, when the control terminal of a P-type transistor is low, its first and second terminals are connected; when the control terminal of a P-type transistor is high, its first and second terminals are turned off. In specific implementation, the gate of each transistor is used as its control electrode. Furthermore, depending on the signal and type of the gate of each transistor, its first electrode can be used as the source and its second electrode as the drain, or its first electrode can be used as the drain and its second electrode as the source. No distinction is made here. In addition, the enable level and non-enable level in the embodiments of the present invention are general terms. The enable level refers to any level that can turn on the transistor, and the non-enable level refers to any level that can turn off / turn off the transistor.

[0044] In the embodiments of this application, the term "electrical connection" can refer to a direct electrical connection between two components, or it can refer to an electrical connection between two components via one or more other components.

[0045] In the embodiments of this application, the first node, the second node, and the third node are defined only for the convenience of describing the circuit structure, and the first node, the second node, and the third node are not actual circuit units.

[0046] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this application can be combined with each other without contradiction.

[0047] Before describing the technical solutions provided in the embodiments of this application, in order to facilitate understanding of the embodiments of this application, this application first specifically explains the problems existing in the related technologies:

[0048] As mentioned above, the inventors of this application have discovered that with the rapid development of display technology, people's demand for display panels is increasing daily. Therefore, how to fully guarantee the display effect of display panels is one of the hot issues of continuous concern in this field.

[0049] Further research by the inventors of this application revealed that, as a current-driven element, the luminous intensity of an OLED is closely related to its driving current. Within the commonly used brightness range, the luminous intensity of an OLED increases with the increase of the driving current. In actual display illumination, an OLED device can be simply represented as a parallel model of a resistor and a capacitor. During the luminous phase of a pixel's driving cycle, the OLED anode must be charged first; that is, the OLED can only begin to emit light after its equivalent capacitance has been fully charged. When the capacitance values ​​of different OLED capacitors vary significantly, the charging time required for each capacitor will also be inconsistent, significantly impacting the luminous response time within the luminous phase, thus affecting the uniformity of the display panel's luminous intensity and the display effect.

[0050] Currently, in low-brightness mode, due to the timing of the pixel circuits in the display panel, the light-emitting elements need to be charged after the light-emitting control transistor is turned on before they can start emitting light. This means that when the capacitance values ​​of the internal capacitors of different light-emitting elements vary significantly, the charging time required for each element will also be inconsistent, which has a significant impact on the light-emitting response time during the light-emitting stage, leading to color shift and severely affecting the uniformity of light emission and display effect of the display panel.

[0051] To address the aforementioned technical problems, this application provides a pixel circuit, a driving method, a display panel, and a display device, which can solve the problem in the related art where the charging time required for different light-emitting elements is inconsistent during the light-emitting stage, resulting in differences in the actual lighting time of each light-emitting element, thereby affecting the uniformity of the display panel and the display effect.

[0052] It should be noted that the embodiments provided in this application are not intended to limit the scope of this application.

[0053] The technical concept of this application embodiment lies in the fact that different light-emitting elements require different anode charging times during the light-emitting stage. This can be addressed by pre-charging the different light-emitting elements through the pixel circuit to improve the display effect. Specifically, the anodes of the light-emitting elements can be pre-charged during the period after the data writing stage and before the light-emitting stage. Thus, when the light-emitting stage is officially activated, since the anode charging of each light-emitting element has been completed, each element can quickly respond and emit light after the light-emitting stage is activated. This effectively avoids the problem of inconsistent charging times for different light-emitting elements affecting the display effect during the light-emitting stage, helping to improve color shift and enhance the uniformity and display effect of the display panel.

[0054] The pixel circuit provided in the embodiments of this application will be described below.

[0055] Figure 1 A schematic diagram of a pixel circuit provided in an embodiment of this application is shown. Figure 1 As shown, a pixel circuit 10 provided in this application embodiment may include a first light emission control module 101, a driving module 102, and a pre-charging module 103.

[0056] Specifically, the control terminal of the driving module 102 is electrically connected to the first node N1, the first end of the driving module 102 is electrically connected to the second node N2, and the second end of the driving module 102 is electrically connected to the third node N3. The control terminal of the first light-emitting control module 101 is electrically connected to the first light-emitting control signal line Emit1, the first end of the first light-emitting control module 101 is electrically connected to the first power supply voltage signal terminal PVDD, and the second end of the first light-emitting control module 101 is electrically connected to the second node N2. The control terminal of the pre-charging module 103 is electrically connected to the pre-charging control signal line Pre, the first end of the pre-charging module 103 is electrically connected to the third node N3, and the second end of the pre-charging module 103 is electrically connected to the first electrode of the light-emitting element. The second electrode of the light-emitting element is electrically connected to PVEE, which is the second power supply voltage signal terminal. The aforementioned first power supply voltage signal terminal PVDD provides a first power supply voltage, which can be a positive voltage signal. The second power supply voltage signal terminal PVEE provides a second power supply voltage, which can be a negative voltage signal. The aforementioned light-emitting element can be an LED (Light-Emitting Diode), an OLED (Organic Electroluminescence Display), or others.

[0057] Combination Figure 1 Please see below. Figure 2 , Figure 2This is a timing diagram of a pixel circuit provided in an embodiment of this application. In this embodiment, the on-level is low and the off-level is high.

[0058] like Figure 2 As shown, the operation of the pixel circuit 10 can include a data writing stage and a light-emitting stage. During the data writing stage, data signals are written to the control terminal of the driving module 102. During the light-emitting stage, the driving module 102 provides a driving current based on the data voltage written in the previous data writing stage to drive the light-emitting element to emit light.

[0059] During the first time period T1, after the data writing phase and before the light emission phase, the first light emission control signal line Emit1 provides a conduction level. The first light emission control module 101, under the control of Emit1, conducts, transmitting the first power supply voltage provided by the first power supply voltage signal terminal PVDD to the first terminal of the driving module 102, i.e., the second node N2. At this time, since the control terminal of the driving module 102 has pre-written a data voltage (lower than the first power supply voltage), the driving module 102 conducts, transmitting the node potential at the second node N2 to the third node N3, thereby charging the third node N3. During this first time period T1, the pre-charge control signal line Pre provides a cutoff level, and the pre-charge module 103 remains off to ensure that the light-emitting element does not emit light before reaching the light emission phase.

[0060] During the second time period T2, which follows the first time period T1 and precedes the light-emitting stage, the pre-charge control signal line Pre provides an on-level. Under the control of Pre, the pre-charge module 103 is turned on, transmitting the pre-charged voltage signal at the third node N3 to the anode of the light-emitting element, i.e., the fourth node N4. This achieves pre-charging of the anode of the light-emitting element before the light-emitting stage. During this second time period T2, the first light-emitting control signal line Emit1 provides a off-level. Under the control of Emit1, the first light-emitting control module 101 is turned off to ensure that the light-emitting element does not emit light before reaching the light-emitting stage.

[0061] As described above, a pixel circuit 10 according to an embodiment of this application includes a first light-emitting control module 101, a driving module 102, and a pre-charging module 103. During a first time period T1 after the data writing phase, the first light-emitting control module 101 and the driving module 102 are turned on, transmitting the first power supply voltage provided by the first power supply voltage signal terminal PVDD to the third node N3 to charge the third node N3. During a second time period T2 after the first time period T1 and before the light-emitting phase, the first light-emitting control module 101 is turned off, and the pre-charging module 103 is turned on, transmitting the pre-charged voltage signal at the third node N3 to the anode of the light-emitting element, thereby pre-charging the anode of the light-emitting element in advance.

[0062] Compared to existing technologies, a pixel circuit 10 in this application embodiment achieves pre-charging of the anode of the light-emitting element by setting the aforementioned first time period T1 and second time period T2 between the data writing stage and the light-emitting stage. In this way, different light-emitting elements can quickly respond and emit light when the formal light-emitting stage is activated, indirectly avoiding the problem of inconsistent charging times required by different light-emitting elements affecting the display effect during the light-emitting stage. This pixel circuit 10 can help improve color shift phenomena and effectively improve the uniformity of light emission and display effect of the display panel.

[0063] According to some embodiments of this application, optionally, the pixel circuit 10 may further include a second light-emitting control module 104. The control terminal of the second light-emitting control module 104 is electrically connected to the second light-emitting control signal line Emit2, the first terminal of the second light-emitting control module 104 is electrically connected to the third node N3, and the second terminal of the second light-emitting control module 104 is electrically connected to the first electrode of the light-emitting element. During the light-emitting phase, the second light-emitting control signal line Emit2 provides an enable level, the second light-emitting control module 104 is turned on, and the node potential of the third node N3 is transmitted to the first electrode of the light-emitting element.

[0064] In some specific embodiments, in order to minimize the number of devices and signal lines in the pixel circuit, thereby significantly reducing the production cost and wiring difficulty of the display panel and achieving a narrow bezel design for the display screen, the aforementioned pre-charging module 103 can be reused as the second light-emitting control module 104, and the pre-charging control signal line Pre can be reused as the second light-emitting control signal line Emit2.

[0065] The timing diagram of pixel circuit 10 at this time can be found in [reference needed]. Figure 3 .like Figure 3As shown, when the pre-charging module 103 is multiplexed as the second light-emitting control module 104, and the pre-charging control signal line Pre is multiplexed as the second light-emitting control signal line Emit2, the second light-emitting control signal line Emit2 provides a conduction level in the second time period T2, so that the second light-emitting control module 104 / pre-charging module 103 transmits the pre-charged voltage signal at the third node N3 to the fourth node N4, thereby realizing the charging of the anode of the light-emitting element. Furthermore, the second light-emitting control signal line Emit2 provides a conduction level during the light-emitting stage, so that the second light-emitting control signal line Emit2 transmits the driving current provided by the driving module 102 to the anode of the light-emitting element, thereby driving the light-emitting element to emit light.

[0066] According to some embodiments of this application, optionally, please refer to... Figure 4 , Figure 4 This is a schematic diagram of another pixel circuit structure provided in an embodiment of this application. In specific implementations, to facilitate signal differentiation and control, the pre-charging module 103 and the second light-emitting control module 104 can be separated to separately implement anode pre-charging control and light-emitting control of the light-emitting element. Specifically, the pre-charging module 103 and the second light-emitting control module 104 are connected in parallel. That is, the first end of the pre-charging module 103 and the first end of the second light-emitting control module 104 are electrically connected to the third node N3, and the second end of the pre-charging module 103 and the second end of the second light-emitting control module 104 are electrically connected to the fourth node N4. The control terminal of the pre-charging module 103 is electrically connected to the pre-charging control signal line Pre, and the control terminal of the second light-emitting control module 104 is electrically connected to the second light-emitting control signal line Emit2.

[0067] According to the above embodiments of this application, optionally, when the pre-charging module 103 and the second light-emitting control module 104 are connected in parallel, the timing diagram of the pixel circuit 10 can be found in [reference needed]. Figure 5 .like Figure 5 As shown, during the first time period T1, the first light-emitting control signal line Emit1 provides a conduction level, and the first light-emitting control module 101 is turned on under the control of the first light-emitting control signal line Emit1 to charge the third node N3. During this first time period T1, the pre-charging control signal line Pre and the second light-emitting control signal line Emit2 provide a cutoff level, and both the pre-charging module 103 and the second light-emitting control module 104 remain off to ensure that the light-emitting element does not emit light before reaching the light-emitting stage.

[0068] During the second time period T2, the pre-charge control signal line Pre provides a conduction level, and the pre-charge module 103 is turned on under the control of the pre-charge control signal line Pre. The pre-charged voltage signal at the third node N3 is transmitted to the fourth node N4 through the turned-on pre-charge module 103. During this second time period T2, the first light-emitting control signal line Emit1 provides a cutoff level, and the first light-emitting control module 101 remains off to ensure that the light-emitting element does not emit light before reaching the light-emitting stage. The second light-emitting control signal line Emit2 provides a cutoff level to prevent the pre-charge module 103 and the second light-emitting control module 104 from simultaneously turning on and forming a short circuit, which would affect the normal operation of the pixel circuit 10.

[0069] During the light-emitting stage, both the first light-emitting control signal line Emit1 and the second light-emitting control signal line Emit2 are provided with a conduction level. The first light-emitting control module 101 and the second light-emitting control module 104 are turned on, and the driving module 102 is turned on. The driving current provided by the driving module 102 is transmitted to the anode of the light-emitting element through the turned-on second light-emitting control module 104, thereby driving the light-emitting element to emit light. During this stage, the pre-charge control signal line Pre is provided with a cutoff level to avoid the pre-charge module 103 and the second light-emitting control module 104 from being turned on simultaneously, forming a short circuit and affecting the normal operation of the pixel circuit 10.

[0070] According to some embodiments of this application, optionally, in order to maintain the node potential signal of the third node N3 after pre-charging (first time period T1) to ensure the charging effect of the fourth node N4 in the subsequent second time period, please refer to [link to relevant documentation]. Figure 6 , Figure 6 This is a schematic diagram of another pixel circuit provided in the embodiments of this application.

[0071] like Figure 6 As shown, the pixel circuit 10 may further include a coupling module 105. Specifically, the first end of the coupling module 105 is electrically connected to the target voltage level Vm, and the second end of the coupling module 105 is electrically connected to the third node N3. The target voltage level Vm is kept at a constant potential, and the coupling module 105 can be used to maintain the node potential of the third node N3. In order to minimize the number of voltage signal lines, the aforementioned first power supply voltage terminal PVDD can be reused as the target voltage level Vm, or, as in the subsequent embodiments, the first reference voltage signal terminal used to provide the initialization reset signal can also be reused as the target voltage level Vm. This application does not impose specific limitations on this.

[0072] According to some embodiments of this application, more specifically, the coupling module 105 described above may include a coupling capacitor. The first terminal of the coupling capacitor is electrically connected to the target voltage level terminal Vm, and the second terminal of the coupling capacitor is electrically connected to the third node N3.

[0073] In this embodiment, the coupling capacitor set between the third node N3 and the target voltage terminal Vm can maintain the node potential signal of the third node N3 after pre-charging (first time period), which is beneficial to ensure the charging effect of the fourth node N4 in the subsequent second time period.

[0074] It should be added that, while ensuring the pre-charging effect, it is also necessary to consider that if the capacitance value of the coupling capacitor is too large, it may hinder the normal transmission of driving current in the subsequent light-emitting stage, thereby affecting the display effect. Based on this consideration, and combined with the analysis of actual display driving scenarios, the capacitance value of the coupling capacitor can be less than or equal to 2 × 10⁻⁶. -15 Farah.

[0075] It is worth noting that due to the coupling effects between various module structures and different signal lines and wires in the display panel, the third node N3 in the pixel circuit 10 itself will have a corresponding coupling capacitor. Therefore, the coupling capacitor in this embodiment can refer to either a capacitor added between the third node N3 and the target voltage level Vm, or a coupling capacitor that already exists at the third node N3. In the case where the coupling capacitor is the one already present at the third node N3, the capacitance value of the final coupling capacitor at the third node N3 can be controlled by adjusting the wiring arrangement, the structure between different layers, or the materials used.

[0076] Based on some embodiments of this application, and considering specific device configurations, please refer to [link / reference]. Figure 7 , Figure 7 This is a schematic diagram of another pixel circuit provided in the embodiments of this application. As described above, the first light-emitting control module 101 may include a first transistor, the driving module 102 may include a second transistor M2, and the pre-charging module 103 may include a third transistor M3.

[0077] The control terminal of the first transistor M1 is electrically connected to the first light-emitting control signal line Emit1. The first terminal of the first transistor M1 is electrically connected to the first power supply voltage signal terminal PVDD. The second terminal of the first transistor M1 is electrically connected to the third node N3. The first terminal of the second transistor M2 is electrically connected to the second node N2. The second terminal of the second transistor M2 is electrically connected to the second node N2. The control terminal of the third transistor M3 is electrically connected to the pre-charge control signal line Pre. The first terminal of the third transistor M3 is electrically connected to the third node N3. The second terminal of the third transistor M3 is electrically connected to the first electrode of the light-emitting element.

[0078] The aforementioned second transistor M2 (driving transistor) can be an oxide semiconductor transistor, specifically an IGZO (Indium Gallium Zinc Oxide) transistor, or a silicon transistor, specifically an LTPS (Low Temperature Poly-Silicon) transistor, or others.

[0079] According to some embodiments of this application, optionally, the pixel circuit 10 may further include a second light-emitting control module 104. The second light-emitting control module 104 may include a fourth transistor M4. The control terminal of the fourth transistor M4 is electrically connected to the second light-emitting control signal line Emit2, the first terminal of the fourth transistor M4 is electrically connected to the third node N3, and the second terminal of the fourth transistor M4 is electrically connected to the first electrode of the light-emitting element.

[0080] In some possible implementations, the pre-charge module 103 can be reused as the second light-emitting control module 104, and the pre-charge control signal line Pre can be reused as the second light-emitting control signal line Emit2. Figure 7 The third transistor M3 shown is the same transistor as the fourth transistor mentioned above, and the pre-charge control signal line Pre and the second light emission control signal line Emit2 are the same control signal line.

[0081] In some other possible implementations, where the pre-charging module 103 and the second light-emitting control module 104 are connected in parallel, please refer to [link to relevant documentation]. Figure 8 , Figure 8 This is a schematic diagram of another pixel circuit provided in the embodiments of this application. Figure 8 In the pixel circuit 10 shown, the third transistor M3 and the fourth transistor M4 are different transistors. The first terminal of the third transistor M3 and the first terminal of the fourth transistor M4 are both electrically connected to the third node N3, and the second terminal of the third transistor M3 and the second terminal of the fourth transistor M4 are both electrically connected to the fourth node N4. The control terminal of the third transistor M3 is electrically connected to the pre-charge control signal line Pre, and the control terminal of the fourth transistor M4 is electrically connected to the second light emission control signal line Emit2. The pre-charge control signal line Pre and the second light emission control signal line Emit2 are different control signal lines.

[0082] In some more specific implementations, depending on the actual pixel-driven scenario, please refer to [link / reference]. Figure 9 and Figure 10 , Figure 9 and Figure 10 Both are schematic diagrams of another pixel circuit provided in the embodiments of this application, the difference between the two being: Figure 9In the pixel circuit 10 shown, the second light emission control module 104 is reused as the pre-charge module 103; Figure 10 In the pixel circuit 10 shown, the second light emission control module 104 is connected in parallel with the pre-charge module 103.

[0083] Combination Figure 9 and Figure 10 The pixel circuit 10 may also include a data writing module 106, a threshold compensation module 107, a storage module 108, a first initialization module 109, and a second initialization module 110, which are used to perform different functions in the display light emission process and jointly realize the light emission of the light-emitting element.

[0084] In terms of specific connections, the control terminal of the data writing module 106 is electrically connected to the second scan signal line Scan2, the first terminal of the data writing module 106 is electrically connected to the data voltage signal line Data, and the second terminal of the data writing module 106 is electrically connected to the first terminal of the drive module 102. The control terminal of the threshold compensation module 107 is electrically connected to the second scan signal line Scan2, the first terminal of the threshold compensation module 107 is electrically connected to the control terminal of the drive module 102, and the second terminal of the threshold compensation module 107 is electrically connected to the second terminal of the drive module 102. During the data writing phase, the second scan signal line Scan2 provides an enable level, and the data voltage provided by the data voltage signal line Data is transmitted to the control terminal of the drive module 102. The first terminal of the storage module 108 is electrically connected to the first power supply voltage signal terminal PVDD, and the second terminal of the storage module 108 is electrically connected to the control terminal of the drive module 102. The control terminal of the first initialization module 109 is electrically connected to the first scan signal line Scan1. The first terminal of the first initialization module 109 is electrically connected to the control terminal of the drive module 102. The second terminal of the first initialization module 109 is electrically connected to the first reference level voltage terminal Vref. The control terminal of the second initialization module 110 is electrically connected to the second scan signal line Scan2. The first terminal of the second initialization module 110 is electrically connected to the first reference level voltage terminal Vref. The second terminal of the second initialization module 110 is electrically connected to the first electrode of the light-emitting element.

[0085] To facilitate understanding of the pixel circuit provided in this application, the following description is provided in conjunction with some specific application embodiments.

[0086] Please see below. Figure 11 , Figure 11In this configuration, the third transistor M3 and the fourth transistor M4 are the same transistor, and the pre-charge control signal line Pre and the second light emission control signal line Emit2 are the same control signal line. According to some embodiments of this application, more specifically, the data writing module 106 may include a fifth transistor M5, the threshold compensation module 107 may include a sixth transistor M6, the first initialization module 109 may include a seventh transistor M7, and the second initialization module 110 may include an eighth transistor. The control terminal of the fifth transistor M5 is electrically connected to the second scan signal line Scan2, the first terminal of the fifth transistor M5 is electrically connected to the data voltage signal line Data, and the second terminal of the fifth transistor M5 is electrically connected to the first terminal of the second transistor M2. The control terminal of the sixth transistor M6 is electrically connected to the second scan signal line Scan2, the first terminal of the sixth transistor M6 is electrically connected to the control terminal of the second transistor M2, and the second terminal of the sixth transistor M6 is electrically connected to the second terminal of the second transistor M2. The first terminal of the storage capacitor Cst is electrically connected to the first power supply voltage signal terminal PVDD, and the second terminal of the storage capacitor Cst is electrically connected to the control terminal of the second transistor M2. The control terminal of the seventh transistor M7 is electrically connected to the first scan signal line Scan1. The first terminal of the seventh transistor M7 is electrically connected to the control terminal of the second transistor M2, and the second terminal of the seventh transistor M7 is electrically connected to the first reference level voltage terminal Vref. The control terminal of the eighth transistor M8 is electrically connected to the second scan signal line Scan2. The first terminal of the eighth transistor M8 is electrically connected to the first reference level voltage terminal Vref, and the second terminal of the eighth transistor M8 is electrically connected to the first electrode of the light-emitting element.

[0087] It should be understood that, in order to reduce leakage current and thus further ensure the display effect of the display panel, the sixth and seventh transistors mentioned above can specifically be dual-gate thin-film transistors. Alternatively, in some other feasible embodiments, the sixth and seventh transistors can also be IGZO (Indium Gallium Zinc Oxide) transistors, and this application does not impose specific limitations on this.

[0088] and Figure 11 For the pixel circuit structure shown, please refer to [link / reference]. Figure 12 , Figure 12 This is a timing diagram of another pixel circuit provided in the embodiments of this application. The following is in conjunction with... Figure 12 The timing pairs shown Figure 11 The pixel circuit shown is described below. In this embodiment, the enable / conduct level is low, and the disable / cutoff level is high.

[0089] Figure 11In the specific operation of the pixel circuit 10 shown, during the initialization phase, the first scan signal line Scan1 provides an enable level, while the remaining control signal lines provide a disable level. In response to the enable level provided by the first scan signal line Scan1, the seventh transistor M7 is turned on, transmitting the reference level voltage signal provided by the first reference level voltage terminal Vref to the second terminal of the storage capacitor Cst to initialize the second terminal of the storage capacitor Cst.

[0090] During the data writing phase, the second scan signal line Scan2 provides an enable level. In response to the enable level provided by Scan2, the fifth transistor M5 turns on, writing the data voltage provided by the data voltage signal line Data to the control terminal of the second transistor M2 to achieve data writing. The sixth transistor M6 turns on, connecting the control terminal and the second terminal of the second transistor M2 to achieve threshold voltage compensation for the driving transistor, i.e., the second transistor M2. The eighth transistor M8 turns on, transmitting the reference level voltage signal provided by the first reference level voltage terminal Vref to the anode of the light-emitting element, thereby resetting the anode of the light-emitting element.

[0091] During the first time period T1, the first light-emitting control signal line Emit1 provides a conduction level, and the first transistor M1 conducts under the control of the first light-emitting control signal line Emit1, transmitting the first power supply voltage provided by the first power supply voltage signal terminal PVDD to the first terminal of the second transistor M2, i.e., the second node N2. At this time, since the data voltage (lower than the first power supply voltage) has been pre-written to the control terminal of the driving module 102, the second transistor M2 conducts, transmitting the node potential at the second node N2 to the third node N3 to charge the third node N3. During this first time period T1, the second light-emitting control signal line Emit2 provides a cutoff level, and the third transistor M3 (fourth transistor M4) remains off to ensure that the light-emitting element does not emit light before reaching the light-emitting stage.

[0092] During the second time period T2, the second light-emitting control signal line Emit2 provides a conduction level, and the third transistor M3 (and fourth transistor M4) is turned on, transmitting the pre-charged voltage signal at the third node N3 to the anode of the light-emitting element, i.e., the fourth node N4, thereby achieving a pre-charging operation of the anode of the light-emitting element before the light-emitting stage. During this second time period T2, the first light-emitting control signal line Emit1 provides a cutoff level, and the first transistor M1 is turned off under the control of the first light-emitting control signal line Emit1 to ensure that the light-emitting element does not emit light before reaching the light-emitting stage.

[0093] During the light-emitting stage, both the first light-emitting control signal line Emit1 and the second light-emitting control signal line Emit2 are provided with a conduction level, the first transistor M1 and the third transistor M3 (the fourth transistor M4) are turned on, and the second transistor M2 provides a drive current according to the data voltage written in the previous data writing stage to drive the light-emitting element to emit light.

[0094] Please see below. Figure 13 , Figure 13 This is a schematic diagram of another pixel circuit provided in an embodiment of this application. Figure 13 and Figure 11 The structures are basically the same, the difference lies in: Figure 11 In the pixel circuit 10 shown, the third transistor M3 and the fourth transistor M4 are the same transistor, and the pre-charge control signal line Pre and the second light emission control signal line Emit2 are the same control signal line. Figure 13 In the pixel circuit 10 shown, the third transistor M3 and the fourth transistor M4 are connected in parallel, and the pre-charge control signal line Pre and the second light emission control signal line Emit2 are different control signal lines.

[0095] and Figure 13 For the pixel circuit structure shown, please refer to [link / reference]. Figure 14 , Figure 14 This is a timing diagram of another pixel circuit provided in the embodiments of this application. The following is in conjunction with... Figure 14 The timing pairs shown Figure 13 The pixel circuit shown is described below. In this embodiment, the enable / conduct level is low, and the disable / cutoff level is high.

[0096] Figure 13 The pixel circuit 10 shown operates in a manner that is basically the same as described above in its initialization and data writing phases, and will not be repeated in this embodiment. The following description will focus on its operation during the first time period T1, the second time period T2, and the light emission phase.

[0097] During the first time period T1, the first light-emitting control signal line Emit1 provides a conduction level, and the first transistor M1 is turned on under the control of the first light-emitting control signal line Emit1 to charge the third node N3. During this first time period T1, the pre-charge control signal line Pre and the second light-emitting control signal line Emit2 both provide a cutoff level, and the third transistor M3 and the fourth transistor M4 remain off to ensure that the light-emitting element does not emit light before reaching the light-emitting stage.

[0098] During the second time period T2, the pre-charge control signal line Pre provides a conduction level, and the third transistor M3 is turned on under the control of the pre-charge control signal line Pre. The pre-charged voltage signal at the third node N3 is transmitted to the fourth node N4 through the turned-on third transistor M3. During this second time period T2, the first light emission control signal line Emit1 provides a cutoff level, and the first transistor M1 remains off to ensure that the light-emitting element does not emit light before reaching the light emission stage. The second light emission control signal line Emit2 provides a cutoff level to prevent the third transistor M3 and the fourth transistor M4 from simultaneously turning on and forming a short circuit, which would affect the normal operation of the pixel circuit 10.

[0099] During the light-emitting stage, both the first light-emitting control signal line Emit1 and the second light-emitting control signal line Emit2 are provided with a conduction level, the first transistor M1 and the fourth transistor M4 are turned on, the driving module 102 is turned on, and the driving current provided by the second transistor M2 is transmitted to the anode of the light-emitting element through the turned-on second light-emitting control module 104, thereby driving the light-emitting element to emit light. During this stage, the pre-charge control signal line Pre is provided with a cutoff level, and the third transistor M3 remains off to avoid the third transistor M3 and the fourth transistor M4 from being turned on simultaneously and forming a short circuit, which would affect the normal operation of the pixel circuit 10.

[0100] It should be noted that the driving timing given in the embodiments of this application is only one possible example. In other embodiments, the operating timing of the pixel circuit can be flexibly adjusted according to the actual situation and requirements. This application does not impose specific limitations on it here.

[0101] According to some embodiments of this application, optionally, the following can be continued: Figure 13 and Figure 14 To fully guarantee the display effect of the display panel and enhance its competitiveness, the first light-emitting control signal line Emit1 provides an enable level at the first moment and a disable level at the second moment; the second light-emitting control signal line Emit2 provides an enable level at the third moment and a disable level at the fourth moment; the period from the third moment to the fourth moment is the light-emitting phase; wherein, the first moment is later than the end of the second time period T2; the first moment is earlier than or synchronous with the third moment, and / or, the second moment is later than or synchronous with the fourth moment.

[0102] exist Figure 14 In the first light emission control signal line Emit1, there are two enable / low level phases. The first enable level phase is the first time period T1, the first moment is the start moment of the second enable level phase, and the second moment is the end moment of the second enable level phase.

[0103] The second light emission control signal line, Emit2, includes an enable level phase, which begins at the third time and ends at the fourth time. This enable level phase coincides with the light emission phase, meaning that the period from the third time to the fourth time is the light emission phase.

[0104] In this embodiment, the first moment can precede the third moment. In this way, before the formal light-emitting stage, the first transistor M1 turns on before the fourth transistor M4, transmitting the first power supply voltage (PVDD) from the first power supply voltage signal terminal to the third node N3. This allows the potential of the third node N3 to stabilize earlier, avoiding current spikes at the third node N3 when the first transistor M1 and the fourth transistor are simultaneously turned on. This helps ensure the stability of the driving current in the subsequent light-emitting stage, improving the display effect and competitiveness of the display panel. Alternatively, in some embodiments, the first moment can also be synchronized with the third moment; this application does not impose specific limitations on this.

[0105] The aforementioned second time point is later than or synchronized with the fourth time point. This effectively avoids the current step caused by leakage current when the first transistor M1 and the fourth transistor M4 are simultaneously turned off, reducing the adverse effects on the normal turn-off process of the light-emitting elements and improving the display effect and competitiveness of the display panel. Of course, in some embodiments, the aforementioned second time point may also be synchronized with the fourth time point; this application does not impose specific limitations on this.

[0106] Please see below. Figure 15 , Figure 15 This is a timing diagram of another pixel circuit provided in an embodiment of this application. Combined with... Figure 15 According to some embodiments of this application, optionally, and considering the actual display scenario, in order to more reasonably achieve the pre-charging process of the anode of the light-emitting element, a display time period of one frame may include N pixel driving cycles, where N is a positive integer. The pixel driving cycle may include a non-light-emitting phase and a light-emitting phase.

[0107] In this field, the aforementioned display time frame can also be understood as a data refresh cycle. A data refresh cycle typically includes a data write subframe and several hold subframes. The aforementioned pixel driving cycle can be called a PULSE. The number of PULSEs included in a display time frame is typically between 12 and 16, which is consistent with the sum of the number of data write subframes and several hold subframes. This pixel driving cycle can be calculated using the minimum cycle of a light emission phase. The first pixel driving cycle within a display time frame can include a first time period T1 and a second time period T2.

[0108] For example, such as Figure 15As shown, if N=2, there are two pixel driving cycles within a single frame display time period: the first pixel driving cycle is PULSE1, and the second pixel driving cycle is PULSE2. During actual display operation, if pre-charging occurs in multiple PULSE cycles, a potential overflow phenomenon at the fourth node N4 may occur in subsequent PULSE cycles, which is also detrimental to the normal operation of the light-emitting element.

[0109] Therefore, in order to ensure that the pre-charging effect can be fully utilized while avoiding adverse effects on subsequent pixel operation, this embodiment can set the first time period T1 and the second time period T2 only in the first pixel driving cycle PULSE1 within a frame display time period to achieve pre-charging of the anode of the light-emitting element. In the subsequent PULSE2, the first time period T1 and the second time period T2 may not be set.

[0110] It is understandable that, in some other possible implementations, alternatively, such as Figure 16 In the timing diagram of another pixel circuit shown, if a display time frame can include N pixel driving cycles, where N is a positive integer, the N pixel driving cycles in a display time frame can also each include a first time frame T1 and a second time frame T2. This application does not impose strict limitations on this, and the specific settings can be made according to actual display requirements.

[0111] Based on the timing diagrams of any of the aforementioned pixel circuits, and according to some embodiments of this application, optionally, and considering the specific circumstances of the actual pixel circuit, when pre-charging is performed on the third node N3 and the fourth node N4 respectively, the coupling capacitance at the third node N3 is usually small, and the required pre-charging time is short. When pre-charging the fourth node N4, i.e., the anode of the light-emitting element, it is actually necessary to pre-charge both the coupling capacitance of the fourth node N4 and the capacitance in the light-emitting element simultaneously. In comparison, the sum of the capacitance values ​​of the coupling capacitance and the capacitance of the light-emitting element at the fourth node N4 is much larger than the coupling capacitance at the third node N3, and the required pre-charging time for the fourth node N4 is relatively longer than that for the third node N3. Based on this, the duration of the first time period T1 can be shorter than the duration of the second time period T2, so as to more reasonably realize the pre-charging of the third node N3 and the fourth node N4 according to actual needs.

[0112] Based on the timing diagram of any of the aforementioned pixel circuits, and according to some embodiments of this application, optionally, considering the leakage current effect under the actual transistor off-state, the interval between the first time period T1 and the second time period T2 is longer than a preset threshold. This preset threshold can be set based on simulation results or actual testing, and this application does not impose specific limitations on it.

[0113] Specifically, in conjunction with the aforementioned Figure 13As illustrated by the pixel circuit example, during the first time period T1, the first transistor M1 is turned on, and the third transistor M3 is turned off. During the second time period T2, the third transistor M3 is turned on, and the first transistor M1 is turned off.

[0114] However, in some cases, if the interval between the end of the first time period T1 and the start of the second time period T2 is too short, the first transistor M1 will turn off immediately after the first time period T1 ends, causing leakage current, and the third transistor M3 will immediately turn on. This could lead to the light-emitting element emitting light erroneously, which is detrimental to maintaining the normal light-emitting operation of the light-emitting element in the pixel circuit. Therefore, the interval between the first time period T1 and the second time period T2 can be set to be longer than a preset threshold to avoid the influence of leakage current in the actual transistor off state. More specifically, according to some embodiments of this application, the preset threshold can be greater than or equal to the duration of the first time period T1 to more reasonably achieve pre-charging of the anode of the light-emitting element.

[0115] Please see below. Figure 17 For example, 17 is a timing diagram of another pixel circuit provided in an embodiment of this application. Figure 17 As shown, according to some embodiments of this application, optionally, considering that there may be charge leakage at the third node N3 after charging at the third node N3 and before charging from the third node N3 to the fourth node N4, the potential of the third node N3 may decrease, thereby affecting the pre-charging effect of the fourth node N4 in the second time period T2.

[0116] Based on this, in order to fully guarantee the charging effect of the third node N3 to the fourth node N4 within the second time period T2, the time period after the data writing stage and before the second time period can include multiple first time periods T1.

[0117] Specifically, this embodiment maintains the node potential of the third node N3 by repeatedly charging the third node N3 before the arrival of the second time period T2, which effectively ensures the pre-charging effect of the fourth node N4 in the second time period T2, which is beneficial to improving the display effect of the display panel and enhancing the competitiveness of the display panel.

[0118] Please see Figure 18 Example 18 is a timing diagram of another pixel circuit provided in an embodiment of this application. Based on some embodiments of this application and analysis of the foregoing embodiments, it can be seen that the sum of the capacitance values ​​of the coupling capacitor and the light-emitting element capacitor at the fourth node N4 is much larger than the coupling capacitor at the third node N3, and the pre-charging time required for the fourth node N4 is relatively longer than that for the third node N3. In this case, there may be a situation where the amount of charge injected into the third node N3 during the first time period T1 is insufficient to meet the pre-charging requirements of the fourth node N4.

[0119] Based on this, optionally, combining Figure 18 The time sequence shown can include multiple target time periods within the period after the data writing phase and before the emission phase. Each target time period can include a first time period T1 and a second time period T2.

[0120] The advantages of this are: by setting multiple target time periods including the first time period T1 and the second time period T2, the steps of "pre-charging the third node N3 and charging the fourth node N4 from the third node N3" can be executed multiple times, so as to fully realize the pre-charging of the fourth node N4.

[0121] It should be noted that the number of the aforementioned target time periods can be flexibly set and adjusted in combination with pre-charging requirements and actual data refresh rate, frame refresh rate, or light emission display standards, etc., and this application does not impose specific restrictions on this.

[0122] According to some embodiments of this application, optionally, in conjunction with actual timing analysis, in order to more reasonably achieve pre-charging of the anode of the light-emitting element, the duration of the first time period T1 is between 2H and 200H; and / or, the interval between the first time period T1 and the second time period T2 is between 10H and 100H; and / or, the duration of the second time period T2 is between 2H and 10H.

[0123] Where H is the scan time of a row of pixel circuits.

[0124] It should be noted here that, in the field of display panel technology, a display panel includes multiple rows of pixel circuits. Within a single frame display time period / one data refresh cycle, the scanning signal used to control data writing typically scans each row of pixel circuits sequentially. Therefore, the scanning time for one row of pixel circuits can specifically be equal to one data refresh cycle divided by the total number of rows of pixel circuits.

[0125] For example, taking a data refresh rate of 120Hz as an example, the display time of one frame / one data refresh cycle is 1 / 120Hz. If the display panel includes 3000 rows of pixel circuits, then H = (1 / 120) / 3000 seconds.

[0126] Based on the pixel circuits provided in the above embodiments, this application also provides a driving method. The driving method of this application can be applied to the pixel circuits provided in any of the foregoing embodiments.

[0127] Figure 19 This is a flowchart illustrating a driving method provided in an embodiment of this application. Figure 19 As shown, a driving method according to an embodiment of this application may include the following steps:

[0128] S1901, in the first time period after the data writing stage and before the light emission stage, control the first light emission control module and the drive module to be turned on, and control the pre-charge module to be turned off, so that the first power supply voltage signal provided by the first power supply voltage signal terminal is transmitted to the third node through the first light emission control module and the drive module.

[0129] S1902, in the second time period after the first time period and before the light emission stage, the first light emission control module is turned off and the pre-charging module is turned on, so that the first power supply voltage signal of the third node is transmitted to the first electrode of the light emission element through the pre-charging module.

[0130] It should be understood that, for the sake of brevity, the specific implementation process of S1901 and S1902 can be referred to the corresponding descriptions above, and will not be repeated here.

[0131] One driving method according to an embodiment of this application involves controlling a first light-emitting control module and a driving module to be turned on during a first time period after the data writing phase, transmitting a first power supply voltage provided by a first power supply voltage signal terminal to a third node to charge the third node. During a second time period after the first time period and before the light-emitting phase, the first light-emitting control module is turned off and a pre-charging module is turned on, thereby transmitting the pre-charged voltage signal at the third node to the anode of the light-emitting element, thus pre-charging the anode of the light-emitting element in advance.

[0132] Compared to existing technologies, a driving method in this application embodiment achieves pre-charging of the anode of the light-emitting element by setting the aforementioned first time period and second time period between the data writing stage and the light-emitting stage. This ensures that different light-emitting elements can quickly respond and emit light when the actual light-emitting stage is activated, indirectly avoiding the problem of inconsistent charging times for different light-emitting elements affecting the display effect during the light-emitting stage. This solution can help improve color shift phenomena and effectively improve the uniformity of light emission and display effect of the display panel.

[0133] Based on the pixel circuit provided in any of the above embodiments, this application also provides a display panel, including the pixel circuit provided in any of the foregoing embodiments of this application. Please refer to... Figure 20 , Figure 20 This is a schematic diagram of a display panel provided in an embodiment of this application. Figure 20 As shown, the display panel 100 provided in this application embodiment may include the pixel circuit 10 described in any of the above embodiments. Figure 20 The display panel shown can be an organic light-emitting diode (OLED) display panel.

[0134] Those skilled in the art should understand that in other implementations of this application, the display panel may also be a micro light-emitting diode (Micro LED) display panel, a quantum dot display panel, etc.

[0135] The display panel provided in this application embodiment has the beneficial effects of the pixel circuit 10 provided in this application embodiment. For details, please refer to the specific description of the pixel circuit 10 in the above embodiments. This embodiment will not repeat the description here.

[0136] Based on the display panel provided in the above embodiments, this application also provides a display device, including the display panel provided in this application. Please refer to... Figure 21 , Figure 21 This is a schematic diagram of a display device provided in an embodiment of this application. Figure 21 The provided display device 1000 includes the display panel 100 provided in any of the above embodiments of this application. Figure 21 The embodiments use a mobile phone as an example to describe the display device 1000. It is understood that the display device provided in the embodiments of this application can be other display devices with display functions, such as wearable products, computers, televisions, and in-vehicle display devices. This application does not impose specific limitations on these. The display device provided in the embodiments of this application has the beneficial effects of the display panel 100 provided in the embodiments of this application. For details, please refer to the specific descriptions of the display panel 100 in the above embodiments. These descriptions will not be repeated here.

[0137] It should be understood that the specific circuit structures and cross-sectional structures of the display panels provided in the accompanying drawings of the embodiments of this application are merely examples and are not intended to limit this application. Furthermore, the above embodiments provided in this application can be combined with each other unless there is contradiction.

[0138] It should be clarified that the various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. According to the embodiments described above, these embodiments do not exhaustively describe all details, nor do they limit this application to only the specific embodiments described. Obviously, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to make good use of this application and modifications based on it. This application is limited only by the claims and their full scope and equivalents.

[0139] Those skilled in the art will understand that the above embodiments are exemplary and not restrictive. Different technical features appearing in different embodiments can be combined to achieve beneficial effects. Based on a study of the drawings, specification, and claims, those skilled in the art should be able to understand and implement other variations of the disclosed embodiments. In the claims, the term "comprising" does not exclude other structures; the quantity refers to "one" but does not exclude multiple; the terms "first" and "second" are used to identify names and not to indicate any particular order. Any reference numerals in the claims should not be construed as limiting the scope of protection. The appearance of certain technical features in different dependent claims does not mean that these technical features cannot be combined to achieve beneficial effects.

Claims

1. A pixel circuit, characterized in that, The pixel circuit includes: The first light-emitting control module, driving module, and pre-charging module; the working process of the pixel circuit includes a data writing stage and a light-emitting stage; The control terminal of the drive module is electrically connected to the first node, the first terminal of the drive module is electrically connected to the second node, and the second terminal of the drive module is electrically connected to the third node. The control terminal of the first light-emitting control module is electrically connected to the first light-emitting control signal line, the first terminal of the first light-emitting control module is electrically connected to the first power supply voltage signal terminal, and the second terminal of the first light-emitting control module is electrically connected to the second node. The control terminal of the pre-charging module is electrically connected to the pre-charging control signal line, the first terminal of the pre-charging module is electrically connected to the third node, and the second terminal of the pre-charging module is electrically connected to the first electrode of the light-emitting element. During a first time period after the data writing phase and before the light emission phase, the first light emission control module and the driving module are turned on, and the pre-charging module is turned off. In a second time period following the first time period and preceding the light-emitting stage, the first light-emitting control module is turned off, and the pre-charging module is turned on.

2. The pixel circuit according to claim 1, characterized in that, The pixel circuit also includes a second light-emitting control module; The control terminal of the second light-emitting control module is electrically connected to the second light-emitting control signal line, the first terminal of the second light-emitting control module is electrically connected to the third node, and the second terminal of the second light-emitting control module is electrically connected to the first electrode of the light-emitting element. During the light-emitting phase, the second light-emitting control signal line provides an enable level, the second light-emitting control module is turned on, and the node potential of the third node is transmitted to the first electrode of the light-emitting element.

3. The pixel circuit according to claim 2, characterized in that, The pre-charge module is reused as the second light-emitting control module, and the pre-charge control signal line is reused as the second light-emitting control signal line.

4. The pixel circuit according to claim 2, characterized in that, include: The pre-charging module is connected in parallel with the second light-emitting control module.

5. The pixel circuit according to claim 2, characterized in that, include: The first light emission control signal line starts to provide an enable level at a first moment, and the first light emission control signal line starts to provide a de-enable level at a second moment. The second light emission control signal line begins to provide an enable level at the third time point and begins to provide a de-enable level at the fourth time point; the period from the third time point to the fourth time point is the light emission period; Wherein, the first moment is later than the end moment of the second time period; The first moment precedes or is synchronized with the third moment, and / or the second moment is later than or synchronized with the fourth moment.

6. The pixel circuit according to claim 1, characterized in that, include: A single frame display time period includes N pixel drive cycles, where N is a positive integer; The pixel driving cycle includes a non-light-emitting phase and a light-emitting phase; The first pixel driving cycle within a frame display time period includes the first time period and the second time period.

7. The pixel circuit according to claim 1, characterized in that, The duration of the first time period is shorter than the duration of the second time period.

8. The pixel circuit according to claim 1, characterized in that, The duration of the interval between the first time period and the second time period is greater than a preset threshold.

9. The pixel circuit according to claim 8, characterized in that, The preset threshold is greater than or equal to the duration of the first time period.

10. The pixel circuit according to claim 1, characterized in that, include: The period between the data writing phase and the light emission phase includes multiple target time periods; The target time period includes a first time period and a second time period.

11. The pixel circuit according to claim 1, characterized in that, The duration of the first time period is between 2 hours and 200 hours; And / or, the interval between the first time period and the second time period is between 10 hours and 100 hours; And / or, the duration of the second time period is between 2 hours and 10 hours; Where H is the scan time of a row of pixel circuits.

12. The pixel circuit according to claim 1, characterized in that, The pixel circuit also includes a coupling module; The first end of the coupling module is electrically connected to the target voltage level terminal, and the second end of the coupling module is electrically connected to the third node; The target voltage level terminal is kept at a constant potential, and the coupling module is used to maintain the node potential of the third node.

13. The pixel circuit according to claim 12, characterized in that, The coupling module includes a coupling capacitor; The first terminal of the coupling capacitor is electrically connected to the target voltage level terminal, and the second terminal of the coupling capacitor is electrically connected to the third node; The capacitance value of the coupling capacitor is less than or equal to 2 × 10⁻⁶. -15 Farah.

14. The pixel circuit according to claim 1, characterized in that, The first light-emitting control module includes a first transistor, the driving module includes a second transistor, and the pre-charging module includes a third transistor; The control terminal of the first transistor is electrically connected to the first light-emitting control signal line, the first terminal of the first transistor is electrically connected to the first power supply voltage signal terminal, and the second terminal of the first transistor is electrically connected to the third node. The first terminal of the second transistor is electrically connected to the second node, and the second terminal of the second transistor is electrically connected to the second node. The control terminal of the third transistor is electrically connected to the pre-charge control signal line, the first terminal of the third transistor is electrically connected to the third node, and the second terminal of the third transistor is electrically connected to the first electrode of the light-emitting element.

15. The pixel circuit according to claim 14, characterized in that, The pixel circuit further includes a second light-emitting control module; the second light-emitting control module includes a fourth transistor; The control terminal of the fourth transistor is electrically connected to the second light-emitting control signal line, the first terminal of the fourth transistor is electrically connected to the third node, and the second terminal of the fourth transistor is electrically connected to the first electrode of the light-emitting element.

16. The pixel circuit according to claim 14 or 15, characterized in that, The pixel circuit also includes a data writing module, a threshold compensation module, a storage module, a first initialization module, and a second initialization module; The control terminal of the data writing module is electrically connected to the second scan signal line, the first terminal of the data writing module is electrically connected to the data voltage signal line, and the second terminal of the data writing module is electrically connected to the first terminal of the drive module. The control terminal of the threshold compensation module is electrically connected to the second scan signal line, the first terminal of the threshold compensation module is electrically connected to the control terminal of the drive module, and the second terminal of the threshold compensation module is electrically connected to the second terminal of the drive module. During the data writing phase, the second scan signal line provides an enable level, and the data voltage provided by the data voltage signal line is transmitted to the control terminal of the drive module. The first end of the storage module is electrically connected to the first power supply voltage signal terminal, and the second end of the storage module is electrically connected to the control terminal of the drive module. The control terminal of the first initialization module is electrically connected to the first scan signal line, the first terminal of the first initialization module is electrically connected to the control terminal of the drive module, and the second terminal of the first initialization module is electrically connected to the first reference level voltage terminal. The control terminal of the second initialization module is electrically connected to the second scanning signal line, the first terminal of the second initialization module is electrically connected to the first reference level voltage terminal, and the second terminal of the second initialization module is electrically connected to the first electrode of the light-emitting element.

17. A driving method, characterized in that, Applied to the pixel circuit as described in any one of claims 1-16, the driving method includes: In the first time period after the data writing stage and before the light emission stage, the first light emission control module and the driving module are turned on, and the pre-charging module is turned off, so that the first power supply voltage signal provided by the first power supply voltage signal terminal is transmitted to the third node through the first light emission control module and the driving module. In a second time period following the first time period and preceding the light-emitting stage, the first light-emitting control module is turned off, and the pre-charging module is turned on, so that the first power supply voltage signal of the third node is transmitted to the first electrode of the light-emitting element through the pre-charging module.

18. A display panel, characterized in that, The display panel includes the pixel circuitry as described in any one of claims 1-16.

19. A display device, characterized in that, The display device includes the display panel as described in claim 18.

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