A vertical channel transistor structure and method of manufacture

Abstract

The embodiment of the application discloses a vertical channel transistor structure, which introduces a contact layer between a source and a dielectric layer and between a drain and the dielectric layer. The two contact layers have low resistance, high doping concentration and good metal contact, and can form an ohmic contact between the source, the drain and a semiconductor channel layer. When the vertical channel transistor of the structure works, electrons can directly pass through a potential barrier from the source into the semiconductor channel layer and from the semiconductor channel layer into the drain by using wave motion, that is, tunneling injection of current is realized, the contact resistance of the vertical channel transistor is greatly reduced, and the working current of the vertical channel transistor is increased.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a vertical channel transistor and a method for manufacturing it. Background Technology

[0002] To increase memory array density and reduce costs, vertical-channel transistors (VCTs) have become a mainstream choice. VCTs inherently possess short-channel characteristics, with the semiconductor channel arranged in a sandwich structure between the bottom and top electrodes. Therefore, the development of VCTs holds promise as a novel direction for device miniaturization, potentially reducing channel lengths to 10nm or even below 5nm.

[0003] However, achieving effective doping of the vertical channel in the fabrication process presents significant challenges, including effective control over the uniformity of doping depth and the uniformity of doping concentration at the source and drain. This results in typically high contact resistance in fabricated vertical channel transistors, significantly impacting their electrical performance. Increasing the overall doping concentration to reduce contact resistance leads to a negative threshold voltage shift, which means the transistor turns on prematurely, increasing leakage current and power loss at the given system voltage. Existing technologies employ multi-layer partitioned doping to mitigate these issues, but this increases process costs and introduces reliability risks. Summary of the Invention

[0004] The embodiments of this application provide a vertical channel transistor structure and manufacturing method, which can effectively reduce the contact resistance of the vertical channel transistor.

[0005] This application provides a vertical channel transistor structure, comprising: a stacked structure including a first metal layer, a first contact layer, an insulating dielectric layer, a second contact layer, and a second metal layer; the first contact layer is located between the first metal layer and the insulating dielectric layer, and the second contact layer is located between the second metal layer and the insulating dielectric layer; a groove is provided in the stacked structure, the groove penetrating the second metal layer, the second contact layer, the insulating dielectric layer, and the second contact layer, and the first groove is at least partially embedded in the first metal layer; a semiconductor channel layer, a gate oxide layer, and a gate are disposed within the groove; wherein the materials of the first contact layer and the second contact layer are conductive materials or semiconductor materials with conductivity higher than that of the semiconductor channel layer; the semiconductor channel layer contacts the first metal layer and the second metal layer respectively within the groove, and the gate oxide layer is disposed between the semiconductor channel layer and the gate.

[0006] It should be understood that one of the first metal layer and the second metal layer is the source and the other is the drain.

[0007] In existing technologies, electrons need to pass through two contact surfaces to travel from the source to the semiconductor channel layer and then to the drain: the contact surface between the source and the semiconductor channel layer, and the contact surface between the semiconductor channel layer and the drain. In vertical device structures, the contacts between the source and the semiconductor channel layer, and between the semiconductor channel layer and the drain, are typically Schottky contacts. Current injection is thermally excited, resulting in high contact resistance, high electron potential energy required to cross the barrier, and low current. However, in the vertical channel transistor structure provided in this application, contact layers are provided between the drain and the insulating dielectric layer, and between the source and the insulating dielectric layer. Electrons need to pass through four contact surfaces to travel from the source to the drain: the contact surface between the source and the first contact layer, the contact surface between the first contact layer and the semiconductor channel layer, the contact surface between the semiconductor channel layer and the second contact layer, and the contact surface between the second contact layer and the drain. Since the materials of these two contact layers are conductive materials or semiconductor materials with higher conductivity than the semiconductor channel layer, and the conductive materials used in the contact layers are different from the metals of the source and drain metal layers, they can form a conductive barrier with the semiconductor channel layer. The contact is excellent; the contact resistance between the contact layer and the semiconductor channel layer is much smaller than the contact resistance between the source and drain and the semiconductor channel layer. Furthermore, due to the good contact between the contact layer and the metal, the contact resistance between the source and drain and the contact layer is also very small. Therefore, the sum of the resistances of the contact surfaces between the source and the contact layer and between the contact layer and the semiconductor channel layer is less than the resistance of the contact surface between the source and the semiconductor channel layer in the prior art. Correspondingly, the sum of the resistances of the contact surfaces between the drain and the contact layer and between the contact layer and the semiconductor channel layer is less than the resistance of the contact surface between the drain and the semiconductor channel layer in the prior art. Ideally, the contact resistance between the source and drain and the contact layer can be ignored. Therefore, after introducing two contact layers, the total resistance of the four contact surfaces through which electrons pass from the source to the drain is less than the total resistance of the two contact surfaces through which electrons pass from the source to the drain in the prior art. This allows for the formation of an ohmic contact (also known as a quasi-ohmic contact) between the source, drain, and semiconductor channel layer. Compared to vertical channel transistors without a contact layer, this significantly reduces the contact resistance of the vertical channel transistor and increases the current flowing from the source to the drain, thus increasing the operating current of the vertical channel transistor. In other words, even if the contact layer uses the same semiconductor material as the channel layer, the increased contact area between the semiconductor and the source / drain layer still reduces the device's contact resistance. Furthermore, the embodiments of this application can increase the contact area between the channel and the source / drain without increasing the horizontal area of ​​the transistor device, effectively reducing contact resistance while maintaining the threshold voltage of the channel material, thereby improving device performance. Moreover, the solution of this application has broad applicability and can be used to optimize the contact resistance of transistors made of any material.

[0008] It should be understood that, assuming the resistance between the source and the semiconductor channel is Rs, and the resistance between the drain and the semiconductor channel is Rd, the transistor's contact resistance (also called the source-drain contact resistance) can be understood as the sum of Rs and Rd. When the transistor's contact resistance is less than a certain threshold, an ohmic contact is considered to have formed in the transistor. Transistors with ohmic contacts have low contact resistance and high operating current. It should be understood that the contact resistance and the sum of Rs and Rd can only be approximated, and are not necessarily strictly equal.

[0009] In one possible implementation, the groove is a first groove, the semiconductor channel layer covers the bottom and sidewalls of the first groove to form a second groove, the gate oxide layer covers the bottom and sidewalls of the second groove to form a third groove, and the gate is disposed in the third groove.

[0010] In one possible implementation, the semiconductor channel layer, the gate oxide layer, and the gate are sequentially disposed on the bottom surface of the groove; and the semiconductor channel layer, the gate oxide layer, and the gate are sequentially disposed from the outside to the inside on the sidewall of the groove.

[0011] In one possible implementation, the resistance of the contact surface formed by the first contact layer and the second contact layer with the semiconductor channel layer is less than the resistance of the contact surface formed by the first metal layer and the second metal layer with the semiconductor channel layer.

[0012] In one possible implementation, the sum of the resistance of the contact surface formed by the first contact layer and the first metal layer and the resistance of the contact surface formed by the first contact layer and the semiconductor channel layer is less than the resistance of the contact surface formed by the first metal layer and the semiconductor channel layer; the sum of the resistance of the contact surface formed by the second contact layer and the second metal layer and the resistance of the contact surface formed by the second contact layer and the semiconductor channel layer is less than the resistance of the contact surface formed by the second metal layer and the semiconductor channel layer.

[0013] In one possible implementation, the resistance of the contact surface formed by the first contact layer and the first metal layer, and the contact surface formed by the second contact layer and the second metal layer, is less than a first threshold value. Ideally, the first threshold value is close to 0, so the resistance of the contact surface formed by the contact layer and the metal layer can be ignored.

[0014] In one possible implementation, when the materials of the first contact layer and the second contact layer are conductive materials, if the semiconductor channel layer is an n-type semiconductor, then the materials of the first contact layer and the second contact layer are first conductive materials, and the work function of the first conductive material is less than or close to the electron affinity of the semiconductor channel layer; if the semiconductor channel layer is a p-type semiconductor, then the materials of the first contact layer and the second contact layer are second conductive materials, and the work function of the second conductive material is greater than or close to the sum of the electron affinity and the bandgap of the semiconductor channel layer.

[0015] In one possible implementation, when the materials of the first contact layer and the second contact layer are semiconductor materials, if the semiconductor channel layer is a first n-type semiconductor, then the materials of the first contact layer and the second contact layer are first semiconductor materials, the conduction band position of the first semiconductor material is close to the conduction band position of the first n-type semiconductor, and the conductivity of the first semiconductor material is greater than or equal to the conductivity of the first n-type semiconductor; if the semiconductor channel layer is a first p-type semiconductor, then the materials of the first contact layer and the second contact layer are second semiconductor materials, the valence band position of the second conductor material is close to the valence band position of the first p-type semiconductor, and the conductivity of the second conductor material is greater than or equal to the conductivity of the first p-type semiconductor. It should be understood that the vertical channel transistor mentioned in the embodiments of this application can be a vertical channel thin film transistor (TFT).

[0016] It should be understood that the first contact layer and the second contact layer can also be referred to as a transition layer, an ohmic contact layer, or an ohmic contact intercalation layer.

[0017] For example, the conductor materials used in the first contact layer and the second contact layer include: titanium (Ti), gold (Au), tungsten (W), molybdenum (Mo), aluminum (Al), or titanium nitride (TiN).

[0018] For example, the semiconductor materials used in the first contact layer and the second contact layer include: indium gallium zinc oxide InGaZnO, indium zinc oxide InZnO, indium tin oxide InSnO, indium oxide In2O3, gallium oxide Ga2O3, indium titanium oxide InTiO, or zinc oxide ZnO.

[0019] For example, the materials used for the first contact layer and the second contact layer may also include: highly doped p-type silicon Si, n-type Si, or any combination of p-type silicon Si and n-type Si.

[0020] In one possible implementation, the first contact layer and the second contact layer are doped semiconductor layers, and the material of the doped semiconductor layer is obtained by doping the material of the semiconductor channel layer.

[0021] The contact layer can be made of the same semiconductor as the semiconductor channel, but the semiconductor in the contact layer needs to be doped or otherwise treated to achieve lower resistance. When both the first and second contact layers are semiconductors, they can also be referred to as doped semiconductor layers, and the resistance of the doped semiconductor layers is lower than that of the semiconductor channel layer.

[0022] In one possible implementation, the first contact layer, the second contact layer, and the semiconductor channel layer are all P-type semiconductors or all N-type semiconductors; or, the first contact layer and the second contact layer are N-type semiconductors and the semiconductor channel layer is a P-type semiconductor; or, the first contact layer and the second contact layer are P-type semiconductors and the semiconductor channel layer is an N-type semiconductor.

[0023] It should be understood that if the materials of the ohmic contact layer and the semiconductor channel layer have the same polarity, an ohmic contact can be formed between the source / drain and the semiconductor channel layer after the introduction of the ohmic contact layer. If the materials of the ohmic contact layer and the semiconductor channel layer have different polarities, the doping concentration of the ohmic contact layer needs to be increased to form a PN junction ohmic contact between the source / drain and the semiconductor channel layer. This broadens the selection of device materials and can be widely used to optimize the contact resistance of devices made of any material, realizing heterojunction transistor devices.

[0024] In one possible implementation, the structure is cylindrical, with the stacked structure surrounding the semiconductor channel layer, which is entirely located within a vertical recess inside the stacked structure. This implementation is a channel-all-around (CAA) approach.

[0025] In one possible implementation, the structure is a square columnar shape. The stacked structure includes a first sub-stacked structure and a second sub-stacked structure. The semiconductor channel layer includes a first semiconductor channel layer and a second semiconductor channel layer. The gate oxide layer includes a first gate oxide layer and a second gate oxide layer. The gate is disposed between the first sub-stacked structure and the second sub-stacked structure. The first semiconductor channel layer and the first gate oxide layer are disposed between the first sub-stacked structure and the gate, and the first semiconductor channel layer is in contact with the side of the first sub-stacked structure. The second semiconductor channel layer and the second gate oxide layer are disposed between the second sub-stacked structure and the gate, and the second semiconductor channel layer is in contact with the side of the second sub-stacked structure.

[0026] After the middle portion of the stacked structure is etched, two sidewalls remain. A semiconductor channel layer, a gate oxide layer, and a gate are sequentially formed on the inner side of each sidewall. Two semiconductor channel layers are located near the two sidewalls of the transistor, thus creating two vertical channels. This dual-channel structure can further increase the operating current of vertical channel transistor devices, thereby improving the operating speed of the memory containing the vertical channel transistor.

[0027] In one possible implementation, a first interface layer and a second interface layer are further included, wherein the first interface layer is located between the first contact layer and the insulating dielectric layer, and the second interface layer is located between the second contact layer and the insulating dielectric layer.

[0028] In one possible implementation, the materials of the first interface layer and the second interface layer are the same as the materials of the first contact layer and the second contact layer, but the doping concentration of the materials of the first interface layer and the second interface layer is lower than the doping concentration of the materials of the first contact layer and the second contact layer.

[0029] This interface layer effectively prevents highly doped elements from diffusing into the insulating dielectric layer, thereby widening the doping concentration window of the contact layer. Higher concentrations can be used to dope the contact layer, resulting in a lower resistance in the PN junction ohmic contact. Furthermore, when heavily doping (or increasing the doping concentration) the first and second contact layers, it prevents highly doped elements from diffusing into the insulating isolation layer and affecting its isolation effect.

[0030] A second aspect of this application provides a vertical channel transistor, comprising: a stacked structure including a first metal layer, a first contact layer, an insulating dielectric layer, a second contact layer, and a second metal layer; the first contact layer is located between the first metal layer and the insulating dielectric layer, and the second contact layer is located between the second metal layer and the insulating dielectric layer; a groove is provided in the stacked structure, the groove penetrating the second metal layer, the second contact layer, the insulating dielectric layer, and the second contact layer, and the first groove is at least partially embedded in the first metal layer; a semiconductor channel layer, a gate oxide layer, and a gate are disposed within the groove; wherein the semiconductor channel layer contacts the first metal layer and the second metal layer respectively within the groove, and the gate oxide layer is disposed between the semiconductor channel layer and the gate; the resistance of the contact surfaces formed by the first contact layer and the second contact layer with the semiconductor channel layer is less than the resistance of the contact surfaces formed by the first metal layer and the second metal layer with the semiconductor channel layer.

[0031] In one possible implementation, the resistance of the contact surface formed by the first contact layer and the first metal layer, and the contact surface formed by the second contact layer and the second metal layer, is less than a first threshold value. For example, the first threshold value is a relatively small value, close to 0. In another possible implementation, the materials of the first contact layer and the second contact layer are conductive materials, and the conductive materials of the first metal layer and the second metal layer are different from the materials of the first metal layer and the second metal layer; or, the materials of the first contact layer and the second contact layer are semiconductor materials with higher conductivity than the semiconductor channel layer.

[0032] A third aspect of this application provides a vertical channel transistor, comprising: a stacked structure and a semiconductor channel layer, wherein a vertical groove is disposed within the stacked structure, and the semiconductor channel layer is disposed within the groove; the stacked structure includes a first metal layer, a second metal layer, and a third metal layer, the third metal layer being located between the first metal layer and the second metal layer, and a first dielectric layer surrounding the first interface, the second interface, and the third interface of the third metal layer; the first interface is the interface of the third metal layer facing the first metal layer, the second interface is the interface of the third metal layer facing the second metal layer, and the third interface is the interface of the third metal layer facing the semiconductor channel layer; the stacked structure further includes a first contact layer and a second contact layer, the first contact layer being located between the first metal layer and the first dielectric layer, and the second contact layer being located between the second metal layer and the first dielectric layer; the semiconductor channel layer is in contact with the first metal layer and the second metal layer respectively.

[0033] It should be understood that one of the first and second metal layers is the source, the other is the drain, and the third metal layer is the gate. The first dielectric layer can also be called the gate oxide dielectric layer.

[0034] The vertical channel transistor provided in this application has its source and drain located at the top and bottom of the device, with the gate positioned vertically between the source and drain. The gate regulates the current within the semiconductor channel layer from the outside. Gate oxide layers are disposed on the surface of the gate facing the source, the surface facing the drain, and the surface near the semiconductor channel layer. A contact layer is disposed between the drain and the gate oxide layer, and also between the source and the gate oxide layer, thereby forming an ohmic contact between the source / drain and the vertical channel layer. Besides effectively reducing contact resistance and improving device performance, this structure, by placing the gate and gate oxide layer between the source and drain and omitting the insulating dielectric layer, allows for a smaller transistor device size, which is more conducive to improving integration density.

[0035] In one possible implementation, the groove extends through the stacked structure.

[0036] In one possible implementation, the materials of the first contact layer and the second contact layer are conductive materials, and the conductive materials of the first metal layer and the second metal layer are different from the materials of the first metal layer and the second metal layer; or, the materials of the first contact layer and the second contact layer are semiconductor materials with higher conductivity than the semiconductor channel layer.

[0037] In one possible implementation, the resistance of the contact surface formed by the first contact layer and the second contact layer with the semiconductor channel layer is less than the resistance of the contact surface formed by the first metal layer and the second metal layer with the semiconductor channel layer.

[0038] In one possible implementation, the resistance of the contact surface formed by the first contact layer and the first metal layer, and the contact surface formed by the second contact layer and the second metal layer, is less than a first threshold value.

[0039] In one possible implementation, the structure is cylindrical, with the stacked structure surrounding the semiconductor channel layer, which is entirely located within the vertical recess inside the stacked structure.

[0040] In one possible implementation, the structure is a square column, and the stacked structure includes a first sub-stacked structure and a second sub-stacked structure. The semiconductor channel layer is located between the first sub-stacked structure and the second sub-stacked structure, and the first semiconductor channel layer is in contact with the side surface of the first sub-stacked structure and the side surface of the second sub-stacked structure, respectively.

[0041] This vertical channel transistor includes two vertical channels, which can further increase the operating current of the vertical channel transistor device, thereby improving the operating speed of the memory where the vertical channel transistor is located.

[0042] In one possible implementation, the first contact layer and the second contact layer are doped semiconductor layers, and the material of the doped semiconductor layer is obtained by doping the material of the semiconductor channel layer.

[0043] For details on the specific materials that can be selected for the contact layer, please refer to the description in the first part, which will not be repeated here.

[0044] In one possible implementation, the first contact layer, the second contact layer, and the semiconductor channel layer are all P-type semiconductors or all N-type semiconductors; or, the first contact layer and the second contact layer are N-type semiconductors and the semiconductor channel layer is a P-type semiconductor; or, the first contact layer and the second contact layer are P-type semiconductors and the semiconductor channel layer is an N-type semiconductor.

[0045] It should be understood that if the materials of the ohmic contact layer and the semiconductor channel layer have the same polarity, an ohmic contact can be formed between the source / drain and the semiconductor channel layer after the introduction of the ohmic contact layer. If the materials of the ohmic contact layer and the semiconductor channel layer have different polarities, the doping concentration of the ohmic contact layer needs to be increased to form a PN junction ohmic contact between the source / drain and the semiconductor channel layer. This broadens the selection of device materials and can be widely used to optimize the contact resistance of devices made of any material, realizing heterojunction transistor devices.

[0046] In one possible implementation, a first interface layer and a second interface layer are further included, wherein the first interface layer is located between the first contact layer and the first dielectric layer, and the second interface layer is located between the second contact layer and the first dielectric layer.

[0047] In one possible implementation, the materials of the first interface layer and the second interface layer are the same as the materials of the first contact layer and the second contact layer, but the doping concentration of the materials of the first interface layer and the second interface layer is lower than the doping concentration of the materials of the first contact layer and the second contact layer.

[0048] Introducing interface layers at the interface between the first contact layer and the gate oxide dielectric layer, and at the interface between the second contact layer and the gate oxide dielectric layer, can effectively prevent highly doped elements from diffusing into the gate oxide dielectric layer.

[0049] A fourth aspect of this application provides a method for manufacturing a vertical channel transistor, the method comprising: sequentially depositing a first metal layer, a first contact layer, an insulating dielectric layer, a second contact layer, and a second metal layer to form a stacked structure; etching the stacked structure to form a first trench; growing a semiconductor channel layer in the first trench to form a second trench; growing a gate oxide dielectric layer in the second trench to form a third trench; and growing a gate electrode in the third trench; wherein the materials of the first contact layer and the second contact layer are conductive materials or semiconductor materials with conductivity higher than that of the semiconductor channel layer.

[0050] Applying traditional processes to vertical channel transistors, in the formation of... Figure 6 When constructing the structure shown in b, it is necessary to dope the source and drain electrodes before forming... Figure 6In the structure shown in c, the semiconductor channel layer is doped to reduce the contact resistance between the source / drain and the semiconductor channel. Since the semiconductor channel layer is vertical, bombarding it with an ion beam to achieve doping results in uneven doping concentration across the channel layer. This uneven doping concentration also exists when doping the source and drain. The manufacturing method of this application reduces the contact resistance between the source / drain and the semiconductor channel layer by introducing an ohmic contact layer, without needing to dope the source, drain, and semiconductor channel layer. Therefore, it avoids the problem of uneven doping concentration and eliminates the need for an additional photomask required for the doping process, simplifying the process and reducing application costs. Furthermore, in vertical channel transistors, the source / drain metals contact the semiconductor channel, and the contact surface undergoes oxidation during annealing, which increases the contact resistance. After introducing the contact layer, even if the metal is oxidized, it will not have a significant impact on the contact resistance of the transistor device. Therefore, it can prevent the negative effect of increased contact resistance caused by oxidation of the metal-channel contact surface during subsequent annealing, and improve the thermal stability of the device.

[0051] In one possible implementation, after growing the gate on the gate oxide layer, the method further includes etching the gate, the gate oxide layer, and the semiconductor channel layer to isolate the vertical channel transistor from other adjacent vertical channel transistors.

[0052] In one possible implementation, the resistance of the contact surface formed by the first contact layer and the second contact layer with the semiconductor channel layer is less than the resistance of the contact surface formed by the first metal layer and the second metal layer with the semiconductor channel layer.

[0053] In one possible implementation, the materials of the first contact layer and the second contact layer include: titanium (Ti), gold (Au), tungsten (W), molybdenum (Mo), aluminum (Al), or titanium nitride (TiN).

[0054] In one possible implementation, the materials of the first contact layer and the second contact layer include: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium tin oxide (InSnO), indium oxide (In2O3), gallium oxide (Ga2O3), indium titanium oxide (InTiO), or zinc oxide (ZnO).

[0055] In one possible implementation, the materials of the first contact layer and the second contact layer include: highly doped p-type silicon Si, n-type Si, or any combination of p-type silicon Si and n-type Si.

[0056] In one possible implementation, the first contact layer and the second contact layer are doped semiconductor layers, and the material of the doped semiconductor layer is obtained by doping the material of the semiconductor channel layer.

[0057] In one possible implementation, when the polarity of the first contact layer and the second contact layer is different from that of the semiconductor of the semiconductor channel layer, the doping concentration of the first contact layer and the second contact layer is higher than that of the semiconductor channel layer.

[0058] In one possible implementation, a first metal layer, a first contact layer, an insulating dielectric layer, a second contact layer, and a second metal layer are sequentially deposited to form a stacked structure. Specifically, this includes: sequentially depositing the first metal layer, the first contact layer, the first interface layer, the insulating dielectric layer, the second interface layer, the second contact layer, and the second metal layer to form a stacked structure.

[0059] In this embodiment, a vertical channel transistor comprising an interface layer is fabricated. Because the interface layer effectively prevents highly doped elements from diffusing into the insulating dielectric layer, the doping concentration window of the contact layer is widened, allowing for higher doping concentrations in the contact layer, resulting in a lower resistance in the ohmic contact of the formed PN junction. Furthermore, when heavily doping the first and second contact layers, the diffusion of highly doped elements into the insulating isolation layer is prevented, thus avoiding any impact on the isolation effect of the insulating isolation layer.

[0060] In one possible implementation, the process for growing the semiconductor channel layer, the gate oxide dielectric layer, and the gate includes atomic layer deposition (ALD) or chemical vapor deposition (CVD).

[0061] The fifth aspect of this application provides a method for manufacturing a vertical channel transistor, the method comprising: sequentially depositing a first metal layer, a first contact layer, an insulating dielectric layer, a second contact layer, and a second metal layer to form a stacked structure; etching the stacked structure to form a via; growing a semiconductor channel layer in the via; removing the insulating dielectric layer in the stacked structure by wet etching; and sequentially growing a gate oxide dielectric layer and a gate electrode in the space after the insulating dielectric layer has been removed.

[0062] The manufacturing method of this application reduces the contact resistance between the source / drain and the semiconductor channel layer by introducing an ohmic contact layer, without requiring doping of the source, drain, and semiconductor channel layer to reduce contact resistance. Therefore, it avoids the problem of uneven doping concentration and eliminates the need for additional photomasks required for doping processes, simplifying the process and reducing application costs. Furthermore, in vertical channel transistors, the source / drain metals contact the semiconductor channel, and the contact surface undergoes a certain degree of oxidation during annealing, which increases contact resistance. With the introduction of the contact layer, even if the metal oxidizes, it will not significantly affect the contact resistance of the transistor device. Therefore, it can prevent the negative effect of increased contact resistance caused by oxidation of the metal-channel contact surface during subsequent annealing, improving the thermal stability of the device.

[0063] In one possible implementation, the resistance of the contact surface formed by the first contact layer and the second contact layer with the semiconductor channel layer is less than the resistance of the contact surface formed by the first metal layer and the second metal layer with the semiconductor channel layer.

[0064] In one possible implementation, the resistance of the contact surface formed by the first contact layer and the first metal layer, and the contact surface formed by the second contact layer and the second metal layer, is less than a first threshold value.

[0065] In one possible implementation, the materials of the first contact layer and the second contact layer are conductive materials, and the conductive materials of the first metal layer and the second metal layer are different from the materials of the first metal layer and the second metal layer; or, the materials of the first contact layer and the second contact layer are semiconductor materials with higher conductivity than the semiconductor channel layer.

[0066] In one possible implementation, the first contact layer and the second contact layer are doped semiconductor layers, and the material of the doped semiconductor layer is obtained by doping the material of the semiconductor channel layer.

[0067] In one possible implementation, when the polarity of the first contact layer and the second contact layer is different from that of the semiconductor of the semiconductor channel layer, the doping concentration of the first contact layer and the second contact layer is higher than that of the semiconductor channel layer.

[0068] In one possible implementation, the sequential deposition of a first metal layer, a first contact layer, an insulating dielectric layer, a second contact layer, and a second metal layer to form a stacked structure includes: sequentially depositing the first metal layer, the first contact layer, the first interface layer, the insulating dielectric layer, the second interface layer, the second contact layer, and the second metal layer to form a stacked structure.

[0069] In order to fabricate a vertical channel transistor with an interface layer, an interface layer can be formed between the first contact layer and the dielectric layer, and between the second contact layer and the dielectric layer, respectively, during the fabrication of the stacked structure. This can effectively prevent highly doped elements from diffusing into the dielectric layer, thereby widening the doping concentration window of the contact layer. Attached Figure Description

[0070] Figure 1 A comparison diagram of a conventional vertical channel transistor provided in the embodiments of this application and a vertical channel transistor proposed in the embodiments of this application;

[0071] Figure 2a This application provides a schematic diagram of the structure of a vertical channel transistor.

[0072] Figure 2b for Figure 2a A magnified view of a portion of the image;

[0073] Figure 2c for Figure 2b Cross-sectional view along dashed line 110;

[0074] Figure 3a A top view of an exemplary vertical channel transistor provided for an embodiment of this application;

[0075] Figure 3b A top view of another exemplary vertical channel transistor provided for embodiments of this application;

[0076] Figure 4a A schematic side cross-sectional view of an exemplary vertical channel transistor provided for an embodiment of this application;

[0077] Figure 4b for Figure 4a A top view of a vertical channel transistor;

[0078] Figure 4c for Figure 4a Another top view corresponding to a vertical channel transistor;

[0079] Figure 5 This is a schematic diagram of another vertical channel transistor structure provided in an embodiment of this application;

[0080] Figure 6 a- Figure 6 f is a schematic diagram of the fabrication process of a vertical channel transistor provided in an embodiment of this application;

[0081] Figure 7 This application provides a schematic flowchart of a method for manufacturing a vertical channel transistor.

[0082] Figure 8A schematic flowchart of another method for manufacturing a vertical channel transistor provided in this application embodiment;

[0083] Figure 9 a- Figure 9 e is a schematic diagram of another vertical channel transistor fabrication process provided in the embodiments of this application;

[0084] Figure 10 This is a schematic flowchart of another method for manufacturing a vertical channel transistor provided in an embodiment of this application. Detailed Implementation

[0085] The terms "first," "second," etc., in the specification, embodiments, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, such as including a series of steps or units. A method, system, product, or apparatus is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses.

[0086] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0087] Current vertical-channel transistors typically face the problem of high contact resistance, which significantly affects their electrical performance. For example... Figure 1 As shown, the left side is a schematic diagram of a conventional vertical channel transistor structure and its corresponding band diagram, while the right side is a schematic diagram of a vertical channel transistor with a contact layer proposed in this application and its corresponding band diagram. Figure 1As shown on the left, in the prior art, electrons need to pass through two contact surfaces to travel from the source to the semiconductor channel layer and then to the drain: the contact surface between the source and the semiconductor channel layer, and the contact surface between the semiconductor channel layer and the drain. Both the contact surface between the source and the semiconductor channel layer, and the contact surface between the semiconductor channel layer and the drain, are Schottky contacts. Current injection is in a thermally excited mode, resulting in high contact resistance, high electron potential energy required to cross the potential barrier, and low current. However, as... Figure 1 The right side shows the vertical channel transistor structure provided in this application. Contact layers are provided between the drain and the insulating dielectric layer, and between the source and the insulating dielectric layer. Electrons need to pass through four contact surfaces from the source to the drain: the contact surface between the source and the first contact layer, the contact surface between the first contact layer and the semiconductor channel layer, the contact surface between the semiconductor channel layer and the second contact layer, and the contact surface between the second contact layer and the drain. Since the materials of these two contact layers are conductive materials or semiconductor materials with higher conductivity than the semiconductor channel layer, their resistance is low. Therefore, the contact performance between the contact layer and the semiconductor channel layer is much better than the contact performance between the source and drain and the semiconductor channel layer. The contact resistance between the contact layer and the semiconductor channel layer is much smaller than the contact resistance between the source and drain and the semiconductor channel layer. Furthermore, since the contact layer has good contact with the metal, ideally, the contact resistance formed between the source and drain and the contact layer can be ignored. Therefore, after introducing two contact layers, the total resistance of the four contact surfaces through which electrons pass from the source to the drain is less than the total resistance of the two contact surfaces through which electrons pass from the source to the drain in the prior art. This allows an ohmic contact (also known as a near-ohmic contact) to be formed between the source, drain, and semiconductor channel layer. When this type of vertical channel transistor is working, electrons can directly pass through the potential barrier from the source to the semiconductor channel layer and from the semiconductor channel layer to the drain using wave properties, which realizes current tunneling injection. Compared with vertical channel transistors without a contact layer, this greatly reduces the contact resistance of the vertical channel transistor and increases the current flowing from the source to the drain, which in turn increases the operating current of the vertical channel transistor.

[0088] It should be understood that the contact resistance in the embodiments of this application can be understood as the sum of the resistance Rs between the source and the channel and the resistance Rd between the channel and the drain. It should be understood that the contact resistance and the sum of Rs and Rd can only be approximated, and are not necessarily strictly equal. This contact resistance can also be called the source-drain contact resistance.

[0089] This application provides a vertical channel transistor structure, which includes a stacked structure comprising a first metal layer, a first contact layer, an insulating dielectric layer, a second contact layer, and a second metal layer; the first contact layer is located between the first metal layer and the insulating dielectric layer, and the second contact layer is located between the second metal layer and the insulating dielectric layer; a groove is provided in the stacked structure, and a semiconductor channel layer, a gate oxide layer, and a gate are disposed in the groove; wherein the semiconductor channel layer is in contact with the first metal layer and the second metal layer respectively, and the gate oxide layer is disposed between the semiconductor channel layer and the gate.

[0090] like Figure 2a The diagram shown is a schematic representation of a vertical channel transistor according to an embodiment of this application. Figure 2b for Figure 2a A magnified view of a portion of the image. Figure 2c for Figure 2b Cross-sectional view along dashed line 110. Based on Figures 2a-2c As can be seen, the vertical channel transistor includes a drain 103, a source 104, a gate 105, a semiconductor channel layer 106, a gate oxide dielectric layer 107, an insulating dielectric layer 108, a first contact layer 101, and a second contact layer 102. The vertical channel transistor has a columnar structure with a vertically oriented semiconductor channel. The drain 103, the first contact layer 101, the insulating dielectric layer 108, the second contact layer 102, and the source 104 form a stacked structure in the vertical direction. A deep hole, or groove, is provided inside this stacked structure. The semiconductor channel layer 106, the gate oxide dielectric layer 107, and the gate 105 are sequentially disposed within this deep hole. The semiconductor channel layer 106 forms contact with both the source 104 and the drain 103. The gate oxide dielectric layer 107 is disposed between the gate 105 and the semiconductor channel layer 106. It should be understood that the positions of the source 103 and the drain 104 can be interchanged. Figure 2a The drain is located on the lower side of the device, and the source is located on the upper side. In an optional case, the source is located on the lower side of the device, and the drain is located on the upper side. This application embodiment does not limit the positions of the source and drain. For example, the vertical channel transistor in this application embodiment can be a vertical channel TFT.

[0091] For example, the deep hole in the stacked structure penetrates the source layer 104, the second contact layer 102, the insulating dielectric layer 108, and the first contact layer 101, and is embedded in the drain 103. Typically, the insulating dielectric layer 108 is disposed between the drain 103 and the source 104 to achieve electrical isolation between the source metal and the drain metal.

[0092] In this embodiment, a first contact layer 101 is provided between the drain 103 and the insulating dielectric layer 108, and a second contact layer 102 is provided between the source 104 and the insulating dielectric layer 108. These two contact layers have low resistance, high doping concentration, and good contact with the metal. This allows an ohmic contact (also known as a quasi-ohmic contact) to be formed between the source 104, the drain 103, and the semiconductor channel layer 106. When this type of vertical channel transistor is working, electrons can directly pass through the potential barrier from the source to the semiconductor channel layer and from the semiconductor channel layer to the drain using wave properties, which realizes current tunneling injection. Compared with vertical channel transistors without the first contact layer 101 and the second contact layer 102, the contact resistance of the vertical channel transistor is greatly reduced, and the current flowing from the source to the drain is increased, which increases the operating current of the vertical channel transistor.

[0093] It should be understood that the insulating dielectric layer can also be called the dielectric layer. The thickness d of this insulating dielectric layer determines the length of the vertical channel. To some extent, the length of the vertical channel is approximately equal to the thickness d of the insulating dielectric layer.

[0094] It should be understood that the first contact layer 101 and the second contact layer 102 can also be referred to as a transition layer, an ohmic contact layer, or an ohmic contact intercalation layer. The names of the contact layers are not limited in this embodiment. For example, the materials of the first contact layer and the second contact layer are conductive materials or semiconductor materials with a conductivity higher than that of the semiconductor channel layer. If the materials of the first contact layer and the second contact layer are conductive materials, then the conductive materials of the first contact layer and the second contact layer are different from the materials of the first metal layer and the second metal layer. The materials of the first contact layer and the second contact layer can form good contact with the semiconductor channel layer. Therefore, the contact resistance of the contact surface between the contact layer and the semiconductor channel layer is much smaller than the contact resistance of the contact surfaces between the source and drain and the semiconductor channel layer. Furthermore, since the contact layer has good contact with the metal, the resistance of the contact surface formed by the first contact layer and the first metal layer, and the contact surface formed by the second contact layer and the second metal layer, is less than a first threshold value. Ideally, the first threshold value is close to 0, so the resistance of the contact surface formed by the contact layer and the metal layer can be ignored.

[0095] In one possible implementation, the sum of the resistance of the contact surface formed by the first contact layer and the first metal layer and the resistance of the contact surface formed by the first contact layer and the semiconductor channel layer is less than the resistance of the contact surface formed by the first metal layer and the semiconductor channel layer. Similarly, the sum of the resistance of the contact surface formed by the second contact layer and the second metal layer and the resistance of the contact surface formed by the second contact layer and the semiconductor channel layer is less than the resistance of the contact surface formed by the second metal layer and the semiconductor channel layer.

[0096] The materials of the first and second contact layers are related to the material of the semiconductor channel layer.

[0097] For example, when the materials of the first contact layer and the second contact layer are conductive materials, if the semiconductor channel layer is an n-type semiconductor, then the materials of the first contact layer and the second contact layer are first conductive materials, and the work function of the first conductive material is less than or close to the electron affinity of the semiconductor channel layer; if the semiconductor channel layer is a p-type semiconductor, then the materials of the first contact layer and the second contact layer are second conductive materials, and the work function of the second conductive material is greater than or close to the sum of the electron affinity and the bandgap of the semiconductor channel layer.

[0098] For example, when the materials of the first contact layer and the second contact layer are semiconductor materials, if the semiconductor channel layer is a first n-type semiconductor, then the materials of the first contact layer and the second contact layer are first semiconductor materials, the conduction band position of the first semiconductor material is close to the conduction band position of the first n-type semiconductor, and the conductivity of the first semiconductor material is greater than or equal to the conductivity of the first n-type semiconductor; if the semiconductor channel layer is a first p-type semiconductor, then the materials of the first contact layer and the second contact layer are second semiconductor materials, the valence band position of the second conductor material is close to the valence band position of the first p-type semiconductor, and the conductivity of the second conductor material is greater than or equal to the conductivity of the first p-type semiconductor.

[0099] The following section defines several terms used in the embodiments of this application.

[0100] The work function is the minimum energy required for an electron to immediately escape from the surface of a solid. It is usually measured in electron volts. The word "immediately" indicates that the electron's final position is far from the surface on an atomic scale but still close to the solid on a macroscopic scale. The work function is an important property of metals.

[0101] Electron affinity, also known as electron affinity potential or electron affinity force, is the energy of the affinity interaction between electrons. It is the energy released when a ground-state gaseous atom gains an electron and transforms into a gaseous anion, and is measured in kJ / mol. Electron affinity represents the energy required or released to cause an electron to escape from a gaseous ion or molecule.

[0102] Conduction band: The energy space formed by free electrons. That is, the energy range possessed by freely moving electrons within a solid structure.

[0103] The valence band refers to the region of highest energy in a solid at absolute zero where electrons reside. If an electron in the valence band is given an energy higher than the band gap, it will transition from the valence band to the conduction band. In short, the energy band occupied by valence electrons is the valence band.

[0104] Forbidden band: Often used to represent the energy range between the valence band and the conduction band where the density of states is zero. The gap between the conduction band and the valence band is the forbidden band.

[0105] Band gap (or width of the forbidden band): The energy range of the forbidden band. For a bound electron to become a free electron or a hole, it must acquire enough energy to transition from the valence band to the conduction band. This minimum energy is the band gap. In other words, the band gap is the energy between the lowest energy level of the conduction band and the highest energy level of the valence band.

[0106] For example, the contact layer can be made of the same semiconductor as the semiconductor channel, but the semiconductor of the contact layer needs to be doped or otherwise treated to have a lower resistance than the semiconductor channel layer. When the first and second contact layers are semiconductors, they can also be referred to as doped semiconductor layers.

[0107] By introducing an ohmic contact layer, the contact area between the channel and the source / drain can be increased without increasing the transistor device area, effectively reducing the contact resistance while keeping the threshold of the channel material unchanged, thus improving device performance.

[0108] For example, the materials of the first contact layer 101 and the second contact layer 102 can be selected in conjunction with the semiconductor channel material and the materials of the drain and source metals, such as highly conductive oxide semiconductors, such as indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium tin oxide (InSnO), indium oxide (In2O3), gallium oxide (Ga2O3), indium titanium oxide (InTiO), and zinc oxide (ZnO); conductors can also be selected, such as titanium (Ti), gold (Au), tungsten (W), molybdenum (Mo), aluminum (Al), and titanium nitride (TiN); or highly doped p-type silicon (Si), n-type silicon, or any combination of p-type silicon (Si) and n-type silicon, etc.

[0109] The source 104 and drain 103 can be made of metallic or conductive materials, such as TiN, Ti, Au, W, Mo, In-Ti-O (ITO), Al, copper Cu, ruthenium Ru, silver Ag, or any combination thereof.

[0110] The gate 105 can be a metallic material or a conductive material, such as TiN, Ti, Au, W, Mo, InTiO, InZnO, Al, Cu, Ru, Ag, or any combination thereof.

[0111] The gate oxide dielectric layer 107 can be made of insulating materials such as SiO2, Al2O3, HfO2, ZrO2, TiO2, Y2O3, LaOx, Si3N4, or any combination thereof. The gate oxide dielectric layer 107 can be a stacked structure of a single material or a stacked structure of a combination of materials.

[0112] The semiconductor channel material 106 can be Si, polycrystalline silicon (poly-Si), amorphous silicon (amorphous-Si), IGZO and other multi-component compounds, In2O3, Ga2O3, ZnO, SnOx, ITO, TiO2, MoS2 and other semiconductor materials or any combination thereof.

[0113] The insulating dielectric layer 108 can be made of materials such as SiO2, Si3N4, and Al2O3.

[0114] The vertical channel thin-film crystal provided in this application embodiment can be a cylindrical structure or a square columnar structure, such as... Figure 3a The image shown is a top view of an exemplary vertical channel transistor provided in an embodiment of this application. The vertical channel transistor is cylindrical, with a gate 105 as its innermost layer. A gate oxide dielectric layer 107 surrounds the gate 105, and a semiconductor channel layer 106 surrounds the gate oxide dielectric layer. A stacked structure consisting of a source layer and a drain layer surrounds the semiconductor channel layer 106. Due to… Figure 3a It is a top view, so only the topmost source layer 104 can be seen. This implementation is a channel-all-around (CAA) method, where the semiconductor channel layer 106 is completely filled into the vertical groove inside the stacked structure.

[0115] like Figure 3b The image shown is a top view of another exemplary vertical-channel transistor provided in this application embodiment. This implementation is a dual-channel structure. The vertical-channel transistor is a square columnar structure, therefore its top view is rectangular. The stacked structure formed vertically by the drain 103, the first contact layer 101, the insulating dielectric layer 108, the second contact layer 102, and the source 104 is a square columnar structure, or it can also be called a cube. It should be explained that since the drain 103, the first contact layer 101, the insulating dielectric layer 108, and the second contact layer 102 are all located below the source 104, therefore, in this top view... Figure 3bOnly the topmost source 104 is visible. After the middle portion of the stacked structure is etched, two sidewalls remain. A semiconductor channel layer 106, a gate oxide layer 107, and a gate 105 are sequentially disposed on the inner side of each sidewall. Two semiconductor channel layers 106 are located near the two sidewalls of the transistor, thus creating two vertical channels. Exemplarily, these two sidewalls are referred to as the first sub-stacked structure and the second sub-stacked structure, respectively. A gate is disposed between the first and second sub-stacked structures. A first semiconductor channel layer and a first gate oxide layer are disposed between the first sub-stacked structure and the gate, with the first semiconductor channel layer contacting the side of the first sub-stacked structure. A second semiconductor channel layer and a second gate oxide layer are disposed between the second sub-stacked structure and the gate, with the second semiconductor channel layer contacting the side of the second sub-stacked structure. The contact between the first semiconductor channel layer and the side of the first sub-stacked structure forms one vertical channel, and the contact between the second semiconductor channel layer and the side of the second sub-stacked structure forms another vertical channel. Therefore, this vertical channel transistor has two vertical channels.

[0116] This dual-channel structure can further increase the operating current of vertical channel transistor devices, thereby improving the operating speed of the memory where the vertical channel transistor is located.

[0117] It should be understood that Figure 3b The two insulating dielectric layers 108 shown are used to isolate adjacent vertical channel transistors and are not part of the vertical channel transistors. Insulating dielectric layers Figure 3a and Figure 3b It can have, for example Figure 2a The side view shown. Or rather, Figure 3a and Figure 3b It can be Figure 2a The side view of the vertical channel transistor shown corresponds to two possible top views.

[0118] It should be understood that, in an alternative scenario, a square deep hole can also be provided inside the square columnar structure, and a semiconductor channel layer 106, a gate oxide dielectric layer 107, and a gate 105 can be sequentially arranged inside the square deep hole. In this structure, the semiconductor channel layer 106 is entirely located inside the square columnar body, and the semiconductor channel layer 106 completely encloses the gate oxide dielectric layer 107, and the gate oxide dielectric layer also completely encloses the gate 105.

[0119] In one alternative, the cross-sectional view of the vertical channel transistor in the top view direction can also be a shape other than a circle and a square, such as a polygon, a sector, an irregular shape, etc.

[0120] Furthermore, this application embodiment also provides a vertical channel transistor, including: a stacked structure and a semiconductor channel layer. A vertical groove is disposed within the stacked structure, and the semiconductor channel layer is disposed within the groove. The stacked structure includes a first metal layer, a second metal layer, and a third metal layer. The third metal layer is located between the first and second metal layers. A first dielectric layer surrounds the first, second, and third interfaces of the third metal layer. The first interface is the interface of the third metal layer facing the first metal layer, the second interface is the interface of the third metal layer facing the second metal layer, and the third interface is the interface of the third metal layer facing the semiconductor channel layer. The stacked structure also includes a first contact layer and a second contact layer. The first contact layer is located between the first metal layer and the first dielectric layer, and the second contact layer is located between the second metal layer and the first dielectric layer. The semiconductor channel layer is in contact with both the first metal layer and the second metal layer. It should be understood that one of the first and second metal layers is the source, the other is the drain, and the third metal layer is the gate. The first dielectric layer can also be referred to as a gate oxide dielectric layer. It should be understood that the first contact layer and the second contact layer in the embodiments of this application can be referred to the foregoing description, and will not be repeated here.

[0121] like Figure 4a The image shown is a side cross-sectional schematic diagram of another vertical channel transistor provided in an embodiment of this application. Figure 4b for Figure 4a A top view corresponding to a vertical channel transistor. Figure 4c for Figure 4a Another top view corresponding to the vertical channel transistor.

[0122] Figure 4a In the vertical channel transistor shown, the vertical channel layer 106 fills the vertical channel within the stacked structure, and the channel runs through the entire stacked structure. The source 104 and drain 103 are located at the top and bottom of the device, and the gate 105 is located between the source 104 and drain 103 in the vertical direction. The gate 105 regulates the current in the semiconductor channel layer 106 from the outside. A gate oxide dielectric layer 107 is disposed on the surface of the gate 105 facing the source 104, the surface facing the drain 103, and the surface near the semiconductor channel layer. A first contact layer 101 is located between the drain 103 and the gate oxide dielectric layer 107, and a second contact layer 102 is located between the source 104 and the gate oxide dielectric layer 107, thereby forming an ohmic contact between the source / drain and the vertical channel layer 106. In addition to effectively reducing contact resistance and improving device performance, this structure places the gate and gate oxide dielectric layer between the source 104 and the drain 103, omitting the insulating dielectric layer 108. This allows for smaller transistor device sizes, which is more conducive to improving integration density.

[0123] like Figure 4b As shown, Figure 4aThe vertical channel transistor shown can be made into a cylindrical structure. This implementation is a GAA method. The vertical channel layer 106 is completely filled into the vertical channel in the stacked structure and is wrapped by the source 104, drain 103 and gate 105 that are surrounded in the horizontal direction.

[0124] like Figure 4c As shown, Figure 4a The vertical channel transistor shown can be made into a square columnar structure. The stacked structure formed by the drain 103, the first contact layer 101, the gate 105, the gate oxide dielectric layer 107, the second contact layer 102, and the source 104 in the vertical direction is a square columnar structure, or it can also be called a cubic structure. It should be explained that since the drain 103, the first contact layer 101, the gate 105, the gate oxide dielectric layer 107, and the second contact layer 102 are all located below the source 104, therefore, in this top view... Figure 4c Only the topmost source 104 is visible. After the middle portion of this stacked structure is etched, two sidewalls remain. A semiconductor channel layer 106 is disposed between the two sidewalls. The source 104 and drain 103 are located above and below the vertical channel transistor device, and the gate 105 is located between the source 104 and drain 103. The semiconductor channel layer 106 extends vertically. Figure 4c The structure shown is a dual-gate structure, with a vertical channel generated on each of the two surfaces where the semiconductor channel layer 106 and the stacked structure meet.

[0125] It should be understood that Figure 4c The two insulating dielectric layers 108 shown are used to isolate adjacent vertical channel transistors and are not part of the interior of the vertical channel transistors.

[0126] It should be understood that Figure 4b The circular columnar structure shown can also be made into a square columnar structure. Figure 4a The cross-sectional view of the vertical channel transistor shown in the top view direction can also be in shapes other than circles and squares, such as polygons, sectors, irregular shapes, etc.

[0127] It should be understood that if the materials of the ohmic contact layer and the semiconductor channel layer have the same polarity, an ohmic contact can be formed between the source / drain and the semiconductor channel layer after the ohmic contact layer is introduced; if the materials of the ohmic contact layer and the semiconductor channel layer have different polarities, the doping concentration of the ohmic contact layer needs to be increased in order to form a PN junction ohmic contact between the source / drain and the semiconductor channel layer.

[0128] The materials of the first contact layer 101 and the second contact layer 102 can be selected based on the material of the semiconductor channel layer to achieve a PN junction ohmic contact. If the semiconductor channel material is an N-type semiconductor, the first contact layer 101 and the second contact layer 102 can be formed using a P-type semiconductor to form the PN junction contact; if the semiconductor channel material is a P-type semiconductor, the first contact layer 101 and the second contact layer 102 can be formed using an N-type semiconductor to form the PN junction contact. Furthermore, by increasing the doping concentration of the first contact layer 101 and the second contact layer 102, the contact resistance of the PN junction can be reduced, thereby forming a PN junction ohmic contact between the source / drain and the semiconductor channel layer. This broadens the selection of device materials and can be widely used to optimize the contact resistance of devices made of any material, realizing heterogeneous contact transistor devices.

[0129] like Figure 5 The diagram shown is a schematic representation of another vertical channel transistor provided in this application embodiment. In this implementation, an interface layer 116 is added between the first contact layer 101 and the insulating dielectric layer 108, and between the second contact layer 102 and the insulating dielectric layer 108. For example, the interface layer 116 can be made of the same material as the first contact layer 101 and the second contact layer 102, but the doping concentration of the interface layer 116 is different from that of the first contact layer 101 and the second contact layer 102. The first contact layer 101 and the second contact layer 102 have a high doping concentration, while the interface layer 116 has a low doping concentration.

[0130] The interface layer 116 effectively prevents highly doped elements from diffusing into the insulating dielectric layer 108, thereby widening the doping concentration window of contact layers 101 and 102. Higher concentrations can be used to dop the contact layers 101 and 102, resulting in a lower resistance in the PN junction ohmic contact. Furthermore, when heavily doping (or increasing the doping concentration) the first contact layer 101 and the second contact layer 102, the diffusion of highly doped elements into the insulating isolation layer 108 can be avoided, preventing any impact on the isolation effect of the insulating isolation layer 108.

[0131] In an optional case, such as Figure 4a An interface layer 116 can also be introduced into the vertical channel transistor shown. Specifically, an interface layer can be introduced at the interface between the first contact layer 101 and the gate oxide dielectric layer 107, and at the interface between the second contact layer 102 and the gate oxide dielectric layer 107, thereby effectively preventing highly doped elements from diffusing into the gate oxide dielectric layer 107.

[0132] like Figure 6 a- Figure 6 As shown in figure f, this is a schematic diagram of the fabrication process of a vertical channel transistor provided in an embodiment of this application. Figure 7The diagram shown is a flowchart illustrating a method for manufacturing a vertical channel transistor according to an embodiment of this application.

[0133] The method includes:

[0134] 701. A drain / source metal layer, a first contact layer, an insulating dielectric layer, a second contact layer, and a source / drain metal layer are sequentially epitaxially deposited on a substrate to obtain the following: Figure 6 The five-layer structure shown in diagram a;

[0135] For example, the substrate can also be referred to as a base, and the material of the substrate can be an insulating material such as silicon oxide. It should be understood that the positions of the source and drain can be interchanged; if the drain layer is located below, the source layer is located above, and vice versa. The first contact layer and the second contact layer can be low-resistivity semiconductors. The materials of these five layers can be referred to the foregoing description of the materials of the source 104, drain 103, insulating dielectric layer 108, first contact layer 101, and second contact layer 102, and will not be repeated here.

[0136] In an alternative embodiment, a first interface layer may be grown between the first contact layer and the insulating dielectric layer, and a second interface layer may be grown between the second contact layer and the insulating dielectric layer. The materials of the first and second interface layers can be referred to the foregoing description of interface layer 116, and will not be repeated here.

[0137] 702. Through etching processes, the upper source / drain metal layer, the second contact layer, the insulating dielectric layer, the first contact layer, and the lower drain / source metal layer are etched sequentially to form a structure as shown below. Figure 6 The groove structure shown in b; for example, the Figure 6 The groove shown in b can be called the first groove;

[0138] It should be understood that this etching is a one-step etching process. The etching process can employ either dry etching or wet etching.

[0139] 703. Epitaxial semiconductor channel material is formed in a groove structure to create a structure such as Figure 6 The structure shown in c; for example, the Figure 6 The groove in c can be called the second groove;

[0140] For example, the semiconductor channel layer can be grown by atomic layer deposition (ALD) or chemical vapor deposition (CVD) processes, and the semiconductor channel material is described above with reference to the semiconductor channel material 106, which will not be repeated here.

[0141] 704. In Figure 6Based on the structure shown in c, an epitaxial gate oxide dielectric material is formed, as shown in... Figure 6 The structure shown in d; for example, the Figure 6 The groove in d can be called the third groove;

[0142] For example, the gate oxide dielectric layer can also be grown by ALD or CVD processes. The gate oxide dielectric material is described above with reference to the material of the gate oxide dielectric layer 107, and will not be repeated here.

[0143] 705. Deposit gate metal on the gate oxide dielectric layer within the third groove to form a structure as shown below. Figure 6 The structure shown in e;

[0144] Gate metal filled in Figure 6 The gate is formed within the third groove of d. For example, the gate layer can also be grown using ALD or CVD processes.

[0145] 706. Isolation between vertical channel transistor devices is formed by etching, forming something like... Figure 6 The structure shown in f is...

[0146] In one alternative approach, in order to prepare as described above Figure 5 The vertical channel crystal 701 shown specifically includes: a metal layer, a first contact layer, a first interface layer, an insulating dielectric layer, a second interface layer, a second contact layer, and a metal layer growing sequentially on a substrate to obtain a 7-layer structure.

[0147] like Figure 8 The diagram shown is a schematic flowchart of another method for manufacturing a vertical channel transistor according to an embodiment of this application.

[0148] 801. Sequentially deposit a metal layer, a low-resistivity semiconductor layer, an insulating dielectric layer, another low-resistivity semiconductor layer, and a metal layer to form a structure like... Figure 6 The layered structure shown in a;

[0149] 802. Perform a one-step etching on the layered structure to form the first groove, such as... Figure 6 As shown in b;

[0150] The groove penetrates the upper metal layer, the low-resistivity semiconductor layer, the insulating dielectric layer, the low-resistivity semiconductor layer, and is embedded in the lower metal layer.

[0151] 803. A semiconductor channel layer is grown in the first groove to form a second groove, such as... Figure 6 As shown in c; the second groove is the groove where the semiconductor channel layer is grown;

[0152] 804. A gate oxide dielectric layer is grown in the second groove to form a third groove, as shown below. Figure 6 As shown in d; the third groove is the groove where the gate oxide dielectric layer is grown;

[0153] 805. A gate layer is grown in the third groove to form a structure as shown in the figure. Figure 6 The structure shown in e;

[0154] 806. Isolation between adjacent vertical channel transistors is formed by etching, such as... Figure 6 As shown in f.

[0155] It should be understood that the growth of semiconductor channel layers, gate oxide dielectric layers, and gate layers can all be achieved using ALD or CVD processes.

[0156] In one alternative approach, in order to prepare as described above Figure 5 The vertical channel crystal 801 shown specifically includes: sequentially depositing a metal layer, a first contact layer, a first interface layer, an insulating dielectric layer, a second interface layer, a second contact layer, and a metal layer to obtain a stacked structure containing 7 layers.

[0157] Applying traditional processes to vertical channel transistors, in the formation of... Figure 6 When constructing the structure shown in b, it is necessary to dope the source and drain electrodes before forming... Figure 6 In the structure shown in c, the semiconductor channel layer is doped to reduce the contact resistance between the source / drain and the semiconductor channel. Since the semiconductor channel layer is vertical, bombarding it with an ion beam to achieve doping results in uneven doping concentration across the entire channel layer. This uneven doping concentration also exists when doping the source and drain. The manufacturing method of this application reduces the contact resistance between the source / drain and the semiconductor channel layer by introducing an ohmic contact layer, without needing to dope the source, drain, and semiconductor channel layer. Therefore, it avoids the problem of uneven doping concentration and eliminates the need for an additional photomask required for the doping process, simplifying the process and reducing application costs. Furthermore, in vertical channel transistors, the source / drain metals contact the semiconductor channel, and the contact surface undergoes oxidation during annealing, which increases the contact resistance. After introducing the contact layer, even if the metal is oxidized, it will not have a significant impact on the contact resistance of the transistor device. Therefore, it can prevent the negative effect of increased contact resistance caused by oxidation of the metal-channel contact surface during subsequent annealing, and improve the thermal stability of the device.

[0158] Furthermore, when fabricating a vertical channel transistor including an interface layer, the interface layer effectively prevents highly doped elements from diffusing into the insulating dielectric layer, thereby widening the doping concentration window of the contact layer. Higher concentrations can be used to dope the contact layer, resulting in a lower resistance in the ohmic contact of the formed PN junction. Moreover, when heavily doping the first and second contact layers, it prevents highly doped elements from diffusing into the insulating isolation layer and affecting its isolation effect.

[0159] like Figure 9 a- Figure 9 As shown in Figure e, this is a schematic diagram of the fabrication process of a vertical channel transistor provided in an embodiment of this application. Figure 10 The diagram shown is a schematic flowchart of a method for manufacturing a vertical channel transistor according to an embodiment of this application. Figure 9 a- Figure 9 e and Figure 10 The preparation process shown can be used to prepare the aforementioned Figure 4a The vertical channel transistor shown.

[0160] The method includes:

[0161] 1001. Sequentially deposit the first metal layer, the first contact layer, the dielectric layer, the second contact layer, and the second metal layer to form a stacked structure, such as... Figure 9 As shown in a;

[0162] It should be understood that one of the first metal layer and the second metal layer is the source and the other is the drain. The first contact layer and the second contact layer can be low-resistivity semiconductor layers. For the materials that can be selected for these five layers, please refer to the description of the materials of the drain 103, the first contact layer 101, the insulating dielectric layer 108, the second contact layer 102 and the source 104 above. They will not be repeated here.

[0163] In an alternative embodiment, a first interface layer may be grown between the first contact layer and the dielectric layer, and a second interface layer may be grown between the second contact layer and the insulating dielectric layer. The materials of the first and second interface layers can be referred to the foregoing description of interface layer 116, and will not be repeated here.

[0164] 1002. Etching the layered structure to create perforations, such as... Figure 9 As shown in b;

[0165] It should be understood that this perforation can also be described as a groove penetrating the stacked structure in the vertical direction. This etching is a one-step etching process.

[0166] 1003. Growing a semiconductor channel layer in a via, forming a structure like... Figure 9 The structure shown in c;

[0167] For example, a semiconductor channel layer can be grown by ALD or CVD process, and the semiconductor channel material is described above with reference to the semiconductor channel material 106, which will not be repeated here.

[0168] 1004. Remove the dielectric layer in the stacked structure by wet etching;

[0169] like Figure 9As shown in d, after removing the dielectric layer in the stacked structure, two spaces (or lateral grooves) are formed on both sides of the semiconductor channel layer.

[0170] 1005. In the space after removing the dielectric layer, a gate oxide dielectric layer and a gate are grown sequentially to form a structure as shown in Figure 1005. Figure 9 The structure shown in e.

[0171] Within these two recesses, a gate oxide dielectric layer is first grown using ALD or CVD, and then the gate electrode is grown on the gate oxide dielectric layer using ALD or CVD. The recesses formed after removing the dielectric layer have three sides: a first side facing the first contact layer, a second side adjacent to the second contact layer, and a third side in contact with the semiconductor channel layer; a gate oxide dielectric layer is grown on each of these three sides; the gate oxide dielectric material is described above for the material of the gate oxide dielectric layer 107, and will not be repeated here.

[0172] It should be understood that, since multiple vertical channel transistor devices are typically fabricated simultaneously, although Figure 10 As not shown in the figure, the method may further include:

[0173] 1006. Isolation is achieved between adjacent vertical channel transistors through etching.

[0174] In an optional embodiment, to fabricate a vertical channel transistor including interface layers, during the fabrication of the stacked structure in step 1001, interface layers can be formed between the first contact layer and the dielectric layer, and between the second contact layer and the dielectric layer, respectively. That is, a metal layer, a first contact layer, a first interface layer, a dielectric layer, a second interface layer, a second contact layer, and a metal layer are deposited sequentially to obtain a stacked structure containing 7 layers. Then, subsequent processing steps 1002-1005 are performed on this stacked structure.

[0175] The manufacturing method of this application reduces the contact resistance between the source / drain and the semiconductor channel layer by introducing an ohmic contact layer, without requiring doping of the source, drain, and semiconductor channel layer to reduce contact resistance. Therefore, it avoids the problem of uneven doping concentration and eliminates the need for additional photomasks required for doping processes, simplifying the process and reducing application costs. Furthermore, in vertical channel transistors, the source / drain metals contact the semiconductor channel, and the contact surface undergoes a certain degree of oxidation during annealing, which increases contact resistance. With the introduction of the contact layer, even if the metal oxidizes, it will not significantly affect the contact resistance of the transistor device. Therefore, it can prevent the negative effect of increased contact resistance caused by oxidation of the metal-channel contact surface during subsequent annealing, improving the thermal stability of the device.

[0176] The embodiments described above are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application. For example, some specific operations in the device embodiments can be referred to the previous method embodiments.

Claims

1. A vertical channel transistor structure, characterized in that, include: A laminated structure, the laminated structure including a first metal layer, a first contact layer, an insulating dielectric layer, a second contact layer, and a second metal layer; the first contact layer is located between the first metal layer and the insulating dielectric layer, and the second contact layer is located between the second metal layer and the insulating dielectric layer; The stacked structure is provided with a groove that penetrates the second metal layer, the second contact layer, the insulating dielectric layer and the second contact layer, and the groove is at least partially embedded in the first metal layer; The groove contains a semiconductor channel layer, a gate oxide dielectric layer, and a gate. Wherein, the materials of the first contact layer and the second contact layer are semiconductor materials with higher conductivity than the semiconductor channel layer; the semiconductor channel layer is in contact with the first metal layer and the second metal layer respectively in the groove; and the gate oxide dielectric layer is disposed between the semiconductor channel layer and the gate. A first interface layer and a second interface layer, wherein the first interface layer is located between the first contact layer and the insulating dielectric layer, and the second interface layer is located between the second contact layer and the insulating dielectric layer; the materials of the first interface layer and the second interface layer are the same as the materials of the first contact layer and the second contact layer, and the doping concentration of the materials of the first interface layer and the second interface layer is lower than the doping concentration of the materials of the first contact layer and the second contact layer.

2. The vertical channel transistor structure according to claim 1, characterized in that, The groove is a first groove, the semiconductor channel layer covers the bottom and sidewalls of the first groove to form a second groove, the gate oxide dielectric layer covers the bottom and sidewalls of the second groove to form a third groove, and the gate is disposed in the third groove.

3. The vertical channel transistor structure according to claim 1, characterized in that, The sum of the resistance of the contact surface formed by the first contact layer and the first metal layer and the resistance of the contact surface formed by the first contact layer and the semiconductor channel layer is less than the resistance of the contact surface formed by the first metal layer and the semiconductor channel layer. The sum of the resistance of the contact surface formed by the second contact layer and the second metal layer and the resistance of the contact surface formed by the second contact layer and the semiconductor channel layer is less than the resistance of the contact surface formed by the second metal layer and the semiconductor channel layer.

4. The vertical channel transistor structure according to any one of claims 1-3, characterized in that, If the semiconductor channel layer is a first n-type semiconductor, then the materials of the first contact layer and the second contact layer are first semiconductor materials, the conduction band position of the first semiconductor material is close to the conduction band position of the first n-type semiconductor, and the conductivity of the first semiconductor material is greater than or equal to the conductivity of the first n-type semiconductor. If the semiconductor channel layer is a first p-type semiconductor, then the materials of the first contact layer and the second contact layer are second semiconductor materials, the valence band position of the second semiconductor material is close to the valence band position of the first p-type semiconductor, and the conductivity of the second semiconductor material is greater than or equal to the conductivity of the first p-type semiconductor.

5. The vertical channel transistor structure according to any one of claims 1-3, characterized in that, The materials of the first contact layer and the second contact layer include: indium gallium zinc oxide InGaZnO, indium zinc oxide InZnO, indium tin oxide InSnO, indium oxide In2O3, gallium oxide Ga2O3, indium titanium oxide InTiO or zinc oxide ZnO.

6. The vertical channel transistor structure according to any one of claims 1-3, characterized in that, The materials of the first contact layer and the second contact layer include: highly doped p-type silicon Si, n-type Si, or any combination of p-type silicon Si and n-type Si.

7. The vertical channel transistor structure according to any one of claims 1-3, characterized in that, The first contact layer and the second contact layer are doped semiconductor layers, and the material of the doped semiconductor layer is obtained by doping the material of the semiconductor channel layer.

8. The vertical channel transistor structure according to any one of claims 1-3, characterized in that, The first contact layer, the second contact layer, and the semiconductor channel layer are all P-type semiconductors or all N-type semiconductors; or, The first contact layer and the second contact layer are N-type semiconductors, and the semiconductor channel layer is a P-type semiconductor; or, The first contact layer and the second contact layer are P-type semiconductors, and the semiconductor channel layer is an N-type semiconductor.

9. The vertical channel transistor structure according to any one of claims 1-3, characterized in that, The vertical channel transistor structure is cylindrical, and the stacked structure surrounds the semiconductor channel layer, with the semiconductor channel layer completely located in the vertical groove inside the stacked structure.

10. The vertical channel transistor structure according to any one of claims 1-3, characterized in that, The vertical channel transistor structure is square columnar, the stacked structure includes a first sub-stacked structure and a second sub-stacked structure, the semiconductor channel layer includes a first semiconductor channel layer and a second semiconductor channel layer, and the gate oxide dielectric layer includes a first gate oxide dielectric layer and a second gate oxide dielectric layer. The gate is disposed between the first sub-layer structure and the second sub-layer structure; A first semiconductor channel layer and a first gate oxide dielectric layer are disposed between the first sub-layer structure and the gate, and the first semiconductor channel layer is in contact with the side of the first sub-layer structure. A second semiconductor channel layer and a second gate oxide layer are disposed between the second sub-layer structure and the gate, and the second semiconductor channel layer is in contact with the side of the second sub-layer structure.

11. A vertical channel transistor structure, characterized in that, include: A laminated structure, the laminated structure including a first metal layer, a first contact layer, an insulating dielectric layer, a second contact layer, and a second metal layer; the first contact layer is located between the first metal layer and the insulating dielectric layer, and the second contact layer is located between the second metal layer and the insulating dielectric layer; The stacked structure is provided with a groove that penetrates the second metal layer, the second contact layer, the insulating dielectric layer and the second contact layer, and the groove is at least partially embedded in the first metal layer; The groove contains a semiconductor channel layer, a gate oxide dielectric layer, and a gate. The semiconductor channel layer is in contact with the first metal layer and the second metal layer respectively in the groove, and the gate oxide dielectric layer is disposed between the semiconductor channel layer and the gate. The resistance of the contact surfaces formed between the first contact layer and the second contact layer and the semiconductor channel layer is less than the resistance of the contact surfaces formed between the first metal layer and the second metal layer and the semiconductor channel layer. The materials of the first contact layer and the second contact layer are semiconductor materials with higher conductivity than the semiconductor channel layer; A first interface layer and a second interface layer, wherein the first interface layer is located between the first contact layer and the insulating dielectric layer, and the second interface layer is located between the second contact layer and the insulating dielectric layer; the materials of the first interface layer and the second interface layer are the same as the materials of the first contact layer and the second contact layer, and the doping concentration of the materials of the first interface layer and the second interface layer is lower than the doping concentration of the materials of the first contact layer and the second contact layer.

12. The vertical channel transistor structure according to claim 11, characterized in that, The resistance of the contact surface formed by the first contact layer and the first metal layer, and the contact surface formed by the second contact layer and the second metal layer, is less than the first threshold value.

13. A vertical channel transistor structure, characterized in that, include: Layered structure and semiconductor channel layer, The stacked structure has a groove, and the semiconductor channel layer is disposed in the groove; The stacked structure includes a first metal layer, a second metal layer, and a third metal layer. The third metal layer is located between the first metal layer and the second metal layer. The first interface, the second interface, and the third interface of the third metal layer are wrapped with a first dielectric layer. The first interface is the interface of the third metal layer facing the first metal layer, the second interface is the interface of the third metal layer facing the second metal layer, and the third interface is the interface of the third metal layer facing the semiconductor channel layer. The stacked structure further includes a first contact layer and a second contact layer, wherein the first contact layer is located between the first metal layer and the first dielectric layer, and the second contact layer is located between the second metal layer and the first dielectric layer; The semiconductor channel layer is in contact with the first metal layer and the second metal layer, respectively; The materials of the first contact layer and the second contact layer are semiconductor materials with higher conductivity than the semiconductor channel layer; A first interface layer and a second interface layer, wherein the first interface layer is located between the first contact layer and the first dielectric layer, and the second interface layer is located between the second contact layer and the first dielectric layer; the materials of the first interface layer and the second interface layer are the same as the materials of the first contact layer and the second contact layer, and the doping concentration of the materials of the first interface layer and the second interface layer is lower than the doping concentration of the materials of the first contact layer and the second contact layer.

14. The vertical channel transistor structure according to claim 13, characterized in that, The groove extends through the stacked structure.

15. The vertical channel transistor structure according to claim 13 or 14, characterized in that, The sum of the resistance of the contact surface formed by the first contact layer and the first metal layer and the resistance of the contact surface formed by the first contact layer and the semiconductor channel layer is less than the resistance of the contact surface formed by the first metal layer and the semiconductor channel layer. The sum of the resistance of the contact surface formed by the second contact layer and the second metal layer and the resistance of the contact surface formed by the second contact layer and the semiconductor channel layer is less than the resistance of the contact surface formed by the second metal layer and the semiconductor channel layer.

16. The vertical channel transistor structure according to claim 13 or 14, characterized in that, The structure is cylindrical, and the stacked structure surrounds the semiconductor channel layer, with the semiconductor channel layer completely located within the vertical groove inside the stacked structure.

17. The vertical channel transistor structure according to claim 13 or 14, characterized in that, The structure is a square column, and the stacked structure includes a first sub-stacked structure and a second sub-stacked structure. The semiconductor channel layer is located between the first sub-stacked structure and the second sub-stacked structure, and the semiconductor channel layer is in contact with the side surface of the first sub-stacked structure and the side surface of the second sub-stacked structure, respectively.

18. The vertical channel transistor structure according to claim 13 or 14, characterized in that, The first contact layer and the second contact layer are doped semiconductor layers, and the material of the doped semiconductor layer is obtained by doping the material of the semiconductor channel layer.

19. The vertical channel transistor structure according to claim 13 or 14, characterized in that, The first contact layer, the second contact layer, and the semiconductor channel layer are all P-type semiconductors or all N-type semiconductors; or, The first contact layer and the second contact layer are N-type semiconductors, and the semiconductor channel layer is a P-type semiconductor; or, The first contact layer and the second contact layer are P-type semiconductors, and the semiconductor channel layer is an N-type semiconductor.

20. A method for manufacturing a vertical channel transistor, characterized in that, The method includes: A first metal layer, a first contact layer, a first interface layer, an insulating dielectric layer, a second interface layer, a second contact layer, and a second metal layer are deposited sequentially to form a stacked structure. The layered structure is etched to form a first groove; A semiconductor channel layer is grown in the first groove to form a second groove; A gate oxide dielectric layer is grown in the second groove to form a third groove; The gate is grown in the third groove; The materials of the first contact layer and the second contact layer are semiconductor materials with higher conductivity than the semiconductor channel layer; The first interface layer is located between the first contact layer and the insulating dielectric layer, and the second interface layer is located between the second contact layer and the insulating dielectric layer; the materials of the first interface layer and the second interface layer are the same as the materials of the first contact layer and the second contact layer, and the doping concentration of the materials of the first interface layer and the second interface layer is lower than the doping concentration of the materials of the first contact layer and the second contact layer.

21. The method according to claim 20, characterized in that, After growing the gate in the third groove, the method further includes: The gate, the gate oxide dielectric layer, and the semiconductor channel layer are etched to isolate the vertical channel transistor from other adjacent vertical channel transistors.

22. The method according to claim 20 or 21, characterized in that, The sum of the resistance of the contact surface formed by the first contact layer and the first metal layer and the resistance of the contact surface formed by the first contact layer and the semiconductor channel layer is less than the resistance of the contact surface formed by the first metal layer and the semiconductor channel layer. The sum of the resistance of the contact surface formed by the second contact layer and the second metal layer and the resistance of the contact surface formed by the second contact layer and the semiconductor channel layer is less than the resistance of the contact surface formed by the second metal layer and the semiconductor channel layer.

23. The method according to claim 20 or 21, characterized in that, The materials of the first contact layer and the second contact layer include: indium gallium zinc oxide InGaZnO, indium zinc oxide InZnO, indium tin oxide InSnO, indium oxide In2O3, gallium oxide Ga2O3, indium titanium oxide InTiO or zinc oxide ZnO.

24. The method according to claim 20 or 21, characterized in that, The materials of the first contact layer and the second contact layer include: highly doped p-type silicon Si, n-type Si, or any combination of p-type silicon Si and n-type Si.

25. The method according to claim 20 or 21, characterized in that, The first contact layer and the second contact layer are doped semiconductor layers, and the material of the doped semiconductor layer is obtained by doping the material of the semiconductor channel layer.

26. The method according to claim 20 or 21, characterized in that, When the polarity of the first contact layer and the second contact layer is different from that of the semiconductor in the semiconductor channel layer, the doping concentration of the first contact layer and the second contact layer is higher than that of the semiconductor channel layer.

27. A method for manufacturing a vertical channel transistor, characterized in that, The method includes: A first metal layer, a first contact layer, a first interface layer, an insulating dielectric layer, a second interface layer, a second contact layer, and a second metal layer are deposited sequentially to form a stacked structure. The layered structure is etched to form perforations; A semiconductor channel layer is grown in the perforation; The insulating dielectric layer in the stacked structure is removed by wet etching; A gate oxide dielectric layer and a gate are grown sequentially in the space after the insulating dielectric layer is removed. The materials of the first contact layer and the second contact layer are semiconductor materials with higher conductivity than the semiconductor channel layer; A first interface layer and a second interface layer, wherein the first interface layer is located between the first contact layer and the insulating dielectric layer, and the second interface layer is located between the second contact layer and the insulating dielectric layer; the materials of the first interface layer and the second interface layer are the same as the materials of the first contact layer and the second contact layer, and the doping concentration of the materials of the first interface layer and the second interface layer is lower than the doping concentration of the materials of the first contact layer and the second contact layer.

28. The method according to claim 27, characterized in that, The sum of the resistance of the contact surface formed by the first contact layer and the first metal layer and the resistance of the contact surface formed by the first contact layer and the semiconductor channel layer is less than the resistance of the contact surface formed by the first metal layer and the semiconductor channel layer. The sum of the resistance of the contact surface formed by the second contact layer and the second metal layer and the resistance of the contact surface formed by the second contact layer and the semiconductor channel layer is less than the resistance of the contact surface formed by the second metal layer and the semiconductor channel layer.

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