A laser chip with improved reliability and a preparation process thereof

Abstract

The application provides a laser chip with improved reliability and a preparation process thereof, and aims to solve the technical problem that an edge-emitting laser is prone to end face failure.The laser chip comprises a substrate, the back surface of the substrate is provided with an N electrode, the front surface of the substrate is provided with an epitaxial material, the top layer of the epitaxial material is an ohmic contact layer, the epitaxial material is provided with a waveguide, and the vicinity of the waveguide is a waveguide region; an insulating medium layer is arranged on the surface of the epitaxial material, the waveguide region and the insulating medium layer are provided with a P electrode, but the ohmic contact layer in the waveguide region is not provided with the insulating medium layer, and the P electrode is in contact with the ohmic contact layer; the end surface of the laser chip is provided with an electrode-free area, and the electrode-free area is not provided with the insulating medium layer and the P electrode above the electrode-free area.The application further comprises a preparation method of the laser chip.The electrode-free area is arranged on the end surface of the laser, and the electrode-free area can improve the COD threshold level and improve the reliability.

Description

Technical Field

[0001] This invention belongs to the technical field of laser chips and their fabrication, and particularly relates to a laser chip with improved reliability and its fabrication process. Background Technology

[0002] In 1962, lasing was successfully achieved using semiconductor materials. After numerous improvements, semiconductor lasers have gradually developed into laser sources that are small in size, lightweight, highly efficient, and inexpensive. Currently, semiconductor lasers are widely used in fiber optic communications, data centers, laser printers, laser scanners, laser rangefinders, and lidar.

[0003] Reliability is a key indicator for the application of lasers and a decisive factor in their successful market entry. For edge-emitting lasers (such as DFB and FP), the manufacturing process is complex, and each process can potentially become a point of failure for reliability. Conventional laser chips have an insulating dielectric layer and electrodes covering the edge face. During the manufacturing process, the bar-scraping process can damage the crystal structure of the semiconductor, creating numerous dangling bonds, defect centers, and recombination centers on the edge face. During bar removal, the edge face is exposed to air, causing oxidation and contamination. These problems are among the main reasons for the reduced COD (Catastrophic Optical Damage) threshold and reliability failure of edge-emitting lasers.

[0004] Factors such as bar scratches, oxidation, and contamination lead to the formation of numerous nonradiative recombination centers and defect centers on the laser end face. These centers cause nonradiative recombination of electron-hole pairs or absorption of photons, resulting in an increase in temperature at the cavity surface. This temperature rise causes surface defects to move and localize, and also shrinks the band gap of the surface material, exacerbating photon absorption and further increasing the surface temperature. When the carrier density or photon density reaches a certain level, this process enters a vicious cycle, ultimately leading to irreversible COD (Catalytic Degradation). Therefore, reducing nonradiative recombination centers / defect centers caused by bar scratches, lowering the carrier density at the end face, and reducing the photon density will significantly increase the COD threshold level. Summary of the Invention

[0005] To address the technical problem of edge-emitting lasers being prone to end-face failure, this invention proposes a laser chip with improved reliability and its fabrication process. The fabricated chip has no carrier injection at the end face, thereby improving the COD threshold level and enhancing reliability.

[0006] To achieve the above objectives, the technical solution of the present invention is implemented as follows:

[0007] A laser chip with improved reliability includes a substrate, an N-side electrode on the back side of the substrate, an epitaxial material on the front side of the substrate, an ohmic contact layer on the top layer of the epitaxial material, a waveguide in the epitaxial material, and a waveguide region in the vicinity of the waveguide. An insulating dielectric layer is disposed on the surface of the epitaxial material, and a P-side electrode is disposed on the waveguide region and the insulating dielectric layer. However, no insulating dielectric layer is disposed on the ohmic contact layer in the waveguide region, and the P-side electrode is in contact with the ohmic contact layer. An electrode-free region is provided on the end face of the laser chip, and no insulating dielectric layer or P-side electrode is disposed above the electrode-free region.

[0008] The electrode-free region has a length greater than or equal to 1 μm and less than half the chip length along the chip length direction.

[0009] The electrode-free region is the waveguide region on the end face of the laser chip or the entire end face of the laser chip. The main purpose of the electrode-free region is to ensure that there is no voltage in the end face waveguide region. Therefore, the range of the electrode-free region must include the end face waveguide region. Alternatively, the electrode-free region can be formed by extending arbitrarily from the end face waveguide region to both sides or one side.

[0010] The fabrication method of the above-mentioned laser chip includes the following steps:

[0011] (1) Waveguide patterns are fabricated on the epitaxial material of a wafer using photolithography, and then the epitaxial material under the waveguide patterns is removed by etching to fabricate the waveguide;

[0012] (2) An insulating dielectric layer is deposited on the surface of the epitaxial material with waveguide prepared in step (1);

[0013] (3) In step (2), a window pattern is prepared on the insulating dielectric layer using photolithography. Then, the insulating dielectric layer on the ohmic contact layer in the waveguide region below the window pattern is removed using etching. At the same time, the insulating dielectric layer near the end face of the laser chip is removed by etching to create an electrode-free region.

[0014] (4) Prepare P-side electrodes on the ohmic contact layer and insulating dielectric layer of the wafer in step (3);

[0015] (5) After thinning / polishing the back side of the substrate on which the P-side electrode wafer was prepared in step (4), the N-side electrode is prepared to obtain the laser wafer;

[0016] (6) The laser wafer prepared in step (5) is cleaved to obtain laser bars. The laser bars are then arranged, coated, chip cleaved, tested and screened to obtain laser chips.

[0017] The epitaxial material of the chip in step (1) is either FP epitaxial material or DFB epitaxial material.

[0018] The photoresist used in the photolithography process is either positive or negative photoresist, and the exposure method of the photolithography process is either contact exposure or projection exposure.

[0019] The etching process is either dry etching or wet etching.

[0020] In step (2), the insulating dielectric layer is a silicon oxide layer or a silicon nitride layer.

[0021] In step (3), the chip end face is either AR (Anti Reflection) end, HR (High Reflection) end, or AR end and HR end.

[0022] In step (4), the P-side electrode is prepared by one or a combination of two or more of electron beam evaporation, sputtering or electroplating processes; in step (5), the N-side electrode is prepared by one or a combination of two or more of electron beam evaporation, sputtering or electroplating processes.

[0023] The beneficial effects of this invention are as follows: At the chip end face, only the substrate and epitaxial material exist. During bar cleaving, perfect cleavage can be achieved only along the crystal orientation of the substrate and epitaxial material, unaffected by the insulating dielectric layer and P-side electrodes. This significantly reduces non-radiative recombination centers / defect centers caused by bar cleaving. In the waveguide region of the laser near the chip end face, there is no insulating dielectric layer or electrodes on the upper surface, and no carrier injection occurs near the end face. When the light field passes through this region, there is only optical loss and no optical gain. The carrier density and photon density at the end face are correspondingly reduced, ultimately achieving the goal of improving the COD threshold level and enhancing reliability. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 A top view of the laser chip fabricated for this invention.

[0026] Figure 2 for Figure 1 A cross-sectional view of plane AA in the diagram.

[0027] Figure 3 for Figure 1 A cross-sectional view of the BB plane.

[0028] Figure 4 This is a cross-sectional view after one extension.

[0029] Figure 5 This is a cross-sectional view perpendicular to the grating direction after secondary epitaxy.

[0030] Figure 6 This is a cross-sectional view parallel to the grating direction after waveguide fabrication.

[0031] In the figure: 1. Substrate; 2. Buffer layer; 3. N-type lower confinement layer; 4. Active region with quantum well structure; 5. P-type upper confinement layer; 6. InP-I layer; 7. InGaAsP grating layer; 8. InP-II layer; 9. InP-III layer; 10. Etching stop layer; 11. P-type InP layer; 12. Ohmic contact layer; 13. Insulating dielectric layer; 14. P-surface electrode; 15. Waveguide region; 16. AR end; 17. HR end; 18. Electrode-free region. Detailed Implementation

[0032] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0033] Example 1

[0034] A laser chip with improved reliability, such as Figure 1-3 As shown in Figure 6, the chip is 250 μm long, 250 μm wide, and 100 μm high, including a substrate 1. A DFB-type epitaxial material is disposed on the substrate 1. The epitaxial material, from bottom to top, includes a buffer layer 2 formed by primary epitaxy, an N-type lower confinement layer 3, an active region 4 with a quantum well structure, a P-type upper confinement layer 5, an InP-I layer 6, an InGaAsP grating layer 7, an InP-II layer 8, an InP-III layer 9 formed by secondary epitaxy, an etch stop layer 10, a P-type InP layer 11, and an ohmic contact layer 12. A waveguide is formed in the epitaxial material, and a waveguide region 15 is formed in the epitaxial material. The waveguide region 15 is the laser emission region. After a voltage is applied to the chip, the laser is emitted from the waveguide region 15. An insulating dielectric layer 13 is covered on the upper surface of the epitaxial material. P-side electrodes 14 are provided on the waveguide region 15 and the insulating dielectric layer 13, but no insulating dielectric layer 13 is provided on the ohmic contact layer 12 in the waveguide region 15. The P-side electrodes 14 are in contact with the ohmic contact layer 12. Electrode-free regions 18 are respectively provided on the AR end 16 and HR end 17 of the laser chip. The length of the electrode-free region 18 in the chip length direction is 10μm, and the width is the same as the width of the laser chip. No insulating dielectric layer 13 and P-side electrodes 14 are provided above the electrode-free region 18.

[0035] The method for fabricating the aforementioned laser chip includes the following steps:

[0036] (1) A buffer layer 2, an N-type lower confinement layer 3, an active region with a quantum well structure 4, a P-type upper confinement layer 5, an InP-I layer 6, an InGaAsP grating layer 7, and an InP-II layer 8 are sequentially grown on a wafer substrate 1, as follows: Figure 4 As shown. The grating pattern was fabricated using electron beam lithography. Dry etching was used to etch the InGaAsP grating layer 7 and the InP-II layer 8, ensuring etching reached the InGaAsP grating layer 7 without over-etching. The InGaAsP layer 7 was etched using an etchant with a volume ratio of 1:1:20 of H2SO4, H2O2, and H2O, with etching stopping at the upper surface of the InP-I layer 6. Secondary epitaxial growth was then performed on the InP-III layer 9, the etch-stop layer 10, the P-type InP layer 11, and the ohmic contact layer 12. Figure 5 As shown. A layer of photoresist is coated onto the epitaxial material using a spin coating process. A waveguide pattern is obtained on the photoresist through contact exposure, development, and fixing processes. The P-type InP layer 11 and the ohmic contact layer 12 beneath the waveguide pattern are etched using an etching process, ensuring that the etching reaches the P-type InP layer 11 without over-etching. The P-type InP layer 11 is etched using a 1:3 volume ratio HCl:H3PO4 etchant, and the etching stops on the surface of the etch stop layer 10. A waveguide is fabricated on the epitaxial material, as shown. Figure 6 As shown.

[0037] (2) A 350 nm thick SiO2 insulating dielectric layer 13 is deposited on the surface of the epitaxial material using PECVD process.

[0038] (3) A layer of photoresist is coated onto the SiO2 insulating dielectric layer 13 using a spin coating process. The photoresist on the SiO2 insulating dielectric layer 13 on the chip scribe line is removed by contact exposure, development, and fixing processes. The photoresist on the SiO2 insulating dielectric layer 13 on the ohmic contact layer 12 in the waveguide region 15 is also removed. The photoresist on the electrodeless region 18 on the laser chip end face is removed, and a window pattern is obtained on the photoresist. The SiO2 insulating dielectric layer 13 below the window pattern is removed by ICP etching, exposing the ohmic contact layer 12 below the insulating dielectric layer 13.

[0039] (4) Electrode patterns are prepared on the photoresist through processes such as spin coating, contact exposure, development and fixing on the ohmic contact layer 12 and the insulating dielectric layer 13, but no electrode patterns are prepared on the electrode-free area 18; Ti-Pt-Au metal is obtained by electron beam evaporation in the electrode pattern; P-side electrode 14 is obtained by stripping process; finally, P-side electrode 14 is thickened by 1.5 μm by electroplating process.

[0040] (5) After thinning / polishing the back side of substrate 1, AuGeNi alloy is prepared on the back side of substrate 1 by sputtering process to form N-face electrode, thereby obtaining laser wafer.

[0041] (6) Cleave along the specified end face position on the laser wafer to obtain laser bars; then arrange the bars and coat them, coating AR film and HR film on the front and rear end faces of the laser chip respectively, and cleave the chip along the chip cleaving path without SiO2 insulating dielectric layer 13. Use a chip testing machine to perform performance testing on the laser chip and remove laser chips with poor performance; use AOI equipment to perform appearance judgment on the laser chip and remove laser chips with poor appearance; finally, obtain laser chips that meet the requirements in terms of both performance and appearance.

[0042] Example 2

[0043] A laser chip with improved reliability, such as Figure 2-4 As shown, an electrodeless region 18 is provided only at the AR end 16 of the laser chip. The length of the electrodeless region 18 in the chip length direction is 10μm. The electrodeless region 18 coincides with the waveguide region 15 on the end face. No insulating dielectric layer 13 and P-side electrode 14 are provided above the electrodeless region 18.

[0044] Example 3

[0045] A laser chip with improved reliability, such as Figure 1-3 As shown, the difference from Example 2 is that the length of the electrodeless region 18 in the chip length direction is 100 μm.

[0046] Example 4

[0047] A laser chip with improved reliability, such as Figure 1-3 As shown, the chip is 250μm long, 250μm wide, and 80μm high, and includes a substrate 1. An FP-type epitaxial material is disposed on the substrate 1. The epitaxial material includes, from bottom to top, a buffer layer generated by a single epitaxial layer, an N-type lower confinement layer, an active region with a quantum well structure, a P-type upper confinement layer, an etch stop layer, a P-type InP layer 11, and an ohmic contact layer 12. A waveguide is formed in the epitaxial material, and the waveguide forms a waveguide region 15 in the epitaxial material. The waveguide region 15 is the laser emission region. An insulating dielectric layer 13 covers the upper surface of the epitaxial material. P-side electrodes 14 are provided on the waveguide region 15 and the insulating dielectric layer 13, but no insulating dielectric layer 13 is provided on the ohmic contact layer 12 in the waveguide region 15. The P-side electrodes 14 are in contact with the ohmic contact layer 12. Electrode-free regions 18 are respectively provided on the AR end 16 and HR end 17 of the laser chip. The length of the electrode-free region 18 in the chip length direction is 10μm, and the width is the same as the width of the laser chip. No insulating dielectric layer 13 and P-side electrodes 14 are provided above the electrode-free region 18.

[0048] The method for fabricating the aforementioned laser chip includes the following steps:

[0049] (1) A buffer layer, an N-type lower confinement layer, an active region with a quantum well structure, a P-type upper confinement layer, an etch stop layer, a P-type InP layer 11, and an ohmic contact layer 12 are sequentially grown on a wafer substrate 1. A layer of photoresist is coated on the epitaxial material using a spin coating process. A waveguide pattern is obtained on the photoresist through contact exposure, development, fixing, and other processes. The P-type InP layer 11 and the ohmic contact layer 12 below the waveguide pattern are etched using an etching process to ensure that the P-type InP layer 11 is etched but not over-etched. The P-type InP layer 11 is etched using an HCl:H3PO4 etch solution with a volume ratio of 1:3. The etching stops on the upper surface of the etch stop layer 10, and a waveguide is fabricated on the epitaxial material.

[0050] (2) A 350 nm thick SiO2 insulating dielectric layer 13 is deposited on the surface of the epitaxial material using PECVD process.

[0051] (3) A layer of photoresist is coated onto the SiO2 insulating dielectric layer 13 using a spin coating process. The photoresist on the SiO2 insulating dielectric layer 13 on the chip scribe line is removed by contact exposure, development, and fixing processes. The photoresist on the SiO2 insulating dielectric layer 13 on the ohmic contact layer 12 in the waveguide region 15 is also removed. The photoresist on the electrodeless region 18 on the laser chip end face is removed, and a window pattern is obtained on the photoresist. The SiO2 insulating dielectric layer 13 below the window pattern is removed by ICP etching, exposing the ohmic contact layer 12 below the insulating dielectric layer 13.

[0052] (4) Electrode patterns are prepared on the photoresist through processes such as spin coating, contact exposure, development and fixing on the ohmic contact layer 12 and the insulating dielectric layer 13, but no electrode patterns are prepared on the electrode-free area 18; Ti-Pt-Au metal is obtained by electron beam evaporation in the electrode pattern; P-side electrode 14 is obtained by stripping process; finally, P-side electrode 14 is thickened by 1.5 μm by electroplating process.

[0053] (5) After thinning / polishing the back side of substrate 1, AuGeNi alloy is prepared on the back side of substrate 1 by sputtering process to form N-face electrode, thereby obtaining laser wafer.

[0054] (6) Cleave along the specified end face position on the laser wafer to obtain laser bars; then arrange the bars and coat them, coating AR film and HR film on the front and rear end faces of the laser chip respectively, and cleave the chip along the chip cleaving path without SiO2 insulating dielectric layer 13. Use a chip testing machine to perform performance testing on the laser chip and remove laser chips with poor performance; use AOI equipment to perform appearance judgment on the laser chip and remove laser chips with poor appearance; finally, obtain laser chips that meet the requirements in terms of both performance and appearance.

[0055] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A laser chip with improved reliability, comprising a substrate (1), an N-sided electrode on the back side of the substrate, an epitaxial material on the front side of the substrate, the top layer of the epitaxial material being an ohmic contact layer (12), characterized in that, The epitaxial material contains a waveguide, and the area near the waveguide is the waveguide region (15); an insulating dielectric layer (13) is provided on the surface of the epitaxial material, and P-side electrodes are provided on the waveguide region and the insulating dielectric layer, but the insulating dielectric layer (13) is not provided on the ohmic contact layer (12) in the waveguide region (15), and the P-side electrodes are in contact with the ohmic contact layer (12); an electrode-free region (18) is provided on the end face of the laser chip, and the insulating dielectric layer (13) and P-side electrodes are not provided above the electrode-free region (18); The electrode-free region (18) is the waveguide region (15) on the end face of the laser chip or the entire end face of the laser chip. The method for fabricating the laser chip comprises the following steps: (1) Waveguide patterns are fabricated on the epitaxial material of a wafer using photolithography, and then the epitaxial material under the waveguide patterns is removed by etching to fabricate the waveguide; (2) An insulating dielectric layer (13) is deposited on the surface of the epitaxial material with waveguide prepared in step (1). (3) In step (2), a window pattern is prepared on the insulating dielectric layer (13) using photolithography. Then, the insulating dielectric layer (13) on the ohmic contact layer (12) in the waveguide region (15) below the window pattern is removed by etching. At the same time, the insulating dielectric layer (13) near the end face of the laser chip is removed by etching to create an electrode-free region (18). (4) A P-side electrode (14) is fabricated on the ohmic contact layer (12) and insulating dielectric layer (13) of the wafer in step (3). (5) After thinning / polishing the back side of the substrate (1) on which the P-side electrode (14) wafer was prepared in step (4), the N-side electrode is prepared to obtain the laser wafer; (6) Use the laser wafer prepared in step (5) to prepare a laser chip.

2. The laser chip with improved reliability according to claim 1, characterized in that, The electrodeless region (18) has a length greater than or equal to 1 μm and less than half the length of the chip in the chip length direction.

3. The laser chip according to claim 2, characterized in that, The epitaxial material of the chip in step (1) is either FP epitaxial material or DFB epitaxial material.

4. The laser chip according to claim 3, characterized in that, The photoresist used in the photolithography process is either positive or negative photoresist, and the exposure method of the photolithography process is either contact exposure or projection exposure.

5. The laser chip according to claim 4, characterized in that, The etching process is either dry etching or wet etching.

6. The laser chip according to claim 5, characterized in that, In step (2), the insulating dielectric layer (13) is a silicon oxide layer or a silicon nitride layer.

7. The laser chip according to claim 6, characterized in that, In step (3), the chip end face is AR end (16) and HR end (17), or AR end (16) and HR end (17).

8. The laser chip according to claim 7, characterized in that, In step (4), the P-side electrode (14) is prepared by one or a combination of two or more of electron beam evaporation, sputtering or electroplating processes; in step (5), the N-side electrode is prepared by one or a combination of two or more of electron beam evaporation, sputtering or electroplating processes.

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