Converter circuit and corresponding method of testing a converter circuit

Abstract

The present disclosure relates to a converter circuit and a corresponding method of testing the converter circuit. The switching DC-DC converter circuit comprises a switching stage having an input node receiving an input voltage and an output node generating an output voltage. The converter comprises a feedback loop circuit arrangement coupled to the output node of the switching stage to generate a control signal of the converter circuit at the respective output node dependent on a difference between the output voltage and a reference voltage. The converter comprises a test loop circuit arrangement arranged between an output node of the feedback loop circuit arrangement and the output node of the switching stage. When enabled, the test loop provides a current to the output node of the switching stage or sinks a current from the output node of the switching stage dependent on a value of the control signal of the converter circuit. The feedback loop circuit arrangement is calibrated during a test phase of the switching DC-DC converter circuit.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Italian Patent Application No. 102022000005477, filed on March 21, 2022, the contents of which are incorporated herein by reference in their entirety to the fullest extent permitted by law. Technical Field

[0003] This disclosure relates to DC-DC converter circuits and methods for testing DC-DC converter circuits (e.g., integrated circuit testing, IC testing) to fine-tune and / or calibrate them. For example, one or more embodiments can be applied to power management integrated circuits (PMICs) for active-matrix organic light-emitting diode (AMOLED) display drivers. Background Technology

[0004] DC-DC converters are used in a variety of applications to generate appropriate supply voltages for use by complex systems to operate and provide the desired performance. In many of these applications, it is expected that the DC-DC converter will provide an accurate output voltage to meet the application specifications. Therefore, the expected operating point (e.g., expected output voltage) of the DC-DC converter will be considered during the converter design phase, especially taking into account the typical statistical and / or systematic errors of the integrated electronics. Dedicated trimmer circuitry can be implemented in the DC-DC converter to compensate for such errors during the IC testing phase performed during the IC manufacturing process (e.g., before dicing and packaging, or even on the final sample that has already been diced and packaged).

[0005] Therefore, during the IC testing phase, fine-tuning circuitry implemented in the integrated circuit is set up to meet the chip's expected performance. However, in many automated test setups (e.g., automated test equipment (ATE)), testing DC-DC converters operating in a closed loop may be impossible or inconvenient, for example, due to instability issues that may arise from non-optimized ATE connections (e.g., due to board parasitic effects and other non-ideals), and / or due to noise that may affect ATE measurements, and / or due to the excessive time required to perform accurate ATE measurements on switching DC-DC converters.

[0006] Traditionally, known methods for measuring the accuracy of DC-DC converters during the testing phase and thus fine-tuning the converter rely on implementing a closed-loop architecture on an automated test board and operating the converter in normal regulation mode (i.e., as it will operate in the final application) during testing. This approach increases the complexity and cost of the test board used and can still fail to get the DC-DC converter operating under stable conditions. Furthermore, even to achieve stable operation of the converter, the output voltage may exhibit ripple, which needs to be filtered to measure the accurate value of the regulated output voltage. Ripple filtering is typically achieved by applying long-term averaging, resulting in excessively long test times, which increases testing costs, especially with DC-DC converters having multiple outputs under test.

[0007] Another known method can be used to measure the accuracy of a DC-DC converter and thus adjust the converter itself, but this is limited to situations where the converter can operate under pulse-skipping conditions. This method relies on operating the converter in open-loop conditions (e.g., without an inductor) during testing, forcing the output voltage to a value close to the desired regulation value, and analyzing the behavior of the converter's switching nodes (e.g., sensing the voltage at the switching nodes). If the output voltage is forced to a value below the desired setpoint (expected value), the switching nodes exhibit switching activity because the DC-DC converter attempts to increase the output voltage but fails due to the lack of an external inductor. If the output voltage is forced to a value above the desired setpoint, the switching nodes do not exhibit switching activity because the DC-DC converter enters pulse-skipping operating mode. Therefore, by applying a ramp voltage signal at the converter's output node, the voltage value at which the converter stops switching can be detected and estimated as the accurate converter output value. However, this test method is not applicable to all DC-DC converters (e.g., DC-DC converters operating in forced continuous conduction mode (CCM) will not exhibit this behavior). In addition, this testing method involves applying a slow ramp to improve measurement accuracy, and thus also results in excessively long testing times, which increases testing costs, especially in the case of DC-DC converters with multiple outputs to be tested.

[0008] Therefore, there is a need in the art to provide improved DC-DC converters and related testing methods that make the testing phase easier, faster, and / or more convenient.

[0009] There is also a need in this field to help provide such improved DC-DC converters and related testing methods. Summary of the Invention

[0010] One or more embodiments relate to DC-DC converter circuits.

[0011] One or more embodiments relate to corresponding methods for testing DC-DC converter circuits.

[0012] In one or more embodiments, a switching DC-DC converter circuit includes a switching stage having an input node configured to receive an input voltage and an output node configured to generate an output voltage. The converter includes a feedback loop circuit arrangement coupled to the output node of the switching stage and configured to generate a control signal for the converter circuit at the respective output node as a function of the difference between the output voltage and a reference voltage. The converter includes a test loop circuit arrangement disposed between the output node of the feedback loop circuit arrangement and the output node of the switching stage. The test loop circuit arrangement is configured, when enabled, to supply current to or draw current from the output node of the switching stage based on the value of the control signal for the converter circuit. The feedback loop circuit arrangement is calibrable (e.g., fine-tunable) during the testing phase of the switching DC-DC converter circuit.

[0013] Therefore, one or more embodiments facilitate the testing and calibration of DC-DC converter circuits.

[0014] In one or more embodiments, the test loop circuit device includes one or more enable switches configured to selectively couple the test loop circuit device to the output node of the feedback loop circuit device and / or the output node of the switching stage. The test loop circuit device is enabled by turning on the one or more enable switches and disabled by turning off the one or more enable switches.

[0015] In one or more embodiments, the test loop circuitry is permanently coupled between the output node of the feedback loop circuitry and the output node of the switching stage. The test loop circuitry is enabled and disabled based on a test mode signal.

[0016] In one or more embodiments, the test loop circuit arrangement includes a first transistor whose control terminal is coupled to the output node of the feedback loop circuit arrangement to receive a control signal, such that the current flowing through the first transistor depends on the control signal. The test loop circuit arrangement includes a current-to-voltage conversion circuit configured to generate a transistor control voltage for controlling an output transistor, the transistor control voltage depending on the current flowing through the first transistor. The test loop circuit arrangement includes an output transistor coupled to the output node of a switching stage. The output transistor is configured to receive the transistor control voltage at a corresponding control terminal and supply current to the output node of the switching stage or absorb current from the output node of the switching stage, depending on the value of the transistor control voltage.

[0017] In one or more embodiments, the first transistor includes a p-channel MOS transistor having a source terminal coupled to a first power supply voltage rail and a gate terminal coupled to an output node of a feedback loop circuit arrangement to receive a control signal. The current-to-voltage conversion circuit includes a current mirror circuit having a mirror input node coupled to a drain terminal of the first transistor and a mirror output node coupled to a first terminal of a resistor, the resistor having a second terminal coupled to a second power supply voltage rail. The output transistor includes a p-channel MOS transistor with its source terminal coupled to the second power supply voltage rail, its gate terminal coupled to the first terminal of the resistor, and its drain terminal coupled to the output node of the switching stage. The output transistor is configured to provide current to the output node of the switching stage.

[0018] In one or more embodiments, the first power supply voltage rail is an internal power supply voltage rail of the converter circuit, and the second power supply voltage rail is configured to receive the input voltage of the converter circuit.

[0019] In one or more embodiments, the first transistor includes an n-channel MOS transistor having a source terminal coupled to ground and a gate terminal coupled to the output node of a feedback loop circuit arrangement to receive a control signal. The current-to-voltage conversion circuit includes a resistor having a first terminal coupled to the drain terminal of the first transistor and a second terminal coupled to a power supply voltage rail. The output transistor includes an n-channel MOS transistor having a source terminal coupled to ground, a gate terminal coupled to the first terminal of the resistor, and a drain terminal coupled to the output node of the switching stage. The output transistor is configured to draw current from the output node of the switching stage.

[0020] In one or more embodiments, the feedback loop circuit arrangement includes: a feedback voltage divider circuit coupled to the output node of the switching stage and configured to generate a feedback voltage that is voltage partitioning dependent on the output voltage; and an error amplifier configured to amplify the difference between the feedback voltage and a reference voltage to generate a control signal. The offset voltage of the error amplifier and / or the reference voltage of the error amplifier are calibrable (e.g., fine-tunable) during the testing phase of the switching DC-DC converter circuit.

[0021] In one or more embodiments, the feedback voltage divider circuit includes: a digital-to-analog converter circuit configured to convert a digital signal into an analog voltage signal; a buffer circuit configured to receive the analog voltage signal output from the digital-to-analog converter circuit and generate a buffered analog voltage signal; and a voltage ladder circuit disposed between the output node of the buffer circuit and the output node of the switching stage, and configured to generate a feedback voltage at its intermediate node. The offset voltage of the buffer circuit is calibrable (e.g., fine-tunable) during the testing phase of the switching DC-DC converter circuit.

[0022] In one or more embodiments, the feedback voltage divider circuit includes a voltage ladder circuit arranged between the output node of the switching stage and the ground node, and configured to generate a feedback voltage at its intermediate node.

[0023] In one or more embodiments, the switching DC-DC converter circuit further includes a voltage ramp generation circuit arrangement configured to generate a ramp signal, and a comparator circuit configured to compare the ramp signal with a control signal to generate a pulse-width modulated signal for controlling the switching activity of the switching stage. Optionally, the voltage ramp generation circuit arrangement includes: a ramp generator circuit configured to generate a basic ramp signal; a current sensing circuit configured to sense current flowing through one or more switches of the switching stage and generate a signal indicating the sensed current; and an adder circuit configured to add the basic ramp signal and the signal indicating the sensed current to generate the ramp signal.

[0024] In one or more embodiments, a method for testing a switching DC-DC converter circuit according to one or more embodiments includes the following steps:

[0025] - The switching DC-DC converter circuit is set to test operation mode by blocking the switching activity of the switching stage and enabling the test loop circuit device;

[0026] - Through the test loop circuit device, current is supplied to or drawn from the output node of the switching stage according to the value of the control signal of the converter circuit;

[0027] - Draw current from the output node of the switching stage or supply current to the output node of the switching stage via an external current generator device;

[0028] -Sense the value of the output voltage generated at the output node of the conversion stage; and

[0029] - Calibrate one or more electronic components of the feedback loop circuit device until the desired output voltage is generated at the output node of the switching stage.

[0030] In one or more embodiments, the method includes calibrating the offset voltage of the error amplifier and / or the reference voltage of the error amplifier until a desired output voltage is generated at the output node of the switching stage.

[0031] In one or more embodiments, the method includes calibrating the offset voltage of the error amplifier and / or the offset voltage of the buffer circuit until a desired output voltage is generated at the output node of the switching stage. Attached Figure Description

[0032] One or more embodiments will now be described by way of example with reference to the accompanying drawings, wherein:

[0033] Figure 1 This is an example of a circuit block diagram for a conventional DC-DC buck-boost converter device;

[0034] Figure 2 This is an exemplary circuit block diagram of a DC-DC buck-boost converter device including an auxiliary circuit for testing, according to one or more embodiments of the present disclosure;

[0035] Figure 3 This is a circuit block diagram illustrating exemplary implementation details of a DC-DC buck-boost converter device including an auxiliary circuit for testing, according to one or more embodiments of this disclosure; and

[0036] Figure 4 This is a circuit block diagram illustrating exemplary implementation details of a DC-DC boost converter device including an auxiliary circuit for testing, according to one or more embodiments of this disclosure. Detailed Implementation

[0037] In the following description, one or more specific details are shown to provide a thorough understanding of examples of embodiments described herein. Embodiments may be obtained without one or more specific details, or by utilizing other methods, components, materials, etc. In other instances, known structures, materials, or operations have not been shown or described in detail so as not to obscure certain aspects of the embodiments.

[0038] References to "an embodiment" or "one embodiment" within the framework of this specification are intended to indicate that a particular configuration, structure, or feature described with respect to that embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in one embodiment" that may appear at one or more points in this specification do not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, a particular configuration, structure, or feature may be combined in any suitable manner.

[0039] The headings / references used herein are provided for convenience only and are not intended to limit the scope of protection or the scope of the embodiments.

[0040] In the accompanying drawings, unless the context otherwise requires, the same parts or elements are indicated by the same reference numerals / numbers, and for the sake of brevity, the corresponding descriptions will not be repeated.

[0041] Through the detailed description of exemplary embodiments, first refer to Figure 1 , Figure 1 This is an exemplary circuit block diagram of a DC-DC converter device 1, particularly a buck-boost DC-DC converter including a current control feedback loop. Figure 1 The DC-DC converter 1 illustrated includes a switching stage HB (e.g., a half-bridge circuit) which has a configuration to receive an input voltage V. IN The input node is configured to generate the output voltage V. OUT The output node. For example, the switching stage HB may include a first high-side switch HS1 coupled between the input node and the switching node LX, and a first low-side switch LS1 coupled between the switching node LX and the output node. The switching stage HB may also include a second high-side switch HS2 coupled between the input node and the switching node LX, and a second low-side switch LS2 coupled between the switching node LX and the output node, for example, in cases where the DC-DC converter 1 involves dynamic control of the switching stage HB to adapt to different operating conditions. Figure 1 As shown, switches HS1, HS2, LS1, and LS2 may include (power) transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), such as n-channel MOS transistors. For example, when the DC-DC converter chip 1 is mounted on a printed circuit board (PCB) in the final application, an inductor L (e.g., an external inductor) may be coupled between the switch node LX and the ground node GND.

[0042] like Figure 1 As illustrated, the DC-DC converter 1 may further include a ramp generator circuit 12, a current sensing circuit 14 coupled to one or more high-side switches of the switching stage HB (e.g., configured to sense current flowing through high-side switches HS1 and / or HS2), and a circuit configured to sum the output signals from the ramp generator circuit 12 and the current sensing circuit 14 to generate a ramp signal V. SUM Adder node 15.

[0043] like Figure 1 As shown, the DC-DC converter 1 may further include a feedback voltage divider circuit 16 and an error amplifier 18. The feedback voltage divider circuit 16 is coupled to the output node of the switching stage HB and is configured to generate an indication output voltage V. OUT (For example, with output voltage V) OUT (proportional) feedback voltage VFB Error amplifier 18 has a configuration to receive reference voltage V REF The first input is configured to receive feedback voltage V from circuit 16. FB To generate the control voltage V of DC-DC converter 1 C The second input.

[0044] like Figure 1 As shown, the DC-DC converter 1 may also include a comparator circuit 20 (e.g., a voltage comparator) configured to convert the ramp signal V SUM With control signal V C A comparison is made to generate a pulse width modulated signal P for controlling the switching activity of the switching stage HB. The DC-DC converter 1 may further include: a digital circuit 22 configured to receive the PWM signal P from the comparator 20 and generate a high-side activation signal and a low-side activation signal for the switching stage HB; and a driver circuit 10 coupled to the digital circuit 22 and the switching stage HB and configured to generate drive signals VHS1, VHS2, VLS1, VLS2 for driving the commutation of switches HS1, HS2, LS1, LS2 according to the received high-side and low-side activation signals.

[0045] Figure 1 Therefore, this is an example of a peak current feedback loop for DC-DC converter 1, which is suitable for testing according to one or more of the known methods previously discussed.

[0046] To mitigate or overcome one or more drawbacks of the known test architectures discussed earlier, one or more converter embodiments may rely on providing an auxiliary loop (e.g., a linear loop) within the converter architecture for testing purposes. Such an auxiliary loop can facilitate measuring the accuracy of the DC-DC converter and / or applying fine-tuning procedures during the testing phase in a simpler, easier, and / or faster manner. In particular, providing an auxiliary loop allows for test procedures that do not rely on the results of difficult and / or unreliable measurements performed under switching conditions.

[0047] For example, Figure 2 This is an exemplary circuit block diagram of a DC-DC converter device 2, particularly a buck-boost DC-DC converter, including, as shown in the reference... Figure 1The discussion focuses on the main feedback loop and the auxiliary loop 24 used for fine-tuning during the testing phase of the converter integrated circuit. For example, the auxiliary loop 24 can be positioned between the output of the error amplifier 18 and the output node of the switching stage HB. During normal operation of the DC-DC converter 2 (e.g., when implementing the converter 2 in the final application), the auxiliary loop 24 remains inactive (e.g., disconnected) so that it does not affect the normal operation of the converter 2 and does not increase power consumption. For example, the auxiliary loop 24 can be connected via one or more electronic switches (in... Figure 2 (Not visible in 3 and 4, but their design and implementation can be provided by those skilled in the art) Disconnected from the output of error amplifier 18 and / or from the output node of switching stage HB; additionally or alternatively, auxiliary circuit 24 may remain connected to error amplifier 18 and / or switching stage HB, but may be deactivated or turned off. Conversely, during the test phase, as Figure 2 The auxiliary loop 24 is connected as shown, and the auxiliary loop 24 is enabled to properly resolve the linear loop test method, during which the switching activity of the main feedback loop of the DC-DC converter 2 is kept suspended (e.g., paused, blocked, disabled, or jammed). For example, the converter 2 can be kept suspended by disabling the converter clock to stop the switching activity, and / or by disabling one or more control circuits of the DC-DC converter, such as a comparator (e.g., comparator 20) or a digital core (e.g., digital circuit 22).

[0048] As an example, Figure 2 A possible implementation of the feedback voltage divider circuit 16 is also shown. For example... Figure 2 As illustrated, circuit 16 may include digital-to-analog converter circuit 161 (e.g., a 7-bit DAC converter) configured to receive a reference voltage V. REF_DAC and digital signal SET (e.g., 7-bit signal), and equal to V REF_DAC The output produces an analog voltage V corresponding to the value of the digital signal SET (e.g., proportional to the signal SET) across its entire range. DAC Circuit 16 may further include a buffer circuit 162, which is coupled to the output of DAC circuit 161 and configured to receive the analog signal V therefrom. DAC To generate a buffered analog voltage V TOP The voltage ladder is configured to receive an analog voltage V. TOP The first terminal is configured to receive the converter output voltage V. OUT To generate a feedback voltage V at the intermediate node of the step. FBThe second end. For example, the voltage step can be a resistive step, which includes a first resistor coupled between the output of buffer 162 and the feedback input of error amplifier 18, and a second resistor coupled between the feedback input of error amplifier 18 and the output of switching stage HB of converter 2.

[0049] As an example, Figure 2 A pulse-skipping circuit that can be implemented in the DC-DC converter 2 is also shown. For example, the pulse-skipping circuit may include a skip comparator 26 (e.g., a comparator with hysteresis) configured to switch the control voltage V C With reference voltage V REF_SKIP The comparison is performed to generate a jumping signal S that is fed to the digital circuit 22.

[0050] Figure 3 During the testing phase Figure 2 An exemplary circuit block diagram of some components of the buck-boost DC-DC converter 2 is shown. Specifically, Figure 2 This is an example of a possible implementation of the auxiliary loop circuit device 24. The auxiliary loop circuit device 24 may include a circuit arranged to provide (e.g., internally) a power supply voltage V. DD A first current line between the (e.g., internal) power supply voltage rail and ground GND. The first current line may include a series-coupled p-channel MOS transistor Q1 and an n-channel MOS transistor Q2. Transistor Q1 has a connection to the power supply voltage rail V. DD The source terminal is coupled (e.g., via a closed switch not visible in the attached diagram) to the output of error amplifier 18 to receive the control voltage V. C The transistor Q2 has a source terminal coupled to ground GND and a gate terminal coupled to its drain terminal (i.e., it is diode-connected). The auxiliary circuit arrangement 24 may include a source terminal provided with a power supply voltage V. INA The second current line between the power supply voltage rail and ground (GND). In one or more embodiments, the power supply voltage V... INA It can be compared with the converter input voltage V IN Same. Or, power supply voltage V INA It can be connected to the converter's internal power supply voltage V DD The same applies. The second current flow line may include a series-coupled resistor R1 and an n-channel MOS transistor Q3. Resistor R1 is coupled to the power supply voltage rail V. INAThe first terminal of transistor Q2 and the second terminal of transistor Q3 are coupled to the drain terminal of transistor Q3. Transistor Q3 has a source terminal coupled to ground GND and a gate terminal coupled to the gate terminal of transistor Q2, such that transistors Q2 and Q3 form a current mirror, wherein the current flowing through transistor Q2 is mirrored through transistor Q3. The auxiliary loop circuit device 24 may include a p-channel MOS transistor Q4, which is disposed on the power supply voltage rail V. INA and the generated voltage V OUT Between the output nodes of the switching stage HB. Specifically, transistor Q4 can have coupling to the supply voltage rail V. INA The source terminal is coupled to the drain terminal of the output node of the switching stage HB, and the gate terminal is coupled to the node intermediate resistor R1 and the transistor Q3.

[0051] like Figure 3 As shown, during the testing phase of converter 2, an external current source 30 (or an equivalent external voltage source with a series-coupled resistor) is connected to the output node of DC-DC converter 2 to draw current I from it, for example, using external hardware available in an automated test apparatus. LOAD External capacitor C OUT It can also be connected between the output node of converter 2 and ground (GND). Therefore, during testing, current I is drawn from the output node of converter 2. LOAD .

[0052] It should also be noted that, in cases such as Figure 3 In one or more embodiments shown, the reference input of the error amplifier 18 may be coupled to ground GND (e.g., a reference voltage V). REF It can be ground voltage, such as 0V.

[0053] In essence, during the testing phase of converter 2, the auxiliary loop circuit device 24 is connected between the output node of error amplifier 18 and the output node of switching stage HB (e.g., via one or more electronic switches not visible in the accompanying drawings) and is operable as discussed below. When the test mode is enabled (e.g., as a function of the value of the test mode signal) and the external current I... LOAD When forced by the ATE, a loop is provided, which includes a feedback voltage divider circuit 16 with corresponding reference voltage generation circuitry (i.e., DAC161 and buffer 162), an error amplifier 18, and an auxiliary loop 24. The auxiliary loop 24 receives the control voltage V generated by the error amplifier 18. C As its input signal, the conductivity of transistor Q1 (e.g., its on-off state) is therefore determined according to the control voltage V. C Modulation is achieved by adjusting the voltage V. Furthermore, the current flowing through transistors Q1 and Q2 is determined by the voltage V. CThis is used for modulation. Since the current is mirrored and forced to flow through transistor Q3 and resistor R1, the gate voltage of transistor Q4 also depends on voltage V. C Modulation is achieved by adjusting the voltage V. Furthermore, the current flowing through transistor Q4 and injected into the output node of the switching stage HB is also modulated according to the voltage V. C It is modulated. Therefore, the circuit will output voltage V. OUT Adjusted to the selected value, and in a steady state, the external current I... LOAD The current will flow through transistor Q4. Under these conditions, the circuit blocks involved in the loop (i.e., feedback divider circuit 16 and error amplifier 18) are the same blocks that also operate during normal operation of the DC-DC converter 2. Therefore, the contribution of the inaccuracies to the converter 2 caused by circuits 16 and 18 is considered during the testing phase, while the additional inaccuracies caused by auxiliary circuit 24 can be ignored because circuit block 24 is arranged downstream of error amplifier 18, which typically introduces a high gain (e.g., 60dB to greater than 100dB), such that circuit 24 affects the output voltage V. OUT The contribution of the value is essentially negligible. During the test, the external capacitor C can be selected (e.g., adjusted). OUT The capacitance and external current I LOAD The value is used to ensure the stability of the loop.

[0054] In one or more embodiments, the fine-tuning process performed during testing of the DC-DC converter 2 may include enabling the auxiliary loop 24 as discussed above (e.g., by closing...). Figure 2 The invisible switches in 3 and 4 connect the loop circuit device 24 to the error amplifier 18, while transistor Q4 can be permanently connected to the output node of the switching stage HB. Then, the available fine-tuning point in the main control loop of converter 2 is set (e.g., adjusted) to adjust the output voltage V. OUT The value is adjusted to the desired value. For example, error amplifier 18 can be fine-tuned by calibrating its offset in an appropriate manner, and / or buffer circuit 162 can be fine-tuned by calibrating its offset in an appropriate manner. Therefore, the fine-tuning process disclosed herein takes into account all circuit blocks (16 and 18) that affect the accuracy of converter 2 during normal operation (i.e., under application conditions), so the fine-tuned output value V OUT The output value will be as close as possible to the value that occurs during normal operation of converter 2. Alternatively, the output voltage V can be adjusted with a slightly different target value if any shift is required. OUT The value is set so that the normal operation of the converter 2, which includes optional shifting, can be arranged.

[0055] Figure 4 This is an exemplary circuit block diagram of some components of the boost DC-DC converter 4. Specifically, Figure 4 This is an example of a possible implementation of the auxiliary loop circuit device 24', which can be positioned between the output node of the error amplifier 18 and the output node of the switching stage HB of the boost DC-DC converter. For simplicity, in Figure 4 The diagram does not show the specific arrangement of certain components of the boost converter 4 (e.g., the high-side switch, low-side switch, and external inductor in the switching stage). The auxiliary circuit arrangement 24' may include components arranged to provide (e.g., internally) the power supply voltage V. DD The current path between the (e.g., internal) power supply voltage rail and ground GND. This current path may include a series-coupled resistor R2 and an n-channel MOS transistor Q5. Resistor R2 has coupling to the power supply voltage rail V... DD The first terminal is coupled to the second terminal of the transistor Q5, and the second terminal is coupled to the drain terminal of the transistor Q5. The transistor Q5 has a source terminal coupled to ground GND and a source terminal coupled to the output of the error amplifier 18 (e.g., via a closed switch not visible in the accompanying figures) to receive the control voltage V. C The gate terminal. The auxiliary circuit device 24' may include a configuration arranged at the voltage V. OUT The n-channel MOS transistor Q6 is located between the output node of the switching stage HB and ground GND. Specifically, transistor Q6 may have a source terminal coupled to ground GND, a drain terminal coupled to the output node of the switching stage HB, and a gate terminal coupled to the node intermediate resistor R2 and transistor Q5.

[0056] like Figure 4 As shown, during the testing phase of converter 4, an external current source 40 (or an equivalent external voltage source with a series-coupled resistor) is connected to the output node of DC-DC converter 4 to supply it with current I, for example, using external hardware available in an automated test apparatus. LOAD External capacitor C OUT It can also be connected between the output node of converter 4 and ground (GND). Therefore, during testing, the current I... LOAD It is provided to the output node of converter 4.

[0057] basically, Figure 4 The test operation of the DC-DC boost converter 4 illustrated in the figure is based on the reference. Figure 3 The same method is discussed in the DC-DC buck-boost converter 2. Also in this example, during the testing phase of converter device 4, the auxiliary loop circuit 24' is connected between the output node of error amplifier 18 and the output node of switching stage HB (e.g., via one or more electronic switches not visible in the attached diagram), and is capable of operating as described below. When the test mode is enabled (e.g., as a function of the value of the test mode signal) and the external current I...LOAD Under ATE-forced conditions, a loop including a feedback voltage divider circuit 16, an error amplifier 18, and an auxiliary loop 24' is provided. The auxiliary loop 24' receives the control voltage V generated by the error amplifier 18. C As its input signal, the conductivity of transistor Q5 (e.g., its on-off state) is thus modulated into the control voltage V. C The function. Therefore, the current flowing through transistor Q5 and resistor R2 is modulated into voltage V. C The function of . The gate voltage of transistor Q6 is therefore also modulated into voltage V. C The current flowing through transistor Q6 and drawn from the output node of the switching stage HB is also a function of the voltage V. C The function is modulated. Therefore, the circuit will output voltage V. OUT Adjusted to the selected value, and in a steady state, the external current I... LOAD The current will flow through transistor Q6. Under these conditions, the circuit blocks involved in the loop (i.e., feedback divider circuit 16 and error amplifier 18) are the same blocks that operate during normal operation of the DC-DC converter 4. Therefore, the contribution of circuits 16 and 18 to the inaccuracy of the converter 4 is considered during the testing phase, while the additional inaccuracy caused by auxiliary circuit 24' can be ignored because circuit block 24' is arranged downstream of error amplifier 18. During testing, the external capacitor C can be selected (e.g., adjusted). OUT The capacitance and external current I LOAD The value is used to ensure the stability of the loop.

[0058] In one or more embodiments, the fine-tuning process performed during testing of the DC-DC converter 4 may include enabling the auxiliary loop 24' as discussed above (e.g., connecting the loop circuit device 24' to the error amplifier 18 by closing a corresponding switch not visible in the attached figure, while transistor Q6 may be permanently connected to the output node of the switching stage HB), and then setting (e.g., adjusting) the available fine-tuning point in the main control loop of the converter 4 to adjust the output voltage V. OUT The value is adjusted to the desired value. For example, the error amplifier 18 can be fine-tuned by calibrating the offset of the error amplifier 18 in an appropriate manner, and / or the reference voltage V can be fine-tuned. REF The value of V is given. The fine-tuning process disclosed here takes into account the circuit blocks (16 and 18) that affect the accuracy of converter 4 during normal operation (i.e., under application conditions), therefore the fine-tuned output value V is... OUT The output value will be as close as possible to the value that occurs during normal operation of converter 4. Alternatively, in the case of a desired shift, the output voltage V can be adjusted with a slightly different target value. OUTThe value is set so that normal operation, including optional shifts, can be arranged.

[0059] Therefore, one or more embodiments illustrated herein may provide one or more of the following advantages:

[0060] - For testing purposes, the same circuitry that was already available in the DC-DC converter loop and was used during normal operation of the DC-DC converter was reused. This helped to monitor converter voltage regulation under operating conditions and detect possible block mismatches of the converter, thus taking into account virtually all sources of inaccuracy during these fine-tuning processes.

[0061] - Provide an auxiliary test loop implemented downstream (e.g., after) of the error amplifier in the feedback loop of the converter, such that the inaccuracy of the auxiliary loop is negligible relative to the inaccuracy of the feedback loop itself.

[0062] -Small silicon area increased;

[0063] - There is no additional power consumption during normal operation of the DC-DC converter (e.g., when deployed in the final application) because once the fine-tuning phase is complete, the auxiliary loop can even be permanently disconnected from the main feedback loop of the converter (e.g., disconnected and not used).

[0064] - The elimination of switching systems in automated testing environments leads to a reduction in the cost and complexity of testing equipment;

[0065] - Faster, more reliable, and / or more accurate testing procedures compared to previously known solutions result in reduced costs and complexity in the testing phase;

[0066] - The applicability of all control schemes to DC-DC converters is independent of their operation in continuous conduction mode (CCM), discontinuous conduction mode (DCM), or pulse-skipping operation mode; and

[0067] - Applicable to all DC-DC converter architectures (e.g., buck-boost, boost, buck, flyback, Cuk, SEPIC and others).

[0068] Without violating the basic principles and without departing from the scope of protection, the details and embodiments may vary significantly from what has been described by example only.

Claims

1. A switching DC-DC converter circuit, comprising: The switching stage includes an input node configured to receive an input voltage and an output node configured to generate an output voltage. A feedback loop circuit arrangement, coupled to the output node of the switching stage, is configured to generate a control signal at the loop output node based on the difference between the output voltage and the reference voltage of the switching DC-DC converter circuit. as well as A test loop circuit device is arranged between the loop output node of the feedback loop circuit device and the output node of the switching stage, wherein the test loop circuit device is configured to apply a current at the output node according to the value of the control signal of the switching DC-DC converter circuit when enabled; The feedback loop circuit device is calibrated during the testing phase of the switching DC-DC converter circuit.

2. The switching DC-DC converter circuit according to claim 1, wherein, The test loop circuit is configured to, when enabled, apply the current at the output node by providing the current to the output node of the switching stage according to the value of the control signal of the switching DC-DC converter circuit.

3. The switching DC-DC converter circuit of claim 1, wherein the test loop circuit device is configured to: when enabled, apply the current at the output node by absorbing the current from the output node of the switching stage according to the value of the control signal of the switching DC-DC converter circuit.

4. The switching DC-DC converter circuit of claim 1, wherein the test loop circuit device includes one or more enable switches configured to selectively couple the test loop circuit device to one or more of the loop output node of the feedback loop circuit device and the output node of the switching stage, and wherein the test loop circuit device is enabled by turning on the one or more enable switches and disabled by turning off the one or more enable switches.

5. The switching DC-DC converter circuit of claim 1, wherein the test loop circuit device is coupled between the loop output node of the feedback loop circuit device and the output node of the switching stage, and wherein the test loop circuit device is enabled and disabled according to a test mode signal.

6. The switching DC-DC converter circuit according to claim 1, wherein the test circuit device comprises: A first transistor has a control terminal coupled to the loop output node of the feedback loop circuit arrangement to receive the control signal, wherein the current flowing through the first transistor depends on the control signal; A current-to-voltage conversion circuit is configured to generate a transistor control voltage for controlling an output transistor based on the current flowing through the first transistor. as well as An output transistor, coupled to the output node of the switching stage, is configured to receive a transistor control voltage at a corresponding control terminal and to supply current to or draw current from the output node of the switching stage according to the value of the transistor control voltage.

7. The switching DC-DC converter circuit according to claim 6, wherein: The first transistor has a source terminal coupled to a first power supply voltage rail and a gate terminal coupled to the loop output node of the feedback loop circuit arrangement to receive the control signal; The current-to-voltage conversion circuit includes a current mirror circuit having a mirror input node coupled to the drain terminal of the first transistor and a mirror output node coupled to the first terminal of a resistor having a second terminal coupled to the second power supply voltage rail. as well as The output transistor has a source terminal coupled to the second power supply voltage rail, a gate terminal coupled to the first terminal of the resistor, and a drain terminal coupled to the output node of the switching stage, the output transistor being configured to provide current to the output node of the switching stage.

8. The switching DC-DC converter circuit of claim 7, wherein the first power supply voltage rail is an internal power supply voltage rail of the switching DC-DC converter circuit, and the second power supply voltage rail is configured to receive the input voltage of the switching DC-DC converter circuit.

9. The switching DC-DC converter circuit according to claim 6, wherein: The first transistor has a source terminal coupled to ground and a gate terminal coupled to the loop output node of the feedback loop circuit arrangement to receive the control signal; The current-to-voltage conversion circuit includes a resistor having a first terminal coupled to the drain terminal of the first transistor and a second terminal coupled to a power supply voltage rail. as well as The output transistor has a source terminal coupled to ground, a gate terminal coupled to the first terminal of the resistor, and a drain terminal coupled to the output node of the switching stage, the output transistor being configured to draw current from the output node of the switching stage.

10. The switching DC-DC converter circuit according to claim 1, wherein the feedback loop circuit device comprises: A feedback voltage divider circuit is coupled to the output node of the switching stage and configured to generate a feedback voltage based on the voltage division of the output voltage. as well as An error amplifier is configured to amplify the difference between the feedback voltage and the reference voltage to generate the control signal. During the testing phase of the switching DC-DC converter circuit, one or more of the offset voltage of the error amplifier and the reference voltage of the error amplifier are calibrated.

11. The switching DC-DC converter circuit according to claim 10, wherein the feedback voltage divider circuit comprises: A digital-to-analog converter circuit is configured to convert digital signals into analog voltage signals; A buffer circuit is configured to receive the analog voltage signal from the digital-to-analog converter circuit and generate a buffered analog voltage signal; as well as A voltage ladder circuit is arranged between the output node of the buffer circuit and the output node of the switching stage and is configured to generate the feedback voltage at an intermediate node of the voltage ladder circuit. The offset voltage of the buffer circuit is calibrated during the testing phase of the switching DC-DC converter circuit.

12. The switching DC-DC converter circuit of claim 10, wherein the feedback voltage divider circuit includes a voltage ladder circuit arranged between the output node and the ground node of the switching stage and configured to generate the feedback voltage at an intermediate node of the voltage ladder circuit.

13. The switching DC-DC converter circuit according to claim 1, further comprising: A voltage ramp generation circuit is configured to generate a ramp signal; as well as A comparator circuit is configured to compare the ramp signal with the control signal to generate a pulse width modulation signal for controlling the switching activity of the switching stage; The voltage ramp generation circuit device includes: A ramp generator circuit is configured to generate a basic ramp signal; A current sensing circuit is configured to sense current flowing through one or more switches of the switching stage and generate a signal indicating the sensed current; and An adder circuit is configured to add the basic ramp signal and the signal indicating the sensed current to generate the ramp signal.

14. A method for testing a switching DC-DC converter circuit, comprising: The switching DC-DC converter circuit is set to test operation mode by blocking the switching activity of the switching stage and enabling the test loop circuit device. A current, based on the value of the control signal of the switching DC-DC converter circuit, is applied to the output node of the switching stage via the test loop circuit device. The current is applied to the output node of the switching stage via an external current generator circuit; Sensing the value of the output voltage generated at the output node of the switching stage; as well as One or more electronic components of the feedback loop circuit device are calibrated until the desired value of the output voltage is generated at the output node of the switching stage.

15. The method of claim 14, wherein applying the current comprises supplying current to the output node of the switching stage; and wherein the external current generator circuit is a current source circuit.

16. The method of claim 14, wherein applying the current includes drawing current from the output node of the switching stage; and wherein the external current generator circuit is a current sink circuit.

17. The method of claim 14, further comprising calibrating the offset voltage of the error amplifier until the desired value of the output voltage is generated at the output node of the switching stage.

18. The method of claim 14, further comprising calibrating the reference voltage of the error amplifier until the desired value of the output voltage is generated at the output node of the switching stage.

19. The method of claim 14, further comprising calibrating the offset voltage of the buffer circuit until the desired value of the output voltage is generated at the output node of the switching stage.

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