A frequency divider circuit, frequency divider and frequency divider system

Abstract

This invention provides a frequency divider circuit, frequency divider, and frequency divider system, comprising: a feedback selection module for selecting a frequency division ratio; a delay module for receiving the output signal of the feedback selection module, the delay module including at least one delay D flip-flop, the output signal of the delay D flip-flop being connected to the feedback selection module; a recovery module for receiving the output signal of the delay module to adjust the duty cycle; and an output module for receiving the output signals of the delay module and the recovery module to output a clock output signal. When there are multiple delay D flip-flops, the multiple delay D flip-flops are connected sequentially, and the clock input signal is connected to the delay module, the recovery module, and the output module. Through the frequency divider circuit, frequency divider, and frequency divider system disclosed in this invention, the duty cycle of the clock output signal can be adjusted.

Description

Technical Field

[0001] This invention relates to the field of frequency division technology, and in particular to a frequency division circuit, frequency divider, and frequency division system. Background Technology

[0002] A frequency divider is a circuit module used to adjust the clock frequency of a clock input signal, converting a high-frequency clock input signal into a low-frequency clock output signal. Commonly used frequency dividers include counters, dual-mode prescalers, and multi-mode prescalers. Current frequency divider architectures suffer from duty cycle misalignment in the clock output signal, failing to meet the requirements of some frequency division systems. Therefore, improvements are needed. Summary of the Invention

[0003] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a frequency divider circuit, frequency divider and frequency divider system that can adjust the duty cycle of the clock output signal.

[0004] To achieve the above and other related objectives, the present invention provides a frequency divider circuit, comprising:

[0005] The feedback selection module is used to select the division ratio;

[0006] A delay module is used to receive the output signal of the feedback selection module. The delay module includes at least one delay D flip-flop, and the output signal of the delay D flip-flop is connected to the feedback selection module.

[0007] The recovery module is used to receive the output signal of the delay module in order to adjust the duty cycle;

[0008] The output module is used to receive the output signals of the delay module and the recovery module, and to output a clock output signal;

[0009] When there are multiple delay D flip-flops, the multiple delay D flip-flops are connected in sequence, and the clock input signal is connected to the delay module, the recovery module and the output module.

[0010] In one embodiment of the present invention, when the frequency division circuit enters the first frequency division mode, it outputs the clock output signal with a division ratio of 1. The first frequency division mode is that the output module receives the clock input signal through the recovery module.

[0011] In one embodiment of the present invention, when the frequency divider circuit enters the second frequency divider mode, it outputs the clock output signal with a 2n division ratio. The second frequency divider mode is that the feedback selection module receives the output signal of the nth delay D flip-flop, and the output module receives the output signal of the delay module, where n is a positive integer.

[0012] In one embodiment of the present invention, when the frequency divider circuit enters the third frequency divider mode, it outputs the clock output signal with a frequency division ratio of 2n+1. The third frequency divider mode is that the feedback selection module receives the output signals of the nth and (n+1th)th delay D flip-flops, and the output module receives the output signal of the delay module through the recovery module, where n is a positive integer.

[0013] In one embodiment of the present invention, the feedback selection module includes:

[0014] A single-signal selection unit is used to receive the output signal of the (2n-1)th delayed D flip-flop;

[0015] A dual-signal selection unit is used to receive the output signal of the 2nth delayed D flip-flop; and

[0016] The NOR gate is used to receive the output signals of the single signal selection unit and the dual signal selection unit, and the output signal of the NOR gate is connected to the delay module.

[0017] In one embodiment of the present invention, the single-signal selection unit has the same structure as the dual-signal selection unit, and the single-signal selection unit includes:

[0018] A feedback multiplexer is used to receive the output signal of the (2n-1)th delayed D flip-flop; and

[0019] AND gate circuit, used to receive the output signal of the feedback multiplexer;

[0020] The feedback multiplexer and the AND gate are used to receive output signals from different frequency division interfaces.

[0021] In one embodiment of the present invention, the recovery module includes:

[0022] A NOT gate circuit is used to receive the clock input signal;

[0023] Restore the D flip-flop to receive the output signals of the NOT gate and the delay module; and

[0024] An OR gate circuit is used to receive the output signals of the recovery D flip-flop and the delay module.

[0025] In one embodiment of the present invention, the recovery module includes an output multiplexer, which is used to receive the output signals of the OR gate, the NOT gate, and the delay module.

[0026] The present invention also provides a frequency divider, including the frequency divider circuit described above.

[0027] The present invention also provides a frequency division system, including a frequency divider and at least one frequency division interface, wherein the frequency division interface is matched with the interface of the feedback selection module of the frequency divider.

[0028] As described above, the present invention provides a frequency divider circuit, a frequency divider, and a frequency divider system capable of outputting clock output signals with different division ratios, enabling the division ratio to continuously vary starting from 1. Simultaneously, it can adjust the duty cycle of the clock output signals with different division ratios as needed, so that the duty cycle can be maintained at 50%. Attached Figure Description

[0029] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 The diagram shown is a schematic diagram of a frequency divider circuit according to the present invention;

[0031] Figure 2 The diagram shown illustrates a frequency divider circuit of the present invention entering a second frequency divider mode.

[0032] Figure 3 Displayed as Figure 2 Timing diagram;

[0033] Figure 4 The diagram shown illustrates a frequency divider circuit of the present invention entering the third frequency divider mode;

[0034] Figure 5 Displayed as Figure 4 Timing diagram;

[0035] Figure 6 The diagram shown is a schematic of a feedback selection module in a frequency division circuit according to the present invention.

[0036] Figure 7 This is a schematic diagram showing the second frequency division mode of the feedback selection module;

[0037] Figure 8 This is a schematic diagram showing the third frequency division mode of the feedback selection module.

[0038] Component designation explanation:

[0039] 10. Feedback selection module; 11. Single signal selection unit; 111. Feedback multiplexer; 112. AND gate; 12. Dual signal selection unit; 13. NOR gate;

[0040] 20. Delay module; 21. Delay D flip-flop;

[0041] 30. Recovery module; 31. NOT gate; 32. Recovery D flip-flop; 33. OR gate;

[0042] 40. Output module; 41. Output multiplexer;

[0043] 50. Clock input signal;

[0044] 60. Clock output signal;

[0045] 70. Frequency divider interface. Detailed Implementation

[0046] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0047] Please see Figure 1 As shown, the present invention provides a frequency divider circuit, which can be used to adjust the clock frequency of a clock input signal 50 to convert a high-clock-frequency clock input signal 50 into a low-clock-frequency clock output signal 60. The frequency divider circuit may include a feedback selection module 10, a delay module 20, a recovery module 30, and an output module 40.

[0048] Specifically, the feedback selection module 10 can communicate with different frequency divider interfaces 70, selecting the appropriate division ratio based on the frequency divider interface 70. The division ratio can be expressed as the ratio of the clock frequency of the clock input signal 50 to the clock frequency of the clock output signal 60. The input of the delay module 20 can communicate with the output of the feedback selection module 10 and the clock input signal 50. The output of the delay module 20 can communicate with the input of the feedback selection module 10, the input of the recovery module 30, and the input of the output module 40. The input of the recovery module 30 can communicate with the clock input signal 50, and the recovery module 30 can be used to adjust the duty cycle of the clock output signal 60. The duty cycle can be expressed as the ratio of the clock high-level period in the clock output signal 50 to the entire clock cycle. The input of the output module 40 can also communicate with the clock input signal 50, and the output of the output module 40 can be used to output the clock output signal 60.

[0049] Please see Figure 1As shown, in one embodiment of the present invention, the delay module 20 may include at least one delay D flip-flop 21. The delay D flip-flop can be a D flip-flop, which is an information storage device with memory function and two stable states. Since the number of delay D flip-flops 21 in the delay module 20 is expandable, and the number of delay D flip-flops 21 can be at least one, the wiring method is different for different numbers of delay D flip-flops 21.

[0050] Taking one delayed D flip-flop 21 as an example, the D input interface of the delayed D flip-flop 21 is communicatively connected to the output of the feedback selection module 10. The clock input interface of the delayed D flip-flop 21 is communicatively connected to the clock input signal 50. The Q output interface of the delayed D flip-flop 21 is communicatively connected to the input of the feedback selection module 10. The Q output interface of the delayed D flip-flop 21 is also communicatively connected to the input of the recovery module 30 and the input of the output module 40.

[0051] Taking multiple delayed D flip-flops 21 as an example, the D input interface of the first delayed D flip-flop is communicatively connected to the output of the feedback selection module 10. The Q output interface of the last delayed D flip-flop is communicatively connected to the input of the recovery module 30 and the input of the output module 40. The clock input interfaces of all delayed D flip-flops 21 are communicatively connected to the clock input signal 50. The Q output interfaces of all delayed D flip-flops 21 are communicatively connected to the input of the feedback selection module 10. In two adjacent delayed D flip-flops 21, the Q output interface of one delayed D flip-flop is communicatively connected to the D input interface of the next delayed D flip-flop.

[0052] Please see Figure 1 As shown, in one embodiment of the present invention, the feedback selection module 10 may include a single-signal selection unit 11, a dual-signal selection unit 12, and a NOR gate circuit 13. When there are multiple delayed D flip-flops 21, they can be ordered. The Q output interface of the (2n-1)th delayed D flip-flop is communicatively connected to the single-signal selection unit 11 to receive the output signal of the (2n-1)th delayed D flip-flop. The Q output interface of the 2nth delayed D flip-flop is communicatively connected to the dual-signal selection unit 12 to receive the output signal of the 2nth delayed D flip-flop. n is a positive integer. The output signal of the single-signal selection unit 11 and the output signal of the dual-signal selection unit 12 are communicatively connected to the NOR gate circuit 13. The output signal of the NOR gate circuit 13 is communicatively connected to the D input interface of the first delayed D flip-flop. The NOR gate circuit 13 may have multiple inputs and one output. In the NOR gate circuit 13, the output is high (logic 1) only when both inputs are low (logic 0).

[0053] In this embodiment, the circuit structure of the single-signal selection unit 11 may or may not be the same as that of the dual-signal selection unit 12. In this embodiment, the example of the single-signal selection unit 11 having the same circuit structure as the dual-signal selection unit 12 will be used for explanation. The single-signal selection unit 11 may include a feedback multiplexer 111 and an AND gate circuit 112. The feedback multiplexer 111 can be a data selector. A data selector can be represented as a circuit that selects any one data path according to requirements during multi-channel data transmission. The AND gate circuit 112 can be an AND circuit. An AND circuit is a basic logic gate circuit that performs the "AND" operation. An AND circuit has multiple input terminals and one output terminal. The output is high only when all inputs are simultaneously high (logic 1); otherwise, the output is low (logic 0).

[0054] Taking four delayed D flip-flops 21 as an example, the Q output interfaces of the first and third delayed D flip-flops can be communicatively connected to the feedback multiplexer 111 of the single-signal selection unit 11. The Q output interfaces of the second and fourth delayed D flip-flops can be communicatively connected to the data selector of the dual-signal selection unit 12. The Q output interface of one delayed D flip-flop can be communicatively connected to the D input interface of the next delayed D flip-flop. The Q output interface of the fourth delayed D flip-flop can also be communicatively connected to the recovery module 30 and the output module 40. The clock input interfaces of all four delayed D flip-flops can be communicatively connected to the clock input signal 50.

[0055] Furthermore, the output of the feedback multiplexer 111 can be communicatively connected to the input of the AND gate 112. One frequency divider interface 70 can be communicatively connected to the input of the feedback multiplexer 111, and another frequency divider interface 70 can be communicatively connected to the input of the AND gate 112. The outputs of the AND gate 112 of the single-signal selection unit 11 and the AND gate of the dual-signal selection unit 12 can be communicatively connected to the input of the NOR gate 13. The output of the NOR gate 13 can be communicatively connected to the D input interface of the first delayed D flip-flop 21. The frequency divider interface 70 can include a frequency divider selection socket and a NOR gate. There can be multiple frequency divider selection sockets; for example, the frequency divider selection sockets can be DIV2 sockets, DIV3 sockets, etc. The DIV2 and DIV3 sockets can be communicatively connected to the inputs of the NOR gates, and the outputs of the NOR gates can be communicatively connected to the inputs of the feedback multiplexer 111 and the AND gate 112. The DIV2 connector can be represented as a 2-way divider connector, and the DIV3 connector as a 3-way divider connector. When an external interface is connected to the DIV2 connector, the DIV2 connector is powered on and at a high level. At this time, the DIV3 connector is not powered on and at a low level. The high-level signal and the low-level signal are input to a NOR gate for operation, and then output a low-level signal.

[0056] In one embodiment of the present invention, the recovery module 30 may include a NOT gate 31, a recovery D flip-flop 32, and an OR gate 33. The NOT gate 31 utilizes an internal structure to make the output level opposite to the input level. The recovery D flip-flop 32 may be a D flip-flop. The OR gate 33 has multiple input terminals and one output terminal; when one of the input signals is high (logic 1), the output signal is high (logic 1). The input terminal of the NOT gate 31 can be communicatively connected to the clock input signal 50. The output terminal of the NOT gate 31 can be communicatively connected to the clock input interface of the recovery D flip-flop 32. The D input interface of the recovery D flip-flop 32 can be communicatively connected to the Q output interface of the last delay D flip-flop 21 in the delay module 20. The Q output interface of the recovery D flip-flop 32 can be communicatively connected to the input terminal of the OR gate 33. The input terminal of the OR gate 33 can also be communicatively connected to the Q output interface of the last delay D flip-flop 21 in the delay module 20. The output terminal of the OR gate 33 can be communicatively connected to the output module 40.

[0057] In one embodiment of the present invention, the output module 40 may include an output multiplexer 41. The output multiplexer 41 may be a data selector. The input of the output multiplexer 41 may be communicatively connected to the Q output interface of the last delay D flip-flop 21 in the delay module 20. The input of the output multiplexer 41 may also be communicatively connected to the output of the OR gate circuit 33 in the recovery module 30. The input of the output multiplexer 41 may also be communicatively connected to the output of the NOT gate circuit 31 in the recovery module 30. The output multiplexer 41 may be used to receive input signals and output a clock output signal 60.

[0058] In one embodiment of the present invention, the frequency divider circuit can output clock output signals 60 with different division ratios. The division ratio can be a positive integer. Therefore, the frequency divider circuit can preset different division modes based on different division ratio requirements. The division modes can include, but are not limited to, a first division mode, a second division mode, and a third division mode. The first division mode can be represented as outputting a clock output signal 60 with a division ratio of 1. The second division mode can be represented as outputting a clock output signal 60 with a division ratio of 2n. The third division mode can be represented as outputting a clock output signal 60 with a division ratio of 2n+1. Here, n is a positive integer and is the same as the number of delay D flip-flops.

[0059] When a clock output signal 60 with a 1 / 1 division ratio is required, the frequency division mode enters the first division mode. At this time, the output module 40 receives the clock input signal 50 through the recovery module 30 and outputs the clock output signal 60. Specifically, the clock input signal 50 can be directly passed through the NOT gate circuit 31 in the recovery module 30 and input from the output terminal of the NOT gate circuit 31 to the output multiplexer 41 for output, so as to output the clock output signal 60 with a duty cycle of 50%.

[0060] Please see Figure 2 and Figure 3 As shown, when a clock output signal 60 with a 2n division ratio is required, the frequency division mode enters the second frequency division mode. At this time, the feedback selection module 10 receives the output signal of the nth delay D flip-flop 21 in the delay module 20, and the output module 40 receives the output signal of the delay module 20 and outputs the clock output signal 60.

[0061] Specifically, let's take a clock output signal 60 with a division ratio of 6 as an example. The Q output interface of the first delayed D flip-flop can be represented as Q1. The Q output interface of the second delayed D flip-flop can be represented as Q2. The Q output interface of the third delayed D flip-flop can be represented as Q3. The Q output interface of the fourth delayed D flip-flop can be represented as Q4. After passing through the third delayed D flip-flop, the clock input signal 50 is output from Q3 to the feedback selection module 10. At this time, the feedback selection module 10 can be simplified to a NOT gate circuit. The clock input signal 50 passes through three delayed D flip-flops, and its division ratio can be 6. At the same time, its duty cycle can be maintained at 50%, so the recovery module 30 does not need to adjust its duty cycle. The output signal of the fourth delayed D flip-flop can be directly input to the output module 40. The output module 40 can output a clock output signal 60 with a division ratio of 6 and a duty cycle of 50%.

[0062] Please see Figure 4 and Figure 5 As shown, when a clock output signal 60 with a division ratio of 2n+1 is required, the frequency division mode enters the third division mode. At this time, the feedback selection module 10 receives the output signals of the nth and (n+1th)th delay D flip-flops in the delay module 20. The output module 40 receives the output signal of the delay module 20 through the recovery module 30 and finally outputs the clock output signal 60.

[0063] Specifically, let's take a clock output signal 60 with a 5-fold frequency division ratio as an example. The clock input signal 50 passes through the second and third delayed D flip-flops and is output from Q2 and Q3 to the feedback selection module 10. At this point, the feedback selection module 10 can be simplified to a NOR gate circuit. The feedback selection module 10 can select the output signals of two adjacent delayed D flip-flops 21 and perform NOR processing to obtain a clock signal with a 2n+1-fold frequency division ratio. The feedback selection module 10 selects the output signals of the second and third delayed D flip-flops to output a clock signal with a 5-fold frequency division ratio. At this point, the duty cycle of the clock signal is offset; due to combinational logic, the high-level time in each cycle of the clock signal is one input clock cycle shorter than the low-level time.

[0064] Furthermore, to adjust the duty cycle of the clock signal to restore it to 50%, the clock signal can be input from Q4 to the D input interface of the recovery D flip-flop 32 and output from the Q output interface of the recovery D flip-flop 32 to the input of the OR gate circuit 33. Simultaneously, the clock signal can also be input from Q4 to the input of the OR gate circuit 33. By sampling the clock signal on the falling edge of the recovery D flip-flop 32 and then performing an OR operation with the clock signal, the high-level time of the clock signal is extended by half an input clock cycle, thereby restoring the output signal of the OR gate circuit 33 to a 50% duty cycle. At this time, the output module 40 can output a clock output signal 60 with a division ratio of 5 and a duty cycle of 50%.

[0065] Please see Figure 6 and Figure 7 As shown, in one embodiment of the present invention, when a clock output signal 60 with a division ratio of 2n needs to be output, the DIV2n socket in the frequency divider interface 70 is connected to an external interface, and Qn outputs a high level. Here, n is the number of delay D flip-flops 21. For example, when a clock output signal 60 with a division ratio of 2 needs to be output, the DIV2 socket in the frequency divider interface 70 is connected to an external interface, and Q1 outputs a high level. When a clock output signal 60 with a division ratio of 4 needs to be output, the DIV4 socket in the frequency divider interface 70 is connected to an external interface, and Q2 outputs a high level. When a clock output signal 60 with a division ratio of 8 needs to be output, the DIV8 socket in the frequency divider interface 70 is connected to an external interface, and Q8 outputs a high level.

[0066] Taking the clock output signal 60 with a division ratio of 6 as an example, the DIV6 connector in the frequency divider interface 70 is connected to an external interface. The DIV6 connector is powered on and at a high level, while the other connectors are not powered on and at a low level. At this time, the NOR gate corresponding to the DIV6 connector outputs a low level (logic 0), while the other NOR gates output a high level (logic 1). Q3 outputs a high level. After logic operation, the single-signal selection unit 11 outputs a high level, and the dual-signal selection unit 12 outputs a low level. After the single-signal selection unit 11 and the dual-signal selection unit 12 perform NOR gate circuit 13 operation, the high level output of Q3 is selected, inverted, and output to form the clock output signal 60 with a division ratio of 6.

[0067] Please see Figure 6 and Figure 8As shown, in one embodiment of the present invention, when a clock output signal 60 with a division ratio of 2n+1 is required, the DIV2n+1 socket in the frequency divider interface 70 is connected to an external interface, and Qn and Qn+1 output high levels. Here, n is the number of delay D flip-flops 21. For example, when a clock output signal 60 with a division ratio of 3 is required, the DIV3 socket in the frequency divider interface 70 is connected to an external interface, and Q1 and Q2 output high levels. When a clock output signal 60 with a division ratio of 5 is required, the DIV5 socket in the frequency divider interface 70 is connected to an external interface, and Q2 and Q3 output high levels.

[0068] Taking a clock output signal 60 with a division ratio of 7 as an example, the DIV7 connector in the divider interface 70 is connected to an external interface. The DIV7 connector is powered on and at a high level, while the other connectors are not powered on and at a low level. At this time, the NOR gate corresponding to the DIV7 connector outputs a low level, while the other NOR gates output a high level. Q3 and Q4 output high levels. After logic operations, the single-signal selection unit 11 outputs a high level, and the dual-signal selection unit 12 outputs a high level. After the single-signal selection unit 11 and the dual-signal selection unit 12 perform NOR gate circuit 13 operations, the high level outputs of Q3+Q4 are selected, inverted, and output to form the clock output signal 60 with a division ratio of 7.

[0069] In one embodiment of the present invention, a frequency divider is also provided. The aforementioned frequency divider circuit can be applied to a frequency divider to enable the frequency divider to output clock output signals 60 with different division ratios and a 50% duty cycle as needed. In other embodiments, a frequency division system is also provided. The frequency division system may include a frequency divider and at least one frequency division interface 70. The frequency division interface 70 may be matched with the interface of the feedback selection module 10 in the frequency divider.

[0070] As can be seen, the above scheme can output clock signals with different division ratios, allowing the division ratio to change continuously starting from 1. Simultaneously, it can adjust the duty cycle of the clock output signals with different division ratios as needed, ensuring the duty cycle remains at 50%.

[0071] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

[0072] Throughout this description, numerous specific details, such as examples of components and / or methods, are provided to provide a complete understanding of embodiments of the invention. However, those skilled in the art will recognize that embodiments of the invention may be practiced without one or more of these specific details or by other devices, systems, components, methods, parts, materials, components, etc. In other instances, well-known structures, materials, or operations have not been specifically shown or described in detail to avoid obscuring aspects of embodiments of the invention.

[0073] Therefore, although the invention has been described herein with reference to specific embodiments thereof, freedom of modification, various changes and substitutions are also within the scope of the foregoing disclosure, and it should be understood that in some cases, certain features of the invention may be adopted without departing from the scope and spirit of the invention and without corresponding use of other features. Thus, many modifications can be made to adapt a particular environment or material to the essential scope and spirit of the invention. The invention is not intended to be limited to the specific terminology used in the following claims and / or the specific embodiments disclosed as the best mode for carrying out the invention, but the invention will include any and all embodiments and equivalents falling within the scope of the appended claims. Therefore, the scope of the invention will be defined only by the appended claims.

Claims

1. A frequency divider circuit, characterized in that, include: The feedback selection module is used to select the division ratio; A delay module is used to receive the output signal of the feedback selection module. The delay module includes at least one delay D flip-flop, and the output signal of the delay D flip-flop is connected to the feedback selection module. The recovery module is used to receive the output signal of the delay module in order to adjust the duty cycle; The output module is used to receive the output signals of the delay module and the recovery module, and to output a clock output signal; When there are multiple delay D flip-flops, the multiple delay D flip-flops are connected in sequence, and the clock input signal is connected to the delay module, the recovery module and the output module; The feedback selection module includes: a single-signal selection unit for receiving the output signal of the (2n-1)th delayed D flip-flop; a dual-signal selection unit for receiving the output signal of the 2nth delayed D flip-flop; and a NOR gate circuit for receiving the output signals of the single-signal selection unit and the dual-signal selection unit, wherein the output signal of the NOR gate circuit is connected to the delay module; n is a positive integer; The single-signal selection unit has the same structure as the dual-signal selection unit; the single-signal selection unit includes: a feedback multiplexer for receiving the output signal of the (2n-1)th delayed D flip-flop, the feedback multiplexer being a data selector; and an AND gate for receiving the output signal of the feedback multiplexer; wherein the feedback multiplexer and the AND gate are used to receive output signals from different frequency division interfaces.

2. The frequency divider circuit according to claim 1, characterized in that, When the frequency divider circuit enters the first frequency divider mode, it outputs the clock output signal with a division ratio of 1. The first frequency divider mode is when the output module receives the clock input signal through the recovery module.

3. The frequency divider circuit according to claim 1, characterized in that, When the frequency divider circuit enters the second frequency divider mode, it outputs the clock output signal with a 2n division ratio. In the second frequency divider mode, the feedback selection module receives the output signal of the nth delay D flip-flop, and the output module receives the output signal of the delay module, where n is a positive integer.

4. The frequency divider circuit according to claim 1, characterized in that, When the frequency divider circuit enters the third frequency divider mode, it outputs the clock output signal with a frequency division ratio of 2n+1. The third frequency divider mode is that the feedback selection module receives the output signals of the nth and (n+1th)th delay D flip-flops, and the output module receives the output signal of the delay module through the recovery module, where n is a positive integer.

5. The frequency divider circuit according to claim 1, characterized in that, The recovery module includes: A NOT gate circuit is used to receive the clock input signal; Restore the D flip-flop to receive the output signals of the NOT gate and the delay module; and An OR gate circuit is used to receive the output signals of the recovery D flip-flop and the delay module.

6. The frequency divider circuit according to claim 5, characterized in that, The recovery module includes an output multiplexer, which is used to receive the output signals of the OR gate, the NOT gate, and the delay module.

7. A frequency divider, characterized in that, Includes the frequency divider circuit as described in any one of claims 1 to 6.

8. A frequency division system, characterized in that, It includes the frequency divider as described in claim 7 and at least one frequency divider interface, the frequency divider interface being matched with the interface of the feedback selection module of the frequency divider.

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