Successive approximation register analog-to-digital converter with reduced data path delay

Abstract

Systems and methods relate to a successive approximation register analog-to-digital converter (SAR ADC) with reduced data path latency. The SAR ADC includes a sampling and digital-to-analog conversion (DAC) circuit configured to sample an input voltage; a comparator circuit coupled to the sampling and DAC circuit and having an output; a first set of storage circuits; and a comparator driver. The comparator driver is disposed between the output and the first set of storage circuits (e.g., a ratio latch). The first set of storage circuits is coupled to the comparator circuit and the sampling and DAC circuit. The comparator driver may include a first driver and a second driver. The first driver is coupled to a first input of a first storage circuit of the first set of storage circuits, and the second driver is coupled to a first input of a second storage circuit within the first set of storage circuits.

Description

Technical Field

[0001] The present disclosure relates generally to communication systems, including but not limited to communication systems that include a successive approximation register analog-to-digital converter (SAR ADC). Background Art

[0002] Recent developments in communication and computing devices require high data rates. For example, network switches, routers, hubs, or any communication device can exchange data at high speeds (e.g., 1 Mbps to 100 Gbps) to stream data in real time or process large amounts of data seamlessly. To efficiently process data in the digital domain, the amplitude or voltage of a signal can be represented by multiple bits, and the signal can be exchanged between two or more communication devices via a cable or wireless medium. For example, a 1.2V signal can be represented as a byte (B), such as 00010110, and a 1.3V signal can be represented as B, such as 00011001. To convert the voltage of an input signal into corresponding bits, some communication devices implement a SAR ADC. For example, a SAR ADC can determine the number of bits corresponding to the input signal through successive approximation. Process, voltage, and temperature (PVT) variations may affect the speed, precision, and / or accuracy of the SAR ADC. Summary of the Invention

[0003] In one aspect, the present application relates to a device comprising: a digital-to-analog conversion (DAC) circuit; a comparator circuit coupled to the DAC circuit having an output; a first set of storage circuits coupled to the comparator circuit and the DAC circuit, the first set of storage circuits being configured to store a plurality of first bits corresponding to an input voltage; and a comparator driver located between the output and the first set of storage circuits, wherein the comparator driver comprises a first driver and a second driver, the first driver being coupled to the input of a first storage circuit of the first set of storage circuits, and the second driver being coupled to the input of a second set of storage circuits within the first set of storage circuits.

[0004] In another aspect, the present application relates to a device comprising: a digital-to-analog conversion (DAC) circuit including a reset transistor; a comparator circuit coupled to the DAC circuit; a first set of storage circuits coupled to the comparator circuit and the DAC circuit, the first set of storage cells being configured to store a plurality of first bits corresponding to an input voltage provided by the comparator circuit; and an enable circuit configured to provide an enable signal to the first set of storage circuits, wherein one of the enable signals is provided to the reset transistor to reset the digital-to-analog conversion DAC circuit.

[0005] In another aspect, the present application relates to a device comprising: a digital-to-analog conversion (DAC) circuit; a comparator circuit coupled to the DAC circuit; a first set of storage circuits coupled to the comparator circuit and the DAC circuit, the first set of storage circuits configured to store a plurality of first bits corresponding to an input voltage, wherein the first set of storage circuits is a ratio latch having an output coupled to a feedback input of the DAC circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various objects, aspects, features and advantages of the present disclosure will become more apparent and better understood by referring to the detailed description taken in conjunction with the accompanying drawings, wherein like reference characters identify corresponding elements throughout. In the accompanying drawings, like reference numerals generally indicate identical, functionally similar and / or structurally similar elements.

[0007] Figure 1A is a general block diagram depicting a network environment including one or more access points in communication with one or more devices or stations in accordance with one or more embodiments.

[0008] Figure 1B and 1C is a general block diagram depicting a computing device that may be used in conjunction with the methods and systems described herein, in accordance with one or more embodiments.

[0009] Figure 2 is a general block diagram depicting a communication device in accordance with one or more embodiments.

[0010] Figure 3A According to one or more embodiments, Figure 2 Schematic diagram of the SAR ADC used in the communication device described in .

[0011] Figure 3B is a more detailed diagram of a portion of the SAR ADC illustrated in FIG. 3 , according to one or more embodiments.

[0012] Figure 4 According to one or more embodiments Figure 3A Schematic diagram of the conversion state circuit of the SAR ADC described in .

[0013] Figure 5 is a diagram showing a method according to one or more embodiments of the present invention. Figure 4 1 is a timing diagram of the conversion state signals provided by the conversion state circuit described in .

[0014] Figure 6 According to one or more embodiments Figure 3A Schematic diagram of the current source circuit of the comparator used in the SAR ADC described in .

[0015] Figure 7 According to one or more embodiments, Figure 3A Schematic diagram of the comparator driver circuit of the SAR ADC described in .

[0016] Figure 8 According to one or more embodiments, Figure 3A Schematic diagram of an alternative comparator driver circuit for the SAR ADC described in .

[0017] Figure 9 is a method for demonstrating a method for Figure 3A Flowchart of the adaptive operation for performance and power efficiency optimization of the SAR ADC described in .

[0018] Figure 10 is to demonstrate according to one or more embodiments Figure 3A Figure 2 is a graph of the probability and conversion margin of a SAR ADC.

[0019] The details of various embodiments of the methods and systems are set forth in the accompanying drawings and the description below. DETAILED DESCRIPTION

[0020] For purposes of reading the description of the various embodiments below, the following description of sections of the specification and their corresponding contents may be helpful:

[0021] - Section A describes a network environment and a computing environment that can be used to practice the embodiments described herein; and

[0022] - Section B describes embodiments of systems and methods for power-efficient SAR ADCs according to one or more embodiments.

[0023] Various embodiments disclosed herein relate to devices for data communication. In some embodiments, the devices include or are SAR ADCs for use in physical layer products. In some embodiments, the SAR ADCs are high speed (e.g., resolution exceeding 7 and operating at hundreds of megasamples per second). In some embodiments, the SAR ADCs are adaptively tuned for PVT operation to appropriately increase speed or reduce noise. In some embodiments, adaptive feedback techniques can adjust comparator driver thresholds to increase operating speed in slow corners without any common mode voltage V in fast (FF) corners. CM Correlated Errors Advantageously, the systems and methods described herein can provide SAR ADCs with reduced latency, reduced area, reduced mismatch, and increased bandwidth for large SAR ADC arrays.

[0024] In some embodiments, an optimized (e.g., for power consumption and performance) SAR ADC with adaptive current or voltage parameter adjustment is provided. The SAR DAC is configured to adjust current or voltage parameters associated with the comparator to adjust the speed of the comparator operation. In some embodiments, the systems and methods adjust the comparator bias current or threshold voltage to achieve a very high speed comparator with low noise and reduced power consumption (reduced by 10% or more). In some embodiments, the current or voltage parameter is adjusted or adaptively tuned based on a conversion margin. In some embodiments, the conversion margin indicates the amount of unused time during the comparison operation available within a sampling cycle. In some embodiments, the conversion margin is determined using time delays and probability relationships. In some embodiments, the current or voltage parameters include a current bias for the comparator current source, a threshold voltage for the comparator driver, a current bias for the comparator driver, and / or a supply voltage (e.g., V for the comparator). DD or other voltages provided by an onboard power regulator. In some embodiments, the SAR ADC employs an operating flow to sense conditions to determine probabilistic relationships and adjust voltage and current parameters.

[0025] In some embodiments, a SAR ADC includes a data path configured for increased speed. The data path uses an enable signal (enable zero) to directly reset the capacitor digital-to-analog converter (CAPDAC) circuit, which achieves faster reset and improved CAPDAC circuit settling time. In some embodiments, the CAPDAC circuit receives feedback signals directly from the ratio latch rather than from a separate driver, thereby increasing speed (e.g., by significantly reducing clock path delays) and reducing layout complexity. In some embodiments, the most significant bit (MSB) ratio latch is driven by a single comparator driver, while the remaining latches are driven by a second driver coupled to the single comparator driver. In some embodiments, the second driver is directly coupled to the single driver. In some embodiments, the use of this driver configuration reduces the load on the single comparator driver, thereby reducing the MSB settling time and reducing layout complexity.

[0026] Various embodiments disclosed herein relate to a device. The device includes a digital-to-analog converter (DAC) circuit configured to sample an input voltage, a comparator circuit coupled to the DAC circuit and having an output, a first set of storage circuits, and a comparator driver. The comparator driver is disposed between the comparator circuit and the first set of storage circuits. The first set of storage circuits is coupled to the comparator circuit and the DAC circuit. The first set of storage circuits is configured to store a first bit corresponding to the input voltage. The comparator driver includes a first driver and a second driver. The first driver is coupled to a first input of a first storage circuit of the first set of storage circuits, and the second driver is coupled to a first input of a second storage circuit within the first set of storage circuits.

[0027] In some embodiments, the second group of storage circuits does not include the first storage circuit. In some embodiments, the first storage circuit stores the most significant bit of the first bits provided by the comparator circuit. In some embodiments, the second group of storage circuits includes all remaining storage circuits in the first group of storage circuits.

[0028] In some embodiments, the device further includes a third set of storage circuits coupled to the comparator circuit and the DAC circuit. The third set of storage circuits is configured to store a second bit corresponding to the input voltage. In some embodiments, the comparator driver includes a third driver and a fourth driver. The third driver is coupled to a first input of a second storage circuit of the third set of storage circuits. The fourth driver is coupled to a first input of a fourth storage circuit within the third set of storage circuits.

[0029] In some embodiments, the third driver is coupled to an input of the fourth driver. In some embodiments, the first driver is coupled to an input of the second driver. In some embodiments, the digital-to-analog converter (DAC) circuit is reset by an enable zero signal received by the first set of storage circuits.

[0030] Various embodiments disclosed herein relate to a device. The device includes a digital-to-analog conversion (DAC) circuit configured to sample an input voltage. The DAC circuit includes a reset transistor. The device also includes a comparator circuit coupled to the DAC circuit, a first set of storage circuits coupled to the comparator circuit and the DAC circuit, and an enable circuit configured to provide an enable signal to the first set of storage circuits. The first set of storage circuits is configured to store a first bit corresponding to the input voltage provided by the comparator circuit. One of the enable signals is provided to the reset transistor to reset the sampling and digital-to-analog conversion (DAC) circuit.

[0031] In some embodiments, one of the enable signals is an enable zero (EN0) signal. In some embodiments, the enable zero signal is a clock signal that indicates that the least significant bit is to be converted. In some embodiments, a delay is provided in a reset path associated with the reset transistor to ensure that the final conversion is not affected. In some embodiments, the enable zero signal is used to stop a comparator clock signal of the comparator circuit. In some embodiments, the enable circuit includes a plurality of flip-flops that are clocked by the comparator clock signal. In some embodiments, the device further includes a conversion state circuit that uses one of the enable signals (e.g., the enable zero EN0 signal) to determine a conversion margin.

[0032] Various embodiments disclosed herein relate to a device. The device includes a digital-to-analog conversion (DAC) circuit configured to sample an input voltage, a comparator circuit coupled to the DAC circuit, and a first set of storage circuits coupled to the comparator circuit and the sampling and DAC circuit. The first set of storage circuits is configured to store a first bit corresponding to the input voltage. The first set of storage circuits is a ratio latch having an output coupled to a feedback input of the DAC circuit.

[0033] In some embodiments, the latch is a set and reset latch. In some embodiments, the device further includes a comparator driver located between the output of the comparator circuit and the first set of storage circuits. The comparator driver includes a first driver and a second driver. The first driver is coupled to a first input of a first storage circuit of the first set of storage circuits, and the second driver is coupled to a first input of a second storage circuit within the first set of storage circuits.

[0034] In some embodiments, the first storage circuit stores the most significant bit of the first bits provided by the comparator circuit, and the second set of storage circuits includes all remaining storage circuits in the first set of storage circuits. In some embodiments, the device further includes an enable circuit configured to provide an enable signal to the first set of storage circuits. One of the enable signals (e.g., an enable zero EN0 signal) is provided to a reset transistor in the sampling and digital-to-analog conversion (DAC) circuit to reset the sampling and digital-to-analog conversion (DAC) circuit.

[0035] In some embodiments, a conversion margin indicates unused or excess time during comparison operations available within a sampling cycle. In some embodiments, a control circuit is configured to determine the conversion margin and adjust a bias current, a threshold voltage, and / or a power supply voltage on a periodic basis. In some embodiments, the control circuit is configured to determine the conversion margin and adjust the bias current, the threshold voltage, and / or the power supply voltage when the device is powered on. In some embodiments, the control circuit is configured to adjust the bias current and the threshold voltage. In some embodiments, the control circuit is configured to adjust the bias current in response to the conversion margin, and the bias current is used for a current mirror or driver in the comparator circuit. In some embodiments, the control circuit is configured to adjust the threshold voltage in response to the conversion margin, and the threshold voltage is used by a driver in the comparator circuit. In some embodiments, the control circuit is configured to adjust the power supply voltage in response to the conversion margin. In some embodiments, the device further includes a conversion state circuit configured to provide a conversion state signal, and the conversion state circuit includes a variable delay circuit. In some embodiments, the control circuit adjusts the variable delay circuit to determine the conversion margin.

[0036] Various embodiments disclosed herein relate to a device including a receiver. The device can be used in communications applications. The receiver includes analog-to-digital conversion (ADC) circuitry, which includes a comparator and a processor. The processor is configured to determine a conversion margin and use the conversion margin to adjust a current or voltage used in the comparator. In some embodiments, a sampling clock signal is used to sample a voltage received by the ADC circuitry.

[0037] A. Computing and Network Environment

[0038] Before discussing specific embodiments of the present solution, it may be helpful to describe aspects of the operating environment and associated system components (eg, hardware elements) in conjunction with the methods and systems described herein. Figure 1A , depicting an embodiment of a network environment. In brief overview, the network environment includes a wireless communication system that includes one or more access points (APs) or network devices 106, one or more wireless communication devices 102, and nodes 192. The wireless communication device 102 may, for example, include a laptop computer, a tablet computer, a personal computer, and / or a cellular telephone device. For details on the embodiments of each wireless communication device 102 and / or network device 106 or AP, refer to Figure 1B and 1CDescribed in more detail. In one embodiment, the network environment may be an ad hoc network environment, an infrastructure wireless network environment, a subnet environment, etc. The network device 106 or AP may be operably coupled to the network hardware or node 192 via a local area network connection. The node 192, which may include a router, gateway, switch, bridge, modem, system controller, equipment, etc., may provide a local area network connection for the communication system. Each of the network devices 106 or APs may have an associated antenna or antenna array to communicate with wireless communication devices in its area. The wireless communication device 102 may register with a specific network device 106 or AP to receive services from the communication system (e.g., via SU-MIMO or MU-MIMO configuration). For direct connections (e.g., point-to-point communication), some wireless communication devices may communicate directly via assigned channels and communication protocols. Some of the wireless communication devices 102 may be mobile or relatively stationary relative to the network device 106 or AP.

[0039] In some embodiments, the network device 106 or AP includes a device or module (comprising a combination of hardware and software) that allows the wireless communication device 102 to connect to a wired network using Wireless Fidelity (WiFi) or other standards. The network device 106 or AP may sometimes be referred to as a wireless access point (WAP). The network device 106 or AP may be implemented (e.g., configured, designed, and / or constructed) to operate in a wireless local area network (WLAN). In some embodiments, the network device 106 or AP may be connected to a router (e.g., via a wired network) as a standalone device. In other embodiments, the network device 106 or AP may be a component of a router. The network device 106 or AP may provide access to a network to multiple devices. For example, the network device 106 or AP may connect to a wired Ethernet connection and use a radio frequency link to provide wireless connectivity so that other devices 102 can utilize the wired connection. The network device 106 or AP may be implemented to support standards for sending and receiving data using one or more radio frequencies. Those standards and the frequencies they use may be defined by the IEEE (e.g., the IEEE 802.11 standard). The network device 106 or AP may be configured and / or used to support public Internet hotspots and / or to extend the Wi-Fi signal range of the network on the network.

[0040] In some embodiments, the access points 106 may be used for wireless networks (e.g., IEEE 802.11, Bluetooth, ZigBee, any other type of radio frequency-based network protocol, and / or variations thereof) (e.g., within a home or within a building). Each of the wireless communication devices 102 may include a built-in radio and / or be coupled to a radio. Such wireless communication devices 102 and / or access points 106 may operate in accordance with various aspects of the present disclosure presented herein to enhance performance, reduce cost and / or size, and / or enhance broadband applications. Each wireless communication device 102 may have the capability to act as a client node seeking access to resources (e.g., data and connections to networked nodes such as servers) via one or more access points 106.

[0041] The network connection may include any type and / or form of network, and may include any of the following: a point-to-point network, a broadcast network, a telecommunications network, a data communications network, or a computer network. The network topology may be a bus, star, or ring network topology. The network may be any such network topology known to those of ordinary skill in the art that is capable of supporting the operations described herein. In some embodiments, different types of data may be transmitted via different protocols. In other embodiments, the same type of data may be transmitted via different protocols.

[0042] The communication device 102 and the access point 106 may be deployed as and / or executed on any type and form of computing device, such as a computer, network device, or appliance capable of communicating over any type and form of network and performing the operations described herein. Figure 1B and 1C A block diagram depicts a computing device 100 that may be used to practice embodiments of a wireless communication device 102 or a network device 106 or an AP. Figure 1B and 1C As shown in FIG, each computing device 100 includes a processor 121 (eg, a central processing unit) and a main memory unit 122. Figure 1B As shown in FIG, computing device 100 may include storage device 128, installation device 116, network interface 118, I / O controller 123, display devices 124a to 124n, keyboard 126, and pointing device 127 (e.g., mouse). Storage device 128 may include an operating system and / or software. Figure 1C As shown in , each computing device 100 may also include additional optional elements that communicate with the central processing unit 121, such as a memory port 103, a bridge 170, one or more input / output devices 130a to 130n, and a cache memory 140.

[0043] The central processing unit 121 is any logic circuit that responds to and processes instructions fetched from the main memory unit 122. In many embodiments, the central processing unit 121 is provided by a microprocessor unit, such as those manufactured by Intel Corporation of Santa Clara, California; by International Business Machines of White Plains, New York; or by Advanced Micro Devices of Sunnyvale, California. The computing device 100 may be based on any of these processors or any other processor capable of operating as described herein.

[0044] The main memory unit 122 may be one or more memory chips capable of storing data and allowing any storage location to be directly accessed by the microprocessor 121, such as any type or variant of static random access memory (SRAM), dynamic random access memory (DRAM), ferroelectric RAM (FRAM), NAND flash memory, NOR flash memory, and solid-state drive (SSD). The main memory 122 may be based on any of the above-mentioned memory chips or any other available memory chip capable of operating as described herein. Figure 1B In the embodiment shown in FIG, processor 121 communicates with main memory 122 via a system bus 150 (described in more detail below). Figure 1C An embodiment of the computing device 100 is depicted in which the processor communicates directly with the main memory 122 via the memory port 103. For example, in Figure 1C In the embodiment, the main memory 122 may be DRDRAM.

[0045] Figure 1C An embodiment is depicted in which the main processor 121 communicates directly with the cache memory 140 via a secondary bus (sometimes referred to as a back-end bus). In other embodiments, the main processor 121 communicates with the cache memory 140 using the system bus 150. The cache memory 140 typically has a faster response time than the main memory 122 and is provided by, for example, SRAM, BSRAM, or EDRAM. Figure 1C, the processor 121 communicates with the various I / O devices 130 via a local system bus 150. Various buses can be used to connect the central processing unit 121 to any of the I / O devices 130, such as a VESAVL bus, an ISA bus, an EISA bus, a Micro Channel Architecture (MCA) bus, a PCI bus, a PCI-X bus, a PCI-Express bus, or a NuBus. For embodiments in which the I / O device is a video display 124, the processor 121 can communicate with the display 124 using an Advanced Graphics Port (AGP). Figure 1C An embodiment of the computer 100 is depicted in which the main processor 121 can communicate directly with the I / O device 130b, for example, via HYPERTRANSPORT, RAPIDIO, or INFINIBAND communication technology. Figure 1C Also depicted are embodiments in which local buses and direct communications are mixed: processor 121 communicates with I / O device 130a using a local interconnect bus while communicating directly with I / O device 130b.

[0046] A variety of I / O devices 130a to 130n may be present in the computing device 100. Input devices include keyboards, mice, trackpads, trackballs, microphones, dials, touchpads, touch screens, and drawing tablets. Output devices include video displays, speakers, inkjet printers, laser printers, projectors, and dye sublimation printers. Figure 1B , the I / O devices may be controlled by an I / O controller 123. The I / O controller may control one or more I / O devices, such as a keyboard 126 and a pointing device 127, such as a mouse or an optical pen. In addition, the I / O devices may also provide storage and / or installation media 116 for the computing device 100. In yet other embodiments, the computing device 100 may provide a USB connection (not shown) to accept a handheld USB storage device, such as the USB flash drive family of devices manufactured by Twintech Industry, Inc. of Los Alamitos, California.

[0047] Reference again Figure 1B, the computing device 100 may support any suitable installation device 116, such as a disk drive, a CD-ROM drive, a CD-R / RW drive, a DVD-ROM drive, a flash drive, tape drives of various formats, a USB device, a hard drive, a network interface, or any other device suitable for installing software and programs. The computing device 100 may further include storage devices, such as one or more hard drives or redundant arrays of independent disks, for storing an operating system and other related software and for storing application software programs (e.g., any program or software 120 used to implement (e.g., configured and / or designed for) the systems and methods described herein). Optionally, any of the installation devices 116 may also serve as a storage device. In addition, the operating system and software may be run from bootable media.

[0048] Furthermore, the computing device 100 may include a network interface 118 to interface to a network through various connections, including, but not limited to, a standard telephone line, a LAN or WAN link (e.g., 802.11, T1, T3, 56 kb, X.25, SNA, DECNET), a broadband connection (e.g., ISDN, Frame Relay, ATM, Gigabit Ethernet, Ethernet-over-SONET), a wireless connection, or some combination of any or all of the above. The connection may be established using various communication protocols (e.g., TCP / IP, IPX, SPX, NetBIOS, Ethernet, ARCNET, SONET, SDH, Fiber Distributed Data Interface (FDDI), RS232, IEEE 802.11, IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, IEEE 802.11n, IEEE 802.11ac, IEEE 802.11ad, CDMA, GSM, WiMax, and direct asynchronous connection). In one embodiment, the computing device 100 communicates with other computing devices 100' via any type and / or form of gateway or tunneling protocol, such as Secure Sockets Layer (SSL) or Transport Layer Security (TLS). The network interface 118 may include a built-in network adapter, a network interface card, a PCMCIA network card, a card bus network adapter, a wireless network adapter, a USB network adapter, a modem, or any other device suitable for interfacing the computing device 100 to any type of network capable of communicating and performing the operations described herein.

[0049] In some embodiments, computing device 100 may include or be connected to one or more display devices 124a-124n. Thus, any of I / O devices 130a-130n and / or I / O controller 123 may include any type and / or form of suitable hardware, software, or combination of hardware and software to support, enable, or provide for connection to and use of display device(s) 124a-124n by computing device 100. For example, computing device 100 may include any type and / or form of video adapter, video card, driver, and / or library to interface, communicate, connect, or otherwise use display device(s) 124a-124n. In one embodiment, a video adapter may include multiple connectors to interface to display device(s) 124a-124n. In other embodiments, computing device 100 may include multiple video adapters, each of which is connected to display device(s) 124a-124n. In some embodiments, any portion of the operating system of computing device 100 may be configured to use multiple displays 124a-124n. In a further embodiment, the I / O device 130 may be a bridge between the system bus 150 and an external communication bus, such as a USB bus, an Apple Desktop bus, an RS-232 serial connection, a SCSI bus, a FireWire bus, a FireWire 800 bus, an Ethernet bus, an AppleTalk bus, a Gigabit Ethernet bus, an Asynchronous Transfer Mode bus, a Fibre Channel bus, a fiber optic bus, a Serial Attached Small Computer System Interface bus, a USB connection, or an HDMI bus.

[0050] Figure 1B and 1CA computing device 100 of the type depicted in the drawings may operate under the control of an operating system that controls the scheduling of tasks and access to system resources. The computing device 100 may run any operating system, such as any version of the MICROSOFT WINDOWS operating system, different versions of the Unix and Linux operating systems, any version of the MAC OS for Macintosh computers, any embedded operating system, any real-time operating system, any open source operating system, any proprietary operating system, any operating system for mobile computing devices, or any other operating system capable of running on a computing device and performing the operations described herein. Typical operating systems include (but are not limited to): Android produced by Google Inc.; WINDOWS 7, 8 and 10 produced by Microsoft Corporation of Redmond, Washington; MACOS produced by Apple Computer of Cupertino, California; WebOS produced by Research In Motion (RIM); OS / 2 produced by International Business Machines of Armonk, New York; and Linux, a freely available operating system distributed by Caldera Corp. of Salt Lake City, Utah, or any type and / or form of Unix operating system, etc.

[0051] The computer system 100 may be any workstation, phone, desktop computer, laptop or notebook computer, server, handheld computer, mobile phone or other portable telecommunication device, media playback device, gaming system, mobile computing device, or any other type and / or form of computing, telecommunication, or media device capable of communication. In some embodiments, the computing device 100 may have a different processor, operating system, and input device consistent with such a device. For example, in one embodiment, the computing device 100 is a smartphone, mobile device, tablet computer, or personal digital assistant. Furthermore, the computing device 100 may be any workstation, desktop computer, laptop or notebook computer, server, handheld computer, mobile phone, any other computer, or other form of computing or telecommunication device capable of communication and having sufficient processor power and memory capacity to perform the operations described herein.

[0052] Aspects of the operating environment and components described above will become apparent in the context of the systems and methods disclosed herein.

[0053] B.SAR ADC

[0054] Various embodiments disclosed herein relate to SAR ADCs, such as high-speed SAR ADCs or ultra-high-speed SAR ADCs. In some embodiments, the SAR ADCs are relatively immune to PVT variations and are configured for use in 200G / 100G networking applications. In some embodiments, systems and methods described herein are provided for SAR ADCs used in network integrated circuits (ICs), such as 225Gbps PAM4 optical transceivers or other transceivers. In some embodiments, the systems and methods described herein provide speed advantages without significant power / area penalties. The SAR ADCs may be described above with reference to Figure 1A to utilize or communicate with the various components discussed in C. The SAR ADC may operate according to the principles described herein and use the conversion structure and operation described in U.S. Patent No. 10,903,846, assigned to the assignee of the present application, and the entire contents of which are incorporated herein by reference. The SAR ADC may operate according to the principles described herein and use the conversion structure and operation described in U.S. Patent Application Serial No. ____(106861 6120), invented by Singh et al. and filed on the same date as herein, and U.S. Patent Application Serial No. 17 / 694225, invented by Liu et al. and filed on March 14, 2022, both of which are assigned to the assignee of the present application, and the entire contents of which are incorporated herein by reference.

[0055] Figure 2 2 is a block diagram depicting a communication device 200 according to one or more embodiments. In some embodiments, the communication device 200 is a system, device, or apparatus for network communications. For example, the communication device 200 is implemented as a network device 106, a node 192 or a network component, a device 102, or part of a network equipment serving a network in communication with the device 102. In some embodiments, the device 200 includes a transmitter 210, a receiver 220, and a processor 280. These components can operate together to communicate with another communication device over a network cable (e.g., Ethernet, USB, Firewire, etc.) and / or over a wireless medium (e.g., Wi-Fi, Bluetooth, a 60GHz link, a cellular network, etc.). In some embodiments, the communication device 200 includes a plurality of processors. Figure 2 More, fewer, or different components than those shown.

[0056] Transmitter 210 is a circuit or component that receives transmission data TX Data from processor 280 and generates output signals Out+ and Out-. Transmitter 210 can receive N-bit digital data TX Data from processor 280 and generate output signals Out+ and Out- having a voltage or current corresponding to the digital data TX Data. The output signals Out+ and Out- can be differential signals. In some embodiments, transmitter 210 can generate single-ended signals or signals in different representations for the output signals Out+ and Out-. In some embodiments, transmitter 210 transmits the output signals Out+ and Out- via a network cable. In some embodiments, transmitter 210 provides the output signals Out+ and Out- to a wireless transmitter (not shown), which can upconvert the output signals Out+ and Out- to generate wireless transmission signals at a radio frequency and transmit the wireless transmission signals via a wireless medium.

[0057] Receiver 220 is a circuit or component that receives input signals In+ and In- and generates receive data RX Data. In some embodiments, receiver 220 receives input signals In+ and In- via a network cable. Input signals In+ and In- may be differential signals. In some embodiments, receiver 220 may receive single-ended signals or signals representing different representations of input signals In+ and In-. In some embodiments, receiver 220 receives input signals In+ and In- from a wireless receiver (not shown), which may receive wireless receive signals via a wireless medium and down-convert the wireless receive signals to generate input signals In+ and In- at baseband frequency. In some embodiments, receiver 220 receives input signals In+ and In- and generates N-bit digital data RX Data corresponding to the voltage or current of input signals In+ and In-. Receiver 220 may provide digital data RX Data to processor 280. In some embodiments, receiver 220 includes a SAR ADC 225, which may convert input signals In+ and In- into N-bit digital data RX Data.

[0058] Processor 280 is a circuit or component capable of performing logical calculations. In some embodiments, processor 280 is implemented as a field programmable gate array, an application-specific integrated circuit, or a state machine. Processor 280 may be electrically coupled to transmitter 210 and receiver 220 via conductive traces or a bus connection. In this configuration, processor 280 may receive data RX Data from receiver 220 and perform logical calculations or execute various applications based on the state of the received data RX Data. Processor 280 may also generate data TX Data and provide the data TX Data to transmitter 210.

[0059] refer to Figure 3A, the SAR ADC 300 may be implemented as Figure 2 3 . In some embodiments, the SAR ADC 300 includes a sampling capacitor and digital-to-analog (CAPDAC) circuit 310, a comparator circuit 330, a conversion state circuit 350, a first set of storage circuits 360A, a second set of storage circuits 360B, an enable circuit 370, a clock path circuit 380, a controller 382, and a retimer circuit 400. These components can operate together to receive input signals In+, In- and perform successive approximation analog-to-digital conversion to generate L-bit data RX Data corresponding to the voltage of the input signals In+, In-, where L is any integer. In some embodiments, the SAR ADC 300 includes more, fewer, or different components than shown in FIG. Although FIG. Figure 3A In the embodiment of the present invention, CAPDAC circuit 310, comparator circuit 330, and storage circuits 360A and 360B are shown as generating and processing differential signals, but some or all of these components may generate and process single-ended signals. Additional comparator circuits and storage circuits may be provided in a cascaded, pipelined, or serial manner (e.g., a dual comparator design for SAR ADC 300). SAR ADC 300 is an IC device integrated on a single substrate, provided in a multi-chip package, or, in some embodiments, is part of another IC device.

[0060] In some embodiments, sampling and DAC circuit 310 is a circuit or component that samples input signals In+ and In- and generates DAC output signals DAC Out+ and DAC Out-. In one embodiment, sampling and DAC circuit 310 is embodied as a capacitive DAC circuit. In some embodiments, sampling and DAC circuit 310 includes inputs 311 and 312 configured to receive input signals In+ and In-, feedback ports 313, 314, 315, and 316 configured to receive L-bit data RX Data, and output ports 331 and 332 configured to output DAC output signals DAC Out+ and DAC Out-. In some embodiments, N feedback ports 315 and 316 are coupled to N output ports of the first set of storage circuits 360A, and M feedback ports 313 and 314 are coupled to M output ports of the second set of storage circuits 360B, where M and N are arbitrary integers. In some examples, N may be 4, 6, 8, 9, 10, 16, or 32, and M may be 4, 6, 8, 9, 10, 16, or 31. In some embodiments, N and M may be equal and may be equal to L. In some embodiments, a first output port 331 of the sampling and DAC circuit 310 is coupled to a first input port of the comparator circuit 330. A second output port 333 of the sampling and DAC circuit 310 is coupled to a second input port of the comparator circuit 330. In some embodiments, the sampling and DAC circuit 310 receives input signals In+ and In- at inputs 311 and 312, and receives L-bit data RX Data at feedback ports 313, 314, 315, and 316, and samples the input signals In- and In-. The sampling and DAC circuit 310 may perform DAC based on the L-bit data RX Data to generate DAC output signals DAC Out+ and DAC Out- at output ports 331 and 332. The sampling and DAC circuit 310 can provide DAC output signals DAC Out+ and DAC Out- to the comparator circuit 330. In one approach, for the Xth bit of the L-bit data RX Data, the DAC output signals DAC Out+ and DAC Out- indicate the voltages of the input signals In+ and In- (e.g., Vin+ and Vin-), where the voltages correspond to the L to X MSBs of Data RX. In one approach, the sampling and DAC circuit 310 generates the DAC output signals DAC Out+ and DAC Out- according to the following equations:

[0061]

[0062] Where V DAC Out+ is the voltage of the DAC Out+ signal, V DAC Out-is the voltage of the DAC Out- signal, and V ref is the reference voltage.

[0063] In some embodiments, comparator circuit 330 is a circuit or component that receives DAC output signals DAC Out+ and DAC Out− and determines the state of corresponding bits of data RX Data based on the DAC output signals DAC Out+ and DAC Out−. In some embodiments, comparator circuit 330 includes a first output port 361 coupled to a first input port of a first group of storage circuits 360A via inverter 336 and inverter 1132, a second output port 362 coupled to an input port of a second group of storage circuits 360B via inverter 338 and inverter 1134, and a clock input 339 coupled to conductor 373.

[0064] Conductor 373 is coupled to the output of a flip-flop 344 (e.g., a D flip-flop) of clock path circuit 380. Clock path 340 includes conductor 373, inverters 336 and 338, and clock path circuit 380, which includes logic device 342 and flip-flop 344. Data path 302 includes a first set of storage circuits 360A and a second set of storage circuits 360B, and extends between feedback ports 313, 314, 315, and 316 of CAPDAC circuit 310 and output ports 361 and 362 of comparator circuit 330. In some embodiments, first output port 361 of comparator circuit 330 can be directly coupled to a first input port of storage circuit 360A, and second output port 362 of comparator circuit 320 can be directly coupled to an input port of second storage circuit 360B.

[0065] Comparator circuit 330 can be enabled or disabled based on a clock signal CLK_SAR at clock input 339 from clock path circuit 380 on conductor 373. Clock signal CLK_SAR is the comparator clock signal for comparator circuit 330, which is disabled or stopped using an enable zero signal. For example, comparator circuit 330 is enabled in response to a rising edge or logic state '1' of clock signal CLK_SAR and is disabled in response to a falling edge or logic state '0' of clock signal CLK_SAR. When comparator circuit 330 is enabled, comparator circuit 330 can determine the state of a bit based on DAC output signals DAC Out+, DAC Out-, and generate comparator outputs Comp Out1+, Comp Out1- at output ports 361 and 362 indicating the determined state of the bit. For example, when the comparator circuit 330 is enabled, in response to the voltage difference between the DAC output signals DAC Out+ and DAC Out- being greater than 0V or a reference voltage, the comparator circuit 330 may generate a comparator output Comp Out1+ having a logic state of '1' and a comparator output Comp Out1- having a logic state of '0'. For example, when the comparator circuit 330 is enabled, in response to the voltage difference between the DAC output signals DAC Out+ and DAC Out- being less than 0V or a reference voltage, the comparator circuit 330 may generate a comparator output Comp Out1+ having a logic state of '0' and a comparator output Comp Out1- having a logic state of '1'. When the comparator circuit 330 is disabled, the comparator circuit 330 may reset the comparator outputs Comp Out1+ and Comp Out1- to a logic state of '0'. The comparator circuit 330 may provide the comparator outputs Comp Out1+ and Comp Out1- to the first and second storage circuits 360A and 360B. The comparator outputs Comp Out1+ and Comp Out1- may be differential signals.

[0066] refer to Figure 3B In some embodiments, the first group of storage circuits 360A is a group of components that stores N bits (e.g., 2, 4, 6, 8, 9, 16, 32 bits, etc.) of data. In one embodiment, the first group of storage circuits 360A is embodied as N flip-flops or latches. In some embodiments, the group of storage circuits 360A is a ratio set reset (SR) latch. In some embodiments, the ratio latches each include an output stage that is configured to drive feedback ports 313, 314, 315, and 316 according to their bit positions. In some embodiments, the first input port of each storage circuit 360A, except for storage circuit 1102, is connected via inverters 336 and 1132 ( Figure 3B ) is coupled to the first output port 361 of the comparator circuit 330 ( Figure 3A). In some embodiments, the enable port of each storage circuit 360A is coupled to a corresponding enable output port of enable circuit 370, and the output port of each storage circuit 360A is coupled to corresponding feedback ports 315 and 316 of sampling and DAC circuit 310. In some embodiments, the first input port of storage circuit 1102 (e.g., corresponding to the most significant bit (MSB)) in a group of storage circuits 360A is coupled to the first output port 361 of the comparator circuit through inverter 336. In this configuration, each storage circuit 360A can be enabled or disabled according to a corresponding bit of enable signal EN on enable bus 371. For example, in response to the enable signal EN being 00001 (enable zero signal EN0), the first storage circuit of storage circuit 360A is enabled; in response to the enable signal EN being 00010, the second storage circuit of storage circuit 360A is enabled; in response to the enable signal EN being 00100, the third storage circuit of storage circuit 360A is enabled; in response to the enable signal EN being 01000, the fourth storage circuit of storage circuit 360A is enabled; and in response to the enable signal EN being 10000, the fifth storage circuit of storage circuit 360A is enabled. In some embodiments, the enabling scheme follows the scheme described above for the remaining storage circuits 360A and 360B. For example, in response to the enable signal EN being 00000, all first group storage circuits 360A are disabled. When storage circuit 360A is enabled, storage circuit 360B may update corresponding bits of data RX Data based on the comparator outputs Comp Out1+ and Comp Out1-. For example, if the storage circuit 360A is enabled, then in response to the comparator output Comp Out1+ having a logic state of '1' and the comparator output Comp Out1- having a logic state of '0', the storage circuit 360A may update the corresponding bit of the data RX Data to '1'. For example, if the storage circuit 360A is enabled, then in response to the comparator output Comp Out1- having a logic state of '1' and the comparator output Comp Out1+ having a logic state of '0', the storage circuit 360A may update the corresponding bit of the data RX Data to '0'. If the storage circuit of the storage circuit 360A is disabled, the storage circuit may retain or store the corresponding bit of the data RX Data regardless of the comparator outputs Comp Out1+ and Comp Out1- at the input port.

[0067] In some embodiments, the second group of storage circuits 360B is a group of components that stores M bits of data. In one embodiment, the second group of storage circuits 360B is embodied as M flip-flops or latches. In some embodiments, a group of storage circuits 360B is a ratio set reset (SR) latch. In some embodiments, except for storage circuit 1104, the first input port of each storage circuit 360B is coupled to the first output port 362 ( ) of comparator circuit 330 via inverters 338 and 1134. Figure 3A In some embodiments, the enable port of each storage circuit 360B is coupled to the corresponding enable output port of the enable circuit 370 via bus 371. In some embodiments, the storage circuit 1104 ( Figure 3B The first input port of the first group of storage circuits 360B (e.g., corresponding to the most significant bit (MSB)) is coupled to the first output port 362 of the comparator circuit 330 through the inverter 338. The output port of each storage circuit 360B is coupled to the corresponding feedback ports 313 and 314 of the sampling and DAC circuit 310. In some embodiments, the operation of the storage circuits 360B is similar to the operation of the first group of storage circuits 360A, and the enabling of the storage circuits 360B occurs as discussed above using the enable signal EN on the bus 371. In some embodiments, the storage circuits 360A are used for the positive portion of the differential signal, and the storage circuits 360B are used for the negative portion of the differential signal.

[0068] By directly driving only storage circuit 1102 with a driver (e.g., inverter 336) and only storage circuit 1104 with a driver (e.g., inverter 338), the load on the comparator drivers (e.g., inverters 336 and 338) is reduced. This driving scheme can also simplify the circuit layout. In some embodiments, the remaining storage circuits of storage circuits 360A-B are driven by different drivers (e.g., inverters 1132 and 1134, respectively). In some embodiments, inverter 336 has an output directly coupled to the input of inverter 1132, and inverter 338 has an output directly coupled to the input of inverter 1134. In some embodiments, inverters 336 and 338 directly drive the inputs of storage circuits 1102 and 1104 representing the MSB.

[0069] The data path 302 can be reduced by using an SR latch to directly drive the CAPDAC circuit 310 instead of using a ratio inverter between the storage circuits 360A-B and the CAPDAC circuit 310. Figure 3A ) in the delay. Figure 3B, the enable 0 (EN0) signal on conductor 345 resets the CAPDAC circuit by driving the gate of switch or transistor 1130 in CAPDAC circuit 310. As described above, storage circuits 360A and 360B are enabled by the enable signal EN provided on bus 371.

[0070] Retimer circuit 400 is a flip-flop or latch based circuit that receives outputs from storage circuits 360A and 360B. In some embodiments, retimer circuit 400 aligns timing of downstream devices or components.

[0071] In some embodiments, conversion state circuit 350, enable circuit 370, and clock path circuit 380 enable comparator circuit 330 and storage circuits 360A and 360B to perform successive approximation analog-to-digital conversion. In some embodiments, conversion state circuit 350, enable circuit 370, and clock path circuit 380 are implemented as a state machine and / or digital logic circuit. In some embodiments, conductor 372 receives a T clock signal (T CLK), for example, from a clock generator (not shown). The T clock signal is a sampling clock and has a period corresponding to a sampling cycle.

[0072] refer to Figure 3A Clock path circuit 380 provides a CLK_SAR signal on clock path 340 at conductor 373 to comparator circuit 330 and enable circuit 370, which provides an enable signal on bus 371. Flip-flop 344 is configured as a D-type flip-flop and includes an input coupled to conductor 345, which receives an enable 0 (EN0) signal from enable circuit 370. Flip-flop 344 includes a clock input coupled to logic device 342, which may be configured as a NAND gate. Logic device 342 receives signals from inverters 336 and 338. Inverters 336, 338, 1132, and 1134 are configured as a comparator driver. In some embodiments, the CLK_SAR signal is an internally generated clock signal provided by flip-flop 344, logic device 342, inverters 336 and 338, and comparator circuit 330. In some embodiments, the CLK_SAR signal is generated by comparator transitions and the enable 0 (EN0) signal.

[0073] The enable circuit 370 is a latch or flip-flop (e.g., D flip-flop) based timing circuit that provides an enable EN signal on bus 371 for storage elements 360A and 360B in response to a clock signal on conductor 373. Each flip-flop or latch in the enable circuit 370 is driven at the clock input by the CLK_SAR signal on conductor 373 and provides a one-bit enable EN signal on bus 371. The enable 0 (EN0) signal from the enable circuit 370 is provided on conductor 345 for use by the flip-flop 344 of the conversion state circuit 350 and the clock path circuit 380. The enable 0 (EN0) signal, as an indicator of the start of the last conversion cycle, is used to force an early reset (e.g., using transistor 1130 ( Figure 3B )). Transistor 303 can be used to reset CAPDAC circuit 310 using an enable 0 (EN0) signal or other reset signal. A delay (e.g., a delay path or element) can be provided in the reset path associated with the enable 0 (EN0) signal to ensure that the last conversion is not affected by the reset operation using the enable 0 (EN0) signal. In some embodiments, conductor 345 is directly coupled to transistor 1130.

[0074] Conversion state circuit 350 includes inverter 352, conversion margin indicator circuit 354, and conversion state output 356. Inverter 354 receives the T clock signal at conductor 372 and provides a CLK_RT signal to conversion margin indicator circuit 354. Conversion margin indicator circuit 354 receives an enable 0 (EN0) signal at conductor 345 and a CLK_SAR signal at conductor 372. Conversion state circuit 350 provides a conversion state signal at output 356 that indicates a state conversion operation. Conversion margin indicator circuit 354 provides a signal at conductor 372 for determining a conversion margin using the CLK_RT signal, the enable 0 (EN0) signal, and the CLK_SAR signal.

[0075] In some embodiments, the controller 382 is an on-chip controller configured to determine the conversion margin and adjust the current and voltage parameters to achieve faster operation or less noise. Advantageously, in some embodiments, the controller 382 implements the systems and methods described herein for determining the conversion margin and adjusting the voltage and current parameters. The controller 382 may be a hardware implementation or software (e.g., a firmware implementation) integrated with the SAR ADC 300 (e.g., provided as part of the conversion state circuit 350 or other part of the SAR ADC 300). In some embodiments, the processor or controller 382 determines the probability of a successful conversion greater than a first threshold, and defines a successful conversion when the conversion margin is greater than a second threshold. In some embodiments, the controller 382 is a processor, a microcontroller, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or a logic device, or any other type and form of dedicated semiconductor logic or processing circuit system capable of processing or supporting the operations described herein. In some embodiments, the operations associated with the controller 382 are performed in whole or in part by the processor 280 ( Figure 2 )implement.

[0076] refer to Figure 4 Conversion margin indicator circuit 354 includes a D flip-flop 402, a variable time delay circuit 404, and a D flip-flop 406. In some embodiments, variable time delay circuit 404 is a programmable or configurable circuit that provides a selectable delay. D flip-flop 402 includes a reset input coupled to conductor 353 for receiving the CLK_RT signal from inverter 352 ( FIG. 3 ), and D flip-flop 406 includes a clock input coupled to conductor 353 for receiving the CLK_RT signal from inverter 352. The D input of flip-flop 402 is coupled to conductor 345 to receive an enable 0 (EN0) signal. The output of D flip-flop 402 is coupled to the input of delay circuit 404. The clock input of D flip-flop 402 is coupled to conductor 372 to receive the CLK_SAR signal. The D input of flip-flop 406 is coupled to receive the conversion complete signal from variable time delay circuit 404.

[0077] In some embodiments, a conversion complete signal indicates when the conversion of the analog signals at inputs 311 and 312 to digital representations in storage circuits 360A and 360B is complete. In some embodiments, a conversion status signal indicates that a conversion has occurred before the end of a sampling cycle. In some embodiments, the conversion margin may be represented by or proportional to the difference between the leading edges of the conversion complete signal and the conversion status signal. In some embodiments, conversion status circuit 350 provides the conversion status signal at output 356. SAR ADC 300 (e.g., microcontroller 382) may employ adaptive feedback techniques using the conversion margin determined from the conversion status signal and the conversion complete signal or other parameters related thereto. Adaptive feedback may advantageously compensate for noise from comparator circuit 330 and process dependencies associated with the drivers of comparator circuit 330 (e.g., inverters 336 and 338). In some embodiments, conversion margin indicator circuit 354 is configured such that an approximation of the conversion margin using the conversion status signal may be inferred.

[0078] refer to Figure 5 , waveform 502 is the CLK_RT signal at conductor 353. Waveform 504 is a conversion complete signal indicating that the conversion is complete and is provided by time delay circuit 404 to the D input of flip-flop 406. Waveform 506 is a conversion status signal at output 356. Waveform 508 is a conversion status signal with T D1 The time delay conversion completion signal is provided by the time delay circuit 404. M Greater than the time delay T D1 , waveform 510 is the switching state signal at output 356. Time period T M Proportional to the conversion margin. Waveform 512 is a waveform with T D2 The time delay conversion completion signal is provided by the time delay circuit 404. M Less than the time delay T D2 , waveform 514 is the switching state signal at output 356. Destructive measurement of the switching state signal at output 356 is used to determine the time period T M For example, changing the value of T D , until the conversion status signal at the output 356 flips from 1 to 0, resulting in a time delay of T D The value corresponds to the time period T M (See waveform 514). Time delay T D Provided by the variable time delay circuit 404. Generally speaking, the time period T M And the conversion margin varies with the input of the SAR ADC 300, system noise, and metastable events.

[0079] In some embodiments, the SAR ADC 300 uses a collection time period T M The values are collected over time. In some embodiments, the values are collected as the time delay changes. The time period T can be calculated for various time delays. M The probability of being greater than a certain value. When the time period T M Greater than the time delay T D When the probability and time period T M The curve of α flattens out, indicating the minimum conversion margin value at that delay. The delay can be used as the minimum conversion margin value, which can be used to provide adaptive feedback for the SAR ADC 300, as described below.

[0080] refer to Figure 6 In some embodiments, comparator circuit 330 includes an adjustable current source circuit 700. Current source circuit 700 includes transistor 702, current source 704, multiplexer 706, transistor 710, and transistor 712, which are configured as adjustable current sources for transistors 714, 716, 718, and 720 of comparator circuit 330. In some embodiments, transistor 712 is driven by the CLK_SAR signal. In some embodiments, transistors 714, 716, 718, and 720 are the first stage of comparator circuit 330, receive signals at output ports 331 and 332 (Figure 3), and can be part of a high-speed comparator. Transistor 710 is configured to provide I max and I min Current within the range I bias Current I bias The value of is controlled by a multiplexer 706, which selects the ground signal or the signal from between transistor 702 and current source 704 based on a select signal provided to a select input of a multiplexer 708. In some embodiments, the select signal is provided by the controller 382. The multiplexer 706 drives the transistor 710 according to the selection. In some embodiments, for the low speed corner (SS), the current source value is adjusted to I for high speed. max In some embodiments, for high-speed corners (FF), the current source value is adjusted to I for low speed. min . Select signal and time period T M related, where a larger switching margin indicates that transistor 710 should provide a lower I bias ,vice versa.

[0081] refer to Figure 7, comparator circuit 330 includes an adjustable driver circuit 800. Adjustable driver circuit 800 includes transistor 804, multiplexer 806, current source 820, transistor 814, transistor 824, transistor 826, transistor 828, and transistor 830. In some embodiments, adjustable driver circuit 800 is an adjustable comparator driver for a high-speed comparator and can be used at outputs 361 and 362 ( Figure 3A ) is provided. Current I biasi The value of is controlled by a multiplexer 806, which selects a ground signal or a signal from a node between transistor 804 and current source 820 to drive the current I of transistors 824, 828, 826, and 830. biasi The select signal at the select input of the multiplexer 806 is used to adaptively tune the current I biasi The select signal is based on the conversion margin and may be provided by the controller 382 ( FIG. 3 ). In some embodiments, the current I through the transistor 814 is adjusted. biasi To change the current I biasi Without significantly affecting the speed. Select the signal and time period T M related, where a larger switching margin indicates that transistor 814 should provide a lower I biasi ,vice versa.

[0082] refer to Figure 8 , comparator circuit 330 may include an adjustable driver circuit 900. Adjustable driver circuit 900 includes input 902, transistor 904, transistor 906, transistor 908, transistor 912, transistor 914, multiplexer 916, transistor 920, multiplexer 922, transistor 924, and output 930. Adjustable driver circuit 900 is configured as an adjustable comparator driver for a high-speed comparator and, in some embodiments, may be provided at outputs 361 and 362. Driver threshold voltage V th The value of is controlled by multiplexers 916 and 922, which respectively select the voltage signal V DD or a clock signal (eg, CLK_SAR) to drive transistors 914 and 924. The select signals at the select inputs of multiplexers 916 and 922 are used to adaptively tune the driver threshold voltage V th The selection signal is based on the conversion margin and can be provided by the controller 382 (Figure 3). The selection signal and the time period T M Related, where a larger switching margin indicates that transistors 914 and 924 should provide a lower threshold voltage V th In some embodiments, the time period T M To set V DD, where a larger conversion margin indicates that a lower voltage V should be provided DD ,vice versa.

[0083] refer to Figure 9 SAR ADC 300 may execute process 1000 to measure and convert a status signal (eg, waveform 506 ( Figure 5 )) associated with the statistic or value. Flow 1000 is executed to evaluate the conversion state signal is 1 (e.g., Figure 5 514 in the waveform 510). In some embodiments, the probability P(CS) can be determined by comparing the conversion margin with a certain value. The probability is the probability of a successful conversion, and in some embodiments, a successful conversion is defined when the conversion margin is greater than a threshold. The value can be a fixed value, a percentage of a sampling cycle, etc. The probability can be represented by curves 1106, 1108, and 1110 provided on an X-axis representing the conversion margin over time and a Y-axis representing the probability. Curves 1106, 1108, and 1110 are each for a specific time delay (100 picoseconds (ps), 200 ps, 300 ps). According to some embodiments, process 1000 is performed so that the SAR ADC 300 is at a given delay T D The conversion margin is greater than the time delay T. D When , the flat portion of curves 1106, 1108 and 1110 begins.

[0084] The process 1000 includes adjusting the current I bias ( Figure 7 ) operation 1002. If the current I bias Greater than I min , then the probability is estimated in operation 1004. If the probability is above the threshold (e.g., above a percentage of 90% (e.g., 0.95)), the process 1000 returns to operation 1002. If the probability is below the threshold (e.g., above a proportion of 90% (e.g., 0.95)), the process 1000 ends the adjustment in operation 1006. If the current I bias ( Figure 7 ) is less than I min (the minimum value of the adjustable bias current of the comparator circuit 330), then in operation 1010 the voltage threshold V th ( Figure 9 ) or current I biasi ( Figure 8 In some embodiments, the voltage threshold V is adjusted in operation 1010. th or current I biasiTo increase the speed. If the current I biasi Greater than I mini or voltage threshold V th Greater than V min (This depends on the implementation, see Figure 8 and 9 ), then the probability is estimated in operation 1012. If the probability is above the threshold (e.g., above a percentage of 90% (e.g., 0.95)), then the process 1000 returns to operation 1008. If the probability is below the threshold (e.g., above a proportion of 90% (e.g., 0.95)), then the process 1000 ends the adjustment in operation 1016. If the current I biasi Less than I mini (minimum value of the adjustable bias current of the comparator driver) or the voltage threshold V th Less than V min (eg, the maximum NMOS adjustable code of the comparator driver), then in operation 1020 the voltage signal V DD If the voltage signal V DD Greater than V DDmin (the minimum supply voltage of the SAR ADC 300), the probability is estimated in operation 1022. If the probability is above the threshold (e.g., above a percentage of 90% (e.g., 0.95)), the process 1000 returns to operation 1020. If the probability is below the threshold (e.g., above a percentage of 90% (e.g., 0.95)), the process 1000 ends the adjustment in operation 1026. The process 1000 can be performed together or sequentially for the threshold voltage V th and current I biasi Both operate operations 1010, 1012, and 1016. In some embodiments, the order of the branches of operations 1002, 1004, and 1006, the branches of operations 1010, 1012, 1016, and the branches of operations 1020, 1022, and 1026 can be switched.

[0085] Process 1000 may be executed in controller 382. Process 1000 may include fewer operations, such as operations 1002, 1004, and 1006, operations 1010, 1012, and 1016, or operations 1020, 1022, and 1026. Process 1000 may be combined with other operations. Process 1000 may be implemented in a hardware implementation or in software (e.g., a firmware implementation) (e.g., provided as part of conversion state circuit 350 or other portion of SAR ADC 300). In some embodiments, controller 382 is any type and form of dedicated semiconductor logic or processing circuitry capable of processing or supporting process 1000. Process 1000 may include software instructions provided on non-transitory media and may be implemented by executing the instructions on controller 382. Process 1000 may be executed at chip initialization, at power-up, and periodically during operation. Conversion margins may be periodically calculated to determine whether adjustments are required when SAR ADC 300 is operating (e.g., heating). Process 1000 can be executed periodically over a millisecond time period (e.g., every 4 milliseconds at startup and every 100 to 400 milliseconds during operation). In some embodiments, historical values of the conversion margin are determined and stored. The larger difference between the values can be used to initiate process 1000. In some embodiments, the conversion margin indicates the amount of unused time before a bit error occurs within a sampling cycle.

[0086] It should be noted that certain paragraphs of this disclosure may refer to terms related to devices or operations, such as "first" and "second," for the purpose of identifying or distinguishing one from another or others. These terms are not intended to relate entities (e.g., a first device and a second device) only in time or according to a sequence, although in some cases, these entities may contain such a relationship. These terms also do not limit the number of possible entities that can operate in a system or environment. It should be understood that the above-described system may provide multiple of any or each of those components, and these components may be provided on a standalone machine or, in some embodiments, on multiple machines in a distributed system. In addition, the above-described systems and methods may be provided as one or more computer-readable programs or executable instructions embodied on or in one or more articles of manufacture (e.g., floppy disk, hard disk, CD-ROM, flash memory card, PROM, RAM, ROM, or tape). The program can be implemented in any programming language (e.g., LISP, PERL, C, C++, C#) or in any bytecode language (e.g., JAVA). The software program or executable instructions may be stored as object code on or in one or more articles of manufacture. Further, some components may be coupled together with intermediate components provided therebetween.

[0087] Although the above written description of the methods and systems enables one of ordinary skill in the art to make and use embodiments thereof, one of ordinary skill in the art will understand and appreciate that variations, combinations, and equivalents exist to the specific embodiments, methods, and examples herein. Accordingly, the methods and systems of the present disclosure should not be limited to the above-described embodiments, methods, and examples, but rather to all embodiments and methods within the scope and spirit of the present disclosure.

Claims

1. A device comprising: Digital / analog conversion DAC circuit; a comparator circuit coupled to the DAC circuit having an output; a first set of storage circuits coupled to the comparator circuit and the DAC circuit, the first set of storage circuits configured to store a plurality of first bits corresponding to an input voltage; as well as a comparator driver located between the output and the first group of storage circuits, wherein the comparator driver includes a first driver and a second driver, the first driver being coupled to an input of a first storage circuit of the first group of storage circuits and the second driver being coupled to an input of a second group of storage circuits within the first group of storage circuits.

2. The device of claim 1, wherein the second set of storage circuits does not include the first storage circuit. 3 . The apparatus of claim 1 , wherein the first storage circuit stores a most significant bit of the first bits provided by the comparator circuit.

4. The apparatus of claim 1, wherein the second group of storage circuits includes all remaining storage circuits in the first group of storage circuits.

5. The device of claim 1, further comprising a third set of storage circuits to the comparator circuit and the DAC circuit, the third set of storage circuits configured to store a plurality of second bits corresponding to the input voltage.

6. The device of claim 5 , wherein the comparator driver comprises a third driver coupled to an input of a second storage circuit of the third group of storage circuits and a fourth driver coupled to an input of a fourth group of storage circuits within the third group of storage circuits.

7. The apparatus of claim 6, wherein the third driver is coupled to an input of the fourth driver.

8. The apparatus of claim 1, wherein the first driver is coupled to an input of the second driver.

9. The apparatus of claim 1, wherein the digital-to-analog conversion (DAC) circuit is reset by an enable zero signal received by the first group of storage circuits.

10. A device comprising: A digital-to-analog conversion (DAC) circuit comprising a reset transistor; a comparator circuit coupled to the DAC circuit; a first set of storage circuits coupled to the comparator circuit and the DAC circuit, the first set of storage circuits configured to store a plurality of first bits corresponding to an input voltage provided by the comparator circuit; as well as An enable circuit is configured to provide enable signals to the first group of storage circuits, wherein one of the enable signals is provided to the reset transistor to reset the digital-to-analog conversion (DAC) circuit. The device of claim 10 , wherein the one of the enable signals is an enable zero signal.

12. The apparatus of claim 11, wherein a delay is provided in a reset path associated with the reset transistor to ensure that a last transition is not affected.

13. The apparatus of claim 11, wherein the enable zero signal is used to disable a comparator clock signal of the comparator circuit.

14. The apparatus of claim 10, wherein the enabling circuit comprises a plurality of flip-flops, the flip-flops being clocked by a comparator clock signal.

15. The device of claim 10, further comprising conversion state circuitry, and wherein the conversion state circuitry uses said one of the enable signals to determine a conversion margin.

16. An apparatus comprising: Digital / analog conversion DAC circuit; a comparator circuit coupled to the DAC circuit; a first set of storage circuits coupled to the comparator circuit and the DAC circuit, the first set of storage circuits configured to store a plurality of first bits corresponding to input voltages, wherein the first set of storage circuits are ratio latches having outputs coupled to a feedback input of the DAC circuit; as well as An enable circuit is configured to provide enable signals to the first set of storage circuits, wherein one of the enable signals is provided to a reset transistor in the digital-to-analog conversion DAC circuit to reset the digital-to-analog conversion DAC circuit.

17. The device of claim 16, wherein the latch is a set and reset latch.

18. An apparatus comprising: Digital / analog conversion DAC circuit; a comparator circuit coupled to the DAC circuit; a first set of storage circuits coupled to the comparator circuit and the DAC circuit, the first set of storage circuits configured to store a plurality of first bits corresponding to input voltages, wherein the first set of storage circuits are ratio latches having outputs coupled to a feedback input of the DAC circuit; as well as a comparator driver positioned between an output of the comparator circuit and the first group of storage circuits, wherein the comparator driver comprises a first driver coupled to a first input of a first storage circuit of the first group of storage circuits and a second driver coupled to a first input of a second group of storage circuits within the first group of storage circuits.

19. The apparatus of claim 18, wherein the first storage circuit stores a most significant bit of the first bits provided by the comparator circuit, and the second group of storage circuits includes all remaining storage circuits in the first group of storage circuits.

20. The device of claim 18, further comprising an enable circuit configured to provide enable signals to the first group of storage circuits, wherein one of the enable signals is provided to a reset transistor in the digital-to-analog conversion DAC circuit to reset the digital-to-analog conversion DAC circuit.

Images